commit 1c13bad27005c8d301ebb33517d40de8e3daac2d Author: = Date: Tue Mar 30 15:04:17 2021 +0200 Initial commit Fichier de base de M.Juton diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h new file mode 100644 index 0000000..9331ae5 --- /dev/null +++ b/Core/Inc/FreeRTOSConfig.h @@ -0,0 +1,144 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.2.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; +#endif +#define configENABLE_FPU 0 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 7 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)32768) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 0 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick, + to prevent overwriting SysTick_Handler defined within STM32Cube HAL */ + +#define xPortSysTickHandler SysTick_Handler + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Core/Inc/ft5336.h b/Core/Inc/ft5336.h new file mode 100644 index 0000000..4f46644 --- /dev/null +++ b/Core/Inc/ft5336.h @@ -0,0 +1,540 @@ +/** + ****************************************************************************** + * @file ft5336.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file contains all the functions prototypes for the + * ft5336.c Touch screen driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT5336_H +#define __FT5336_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Set Multi-touch as supported */ +#if !defined(TS_MONO_TOUCH_SUPPORTED) +#define TS_MULTI_TOUCH_SUPPORTED 1 +#endif /* TS_MONO_TOUCH_SUPPORTED */ + +/* Includes ------------------------------------------------------------------*/ +#include "ts.h" + +/* Macros --------------------------------------------------------------------*/ + +#if defined(FT5336_ENABLE_ASSERT) +/* Assert activated */ +#define FT5336_ASSERT(__condition__) do { if(__condition__) \ + { \ + while(1); \ + } \ + }while(0) +#else +/* Assert not activated : macro has no effect */ +#define FT5336_ASSERT(__condition__) do { if(__condition__) \ + { \ + ; \ + } \ + }while(0) +#endif /* FT5336_ENABLE_ASSERT == 1 */ + +/** @typedef ft5336_handle_TypeDef + * ft5336 Handle definition. + */ +typedef struct +{ + uint8_t i2cInitialized; + + /* field holding the current number of simultaneous active touches */ + uint8_t currActiveTouchNb; + + /* field holding the touch index currently managed */ + uint8_t currActiveTouchIdx; + +} ft5336_handle_TypeDef; + + /** @addtogroup BSP + * @{ + */ + + /** @addtogroup Component + * @{ + */ + + /** @defgroup FT5336 + * @{ + */ + + /* Exported types ------------------------------------------------------------*/ + + /** @defgroup FT5336_Exported_Types + * @{ + */ + + /* Exported constants --------------------------------------------------------*/ + + /** @defgroup FT5336_Exported_Constants + * @{ + */ + + /* I2C Slave address of touchscreen FocalTech FT5336 */ +#define FT5336_I2C_SLAVE_ADDRESS ((uint8_t)0x70) + + /* Maximum border values of the touchscreen pad */ +#define FT5336_MAX_WIDTH ((uint16_t)480) /* Touchscreen pad max width */ +#define FT5336_MAX_HEIGHT ((uint16_t)272) /* Touchscreen pad max height */ + + /* Possible values of driver functions return status */ +#define FT5336_STATUS_OK ((uint8_t)0x00) +#define FT5336_STATUS_NOT_OK ((uint8_t)0x01) + + /* Possible values of global variable 'TS_I2C_Initialized' */ +#define FT5336_I2C_NOT_INITIALIZED ((uint8_t)0x00) +#define FT5336_I2C_INITIALIZED ((uint8_t)0x01) + + /* Max detectable simultaneous touches */ +#define FT5336_MAX_DETECTABLE_TOUCH ((uint8_t)0x05) + + /** + * @brief : Definitions for FT5336 I2C register addresses on 8 bit + **/ + + /* Current mode register of the FT5336 (R/W) */ +#define FT5336_DEV_MODE_REG ((uint8_t)0x00) + + /* Possible values of FT5336_DEV_MODE_REG */ +#define FT5336_DEV_MODE_WORKING ((uint8_t)0x00) +#define FT5336_DEV_MODE_FACTORY ((uint8_t)0x04) + +#define FT5336_DEV_MODE_MASK ((uint8_t)0x07) +#define FT5336_DEV_MODE_SHIFT ((uint8_t)0x04) + + /* Gesture ID register */ +#define FT5336_GEST_ID_REG ((uint8_t)0x01) + + /* Possible values of FT5336_GEST_ID_REG */ +#define FT5336_GEST_ID_NO_GESTURE ((uint8_t)0x00) +#define FT5336_GEST_ID_MOVE_UP ((uint8_t)0x10) +#define FT5336_GEST_ID_MOVE_RIGHT ((uint8_t)0x14) +#define FT5336_GEST_ID_MOVE_DOWN ((uint8_t)0x18) +#define FT5336_GEST_ID_MOVE_LEFT ((uint8_t)0x1C) +#define FT5336_GEST_ID_SINGLE_CLICK ((uint8_t)0x20) +#define FT5336_GEST_ID_DOUBLE_CLICK ((uint8_t)0x22) +#define FT5336_GEST_ID_ROTATE_CLOCKWISE ((uint8_t)0x28) +#define FT5336_GEST_ID_ROTATE_C_CLOCKWISE ((uint8_t)0x29) +#define FT5336_GEST_ID_ZOOM_IN ((uint8_t)0x40) +#define FT5336_GEST_ID_ZOOM_OUT ((uint8_t)0x49) + + /* Touch Data Status register : gives number of active touch points (0..5) */ +#define FT5336_TD_STAT_REG ((uint8_t)0x02) + + /* Values related to FT5336_TD_STAT_REG */ +#define FT5336_TD_STAT_MASK ((uint8_t)0x0F) +#define FT5336_TD_STAT_SHIFT ((uint8_t)0x00) + + /* Values Pn_XH and Pn_YH related */ +#define FT5336_TOUCH_EVT_FLAG_PRESS_DOWN ((uint8_t)0x00) +#define FT5336_TOUCH_EVT_FLAG_LIFT_UP ((uint8_t)0x01) +#define FT5336_TOUCH_EVT_FLAG_CONTACT ((uint8_t)0x02) +#define FT5336_TOUCH_EVT_FLAG_NO_EVENT ((uint8_t)0x03) + +#define FT5336_TOUCH_EVT_FLAG_SHIFT ((uint8_t)0x06) +#define FT5336_TOUCH_EVT_FLAG_MASK ((uint8_t)(3 << FT5336_TOUCH_EVT_FLAG_SHIFT)) + +#define FT5336_TOUCH_POS_MSB_MASK ((uint8_t)0x0F) +#define FT5336_TOUCH_POS_MSB_SHIFT ((uint8_t)0x00) + + /* Values Pn_XL and Pn_YL related */ +#define FT5336_TOUCH_POS_LSB_MASK ((uint8_t)0xFF) +#define FT5336_TOUCH_POS_LSB_SHIFT ((uint8_t)0x00) + +#define FT5336_P1_XH_REG ((uint8_t)0x03) +#define FT5336_P1_XL_REG ((uint8_t)0x04) +#define FT5336_P1_YH_REG ((uint8_t)0x05) +#define FT5336_P1_YL_REG ((uint8_t)0x06) + +/* Touch Pressure register value (R) */ +#define FT5336_P1_WEIGHT_REG ((uint8_t)0x07) + +/* Values Pn_WEIGHT related */ +#define FT5336_TOUCH_WEIGHT_MASK ((uint8_t)0xFF) +#define FT5336_TOUCH_WEIGHT_SHIFT ((uint8_t)0x00) + +/* Touch area register */ +#define FT5336_P1_MISC_REG ((uint8_t)0x08) + +/* Values related to FT5336_Pn_MISC_REG */ +#define FT5336_TOUCH_AREA_MASK ((uint8_t)(0x04 << 4)) +#define FT5336_TOUCH_AREA_SHIFT ((uint8_t)0x04) + +#define FT5336_P2_XH_REG ((uint8_t)0x09) +#define FT5336_P2_XL_REG ((uint8_t)0x0A) +#define FT5336_P2_YH_REG ((uint8_t)0x0B) +#define FT5336_P2_YL_REG ((uint8_t)0x0C) +#define FT5336_P2_WEIGHT_REG ((uint8_t)0x0D) +#define FT5336_P2_MISC_REG ((uint8_t)0x0E) + +#define FT5336_P3_XH_REG ((uint8_t)0x0F) +#define FT5336_P3_XL_REG ((uint8_t)0x10) +#define FT5336_P3_YH_REG ((uint8_t)0x11) +#define FT5336_P3_YL_REG ((uint8_t)0x12) +#define FT5336_P3_WEIGHT_REG ((uint8_t)0x13) +#define FT5336_P3_MISC_REG ((uint8_t)0x14) + +#define FT5336_P4_XH_REG ((uint8_t)0x15) +#define FT5336_P4_XL_REG ((uint8_t)0x16) +#define FT5336_P4_YH_REG ((uint8_t)0x17) +#define FT5336_P4_YL_REG ((uint8_t)0x18) +#define FT5336_P4_WEIGHT_REG ((uint8_t)0x19) +#define FT5336_P4_MISC_REG ((uint8_t)0x1A) + +#define FT5336_P5_XH_REG ((uint8_t)0x1B) +#define FT5336_P5_XL_REG ((uint8_t)0x1C) +#define FT5336_P5_YH_REG ((uint8_t)0x1D) +#define FT5336_P5_YL_REG ((uint8_t)0x1E) +#define FT5336_P5_WEIGHT_REG ((uint8_t)0x1F) +#define FT5336_P5_MISC_REG ((uint8_t)0x20) + +#define FT5336_P6_XH_REG ((uint8_t)0x21) +#define FT5336_P6_XL_REG ((uint8_t)0x22) +#define FT5336_P6_YH_REG ((uint8_t)0x23) +#define FT5336_P6_YL_REG ((uint8_t)0x24) +#define FT5336_P6_WEIGHT_REG ((uint8_t)0x25) +#define FT5336_P6_MISC_REG ((uint8_t)0x26) + +#define FT5336_P7_XH_REG ((uint8_t)0x27) +#define FT5336_P7_XL_REG ((uint8_t)0x28) +#define FT5336_P7_YH_REG ((uint8_t)0x29) +#define FT5336_P7_YL_REG ((uint8_t)0x2A) +#define FT5336_P7_WEIGHT_REG ((uint8_t)0x2B) +#define FT5336_P7_MISC_REG ((uint8_t)0x2C) + +#define FT5336_P8_XH_REG ((uint8_t)0x2D) +#define FT5336_P8_XL_REG ((uint8_t)0x2E) +#define FT5336_P8_YH_REG ((uint8_t)0x2F) +#define FT5336_P8_YL_REG ((uint8_t)0x30) +#define FT5336_P8_WEIGHT_REG ((uint8_t)0x31) +#define FT5336_P8_MISC_REG ((uint8_t)0x32) + +#define FT5336_P9_XH_REG ((uint8_t)0x33) +#define FT5336_P9_XL_REG ((uint8_t)0x34) +#define FT5336_P9_YH_REG ((uint8_t)0x35) +#define FT5336_P9_YL_REG ((uint8_t)0x36) +#define FT5336_P9_WEIGHT_REG ((uint8_t)0x37) +#define FT5336_P9_MISC_REG ((uint8_t)0x38) + +#define FT5336_P10_XH_REG ((uint8_t)0x39) +#define FT5336_P10_XL_REG ((uint8_t)0x3A) +#define FT5336_P10_YH_REG ((uint8_t)0x3B) +#define FT5336_P10_YL_REG ((uint8_t)0x3C) +#define FT5336_P10_WEIGHT_REG ((uint8_t)0x3D) +#define FT5336_P10_MISC_REG ((uint8_t)0x3E) + + /* Threshold for touch detection */ +#define FT5336_TH_GROUP_REG ((uint8_t)0x80) + + /* Values FT5336_TH_GROUP_REG : threshold related */ +#define FT5336_THRESHOLD_MASK ((uint8_t)0xFF) +#define FT5336_THRESHOLD_SHIFT ((uint8_t)0x00) + + /* Filter function coefficients */ +#define FT5336_TH_DIFF_REG ((uint8_t)0x85) + + /* Control register */ +#define FT5336_CTRL_REG ((uint8_t)0x86) + + /* Values related to FT5336_CTRL_REG */ + + /* Will keep the Active mode when there is no touching */ +#define FT5336_CTRL_KEEP_ACTIVE_MODE ((uint8_t)0x00) + + /* Switching from Active mode to Monitor mode automatically when there is no touching */ +#define FT5336_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE ((uint8_t)0x01 + + /* The time period of switching from Active mode to Monitor mode when there is no touching */ +#define FT5336_TIMEENTERMONITOR_REG ((uint8_t)0x87) + + /* Report rate in Active mode */ +#define FT5336_PERIODACTIVE_REG ((uint8_t)0x88) + + /* Report rate in Monitor mode */ +#define FT5336_PERIODMONITOR_REG ((uint8_t)0x89) + + /* The value of the minimum allowed angle while Rotating gesture mode */ +#define FT5336_RADIAN_VALUE_REG ((uint8_t)0x91) + + /* Maximum offset while Moving Left and Moving Right gesture */ +#define FT5336_OFFSET_LEFT_RIGHT_REG ((uint8_t)0x92) + + /* Maximum offset while Moving Up and Moving Down gesture */ +#define FT5336_OFFSET_UP_DOWN_REG ((uint8_t)0x93) + + /* Minimum distance while Moving Left and Moving Right gesture */ +#define FT5336_DISTANCE_LEFT_RIGHT_REG ((uint8_t)0x94) + + /* Minimum distance while Moving Up and Moving Down gesture */ +#define FT5336_DISTANCE_UP_DOWN_REG ((uint8_t)0x95) + + /* Maximum distance while Zoom In and Zoom Out gesture */ +#define FT5336_DISTANCE_ZOOM_REG ((uint8_t)0x96) + + /* High 8-bit of LIB Version info */ +#define FT5336_LIB_VER_H_REG ((uint8_t)0xA1) + + /* Low 8-bit of LIB Version info */ +#define FT5336_LIB_VER_L_REG ((uint8_t)0xA2) + + /* Chip Selecting */ +#define FT5336_CIPHER_REG ((uint8_t)0xA3) + + /* Interrupt mode register (used when in interrupt mode) */ +#define FT5336_GMODE_REG ((uint8_t)0xA4) + +#define FT5336_G_MODE_INTERRUPT_MASK ((uint8_t)0x03) +#define FT5336_G_MODE_INTERRUPT_SHIFT ((uint8_t)0x00) + + /* Possible values of FT5336_GMODE_REG */ +#define FT5336_G_MODE_INTERRUPT_POLLING ((uint8_t)0x00) +#define FT5336_G_MODE_INTERRUPT_TRIGGER ((uint8_t)0x01) + + /* Current power mode the FT5336 system is in (R) */ +#define FT5336_PWR_MODE_REG ((uint8_t)0xA5) + + /* FT5336 firmware version */ +#define FT5336_FIRMID_REG ((uint8_t)0xA6) + + /* FT5336 Chip identification register */ +#define FT5336_CHIP_ID_REG ((uint8_t)0xA8) + + /* Possible values of FT5336_CHIP_ID_REG */ +#define FT5336_ID_VALUE ((uint8_t)0x51) + + /* Release code version */ +#define FT5336_RELEASE_CODE_ID_REG ((uint8_t)0xAF) + + /* Current operating mode the FT5336 system is in (R) */ +#define FT5336_STATE_REG ((uint8_t)0xBC) + + /** + * @} + */ + + /* Exported macro ------------------------------------------------------------*/ + + /** @defgroup ft5336_Exported_Macros + * @{ + */ + + /* Exported functions --------------------------------------------------------*/ + + /** @defgroup ft5336_Exported_Functions + * @{ + */ + + /** + * @brief ft5336 Control functions + */ + + +/** + * @brief Initialize the ft5336 communication bus + * from MCU to FT5336 : ie I2C channel initialization (if required). + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Init(uint16_t DeviceAddr); + +/** + * @brief Software Reset the ft5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Reset(uint16_t DeviceAddr); + +/** + * @brief Read the ft5336 device ID, pre initialize I2C in case of need to be + * able to read the FT5336 device ID, and verify this is a FT5336. + * @param DeviceAddr: I2C FT5336 Slave address. + * @retval The Device ID (two bytes). + */ +uint16_t ft5336_ReadID(uint16_t DeviceAddr); + +/** + * @brief Configures the touch Screen IC device to start detecting touches + * @param DeviceAddr: Device address on communication Bus (I2C slave address). + * @retval None. + */ +void ft5336_TS_Start(uint16_t DeviceAddr); + +/** + * @brief Return if there is touches detected or not. + * Try to detect new touches and forget the old ones (reset internal global + * variables). + * @param DeviceAddr: Device address on communication Bus. + * @retval : Number of active touches detected (can be 0, 1 or 2). + */ +uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr); + +/** + * @brief Get the touch screen X and Y positions values + * Manage multi touch thanks to touch Index global + * variable 'ft5336_handle.currActiveTouchIdx'. + * @param DeviceAddr: Device address on communication Bus. + * @param X: Pointer to X position value + * @param Y: Pointer to Y position value + * @retval None. + */ +void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y); + +/** + * @brief Configure the FT5336 device to generate IT on given INT pin + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_EnableIT(uint16_t DeviceAddr); + +/** + * @brief Configure the FT5336 device to stop generating IT on the given INT pin + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_DisableIT(uint16_t DeviceAddr); + +/** + * @brief Get IT status from FT5336 interrupt status registers + * Should be called Following an EXTI coming to the MCU to know the detailed + * reason of the interrupt. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval TS interrupts status + */ +uint8_t ft5336_TS_ITStatus (uint16_t DeviceAddr); + +/** + * @brief Clear IT status in FT5336 interrupt status clear registers + * Should be called Following an EXTI coming to the MCU. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval TS interrupts status + */ +void ft5336_TS_ClearIT (uint16_t DeviceAddr); + +/**** NEW FEATURES enabled when Multi-touch support is enabled ****/ + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + +/** + * @brief Get the last touch gesture identification (zoom, move up/down...). + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @param pGestureId : Pointer to get last touch gesture Identification. + * @retval None. + */ +void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId); + +/** + * @brief Get the touch detailed informations on touch number 'touchIdx' (0..1) + * This touch detailed information contains : + * - weight that was applied to this touch + * - sub-area of the touch in the touch panel + * - event of linked to the touch (press down, lift up, ...) + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @param touchIdx : Passed index of the touch (0..1) on which we want to get the + * detailed information. + * @param pWeight : Pointer to to get the weight information of 'touchIdx'. + * @param pArea : Pointer to to get the sub-area information of 'touchIdx'. + * @param pEvent : Pointer to to get the event information of 'touchIdx'. + + * @retval None. + */ +void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr, + uint32_t touchIdx, + uint32_t * pWeight, + uint32_t * pArea, + uint32_t * pEvent); + +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + +/* Imported TS IO functions --------------------------------------------------------*/ + +/** @defgroup ft5336_Imported_Functions + * @{ + */ + +/* TouchScreen (TS) external IO functions */ +extern void TS_IO_Init(void); +extern void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value); +extern uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg); +extern void TS_IO_Delay(uint32_t Delay); + + /** + * @} + */ + + /* Imported global variables --------------------------------------------------------*/ + + /** @defgroup ft5336_Imported_Globals + * @{ + */ + + +/* Touch screen driver structure */ +extern TS_DrvTypeDef ft5336_ts_drv; + + /** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* __FT5336_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..5b92fd6 --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,227 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define LCD_B0_Pin GPIO_PIN_4 +#define LCD_B0_GPIO_Port GPIOE +#define ARDUINO_SCL_D15_Pin GPIO_PIN_8 +#define ARDUINO_SCL_D15_GPIO_Port GPIOB +#define ULPI_D7_Pin GPIO_PIN_5 +#define ULPI_D7_GPIO_Port GPIOB +#define BP2_Pin GPIO_PIN_15 +#define BP2_GPIO_Port GPIOA +#define SWCLK_Pin GPIO_PIN_14 +#define SWCLK_GPIO_Port GPIOA +#define SWDIO_Pin GPIO_PIN_13 +#define SWDIO_GPIO_Port GPIOA +#define LED14_Pin GPIO_PIN_5 +#define LED14_GPIO_Port GPIOE +#define LED15_Pin GPIO_PIN_6 +#define LED15_GPIO_Port GPIOE +#define ARDUINO_SDA_D14_Pin GPIO_PIN_9 +#define ARDUINO_SDA_D14_GPIO_Port GPIOB +#define VCP_RX_Pin GPIO_PIN_7 +#define VCP_RX_GPIO_Port GPIOB +#define LCD_B1_Pin GPIO_PIN_13 +#define LCD_B1_GPIO_Port GPIOJ +#define OTG_FS_VBUS_Pin GPIO_PIN_12 +#define OTG_FS_VBUS_GPIO_Port GPIOJ +#define Audio_INT_Pin GPIO_PIN_6 +#define Audio_INT_GPIO_Port GPIOD +#define NC1_Pin GPIO_PIN_8 +#define NC1_GPIO_Port GPIOI +#define LCD_DE_Pin GPIO_PIN_7 +#define LCD_DE_GPIO_Port GPIOK +#define LCD_B7_Pin GPIO_PIN_6 +#define LCD_B7_GPIO_Port GPIOK +#define LCD_B6_Pin GPIO_PIN_5 +#define LCD_B6_GPIO_Port GPIOK +#define LCD_B4_Pin GPIO_PIN_12 +#define LCD_B4_GPIO_Port GPIOG +#define LCD_B2_Pin GPIO_PIN_14 +#define LCD_B2_GPIO_Port GPIOJ +#define OTG_FS_PowerSwitchOn_Pin GPIO_PIN_5 +#define OTG_FS_PowerSwitchOn_GPIO_Port GPIOD +#define LED16_Pin GPIO_PIN_3 +#define LED16_GPIO_Port GPIOD +#define LED3_Pin GPIO_PIN_3 +#define LED3_GPIO_Port GPIOI +#define uSD_Detect_Pin GPIO_PIN_13 +#define uSD_Detect_GPIO_Port GPIOC +#define LCD_HSYNC_Pin GPIO_PIN_10 +#define LCD_HSYNC_GPIO_Port GPIOI +#define LCD_B5_Pin GPIO_PIN_4 +#define LCD_B5_GPIO_Port GPIOK +#define LCD_BL_CTRL_Pin GPIO_PIN_3 +#define LCD_BL_CTRL_GPIO_Port GPIOK +#define LCD_B3_Pin GPIO_PIN_15 +#define LCD_B3_GPIO_Port GPIOJ +#define OTG_FS_OverCurrent_Pin GPIO_PIN_4 +#define OTG_FS_OverCurrent_GPIO_Port GPIOD +#define TP3_Pin GPIO_PIN_15 +#define TP3_GPIO_Port GPIOH +#define ARDUINO_SCK_D13_Pin GPIO_PIN_1 +#define ARDUINO_SCK_D13_GPIO_Port GPIOI +#define RCC_OSC32_IN_Pin GPIO_PIN_14 +#define RCC_OSC32_IN_GPIO_Port GPIOC +#define LCD_DISP_Pin GPIO_PIN_12 +#define LCD_DISP_GPIO_Port GPIOI +#define LCD_VSYNC_Pin GPIO_PIN_9 +#define LCD_VSYNC_GPIO_Port GPIOI +#define LED13_Pin GPIO_PIN_14 +#define LED13_GPIO_Port GPIOH +#define VCP_TX_Pin GPIO_PIN_9 +#define VCP_TX_GPIO_Port GPIOA +#define RCC_OSC32_OUT_Pin GPIO_PIN_15 +#define RCC_OSC32_OUT_GPIO_Port GPIOC +#define LCD_G6_Pin GPIO_PIN_1 +#define LCD_G6_GPIO_Port GPIOK +#define LCD_G7_Pin GPIO_PIN_2 +#define LCD_G7_GPIO_Port GPIOK +#define BP1_Pin GPIO_PIN_8 +#define BP1_GPIO_Port GPIOA +#define OSC_25M_Pin GPIO_PIN_0 +#define OSC_25M_GPIO_Port GPIOH +#define LCD_INT_Pin GPIO_PIN_13 +#define LCD_INT_GPIO_Port GPIOI +#define LCD_R0_Pin GPIO_PIN_15 +#define LCD_R0_GPIO_Port GPIOI +#define LCD_G4_Pin GPIO_PIN_11 +#define LCD_G4_GPIO_Port GPIOJ +#define LCD_G5_Pin GPIO_PIN_0 +#define LCD_G5_GPIO_Port GPIOK +#define LCD_CLK_Pin GPIO_PIN_14 +#define LCD_CLK_GPIO_Port GPIOI +#define ULPI_NXT_Pin GPIO_PIN_4 +#define ULPI_NXT_GPIO_Port GPIOH +#define LCD_G1_Pin GPIO_PIN_8 +#define LCD_G1_GPIO_Port GPIOJ +#define LCD_G3_Pin GPIO_PIN_10 +#define LCD_G3_GPIO_Port GPIOJ +#define LCD_G0_Pin GPIO_PIN_7 +#define LCD_G0_GPIO_Port GPIOJ +#define LCD_G2_Pin GPIO_PIN_9 +#define LCD_G2_GPIO_Port GPIOJ +#define BP_JOYSTICK_Pin GPIO_PIN_7 +#define BP_JOYSTICK_GPIO_Port GPIOG +#define NC2_Pin GPIO_PIN_2 +#define NC2_GPIO_Port GPIOH +#define LCD_R7_Pin GPIO_PIN_6 +#define LCD_R7_GPIO_Port GPIOJ +#define ULPI_D6_Pin GPIO_PIN_13 +#define ULPI_D6_GPIO_Port GPIOB +#define ULPI_D5_Pin GPIO_PIN_12 +#define ULPI_D5_GPIO_Port GPIOB +#define ULPI_STP_Pin GPIO_PIN_0 +#define ULPI_STP_GPIO_Port GPIOC +#define ULPI_DIR_Pin GPIO_PIN_2 +#define ULPI_DIR_GPIO_Port GPIOC +#define LCD_R5_Pin GPIO_PIN_4 +#define LCD_R5_GPIO_Port GPIOJ +#define EXT_RST_Pin GPIO_PIN_3 +#define EXT_RST_GPIO_Port GPIOG +#define RMII_RXER_Pin GPIO_PIN_2 +#define RMII_RXER_GPIO_Port GPIOG +#define LCD_R6_Pin GPIO_PIN_5 +#define LCD_R6_GPIO_Port GPIOJ +#define LED17_Pin GPIO_PIN_12 +#define LED17_GPIO_Port GPIOH +#define LCD_R4_Pin GPIO_PIN_3 +#define LCD_R4_GPIO_Port GPIOJ +#define LCD_SCL_Pin GPIO_PIN_7 +#define LCD_SCL_GPIO_Port GPIOH +#define LED11_Pin GPIO_PIN_9 +#define LED11_GPIO_Port GPIOH +#define LED12_Pin GPIO_PIN_11 +#define LED12_GPIO_Port GPIOH +#define ULPI_CLK_Pin GPIO_PIN_5 +#define ULPI_CLK_GPIO_Port GPIOA +#define LCD_R3_Pin GPIO_PIN_2 +#define LCD_R3_GPIO_Port GPIOJ +#define LED2_Pin GPIO_PIN_6 +#define LED2_GPIO_Port GPIOH +#define LCD_SDA_Pin GPIO_PIN_8 +#define LCD_SDA_GPIO_Port GPIOH +#define LED18_Pin GPIO_PIN_10 +#define LED18_GPIO_Port GPIOH +#define ULPI_D0_Pin GPIO_PIN_3 +#define ULPI_D0_GPIO_Port GPIOA +#define ULPI_D2_Pin GPIO_PIN_1 +#define ULPI_D2_GPIO_Port GPIOB +#define ULPI_D1_Pin GPIO_PIN_0 +#define ULPI_D1_GPIO_Port GPIOB +#define LCD_R1_Pin GPIO_PIN_0 +#define LCD_R1_GPIO_Port GPIOJ +#define LCD_R2_Pin GPIO_PIN_1 +#define LCD_R2_GPIO_Port GPIOJ +#define ULPI_D4_Pin GPIO_PIN_11 +#define ULPI_D4_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/rk043fn48h.h b/Core/Inc/rk043fn48h.h new file mode 100644 index 0000000..c0fe5a9 --- /dev/null +++ b/Core/Inc/rk043fn48h.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file rk043fn48h.h + * @author MCD Application Team + * @brief This file contains all the constants parameters for the RK043FN48H-CT672B + * LCD component. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RK043FN48H_H +#define __RK043FN48H_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup rk043fn48h + * @{ + */ + +/** @defgroup RK043FN48H_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RK043FN48H_Exported_Constants + * @{ + */ + +/** + * @brief RK043FN48H Size + */ +#define RK043FN48H_WIDTH ((uint16_t)480) /* LCD PIXEL WIDTH */ +#define RK043FN48H_HEIGHT ((uint16_t)272) /* LCD PIXEL HEIGHT */ + +/** + * @brief RK043FN48H Timing + */ +#define RK043FN48H_HSYNC ((uint16_t)41) /* Horizontal synchronization */ +#define RK043FN48H_HBP ((uint16_t)13) /* Horizontal back porch */ +#define RK043FN48H_HFP ((uint16_t)32) /* Horizontal front porch */ +#define RK043FN48H_VSYNC ((uint16_t)10) /* Vertical synchronization */ +#define RK043FN48H_VBP ((uint16_t)2) /* Vertical back porch */ +#define RK043FN48H_VFP ((uint16_t)2) /* Vertical front porch */ + +/** + * @brief RK043FN48H frequency divider + */ +#define RK043FN48H_FREQUENCY_DIVIDER 5 /* LCD Frequency divider */ +/** + * @} + */ + +/** @defgroup RK043FN48H_Exported_Functions + * @{ + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __RK043FN48H_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32746g_discovery.h b/Core/Inc/stm32746g_discovery.h new file mode 100644 index 0000000..2e3ff9d --- /dev/null +++ b/Core/Inc/stm32746g_discovery.h @@ -0,0 +1,339 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery.h + * @author MCD Application Team + * @brief This file contains definitions for STM32746G_DISCOVERY's LEDs, + * push-buttons and COM ports hardware resources. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32746G_DISCOVERY_H +#define __STM32746G_DISCOVERY_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Exported_Types STM32746G_DISCOVERY_LOW_LEVEL Exported Types + * @{ + */ +typedef enum +{ +LED1 = 0, +LED_GREEN = LED1, +}Led_TypeDef; + +typedef enum +{ + BUTTON_WAKEUP = 0, + BUTTON_TAMPER = 1, + BUTTON_KEY = 2 +}Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +}ButtonMode_TypeDef; + +typedef enum +{ + COM1 = 0, + COM2 = 1 +}COM_TypeDef; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Exported_Constants STM32746G_DISCOVERY_LOW_LEVEL Exported Constants + * @{ + */ + +/** + * @brief Define for STM32746G_DISCOVERY board + */ +#if !defined (USE_STM32746G_DISCO) + #define USE_STM32746G_DISCO +#endif + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL_LED + * @{ + */ + +#define LEDn ((uint8_t)1) + +#define LED1_GPIO_PORT GPIOI +#define LED1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define LED1_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() +#define LED1_PIN GPIO_PIN_1 + +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL_BUTTON + * @{ + */ +#define BUTTONn ((uint8_t)3) + +/** + * @brief Wakeup push-button + */ +#define WAKEUP_BUTTON_PIN GPIO_PIN_11 +#define WAKEUP_BUTTON_GPIO_PORT GPIOI +#define WAKEUP_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define WAKEUP_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() +#define WAKEUP_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Tamper push-button + */ +#define TAMPER_BUTTON_PIN GPIO_PIN_11 +#define TAMPER_BUTTON_GPIO_PORT GPIOI +#define TAMPER_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define TAMPER_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() +#define TAMPER_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Key push-button + */ +#define KEY_BUTTON_PIN GPIO_PIN_11 +#define KEY_BUTTON_GPIO_PORT GPIOI +#define KEY_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define KEY_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() +#define KEY_BUTTON_EXTI_IRQn EXTI15_10_IRQn + +#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == 0) WAKEUP_BUTTON_GPIO_CLK_ENABLE(); else\ + if((__INDEX__) == 1) TAMPER_BUTTON_GPIO_CLK_ENABLE(); else\ + KEY_BUTTON_GPIO_CLK_ENABLE(); } while(0) + +#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? WAKEUP_BUTTON_GPIO_CLK_DISABLE() :\ + ((__INDEX__) == 1) ? TAMPER_BUTTON_GPIO_CLK_DISABLE() : KEY_BUTTON_GPIO_CLK_DISABLE()) + +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL_SIGNAL + * @{ + */ +#define SIGNALn ((uint8_t)1) + +/** + * @brief SD-detect signal + */ +#define SD_DETECT_PIN GPIO_PIN_13 +#define SD_DETECT_GPIO_PORT GPIOC +#define SD_DETECT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define SD_DETECT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOC_CLK_DISABLE() +#define SD_DETECT_EXTI_IRQn EXTI15_10_IRQn + +/** + * @brief Touch screen interrupt signal + */ +#define TS_INT_PIN GPIO_PIN_13 +#define TS_INT_GPIO_PORT GPIOI +#define TS_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define TS_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() +#define TS_INT_EXTI_IRQn EXTI15_10_IRQn + +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL_COM + * @{ + */ +#define COMn ((uint8_t)1) + +/** + * @brief Definition for COM port1, connected to USART1 + */ +#define DISCOVERY_COM1 USART1 +#define DISCOVERY_COM1_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() +#define DISCOVERY_COM1_CLK_DISABLE() __HAL_RCC_USART1_CLK_DISABLE() + +#define DISCOVERY_COM1_TX_PIN GPIO_PIN_9 +#define DISCOVERY_COM1_TX_GPIO_PORT GPIOA +#define DISCOVERY_COM1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define DISCOVERY_COM1_TX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() +#define DISCOVERY_COM1_TX_AF GPIO_AF7_USART1 + +#define DISCOVERY_COM1_RX_PIN GPIO_PIN_7 +#define DISCOVERY_COM1_RX_GPIO_PORT GPIOB +#define DISCOVERY_COM1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define DISCOVERY_COM1_RX_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE() +#define DISCOVERY_COM1_RX_AF GPIO_AF7_USART1 + +#define DISCOVERY_COM1_IRQn USART1_IRQn + +#define DISCOVERY_COMx_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == COM1) DISCOVERY_COM1_CLK_ENABLE(); } while(0) +#define DISCOVERY_COMx_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? DISCOVERY_COM1_CLK_DISABLE() : 0) + +#define DISCOVERY_COMx_TX_GPIO_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == COM1) DISCOVERY_COM1_TX_GPIO_CLK_ENABLE(); } while(0) +#define DISCOVERY_COMx_TX_GPIO_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? DISCOVERY_COM1_TX_GPIO_CLK_DISABLE() : 0) + +#define DISCOVERY_COMx_RX_GPIO_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == COM1) DISCOVERY_COM1_RX_GPIO_CLK_ENABLE(); } while(0) +#define DISCOVERY_COMx_RX_GPIO_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? DISCOVERY_COM1_RX_GPIO_CLK_DISABLE() : 0) + +/* Exported constant IO ------------------------------------------------------*/ + +#define LCD_I2C_ADDRESS ((uint16_t)0x70) +#define CAMERA_I2C_ADDRESS ((uint16_t)0x60) +#define AUDIO_I2C_ADDRESS ((uint16_t)0x34) +#define EEPROM_I2C_ADDRESS_A01 ((uint16_t)0xA0) +#define EEPROM_I2C_ADDRESS_A02 ((uint16_t)0xA6) +#define TS_I2C_ADDRESS ((uint16_t)0x70) + +/* I2C clock speed configuration (in Hz) + WARNING: + Make sure that this define is not already declared in other files (ie. + stm32746g_discovery.h file). It can be used in parallel by other modules. */ +#ifndef I2C_SPEED + #define I2C_SPEED ((uint32_t)100000) +#endif /* I2C_SPEED */ + +/* User can use this section to tailor I2Cx/I2Cx instance used and associated + resources */ +/* Definition for AUDIO and LCD I2Cx resources */ +#define DISCOVERY_AUDIO_I2Cx I2C3 +#define DISCOVERY_AUDIO_I2Cx_CLK_ENABLE() __HAL_RCC_I2C3_CLK_ENABLE() +#define DISCOVERY_AUDIO_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() +#define DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE() + +#define DISCOVERY_AUDIO_I2Cx_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET() +#define DISCOVERY_AUDIO_I2Cx_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET() + +/* Definition for I2Cx Pins */ +#define DISCOVERY_AUDIO_I2Cx_SCL_PIN GPIO_PIN_7 +#define DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT GPIOH +#define DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF GPIO_AF4_I2C3 +#define DISCOVERY_AUDIO_I2Cx_SDA_PIN GPIO_PIN_8 + +/* I2C interrupt requests */ +#define DISCOVERY_AUDIO_I2Cx_EV_IRQn I2C3_EV_IRQn +#define DISCOVERY_AUDIO_I2Cx_ER_IRQn I2C3_ER_IRQn + +/* Definition for external, camera and Arduino connector I2Cx resources */ +#define DISCOVERY_EXT_I2Cx I2C1 +#define DISCOVERY_EXT_I2Cx_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE() +#define DISCOVERY_EXT_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE() +#define DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() + +#define DISCOVERY_EXT_I2Cx_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET() +#define DISCOVERY_EXT_I2Cx_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET() + +/* Definition for I2Cx Pins */ +#define DISCOVERY_EXT_I2Cx_SCL_PIN GPIO_PIN_8 +#define DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT GPIOB +#define DISCOVERY_EXT_I2Cx_SCL_SDA_AF GPIO_AF4_I2C1 +#define DISCOVERY_EXT_I2Cx_SDA_PIN GPIO_PIN_9 + +/* I2C interrupt requests */ +#define DISCOVERY_EXT_I2Cx_EV_IRQn I2C1_EV_IRQn +#define DISCOVERY_EXT_I2Cx_ER_IRQn I2C1_ER_IRQn + +/* I2C TIMING Register define when I2C clock source is SYSCLK */ +/* I2C TIMING is calculated from APB1 source clock = 50 MHz */ +/* Due to the big MOFSET capacity for adapting the camera level the rising time is very large (>1us) */ +/* 0x40912732 takes in account the big rising and aims a clock of 100khz */ +#ifndef DISCOVERY_I2Cx_TIMING +#define DISCOVERY_I2Cx_TIMING ((uint32_t)0x40912732) +#endif /* DISCOVERY_I2Cx_TIMING */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Exported_Macros STM32746G_DISCOVERY_LOW_LEVEL Exported Macros + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_LOW_LEVEL_Exported_Functions + * @{ + */ +uint32_t BSP_GetVersion(void); +void BSP_LED_Init(Led_TypeDef Led); +void BSP_LED_DeInit(Led_TypeDef Led); +void BSP_LED_On(Led_TypeDef Led); +void BSP_LED_Off(Led_TypeDef Led); +void BSP_LED_Toggle(Led_TypeDef Led); +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +void BSP_PB_DeInit(Button_TypeDef Button); +uint32_t BSP_PB_GetState(Button_TypeDef Button); +void BSP_COM_Init(COM_TypeDef COM, UART_HandleTypeDef *husart); +void BSP_COM_DeInit(COM_TypeDef COM, UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32746g_discovery_lcd.h b/Core/Inc/stm32746g_discovery_lcd.h new file mode 100644 index 0000000..b09cc8a --- /dev/null +++ b/Core/Inc/stm32746g_discovery_lcd.h @@ -0,0 +1,267 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_lcd.h + * @author MCD Application Team + * @brief This file contains the common defines and functions prototypes for + * the stm32746g_discovery_lcd.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32746G_DISCOVERY_LCD_H +#define __STM32746G_DISCOVERY_LCD_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Include LCD component Driver */ +/* LCD RK043FN48H-CT672B 4,3" 480x272 pixels */ +#include "rk043fn48h.h" + +/* Include SDRAM Driver */ +#include "stm32746g_discovery_sdram.h" + +#include "stm32746g_discovery.h" +#include "../../Fonts/fonts.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_LCD + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Exported_Types STM32746G_DISCOVERY_LCD Exported Types + * @{ + */ +typedef struct +{ + uint32_t TextColor; + uint32_t BackColor; + sFONT *pFont; +}LCD_DrawPropTypeDef; + +typedef struct +{ + int16_t X; + int16_t Y; +}Point, * pPoint; + +/** + * @brief Line mode structures definition + */ +typedef enum +{ + CENTER_MODE = 0x01, /* Center mode */ + RIGHT_MODE = 0x02, /* Right mode */ + LEFT_MODE = 0x03 /* Left mode */ +}Text_AlignModeTypdef; + +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Exported_Constants STM32746G_DISCOVERY_LCD Exported Constants + * @{ + */ +#define MAX_LAYER_NUMBER ((uint32_t)2) + +#define LCD_LayerCfgTypeDef LTDC_LayerCfgTypeDef + +#define LTDC_ACTIVE_LAYER ((uint32_t)1) /* Layer 1 */ +/** + * @brief LCD status structure definition + */ +#define LCD_OK ((uint8_t)0x00) +#define LCD_ERROR ((uint8_t)0x01) +#define LCD_TIMEOUT ((uint8_t)0x02) + +/** + * @brief LCD FB_StartAddress + */ +#define LCD_FB_START_ADDRESS ((uint32_t)0xC0000000) + +/** + * @brief LCD color + */ +#define LCD_COLOR_BLUE ((uint32_t)0xFF0000FF) +#define LCD_COLOR_GREEN ((uint32_t)0xFF00FF00) +#define LCD_COLOR_RED ((uint32_t)0xFFFF0000) +#define LCD_COLOR_CYAN ((uint32_t)0xFF00FFFF) +#define LCD_COLOR_MAGENTA ((uint32_t)0xFFFF00FF) +#define LCD_COLOR_YELLOW ((uint32_t)0xFFFFFF00) +#define LCD_COLOR_LIGHTBLUE ((uint32_t)0xFF8080FF) +#define LCD_COLOR_LIGHTGREEN ((uint32_t)0xFF80FF80) +#define LCD_COLOR_LIGHTRED ((uint32_t)0xFFFF8080) +#define LCD_COLOR_LIGHTCYAN ((uint32_t)0xFF80FFFF) +#define LCD_COLOR_LIGHTMAGENTA ((uint32_t)0xFFFF80FF) +#define LCD_COLOR_LIGHTYELLOW ((uint32_t)0xFFFFFF80) +#define LCD_COLOR_DARKBLUE ((uint32_t)0xFF000080) +#define LCD_COLOR_DARKGREEN ((uint32_t)0xFF008000) +#define LCD_COLOR_DARKRED ((uint32_t)0xFF800000) +#define LCD_COLOR_DARKCYAN ((uint32_t)0xFF008080) +#define LCD_COLOR_DARKMAGENTA ((uint32_t)0xFF800080) +#define LCD_COLOR_DARKYELLOW ((uint32_t)0xFF808000) +#define LCD_COLOR_WHITE ((uint32_t)0xFFFFFFFF) +#define LCD_COLOR_LIGHTGRAY ((uint32_t)0xFFD3D3D3) +#define LCD_COLOR_GRAY ((uint32_t)0xFF808080) +#define LCD_COLOR_DARKGRAY ((uint32_t)0xFF404040) +#define LCD_COLOR_BLACK ((uint32_t)0xFF000000) +#define LCD_COLOR_BROWN ((uint32_t)0xFFA52A2A) +#define LCD_COLOR_ORANGE ((uint32_t)0xFFFFA500) +#define LCD_COLOR_TRANSPARENT ((uint32_t)0xFF000000) + +/** + * @brief LCD default font + */ +#define LCD_DEFAULT_FONT Font24 + +/** + * @brief LCD Reload Types + */ +#define LCD_RELOAD_IMMEDIATE ((uint32_t)LTDC_SRCR_IMR) +#define LCD_RELOAD_VERTICAL_BLANKING ((uint32_t)LTDC_SRCR_VBR) + + +/** + * @brief LCD special pins + */ +/* Display enable pin */ +#define LCD_DISP_PIN GPIO_PIN_12 +#define LCD_DISP_GPIO_PORT GPIOI +#define LCD_DISP_GPIO_CLK_ENABLE() __HAL_RCC_GPIOI_CLK_ENABLE() +#define LCD_DISP_GPIO_CLK_DISABLE() __HAL_RCC_GPIOI_CLK_DISABLE() + +/* Backlight control pin */ +#define LCD_BL_CTRL_PIN GPIO_PIN_3 +#define LCD_BL_CTRL_GPIO_PORT GPIOK +#define LCD_BL_CTRL_GPIO_CLK_ENABLE() __HAL_RCC_GPIOK_CLK_ENABLE() +#define LCD_BL_CTRL_GPIO_CLK_DISABLE() __HAL_RCC_GPIOK_CLK_DISABLE() + +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_LCD_Exported_Functions + * @{ + */ +uint8_t BSP_LCD_Init(void); +uint8_t BSP_LCD_DeInit(void); +uint32_t BSP_LCD_GetXSize(void); +uint32_t BSP_LCD_GetYSize(void); +void BSP_LCD_SetXSize(uint32_t imageWidthPixels); +void BSP_LCD_SetYSize(uint32_t imageHeightPixels); + +/* Functions using the LTDC controller */ +void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FrameBuffer); +void BSP_LCD_LayerRgb565Init(uint16_t LayerIndex, uint32_t FB_Address); +void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency); +void BSP_LCD_SetTransparency_NoReload(uint32_t LayerIndex, uint8_t Transparency); +void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address); +void BSP_LCD_SetLayerAddress_NoReload(uint32_t LayerIndex, uint32_t Address); +void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue); +void BSP_LCD_SetColorKeying_NoReload(uint32_t LayerIndex, uint32_t RGBValue); +void BSP_LCD_ResetColorKeying(uint32_t LayerIndex); +void BSP_LCD_ResetColorKeying_NoReload(uint32_t LayerIndex); +void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void BSP_LCD_SetLayerWindow_NoReload(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void BSP_LCD_SelectLayer(uint32_t LayerIndex); +void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State); +void BSP_LCD_SetLayerVisible_NoReload(uint32_t LayerIndex, FunctionalState State); +void BSP_LCD_Reload(uint32_t ReloadType); + +void BSP_LCD_SetTextColor(uint32_t Color); +uint32_t BSP_LCD_GetTextColor(void); +void BSP_LCD_SetBackColor(uint32_t Color); +uint32_t BSP_LCD_GetBackColor(void); +void BSP_LCD_SetFont(sFONT *fonts); +sFONT *BSP_LCD_GetFont(void); + +uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos); +void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t pixel); +void BSP_LCD_Clear(uint32_t Color); +void BSP_LCD_ClearStringLine(uint32_t Line); +void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr); +void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode); +void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii); + +void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length); +void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length); +void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); +void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); +void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount); +void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius); +void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp); + +void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height); +void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius); +void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount); +void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius); + +void BSP_LCD_DisplayOff(void); +void BSP_LCD_DisplayOn(void); + +/* These functions can be modified in case the current settings + need to be changed for specific application needs */ +void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params); +void BSP_LCD_MspDeInit(LTDC_HandleTypeDef *hltdc, void *Params); +void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_LCD_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32746g_discovery_sdram.h b/Core/Inc/stm32746g_discovery_sdram.h new file mode 100644 index 0000000..46bd76b --- /dev/null +++ b/Core/Inc/stm32746g_discovery_sdram.h @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.h + * @author MCD Application Team + * @brief This file contains the common defines and functions prototypes for + * the stm32746g_discovery_sdram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32746G_DISCOVERY_SDRAM_H +#define __STM32746G_DISCOVERY_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types + * @{ + */ + +/** + * @brief SDRAM status structure definition + */ +#define SDRAM_OK ((uint8_t)0x00) +#define SDRAM_ERROR ((uint8_t)0x01) + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants + * @{ + */ +#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) +#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ + +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 + +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ + +#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ + +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +/* DMA definitions for SDRAM DMA transfer */ +#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 +#define SDRAM_DMAx_STREAM DMA2_Stream0 +#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn +#define BSP_SDRAM_DMA_IRQHandler DMA2_Stream0_IRQHandler +/** + * @} + */ + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions + * @{ + */ +uint8_t BSP_SDRAM_Init(void); +uint8_t BSP_SDRAM_DeInit(void); +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); + +/* These functions can be modified in case the current settings (e.g. DMA stream) + need to be changed for specific application needs */ +void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); +void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_SDRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32746g_discovery_ts.h b/Core/Inc/stm32746g_discovery_ts.h new file mode 100644 index 0000000..b35b794 --- /dev/null +++ b/Core/Inc/stm32746g_discovery_ts.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_ts.h + * @author MCD Application Team + * @brief This file contains the common defines and functions prototypes for + * the stm32746g_discovery_ts.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32746G_DISCOVERY_TS_H +#define __STM32746G_DISCOVERY_TS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery.h" +/* Include touch screen FT5336 component Driver */ +#include "ft5336.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_TS + * @{ + */ + + /** @defgroup STM32746G_DISCOVERY_TS_Exported_Constants STM32746G_DISCOVERY_TS Exported Constants + * @{ + */ + +/** @brief With FT5336 : maximum 5 touches detected simultaneously + */ +#define TS_MAX_NB_TOUCH ((uint32_t) FT5336_MAX_DETECTABLE_TOUCH) + +#define TS_NO_IRQ_PENDING ((uint8_t) 0) +#define TS_IRQ_PENDING ((uint8_t) 1) + +#define TS_SWAP_NONE ((uint8_t) 0x01) +#define TS_SWAP_X ((uint8_t) 0x02) +#define TS_SWAP_Y ((uint8_t) 0x04) +#define TS_SWAP_XY ((uint8_t) 0x08) + +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Exported_Types STM32746G_DISCOVERY_TS Exported Types + * @{ + */ +/** +* @brief TS_StateTypeDef +* Define TS State structure +*/ +typedef struct +{ + uint8_t touchDetected; /*!< Total number of active touches detected at last scan */ + uint16_t touchX[TS_MAX_NB_TOUCH]; /*!< Touch X[0], X[1] coordinates on 12 bits */ + uint16_t touchY[TS_MAX_NB_TOUCH]; /*!< Touch Y[0], Y[1] coordinates on 12 bits */ + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + uint8_t touchWeight[TS_MAX_NB_TOUCH]; /*!< Touch_Weight[0], Touch_Weight[1] : weight property of touches */ + uint8_t touchEventId[TS_MAX_NB_TOUCH]; /*!< Touch_EventId[0], Touch_EventId[1] : take value of type @ref TS_TouchEventTypeDef */ + uint8_t touchArea[TS_MAX_NB_TOUCH]; /*!< Touch_Area[0], Touch_Area[1] : touch area of each touch */ + uint32_t gestureId; /*!< type of gesture detected : take value of type @ref TS_GestureIdTypeDef */ +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + +} TS_StateTypeDef; + +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Exported_Constants STM32746G_DISCOVERY_TS Exported Constants + * @{ + */ + +typedef enum +{ + TS_OK = 0x00, /*!< Touch Ok */ + TS_ERROR = 0x01, /*!< Touch Error */ + TS_TIMEOUT = 0x02, /*!< Touch Timeout */ + TS_DEVICE_NOT_FOUND = 0x03 /*!< Touchscreen device not found */ +}TS_StatusTypeDef; + +/** + * @brief TS_GestureIdTypeDef + * Define Possible managed gesture identification values returned by touch screen + * driver. + */ +typedef enum +{ + GEST_ID_NO_GESTURE = 0x00, /*!< Gesture not defined / recognized */ + GEST_ID_MOVE_UP = 0x01, /*!< Gesture Move Up */ + GEST_ID_MOVE_RIGHT = 0x02, /*!< Gesture Move Right */ + GEST_ID_MOVE_DOWN = 0x03, /*!< Gesture Move Down */ + GEST_ID_MOVE_LEFT = 0x04, /*!< Gesture Move Left */ + GEST_ID_ZOOM_IN = 0x05, /*!< Gesture Zoom In */ + GEST_ID_ZOOM_OUT = 0x06, /*!< Gesture Zoom Out */ + GEST_ID_NB_MAX = 0x07 /*!< max number of gesture id */ + +} TS_GestureIdTypeDef; + +/** + * @brief TS_TouchEventTypeDef + * Define Possible touch events kind as returned values + * by touch screen IC Driver. + */ +typedef enum +{ + TOUCH_EVENT_NO_EVT = 0x00, /*!< Touch Event : undetermined */ + TOUCH_EVENT_PRESS_DOWN = 0x01, /*!< Touch Event Press Down */ + TOUCH_EVENT_LIFT_UP = 0x02, /*!< Touch Event Lift Up */ + TOUCH_EVENT_CONTACT = 0x03, /*!< Touch Event Contact */ + TOUCH_EVENT_NB_MAX = 0x04 /*!< max number of touch events kind */ + +} TS_TouchEventTypeDef; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Imported_Variables STM32746G_DISCOVERY_TS Imported Variables + * @{ + */ +/** + * @brief Table for touchscreen event information display on LCD : + * table indexed on enum @ref TS_TouchEventTypeDef information + */ +extern char * ts_event_string_tab[TOUCH_EVENT_NB_MAX]; + +/** + * @brief Table for touchscreen gesture Id information display on LCD : table indexed + * on enum @ref TS_GestureIdTypeDef information + */ +extern char * ts_gesture_id_string_tab[GEST_ID_NB_MAX]; +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_TS_Exported_Functions + * @{ + */ +uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY); +uint8_t BSP_TS_DeInit(void); +uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State); + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) +uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State); +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + +uint8_t BSP_TS_ITConfig(void); +uint8_t BSP_TS_ITGetStatus(void); +void BSP_TS_ITClear(void); +uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_TS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32f7xx_hal_conf.h b/Core/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 0000000..ec035c0 --- /dev/null +++ b/Core/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,480 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + #define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA2D_MODULE_ENABLED +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_LTDC_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/stm32f7xx_it.h b/Core/Inc/stm32f7xx_it.h new file mode 100644 index 0000000..a002466 --- /dev/null +++ b/Core/Inc/stm32f7xx_it.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void TIM6_DAC_IRQHandler(void); +void LTDC_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Inc/ts.h b/Core/Inc/ts.h new file mode 100644 index 0000000..bef7119 --- /dev/null +++ b/Core/Inc/ts.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file ts.h + * @author MCD Application Team + * @version V4.0.1 + * @date 21-July-2015 + * @brief This file contains all the functions prototypes for the Touch Screen driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TS_H +#define __TS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TS + * @{ + */ + +/** @defgroup TS_Exported_Types + * @{ + */ + +/** @defgroup TS_Driver_structure Touch Sensor Driver structure + * @{ + */ +typedef struct +{ + void (*Init)(uint16_t); + uint16_t (*ReadID)(uint16_t); + void (*Reset)(uint16_t); + void (*Start)(uint16_t); + uint8_t (*DetectTouch)(uint16_t); + void (*GetXY)(uint16_t, uint16_t*, uint16_t*); + void (*EnableIT)(uint16_t); + void (*ClearIT)(uint16_t); + uint8_t (*GetITStatus)(uint16_t); + void (*DisableIT)(uint16_t); +}TS_DrvTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c new file mode 100644 index 0000000..c04786e --- /dev/null +++ b/Core/Src/freertos.c @@ -0,0 +1,122 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : freertos.c + * Description : Code for freertos applications + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN Variables */ + +/* USER CODE END Variables */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN FunctionPrototypes */ + +/* USER CODE END FunctionPrototypes */ + +/* GetIdleTaskMemory prototype (linked to static allocation support) */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); + +/* Hook prototypes */ +void vApplicationIdleHook(void); +void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); +void vApplicationMallocFailedHook(void); + +/* USER CODE BEGIN 2 */ +__weak void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/* USER CODE END 2 */ + +/* USER CODE BEGIN 4 */ +__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) +{ + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is + called if a stack overflow is detected. */ +} +/* USER CODE END 4 */ + +/* USER CODE BEGIN 5 */ +__weak void vApplicationMallocFailedHook(void) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ +} +/* USER CODE END 5 */ + +/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ +static StaticTask_t xIdleTaskTCBBuffer; +static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; + +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer; + *ppxIdleTaskStackBuffer = &xIdleStack[0]; + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; + /* place for user code */ +} +/* USER CODE END GET_IDLE_TASK_MEMORY */ + +/* Private application code --------------------------------------------------*/ +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/ft5336.c b/Core/Src/ft5336.c new file mode 100644 index 0000000..64f7016 --- /dev/null +++ b/Core/Src/ft5336.c @@ -0,0 +1,625 @@ +/** + ****************************************************************************** + * @file ft5336.c + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file provides a set of functions needed to manage the FT5336 + * touch screen devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft5336.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup FT5336 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ + +/** @defgroup FT5336_Private_Types_Definitions + * @{ + */ + +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FT5336_Private_Defines + * @{ + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup FT5336_Private_Macros + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup FT5336_Private_Variables + * @{ + */ + +/* Touch screen driver structure initialization */ +TS_DrvTypeDef ft5336_ts_drv = +{ + ft5336_Init, + ft5336_ReadID, + ft5336_Reset, + + ft5336_TS_Start, + ft5336_TS_DetectTouch, + ft5336_TS_GetXY, + + ft5336_TS_EnableIT, + ft5336_TS_ClearIT, + ft5336_TS_ITStatus, + ft5336_TS_DisableIT + +}; + +/* Global ft5336 handle */ +static ft5336_handle_TypeDef ft5336_handle = { FT5336_I2C_NOT_INITIALIZED, 0, 0}; + +/** + * @} + */ + +/** @defgroup ft5336_Private_Function_Prototypes + * @{ + */ + +/* Private functions prototypes-----------------------------------------------*/ + +/** + * @brief Return the status of I2C was initialized or not. + * @param None. + * @retval : I2C initialization status. + */ +static uint8_t ft5336_Get_I2C_InitializedStatus(void); + +/** + * @brief I2C initialize if needed. + * @param None. + * @retval : None. + */ +static void ft5336_I2C_InitializeIfRequired(void); + +/** + * @brief Basic static configuration of TouchScreen + * @param DeviceAddr: FT5336 Device address for communication on I2C Bus. + * @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK. + */ +static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr); + +/** @defgroup ft5336_Private_Functions + * @{ + */ + +/** @defgroup ft5336_Public_Function_Body + * @{ + */ + +/* Public functions bodies-----------------------------------------------*/ + + +/** + * @brief Initialize the ft5336 communication bus + * from MCU to FT5336 : ie I2C channel initialization (if required). + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Init(uint16_t DeviceAddr) +{ + /* Wait at least 200ms after power up before accessing registers + * Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */ + TS_IO_Delay(200); + + /* Initialize I2C link if needed */ + ft5336_I2C_InitializeIfRequired(); +} + +/** + * @brief Software Reset the ft5336. + * @note : Not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Reset(uint16_t DeviceAddr) +{ + /* Do nothing */ + /* No software reset sequence available in FT5336 IC */ +} + +/** + * @brief Read the ft5336 device ID, pre initialize I2C in case of need to be + * able to read the FT5336 device ID, and verify this is a FT5336. + * @param DeviceAddr: I2C FT5336 Slave address. + * @retval The Device ID (two bytes). + */ +uint16_t ft5336_ReadID(uint16_t DeviceAddr) +{ + volatile uint8_t ucReadId = 0; + uint8_t nbReadAttempts = 0; + uint8_t bFoundDevice = 0; /* Device not found by default */ + + /* Initialize I2C link if needed */ + ft5336_I2C_InitializeIfRequired(); + + /* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */ + for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++) + { + /* Read register FT5336_CHIP_ID_REG as DeviceID detection */ + ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG); + + /* Found the searched device ID ? */ + if(ucReadId == FT5336_ID_VALUE) + { + /* Set device as found */ + bFoundDevice = 1; + } + } + + /* Return the device ID value */ + return (ucReadId); +} + +/** + * @brief Configures the touch Screen IC device to start detecting touches + * @param DeviceAddr: Device address on communication Bus (I2C slave address). + * @retval None. + */ +void ft5336_TS_Start(uint16_t DeviceAddr) +{ + /* Minimum static configuration of FT5336 */ + FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr)); + + /* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */ + /* Note TS_INT is active low */ + ft5336_TS_DisableIT(DeviceAddr); +} + +/** + * @brief Return if there is touches detected or not. + * Try to detect new touches and forget the old ones (reset internal global + * variables). + * @param DeviceAddr: Device address on communication Bus. + * @retval : Number of active touches detected (can be 0, 1 or 2). + */ +uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr) +{ + volatile uint8_t nbTouch = 0; + + /* Read register FT5336_TD_STAT_REG to check number of touches detection */ + nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG); + nbTouch &= FT5336_TD_STAT_MASK; + + if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH) + { + /* If invalid number of touch detected, set it to zero */ + nbTouch = 0; + } + + /* Update ft5336 driver internal global : current number of active touches */ + ft5336_handle.currActiveTouchNb = nbTouch; + + /* Reset current active touch index on which to work on */ + ft5336_handle.currActiveTouchIdx = 0; + + return(nbTouch); +} + +/** + * @brief Get the touch screen X and Y positions values + * Manage multi touch thanks to touch Index global + * variable 'ft5336_handle.currActiveTouchIdx'. + * @param DeviceAddr: Device address on communication Bus. + * @param X: Pointer to X position value + * @param Y: Pointer to Y position value + * @retval None. + */ +void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y) +{ + volatile uint8_t ucReadData = 0; + static uint16_t coord; + uint8_t regAddressXLow = 0; + uint8_t regAddressXHigh = 0; + uint8_t regAddressYLow = 0; + uint8_t regAddressYHigh = 0; + + if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) + { + switch(ft5336_handle.currActiveTouchIdx) + { + case 0 : + regAddressXLow = FT5336_P1_XL_REG; + regAddressXHigh = FT5336_P1_XH_REG; + regAddressYLow = FT5336_P1_YL_REG; + regAddressYHigh = FT5336_P1_YH_REG; + break; + + case 1 : + regAddressXLow = FT5336_P2_XL_REG; + regAddressXHigh = FT5336_P2_XH_REG; + regAddressYLow = FT5336_P2_YL_REG; + regAddressYHigh = FT5336_P2_YH_REG; + break; + + case 2 : + regAddressXLow = FT5336_P3_XL_REG; + regAddressXHigh = FT5336_P3_XH_REG; + regAddressYLow = FT5336_P3_YL_REG; + regAddressYHigh = FT5336_P3_YH_REG; + break; + + case 3 : + regAddressXLow = FT5336_P4_XL_REG; + regAddressXHigh = FT5336_P4_XH_REG; + regAddressYLow = FT5336_P4_YL_REG; + regAddressYHigh = FT5336_P4_YH_REG; + break; + + case 4 : + regAddressXLow = FT5336_P5_XL_REG; + regAddressXHigh = FT5336_P5_XH_REG; + regAddressYLow = FT5336_P5_YL_REG; + regAddressYHigh = FT5336_P5_YH_REG; + break; + + case 5 : + regAddressXLow = FT5336_P6_XL_REG; + regAddressXHigh = FT5336_P6_XH_REG; + regAddressYLow = FT5336_P6_YL_REG; + regAddressYHigh = FT5336_P6_YH_REG; + break; + + case 6 : + regAddressXLow = FT5336_P7_XL_REG; + regAddressXHigh = FT5336_P7_XH_REG; + regAddressYLow = FT5336_P7_YL_REG; + regAddressYHigh = FT5336_P7_YH_REG; + break; + + case 7 : + regAddressXLow = FT5336_P8_XL_REG; + regAddressXHigh = FT5336_P8_XH_REG; + regAddressYLow = FT5336_P8_YL_REG; + regAddressYHigh = FT5336_P8_YH_REG; + break; + + case 8 : + regAddressXLow = FT5336_P9_XL_REG; + regAddressXHigh = FT5336_P9_XH_REG; + regAddressYLow = FT5336_P9_YL_REG; + regAddressYHigh = FT5336_P9_YH_REG; + break; + + case 9 : + regAddressXLow = FT5336_P10_XL_REG; + regAddressXHigh = FT5336_P10_XH_REG; + regAddressYLow = FT5336_P10_YL_REG; + regAddressYHigh = FT5336_P10_YH_REG; + break; + + default : + break; + + } /* end switch(ft5336_handle.currActiveTouchIdx) */ + + /* Read low part of X position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow); + coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT; + + /* Read high part of X position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh); + coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8; + + /* Send back ready X position to caller */ + *X = coord; + + /* Read low part of Y position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow); + coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT; + + /* Read high part of Y position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh); + coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8; + + /* Send back ready Y position to caller */ + *Y = coord; + + ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */ + + } /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */ +} + +/** + * @brief Configure the FT5336 device to generate IT on given INT pin + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_EnableIT(uint16_t DeviceAddr) +{ + uint8_t regValue = 0; + regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT; + + /* Set interrupt trigger mode in FT5336_GMODE_REG */ + TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue); +} + +/** + * @brief Configure the FT5336 device to stop generating IT on the given INT pin + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_DisableIT(uint16_t DeviceAddr) +{ + uint8_t regValue = 0; + regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT; + + /* Set interrupt polling mode in FT5336_GMODE_REG */ + TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue); +} + +/** + * @brief Get IT status from FT5336 interrupt status registers + * Should be called Following an EXTI coming to the MCU to know the detailed + * reason of the interrupt. + * @note : This feature is not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval TS interrupts status : always return 0 here + */ +uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr) +{ + /* Always return 0 as feature not applicable to FT5336 */ + return 0; +} + +/** + * @brief Clear IT status in FT5336 interrupt status clear registers + * Should be called Following an EXTI coming to the MCU. + * @note : This feature is not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_TS_ClearIT(uint16_t DeviceAddr) +{ + /* Nothing to be done here for FT5336 */ +} + +/**** NEW FEATURES enabled when Multi-touch support is enabled ****/ + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + +/** + * @brief Get the last touch gesture identification (zoom, move up/down...). + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @param pGestureId : Pointer to get last touch gesture Identification. + * @retval None. + */ +void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId) +{ + volatile uint8_t ucReadData = 0; + + ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG); + + * pGestureId = ucReadData; +} + +/** + * @brief Get the touch detailed informations on touch number 'touchIdx' (0..1) + * This touch detailed information contains : + * - weight that was applied to this touch + * - sub-area of the touch in the touch panel + * - event of linked to the touch (press down, lift up, ...) + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @param touchIdx : Passed index of the touch (0..1) on which we want to get the + * detailed information. + * @param pWeight : Pointer to to get the weight information of 'touchIdx'. + * @param pArea : Pointer to to get the sub-area information of 'touchIdx'. + * @param pEvent : Pointer to to get the event information of 'touchIdx'. + + * @retval None. + */ +void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr, + uint32_t touchIdx, + uint32_t * pWeight, + uint32_t * pArea, + uint32_t * pEvent) +{ + volatile uint8_t ucReadData = 0; + uint8_t regAddressXHigh = 0; + uint8_t regAddressPWeight = 0; + uint8_t regAddressPMisc = 0; + + if(touchIdx < ft5336_handle.currActiveTouchNb) + { + switch(touchIdx) + { + case 0 : + regAddressXHigh = FT5336_P1_XH_REG; + regAddressPWeight = FT5336_P1_WEIGHT_REG; + regAddressPMisc = FT5336_P1_MISC_REG; + break; + + case 1 : + regAddressXHigh = FT5336_P2_XH_REG; + regAddressPWeight = FT5336_P2_WEIGHT_REG; + regAddressPMisc = FT5336_P2_MISC_REG; + break; + + case 2 : + regAddressXHigh = FT5336_P3_XH_REG; + regAddressPWeight = FT5336_P3_WEIGHT_REG; + regAddressPMisc = FT5336_P3_MISC_REG; + break; + + case 3 : + regAddressXHigh = FT5336_P4_XH_REG; + regAddressPWeight = FT5336_P4_WEIGHT_REG; + regAddressPMisc = FT5336_P4_MISC_REG; + break; + + case 4 : + regAddressXHigh = FT5336_P5_XH_REG; + regAddressPWeight = FT5336_P5_WEIGHT_REG; + regAddressPMisc = FT5336_P5_MISC_REG; + break; + + case 5 : + regAddressXHigh = FT5336_P6_XH_REG; + regAddressPWeight = FT5336_P6_WEIGHT_REG; + regAddressPMisc = FT5336_P6_MISC_REG; + break; + + case 6 : + regAddressXHigh = FT5336_P7_XH_REG; + regAddressPWeight = FT5336_P7_WEIGHT_REG; + regAddressPMisc = FT5336_P7_MISC_REG; + break; + + case 7 : + regAddressXHigh = FT5336_P8_XH_REG; + regAddressPWeight = FT5336_P8_WEIGHT_REG; + regAddressPMisc = FT5336_P8_MISC_REG; + break; + + case 8 : + regAddressXHigh = FT5336_P9_XH_REG; + regAddressPWeight = FT5336_P9_WEIGHT_REG; + regAddressPMisc = FT5336_P9_MISC_REG; + break; + + case 9 : + regAddressXHigh = FT5336_P10_XH_REG; + regAddressPWeight = FT5336_P10_WEIGHT_REG; + regAddressPMisc = FT5336_P10_MISC_REG; + break; + + default : + break; + + } /* end switch(touchIdx) */ + + /* Read Event Id of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh); + * pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT; + + /* Read weight of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight); + * pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT; + + /* Read area of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc); + * pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT; + + } /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */ +} + +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + +/** @defgroup ft5336_Static_Function_Body + * @{ + */ + +/* Static functions bodies-----------------------------------------------*/ + + +/** + * @brief Return the status of I2C was initialized or not. + * @param None. + * @retval : I2C initialization status. + */ +static uint8_t ft5336_Get_I2C_InitializedStatus(void) +{ + return(ft5336_handle.i2cInitialized); +} + +/** + * @brief I2C initialize if needed. + * @param None. + * @retval : None. + */ +static void ft5336_I2C_InitializeIfRequired(void) +{ + if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED) + { + /* Initialize TS IO BUS layer (I2C) */ + TS_IO_Init(); + + /* Set state to initialized */ + ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED; + } +} + +/** + * @brief Basic static configuration of TouchScreen + * @param DeviceAddr: FT5336 Device address for communication on I2C Bus. + * @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK. + */ +static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr) +{ + uint32_t status = FT5336_STATUS_OK; + + /* Nothing special to be done for FT5336 */ + + return(status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..60e7937 --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,1480 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "stm32746g_discovery_lcd.h" +#include "stm32746g_discovery_ts.h" +#include "stdio.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; +ADC_HandleTypeDef hadc3; + +DAC_HandleTypeDef hdac; + +DMA2D_HandleTypeDef hdma2d; + +I2C_HandleTypeDef hi2c1; +I2C_HandleTypeDef hi2c3; + +LTDC_HandleTypeDef hltdc; + +RTC_HandleTypeDef hrtc; + +SPI_HandleTypeDef hspi2; + +TIM_HandleTypeDef htim1; +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim5; +TIM_HandleTypeDef htim8; + +UART_HandleTypeDef huart7; +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart6; + +SDRAM_HandleTypeDef hsdram1; + +osThreadId defaultTaskHandle; +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_ADC3_Init(void); +static void MX_I2C1_Init(void); +static void MX_I2C3_Init(void); +static void MX_LTDC_Init(void); +static void MX_RTC_Init(void); +static void MX_SPI2_Init(void); +static void MX_TIM1_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM5_Init(void); +static void MX_TIM8_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USART6_UART_Init(void); +static void MX_ADC1_Init(void); +static void MX_DAC_Init(void); +static void MX_UART7_Init(void); +static void MX_FMC_Init(void); +static void MX_DMA2D_Init(void); +void StartDefaultTask(void const * argument); + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + char text[50]={}; + static TS_StateTypeDef TS_State; + uint32_t potl,potr,joystick_h, joystick_v; + ADC_ChannelConfTypeDef sConfig = {0}; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_ADC3_Init(); + MX_I2C1_Init(); + MX_I2C3_Init(); + MX_LTDC_Init(); + MX_RTC_Init(); + MX_SPI2_Init(); + MX_TIM1_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM5_Init(); + MX_TIM8_Init(); + MX_USART1_UART_Init(); + MX_USART6_UART_Init(); + MX_ADC1_Init(); + MX_DAC_Init(); + MX_UART7_Init(); + MX_FMC_Init(); + MX_DMA2D_Init(); + /* USER CODE BEGIN 2 */ + BSP_LCD_Init(); + BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS); + BSP_LCD_LayerDefaultInit(1, LCD_FB_START_ADDRESS+ BSP_LCD_GetXSize()*BSP_LCD_GetYSize()*4); + BSP_LCD_DisplayOn(); + BSP_LCD_SelectLayer(1); + BSP_LCD_Clear(LCD_COLOR_LIGHTGREEN); + BSP_LCD_SetFont(&Font12); + BSP_LCD_SetTextColor(LCD_COLOR_BLUE); + BSP_LCD_SetBackColor(LCD_COLOR_LIGHTGREEN); + + BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize()); + + /* USER CODE END 2 */ + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* definition and creation of defaultTask */ + osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096); + defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL); + + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + /* USER CODE END RTOS_THREADS */ + + /* Start scheduler */ + //osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* Code de base */ + HAL_GPIO_WritePin(LED13_GPIO_Port,LED13_Pin,HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin)); + HAL_GPIO_WritePin(LED14_GPIO_Port,LED14_Pin,HAL_GPIO_ReadPin(BP2_GPIO_Port,BP2_Pin)); + sprintf(text,"BP1 : %d",HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin)); + BSP_LCD_DisplayStringAtLine(5,(uint8_t*) text); + + sConfig.Channel = ADC_CHANNEL_6; + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + HAL_ADC_Start(&hadc3); + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + potr = HAL_ADC_GetValue(&hadc3); + + sConfig.Channel = ADC_CHANNEL_7; + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + HAL_ADC_Start(&hadc3); + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + potl = HAL_ADC_GetValue(&hadc3); + + sConfig.Channel = ADC_CHANNEL_8; + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + HAL_ADC_Start(&hadc3); + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + joystick_v = HAL_ADC_GetValue(&hadc3); + + HAL_ADC_Start(&hadc1); + while(HAL_ADC_PollForConversion(&hadc1, 100)!=HAL_OK); + joystick_h = HAL_ADC_GetValue(&hadc1); + + sprintf(text,"POTL : %4u POTR : %4u joy_v : %4u joy_h : %4u",(uint)potl,(uint)potr,(uint)joystick_v,(uint)joystick_h); + BSP_LCD_DisplayStringAtLine(9,(uint8_t*) text); + + BSP_TS_GetState(&TS_State); + if(TS_State.touchDetected){ + BSP_LCD_FillCircle(TS_State.touchX[0],TS_State.touchY[0],4); + } + BSP_LCD_DisplyString(0, "coucou"); + BSP_LCD_DisplyString(1, "Tu veux voir ma ****"); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 400; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_RTC + |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART6 + |RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_I2C1 + |RCC_PERIPHCLK_I2C3; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 5; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8; + PeriphClkInitStruct.PLLSAIDivQ = 1; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1; + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_0; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief ADC3 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC3_Init(void) +{ + + /* USER CODE BEGIN ADC3_Init 0 */ + + /* USER CODE END ADC3_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC3_Init 1 */ + + /* USER CODE END ADC3_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc3.Instance = ADC3; + hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc3.Init.Resolution = ADC_RESOLUTION_12B; + hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + hadc3.Init.ContinuousConvMode = DISABLE; + hadc3.Init.DiscontinuousConvMode = DISABLE; + hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc3.Init.NbrOfConversion = 1; + hadc3.Init.DMAContinuousRequests = DISABLE; + hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc3) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_6; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC3_Init 2 */ + + /* USER CODE END ADC3_Init 2 */ + +} + +/** + * @brief DAC Initialization Function + * @param None + * @retval None + */ +static void MX_DAC_Init(void) +{ + + /* USER CODE BEGIN DAC_Init 0 */ + + /* USER CODE END DAC_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN DAC_Init 1 */ + + /* USER CODE END DAC_Init 1 */ + /** DAC Initialization + */ + hdac.Instance = DAC; + if (HAL_DAC_Init(&hdac) != HAL_OK) + { + Error_Handler(); + } + /** DAC channel OUT1 config + */ + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DAC_Init 2 */ + + /* USER CODE END DAC_Init 2 */ + +} + +/** + * @brief DMA2D Initialization Function + * @param None + * @retval None + */ +static void MX_DMA2D_Init(void) +{ + + /* USER CODE BEGIN DMA2D_Init 0 */ + + /* USER CODE END DMA2D_Init 0 */ + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + hdma2d.Instance = DMA2D; + hdma2d.Init.Mode = DMA2D_M2M; + hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; + hdma2d.Init.OutputOffset = 0; + hdma2d.LayerCfg[1].InputOffset = 0; + hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + hdma2d.LayerCfg[1].InputAlpha = 0; + if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + +/** + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x00C0EAFF; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +/** + * @brief I2C3 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C3_Init(void) +{ + + /* USER CODE BEGIN I2C3_Init 0 */ + + /* USER CODE END I2C3_Init 0 */ + + /* USER CODE BEGIN I2C3_Init 1 */ + + /* USER CODE END I2C3_Init 1 */ + hi2c3.Instance = I2C3; + hi2c3.Init.Timing = 0x00C0EAFF; + hi2c3.Init.OwnAddress1 = 0; + hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c3.Init.OwnAddress2 = 0; + hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c3) != HAL_OK) + { + Error_Handler(); + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C3_Init 2 */ + + /* USER CODE END I2C3_Init 2 */ + +} + +/** + * @brief LTDC Initialization Function + * @param None + * @retval None + */ +static void MX_LTDC_Init(void) +{ + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + hltdc.Init.HorizontalSync = 40; + hltdc.Init.VerticalSync = 9; + hltdc.Init.AccumulatedHBP = 53; + hltdc.Init.AccumulatedVBP = 11; + hltdc.Init.AccumulatedActiveW = 533; + hltdc.Init.AccumulatedActiveH = 283; + hltdc.Init.TotalWidth = 565; + hltdc.Init.TotalHeigh = 285; + hltdc.Init.Backcolor.Blue = 0; + hltdc.Init.Backcolor.Green = 0; + hltdc.Init.Backcolor.Red = 0; + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg.WindowX0 = 0; + pLayerCfg.WindowX1 = 480; + pLayerCfg.WindowY0 = 0; + pLayerCfg.WindowY1 = 272; + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; + pLayerCfg.Alpha = 255; + pLayerCfg.Alpha0 = 0; + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + pLayerCfg.FBStartAdress = 0xC0000000; + pLayerCfg.ImageWidth = 480; + pLayerCfg.ImageHeight = 272; + pLayerCfg.Backcolor.Blue = 0; + pLayerCfg.Backcolor.Green = 0; + pLayerCfg.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LTDC_Init 2 */ + + /* USER CODE END LTDC_Init 2 */ + +} + +/** + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + RTC_DateTypeDef sDate = {0}; + RTC_AlarmTypeDef sAlarm = {0}; + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } + + /* USER CODE BEGIN Check_RTC_BKUP */ + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 0x0; + sTime.Minutes = 0x0; + sTime.Seconds = 0x0; + sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + sTime.StoreOperation = RTC_STOREOPERATION_RESET; + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + sDate.Month = RTC_MONTH_JANUARY; + sDate.Date = 0x1; + sDate.Year = 0x0; + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + /** Enable the Alarm A + */ + sAlarm.AlarmTime.Hours = 0x0; + sAlarm.AlarmTime.Minutes = 0x0; + sAlarm.AlarmTime.Seconds = 0x0; + sAlarm.AlarmTime.SubSeconds = 0x0; + sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL; + sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE; + sAlarm.AlarmDateWeekDay = 0x1; + sAlarm.Alarm = RTC_ALARM_A; + if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + /** Enable the Alarm B + */ + sAlarm.Alarm = RTC_ALARM_B; + if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + { + Error_Handler(); + } + /** Enable the TimeStamp + */ + if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_POS1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +/** + * @brief TIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM1_Init(void) +{ + + /* USER CODE BEGIN TIM1_Init 0 */ + + /* USER CODE END TIM1_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM1_Init 1 */ + + /* USER CODE END TIM1_Init 1 */ + htim1.Instance = TIM1; + htim1.Init.Prescaler = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 65535; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM1_Init 2 */ + + /* USER CODE END TIM1_Init 2 */ + +} + +/** + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + +/** + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_SlaveConfigTypeDef sSlaveConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 65535; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE; + sSlaveConfig.InputTrigger = TIM_TS_ITR0; + if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} + +/** + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + htim5.Init.Prescaler = 0; + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + htim5.Init.Period = 4294967295; + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + +/** + * @brief TIM8 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM8_Init(void) +{ + + /* USER CODE BEGIN TIM8_Init 0 */ + + /* USER CODE END TIM8_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; + + /* USER CODE BEGIN TIM8_Init 1 */ + + /* USER CODE END TIM8_Init 1 */ + htim8.Instance = TIM8; + htim8.Init.Prescaler = 0; + htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + htim8.Init.Period = 65535; + htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim8.Init.RepetitionCounter = 0; + htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim8) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = 0; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + sBreakDeadTimeConfig.BreakFilter = 0; + sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; + sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; + sBreakDeadTimeConfig.Break2Filter = 0; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM8_Init 2 */ + + /* USER CODE END TIM8_Init 2 */ + HAL_TIM_MspPostInit(&htim8); + +} + +/** + * @brief UART7 Initialization Function + * @param None + * @retval None + */ +static void MX_UART7_Init(void) +{ + + /* USER CODE BEGIN UART7_Init 0 */ + + /* USER CODE END UART7_Init 0 */ + + /* USER CODE BEGIN UART7_Init 1 */ + + /* USER CODE END UART7_Init 1 */ + huart7.Instance = UART7; + huart7.Init.BaudRate = 115200; + huart7.Init.WordLength = UART_WORDLENGTH_8B; + huart7.Init.StopBits = UART_STOPBITS_1; + huart7.Init.Parity = UART_PARITY_NONE; + huart7.Init.Mode = UART_MODE_TX_RX; + huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart7.Init.OverSampling = UART_OVERSAMPLING_16; + huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart7) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART7_Init 2 */ + + /* USER CODE END UART7_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) +{ + + /* USER CODE BEGIN USART6_Init 0 */ + + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + huart6.Init.BaudRate = 115200; + huart6.Init.WordLength = UART_WORDLENGTH_8B; + huart6.Init.StopBits = UART_STOPBITS_1; + huart6.Init.Parity = UART_PARITY_NONE; + huart6.Init.Mode = UART_MODE_TX_RX; + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart6) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + +/* FMC initialization function */ +static void MX_FMC_Init(void) +{ + + /* USER CODE BEGIN FMC_Init 0 */ + + /* USER CODE END FMC_Init 0 */ + + FMC_SDRAM_TimingTypeDef SdramTiming = {0}; + + /* USER CODE BEGIN FMC_Init 1 */ + + /* USER CODE END FMC_Init 1 */ + + /** Perform the SDRAM1 memory initialization sequence + */ + hsdram1.Instance = FMC_SDRAM_DEVICE; + /* hsdram1.Init */ + hsdram1.Init.SDBank = FMC_SDRAM_BANK1; + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; + hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + /* SdramTiming */ + SdramTiming.LoadToActiveDelay = 16; + SdramTiming.ExitSelfRefreshDelay = 16; + SdramTiming.SelfRefreshTime = 16; + SdramTiming.RowCycleDelay = 16; + SdramTiming.WriteRecoveryTime = 16; + SdramTiming.RPDelay = 16; + SdramTiming.RCDDelay = 16; + + if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + { + Error_Handler( ); + } + + /* USER CODE BEGIN FMC_Init 2 */ + + /* USER CODE END FMC_Init 2 */ +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOJ_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOK_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin + |LED2_Pin|LED18_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : PE3 */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin + ULPI_D1_Pin ULPI_D4_Pin */ + GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin + |ULPI_D1_Pin|ULPI_D4_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : BP2_Pin BP1_Pin */ + GPIO_InitStruct.Pin = BP2_Pin|BP1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : LED14_Pin LED15_Pin */ + GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /*Configure GPIO pin : OTG_FS_VBUS_Pin */ + GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : Audio_INT_Pin */ + GPIO_InitStruct.Pin = Audio_INT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */ + GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */ + GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /*Configure GPIO pin : uSD_Detect_Pin */ + GPIO_InitStruct.Pin = uSD_Detect_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : LCD_BL_CTRL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : OTG_FS_OverCurrent_Pin */ + GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : TP3_Pin NC2_Pin */ + GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin + LED2_Pin LED18_Pin */ + GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin + |LED2_Pin|LED18_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /*Configure GPIO pin : LCD_INT_Pin */ + GPIO_InitStruct.Pin = LCD_INT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : ULPI_NXT_Pin */ + GPIO_InitStruct.Pin = ULPI_NXT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */ + GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */ + GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : EXT_RST_Pin */ + GPIO_InitStruct.Pin = EXT_RST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */ + GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void const * argument) +{ + /* USER CODE BEGIN 5 */ + /* Infinite loop */ + for(;;) + { + osDelay(1); + } + /* USER CODE END 5 */ +} + + /** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32746g_discovery.c b/Core/Src/stm32746g_discovery.c new file mode 100644 index 0000000..98fe4a9 --- /dev/null +++ b/Core/Src/stm32746g_discovery.c @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery.c + * @author MCD Application Team + * @brief This file provides a set of firmware functions to manage LEDs, + * push-buttons and COM ports available on STM32746G-Discovery + * board(MB1191) from STMicroelectronics. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Dependencies +- stm32f7xx_hal_cortex.c +- stm32f7xx_hal_gpio.c +- stm32f7xx_hal_uart.c +- stm32f7xx_hal_i2c.c +EndDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL STM32746G_DISCOVERY_LOW_LEVEL + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions STM32746G_DISCOVERY_LOW_LEVEL Private Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Private_Defines STM32746G_DISCOVERY_LOW_LEVEL Private Defines + * @{ + */ +/** + * @brief STM32746G DISCOVERY BSP Driver version number V2.0.2 + */ +#define __STM32746G_DISCO_BSP_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32746G_DISCO_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __STM32746G_DISCO_BSP_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32746G_DISCO_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32746G_DISCO_BSP_VERSION ((__STM32746G_DISCO_BSP_VERSION_MAIN << 24)\ + |(__STM32746G_DISCO_BSP_VERSION_SUB1 << 16)\ + |(__STM32746G_DISCO_BSP_VERSION_SUB2 << 8 )\ + |(__STM32746G_DISCO_BSP_VERSION_RC)) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Private_Macros STM32746G_DISCOVERY_LOW_LEVEL Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Private_Variables STM32746G_DISCOVERY_LOW_LEVEL Private Variables + * @{ + */ + +const uint32_t GPIO_PIN[LEDn] = {LED1_PIN}; + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, + TAMPER_BUTTON_GPIO_PORT, + KEY_BUTTON_GPIO_PORT}; + +const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, + TAMPER_BUTTON_PIN, + KEY_BUTTON_PIN}; + +const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, + TAMPER_BUTTON_EXTI_IRQn, + KEY_BUTTON_EXTI_IRQn}; + +USART_TypeDef* COM_USART[COMn] = {DISCOVERY_COM1}; + +GPIO_TypeDef* COM_TX_PORT[COMn] = {DISCOVERY_COM1_TX_GPIO_PORT}; + +GPIO_TypeDef* COM_RX_PORT[COMn] = {DISCOVERY_COM1_RX_GPIO_PORT}; + +const uint16_t COM_TX_PIN[COMn] = {DISCOVERY_COM1_TX_PIN}; + +const uint16_t COM_RX_PIN[COMn] = {DISCOVERY_COM1_RX_PIN}; + +const uint16_t COM_TX_AF[COMn] = {DISCOVERY_COM1_TX_AF}; + +const uint16_t COM_RX_AF[COMn] = {DISCOVERY_COM1_RX_AF}; + +static I2C_HandleTypeDef hI2cAudioHandler = {0}; +static I2C_HandleTypeDef hI2cExtHandler = {0}; + +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes STM32746G_DISCOVERY_LOW_LEVEL Private Function Prototypes + * @{ + */ +static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler); +static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler); + +static HAL_StatusTypeDef I2Cx_ReadMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length); +static HAL_StatusTypeDef I2Cx_WriteMultiple(I2C_HandleTypeDef *i2c_handler, uint8_t Addr, uint16_t Reg, uint16_t MemAddSize, uint8_t *Buffer, uint16_t Length); +static HAL_StatusTypeDef I2Cx_IsDeviceReady(I2C_HandleTypeDef *i2c_handler, uint16_t DevAddress, uint32_t Trials); +static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr); + +/* AUDIO IO functions */ +void AUDIO_IO_Init(void); +void AUDIO_IO_DeInit(void); +void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value); +uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg); +void AUDIO_IO_Delay(uint32_t Delay); + +/* TOUCHSCREEN IO functions */ +void TS_IO_Init(void); +void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value); +uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg); +void TS_IO_Delay(uint32_t Delay); + +/* CAMERA IO functions */ +void CAMERA_IO_Init(void); +void CAMERA_Delay(uint32_t Delay); +void CAMERA_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value); +uint8_t CAMERA_IO_Read(uint8_t Addr, uint8_t Reg); + +/* I2C EEPROM IO function */ +void EEPROM_IO_Init(void); +HAL_StatusTypeDef EEPROM_IO_WriteData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize); +HAL_StatusTypeDef EEPROM_IO_ReadData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize); +HAL_StatusTypeDef EEPROM_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials); +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LOW_LEVEL_Exported_Functions STM32746G_DISCOVERY_LOW_LEVELSTM32746G_DISCOVERY_LOW_LEVEL Exported Functions + * @{ + */ + + /** + * @brief This method returns the STM32746G DISCOVERY BSP Driver revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t BSP_GetVersion(void) +{ + return __STM32746G_DISCO_BSP_VERSION; +} + +/** + * @brief Configures LED on GPIO. + * @param Led: LED to be configured. + * This parameter can be one of the following values: + * @arg LED1 + * @retval None + */ +void BSP_LED_Init(Led_TypeDef Led) +{ + GPIO_InitTypeDef gpio_init_structure; + GPIO_TypeDef* gpio_led; + + if (Led == LED1) + { + gpio_led = LED1_GPIO_PORT; + /* Enable the GPIO_LED clock */ + LED1_GPIO_CLK_ENABLE(); + + /* Configure the GPIO_LED pin */ + gpio_init_structure.Pin = GPIO_PIN[Led]; + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_HIGH; + + HAL_GPIO_Init(gpio_led, &gpio_init_structure); + + /* By default, turn off LED */ + HAL_GPIO_WritePin(gpio_led, GPIO_PIN[Led], GPIO_PIN_RESET); + } +} + +/** + * @brief DeInit LEDs. + * @param Led: LED to be configured. + * This parameter can be one of the following values: + * @arg LED1 + * @note Led DeInit does not disable the GPIO clock + * @retval None + */ +void BSP_LED_DeInit(Led_TypeDef Led) +{ + GPIO_InitTypeDef gpio_init_structure; + GPIO_TypeDef* gpio_led; + + if (Led == LED1) + { + gpio_led = LED1_GPIO_PORT; + /* Turn off LED */ + HAL_GPIO_WritePin(gpio_led, GPIO_PIN[Led], GPIO_PIN_RESET); + /* Configure the GPIO_LED pin */ + gpio_init_structure.Pin = GPIO_PIN[Led]; + HAL_GPIO_DeInit(gpio_led, gpio_init_structure.Pin); + } +} + +/** + * @brief Turns selected LED On. + * @param Led: LED to be set on + * This parameter can be one of the following values: + * @arg LED1 + * @retval None + */ +void BSP_LED_On(Led_TypeDef Led) +{ + GPIO_TypeDef* gpio_led; + + if (Led == LED1) /* Switch On LED connected to GPIO */ + { + gpio_led = LED1_GPIO_PORT; + HAL_GPIO_WritePin(gpio_led, GPIO_PIN[Led], GPIO_PIN_SET); + } +} + +/** + * @brief Turns selected LED Off. + * @param Led: LED to be set off + * This parameter can be one of the following values: + * @arg LED1 + * @retval None + */ +void BSP_LED_Off(Led_TypeDef Led) +{ + GPIO_TypeDef* gpio_led; + + if (Led == LED1) /* Switch Off LED connected to GPIO */ + { + gpio_led = LED1_GPIO_PORT; + HAL_GPIO_WritePin(gpio_led, GPIO_PIN[Led], GPIO_PIN_RESET); + } +} + +/** + * @brief Toggles the selected LED. + * @param Led: LED to be toggled + * This parameter can be one of the following values: + * @arg LED1 + * @retval None + */ +void BSP_LED_Toggle(Led_TypeDef Led) +{ + GPIO_TypeDef* gpio_led; + + if (Led == LED1) /* Toggle LED connected to GPIO */ + { + gpio_led = LED1_GPIO_PORT; + HAL_GPIO_TogglePin(gpio_led, GPIO_PIN[Led]); + } +} + +/** + * @brief Configures button GPIO and EXTI Line. + * @param Button: Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @param ButtonMode: Button mode + * This parameter can be one of the following values: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line + * with interrupt generation capability + * @note On STM32746G-Discovery board, the three buttons (Wakeup, Tamper and key buttons) + * are mapped on the same push button named "User" + * on the board serigraphy. + * @retval None + */ +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the BUTTON clock */ + BUTTONx_GPIO_CLK_ENABLE(Button); + + if(ButtonMode == BUTTON_MODE_GPIO) + { + /* Configure Button pin as input */ + gpio_init_structure.Pin = BUTTON_PIN[Button]; + gpio_init_structure.Mode = GPIO_MODE_INPUT; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + } + + if(ButtonMode == BUTTON_MODE_EXTI) + { + /* Configure Button pin as input with External interrupt */ + gpio_init_structure.Pin = BUTTON_PIN[Button]; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + + if(Button != BUTTON_WAKEUP) + { + gpio_init_structure.Mode = GPIO_MODE_IT_FALLING; + } + else + { + gpio_init_structure.Mode = GPIO_MODE_IT_RISING; + } + + HAL_GPIO_Init(BUTTON_PORT[Button], &gpio_init_structure); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00); + HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + } +} + +/** + * @brief Push Button DeInit. + * @param Button: Button to be configured + * This parameter can be one of the following values: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @note On STM32746G-Discovery board, the three buttons (Wakeup, Tamper and key buttons) + * are mapped on the same push button named "User" + * on the board serigraphy. + * @note PB DeInit does not disable the GPIO clock + * @retval None + */ +void BSP_PB_DeInit(Button_TypeDef Button) +{ + GPIO_InitTypeDef gpio_init_structure; + + gpio_init_structure.Pin = BUTTON_PIN[Button]; + HAL_NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + HAL_GPIO_DeInit(BUTTON_PORT[Button], gpio_init_structure.Pin); +} + + +/** + * @brief Returns the selected button state. + * @param Button: Button to be checked + * This parameter can be one of the following values: + * @arg BUTTON_WAKEUP: Wakeup Push Button + * @arg BUTTON_TAMPER: Tamper Push Button + * @arg BUTTON_KEY: Key Push Button + * @note On STM32746G-Discovery board, the three buttons (Wakeup, Tamper and key buttons) + * are mapped on the same push button named "User" + * on the board serigraphy. + * @retval The Button GPIO pin value + */ +uint32_t BSP_PB_GetState(Button_TypeDef Button) +{ + return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + +/** + * @brief Configures COM port. + * @param COM: COM port to be configured. + * This parameter can be one of the following values: + * @arg COM1 + * @arg COM2 + * @param huart: Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval None + */ +void BSP_COM_Init(COM_TypeDef COM, UART_HandleTypeDef *huart) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Enable GPIO clock */ + DISCOVERY_COMx_TX_GPIO_CLK_ENABLE(COM); + DISCOVERY_COMx_RX_GPIO_CLK_ENABLE(COM); + + /* Enable USART clock */ + DISCOVERY_COMx_CLK_ENABLE(COM); + + /* Configure USART Tx as alternate function */ + gpio_init_structure.Pin = COM_TX_PIN[COM]; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Alternate = COM_TX_AF[COM]; + HAL_GPIO_Init(COM_TX_PORT[COM], &gpio_init_structure); + + /* Configure USART Rx as alternate function */ + gpio_init_structure.Pin = COM_RX_PIN[COM]; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = COM_RX_AF[COM]; + HAL_GPIO_Init(COM_RX_PORT[COM], &gpio_init_structure); + + /* USART configuration */ + huart->Instance = COM_USART[COM]; + HAL_UART_Init(huart); +} + +/** + * @brief DeInit COM port. + * @param COM: COM port to be configured. + * This parameter can be one of the following values: + * @arg COM1 + * @arg COM2 + * @param huart: Pointer to a UART_HandleTypeDef structure that contains the + * configuration information for the specified USART peripheral. + * @retval None + */ +void BSP_COM_DeInit(COM_TypeDef COM, UART_HandleTypeDef *huart) +{ + /* USART configuration */ + huart->Instance = COM_USART[COM]; + HAL_UART_DeInit(huart); + + /* Enable USART clock */ + DISCOVERY_COMx_CLK_DISABLE(COM); + + /* DeInit GPIO pins can be done in the application + (by surcharging this __weak function) */ + + /* GPIO pins clock, DMA clock can be shut down in the application + by surcharging this __weak function */ +} + +/******************************************************************************* + BUS OPERATIONS +*******************************************************************************/ + +/******************************* I2C Routines *********************************/ +/** + * @brief Initializes I2C MSP. + * @param i2c_handler : I2C handler + * @retval None + */ +static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler) +{ + GPIO_InitTypeDef gpio_init_structure; + + if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler)) + { + /* AUDIO and LCD I2C MSP init */ + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE(); + + /* Configure I2C Tx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF; + HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + + /* Configure I2C Rx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN; + HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + + /*** Configure the I2C peripheral ***/ + /* Enable I2C clock */ + DISCOVERY_AUDIO_I2Cx_CLK_ENABLE(); + + /* Force the I2C peripheral clock reset */ + DISCOVERY_AUDIO_I2Cx_FORCE_RESET(); + + /* Release the I2C peripheral clock reset */ + DISCOVERY_AUDIO_I2Cx_RELEASE_RESET(); + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn); + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn); + } + else + { + /* External, camera and Arduino connector I2C MSP init */ + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE(); + + /* Configure I2C Tx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF; + HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + + /* Configure I2C Rx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN; + HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + + /*** Configure the I2C peripheral ***/ + /* Enable I2C clock */ + DISCOVERY_EXT_I2Cx_CLK_ENABLE(); + + /* Force the I2C peripheral clock reset */ + DISCOVERY_EXT_I2Cx_FORCE_RESET(); + + /* Release the I2C peripheral clock reset */ + DISCOVERY_EXT_I2Cx_RELEASE_RESET(); + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn); + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn); + } +} + +/** + * @brief Initializes I2C HAL. + * @param i2c_handler : I2C handler + * @retval None + */ +static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler) +{ + if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET) + { + if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler)) + { + /* Audio and LCD I2C configuration */ + i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx; + } + else + { + /* External, camera and Arduino connector I2C configuration */ + i2c_handler->Instance = DISCOVERY_EXT_I2Cx; + } + i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING; + i2c_handler->Init.OwnAddress1 = 0; + i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + i2c_handler->Init.OwnAddress2 = 0; + i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + + /* Init the I2C */ + I2Cx_MspInit(i2c_handler); + HAL_I2C_Init(i2c_handler); + } +} + +/** + * @brief Reads multiple data. + * @param i2c_handler : I2C handler + * @param Addr: I2C address + * @param Reg: Reg address + * @param MemAddress: Memory address + * @param Buffer: Pointer to data buffer + * @param Length: Length of the data + * @retval Number of read data + */ +static HAL_StatusTypeDef I2Cx_ReadMultiple(I2C_HandleTypeDef *i2c_handler, + uint8_t Addr, + uint16_t Reg, + uint16_t MemAddress, + uint8_t *Buffer, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* I2C error occurred */ + I2Cx_Error(i2c_handler, Addr); + } + return status; +} + +/** + * @brief Writes a value in a register of the device through BUS in using DMA mode. + * @param i2c_handler : I2C handler + * @param Addr: Device address on BUS Bus. + * @param Reg: The target register address to write + * @param MemAddress: Memory address + * @param Buffer: The target register value to be written + * @param Length: buffer size to be written + * @retval HAL status + */ +static HAL_StatusTypeDef I2Cx_WriteMultiple(I2C_HandleTypeDef *i2c_handler, + uint8_t Addr, + uint16_t Reg, + uint16_t MemAddress, + uint8_t *Buffer, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + + status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000); + + /* Check the communication status */ + if(status != HAL_OK) + { + /* Re-Initiaize the I2C Bus */ + I2Cx_Error(i2c_handler, Addr); + } + return status; +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param i2c_handler : I2C handler + * @param DevAddress: Target device address + * @param Trials: Number of trials + * @retval HAL status + */ +static HAL_StatusTypeDef I2Cx_IsDeviceReady(I2C_HandleTypeDef *i2c_handler, uint16_t DevAddress, uint32_t Trials) +{ + return (HAL_I2C_IsDeviceReady(i2c_handler, DevAddress, Trials, 1000)); +} + +/** + * @brief Manages error callback by re-initializing I2C. + * @param i2c_handler : I2C handler + * @param Addr: I2C Address + * @retval None + */ +static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr) +{ + /* De-initialize the I2C communication bus */ + HAL_I2C_DeInit(i2c_handler); + + /* Re-Initialize the I2C communication bus */ + I2Cx_Init(i2c_handler); +} + +/******************************************************************************* + LINK OPERATIONS +*******************************************************************************/ + +/********************************* LINK AUDIO *********************************/ + +/** + * @brief Initializes Audio low level. + * @retval None + */ +void AUDIO_IO_Init(void) +{ + I2Cx_Init(&hI2cAudioHandler); +} + +/** + * @brief Deinitializes Audio low level. + * @retval None + */ +void AUDIO_IO_DeInit(void) +{ +} + +/** + * @brief Writes a single data. + * @param Addr: I2C address + * @param Reg: Reg address + * @param Value: Data to be written + * @retval None + */ +void AUDIO_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value) +{ + uint16_t tmp = Value; + + Value = ((uint16_t)(tmp >> 8) & 0x00FF); + + Value |= ((uint16_t)(tmp << 8)& 0xFF00); + + I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_16BIT,(uint8_t*)&Value, 2); +} + +/** + * @brief Reads a single data. + * @param Addr: I2C address + * @param Reg: Reg address + * @retval Data to be read + */ +uint16_t AUDIO_IO_Read(uint8_t Addr, uint16_t Reg) +{ + uint16_t read_value = 0, tmp = 0; + + I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_16BIT, (uint8_t*)&read_value, 2); + + tmp = ((uint16_t)(read_value >> 8) & 0x00FF); + + tmp |= ((uint16_t)(read_value << 8)& 0xFF00); + + read_value = tmp; + + return read_value; +} + +/** + * @brief AUDIO Codec delay + * @param Delay: Delay in ms + * @retval None + */ +void AUDIO_IO_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/********************************* LINK CAMERA ********************************/ + +/** + * @brief Initializes Camera low level. + * @retval None + */ +void CAMERA_IO_Init(void) +{ + I2Cx_Init(&hI2cExtHandler); +} + +/** + * @brief Camera writes single data. + * @param Addr: I2C address + * @param Reg: Register address + * @param Value: Data to be written + * @retval None + */ +void CAMERA_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value) +{ + I2Cx_WriteMultiple(&hI2cExtHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1); +} + +/** + * @brief Camera reads single data. + * @param Addr: I2C address + * @param Reg: Register address + * @retval Read data + */ +uint8_t CAMERA_IO_Read(uint8_t Addr, uint8_t Reg) +{ + uint8_t read_value = 0; + + I2Cx_ReadMultiple(&hI2cExtHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1); + + return read_value; +} + +/** + * @brief Camera delay + * @param Delay: Delay in ms + * @retval None + */ +void CAMERA_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/******************************** LINK I2C EEPROM *****************************/ + +/** + * @brief Initializes peripherals used by the I2C EEPROM driver. + * @retval None + */ +void EEPROM_IO_Init(void) +{ + I2Cx_Init(&hI2cExtHandler); +} + +/** + * @brief Write data to I2C EEPROM driver in using DMA channel. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param pBuffer: Pointer to data buffer + * @param BufferSize: Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef EEPROM_IO_WriteData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize) +{ + return (I2Cx_WriteMultiple(&hI2cExtHandler, DevAddress, MemAddress, I2C_MEMADD_SIZE_16BIT, pBuffer, BufferSize)); +} + +/** + * @brief Read data from I2C EEPROM driver in using DMA channel. + * @param DevAddress: Target device address + * @param MemAddress: Internal memory address + * @param pBuffer: Pointer to data buffer + * @param BufferSize: Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef EEPROM_IO_ReadData(uint16_t DevAddress, uint16_t MemAddress, uint8_t* pBuffer, uint32_t BufferSize) +{ + return (I2Cx_ReadMultiple(&hI2cExtHandler, DevAddress, MemAddress, I2C_MEMADD_SIZE_16BIT, pBuffer, BufferSize)); +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param DevAddress: Target device address + * @param Trials: Number of trials + * @retval HAL status + */ +HAL_StatusTypeDef EEPROM_IO_IsDeviceReady(uint16_t DevAddress, uint32_t Trials) +{ + return (I2Cx_IsDeviceReady(&hI2cExtHandler, DevAddress, Trials)); +} + +/********************************* LINK TOUCHSCREEN *********************************/ + +/** + * @brief Initializes Touchscreen low level. + * @retval None + */ +void TS_IO_Init(void) +{ + I2Cx_Init(&hI2cAudioHandler); +} + +/** + * @brief Writes a single data. + * @param Addr: I2C address + * @param Reg: Reg address + * @param Value: Data to be written + * @retval None + */ +void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value) +{ + I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1); +} + +/** + * @brief Reads a single data. + * @param Addr: I2C address + * @param Reg: Reg address + * @retval Data to be read + */ +uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg) +{ + uint8_t read_value = 0; + + I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1); + + return read_value; +} + +/** + * @brief TS delay + * @param Delay: Delay in ms + * @retval None + */ +void TS_IO_Delay(uint32_t Delay) +{ + HAL_Delay(Delay); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32746g_discovery_lcd.c b/Core/Src/stm32746g_discovery_lcd.c new file mode 100644 index 0000000..cfadf99 --- /dev/null +++ b/Core/Src/stm32746g_discovery_lcd.c @@ -0,0 +1,1663 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_lcd.c + * @author MCD Application Team + * @brief This file includes the driver for Liquid Crystal Display (LCD) module + * mounted on STM32746G-Discovery board. + @verbatim + 1. How To use this driver: + -------------------------- + - This driver is used to drive directly an LCD TFT using the LTDC controller. + - This driver uses timing and setting for RK043FN48H LCD. + + 2. Driver description: + --------------------- + + Initialization steps: + o Initialize the LCD using the BSP_LCD_Init() function. + o Apply the Layer configuration using the BSP_LCD_LayerDefaultInit() function. + o Select the LCD layer to be used using the BSP_LCD_SelectLayer() function. + o Enable the LCD display using the BSP_LCD_DisplayOn() function. + + + Options + o Configure and enable the color keying functionality using the + BSP_LCD_SetColorKeying() function. + o Modify in the fly the transparency and/or the frame buffer address + using the following functions: + - BSP_LCD_SetTransparency() + - BSP_LCD_SetLayerAddress() + + + Display on LCD + o Clear the hole LCD using BSP_LCD_Clear() function or only one specified string + line using the BSP_LCD_ClearStringLine() function. + o Display a character on the specified line and column using the BSP_LCD_DisplayChar() + function or a complete string line using the BSP_LCD_DisplayStringAtLine() function. + o Display a string line on the specified position (x,y in pixel) and align mode + using the BSP_LCD_DisplayStringAtLine() function. + o Draw and fill a basic shapes (dot, line, rectangle, circle, ellipse, .. bitmap) + on LCD using the available set of functions. + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Dependencies +- stm32746g_discovery.c +- stm32746g_discovery_sdram.c +- stm32f7xx_hal_ltdc.c +- stm32f7xx_hal_ltdc_ex.c +- stm32f7xx_hal_dma2d.c +- stm32f7xx_hal_rcc_ex.c +- stm32f7xx_hal_gpio.c +- stm32f7xx_hal_cortex.c +- rk043fn48h.h +- fonts.h +- font24.c +- font20.c +- font16.c +- font12.c +- font8.c" +EndDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery_lcd.h" +#include "../../Fonts/fonts.h" +#include "../../Fonts/font24.c" +#include "../../Fonts/font20.c" +#include "../../Fonts/font16.c" +#include "../../Fonts/font12.c" +#include "../../Fonts/font8.c" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_LCD + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Private_TypesDefinitions STM32746G_DISCOVERY_LCD Private Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Private_Defines STM32746G_DISCOVERY LCD Private Defines + * @{ + */ +#define POLY_X(Z) ((int32_t)((Points + Z)->X)) +#define POLY_Y(Z) ((int32_t)((Points + Z)->Y)) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Private_Macros STM32746G_DISCOVERY_LCD Private Macros + * @{ + */ +#define ABS(X) ((X) > 0 ? (X) : -(X)) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Private_Variables STM32746G_DISCOVERY_LCD Private Variables + * @{ + */ +LTDC_HandleTypeDef hLtdcHandler; +static DMA2D_HandleTypeDef hDma2dHandler; + +/* Default LCD configuration with LCD Layer 1 */ +static uint32_t ActiveLayer = 0; +static LCD_DrawPropTypeDef DrawProp[MAX_LAYER_NUMBER]; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Private_FunctionPrototypes STM32746G_DISCOVERY_LCD Private Function Prototypes + * @{ + */ +static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c); +static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3); +static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex); +static void LL_ConvertLineToARGB8888(void * pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode); +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_LCD_Exported_Functions STM32746G_DISCOVERY_LCD Exported Functions + * @{ + */ + +/** + * @brief Initializes the LCD. + * @retval LCD state + */ +uint8_t BSP_LCD_Init(void) +{ + /* Select the used LCD */ + + /* The RK043FN48H LCD 480x272 is selected */ + /* Timing Configuration */ + hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1); + hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1); + hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1); + hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1); + + /* LCD clock configuration */ + BSP_LCD_ClockConfig(&hLtdcHandler, NULL); + + /* Initialize the LCD pixel width and pixel height */ + hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH; + hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT; + + /* Background value */ + hLtdcHandler.Init.Backcolor.Blue = 0; + hLtdcHandler.Init.Backcolor.Green = 0; + hLtdcHandler.Init.Backcolor.Red = 0; + + /* Polarity */ + hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL; + hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL; + hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL; + hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + hLtdcHandler.Instance = LTDC; + + if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET) + { + /* Initialize the LCD Msp: this __weak function can be rewritten by the application */ + BSP_LCD_MspInit(&hLtdcHandler, NULL); + } + HAL_LTDC_Init(&hLtdcHandler); + + /* Assert display enable LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); + + /* Assert backlight LCD_BL_CTRL pin */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); + +#if !defined(DATA_IN_ExtSDRAM) + /* Initialize the SDRAM */ + BSP_SDRAM_Init(); +#endif + + /* Initialize the font */ + BSP_LCD_SetFont(&LCD_DEFAULT_FONT); + + return LCD_OK; +} + +/** + * @brief DeInitializes the LCD. + * @retval LCD state + */ +uint8_t BSP_LCD_DeInit(void) +{ + /* Initialize the hLtdcHandler Instance parameter */ + hLtdcHandler.Instance = LTDC; + + /* Disable LTDC block */ + __HAL_LTDC_DISABLE(&hLtdcHandler); + + /* DeInit the LTDC */ + HAL_LTDC_DeInit(&hLtdcHandler); + + /* DeInit the LTDC MSP : this __weak function can be rewritten by the application */ + BSP_LCD_MspDeInit(&hLtdcHandler, NULL); + + return LCD_OK; +} + +/** + * @brief Gets the LCD X size. + * @retval Used LCD X size + */ +uint32_t BSP_LCD_GetXSize(void) +{ + return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth; +} + +/** + * @brief Gets the LCD Y size. + * @retval Used LCD Y size + */ +uint32_t BSP_LCD_GetYSize(void) +{ + return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight; +} + +/** + * @brief Set the LCD X size. + * @param imageWidthPixels : image width in pixels unit + * @retval None + */ +void BSP_LCD_SetXSize(uint32_t imageWidthPixels) +{ + hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth = imageWidthPixels; +} + +/** + * @brief Set the LCD Y size. + * @param imageHeightPixels : image height in lines unit + * @retval None + */ +void BSP_LCD_SetYSize(uint32_t imageHeightPixels) +{ + hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight = imageHeightPixels; +} + +/** + * @brief Initializes the LCD layer in ARGB8888 format (32 bits per pixel). + * @param LayerIndex: Layer foreground or background + * @param FB_Address: Layer frame buffer + * @retval None + */ +void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address) +{ + LCD_LayerCfgTypeDef layer_cfg; + + /* Layer Init */ + layer_cfg.WindowX0 = 0; + layer_cfg.WindowX1 = BSP_LCD_GetXSize(); + layer_cfg.WindowY0 = 0; + layer_cfg.WindowY1 = BSP_LCD_GetYSize(); + layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + layer_cfg.FBStartAdress = FB_Address; + layer_cfg.Alpha = 255; + layer_cfg.Alpha0 = 0; + layer_cfg.Backcolor.Blue = 0; + layer_cfg.Backcolor.Green = 0; + layer_cfg.Backcolor.Red = 0; + layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + layer_cfg.ImageWidth = BSP_LCD_GetXSize(); + layer_cfg.ImageHeight = BSP_LCD_GetYSize(); + + HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex); + + DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE; + DrawProp[LayerIndex].pFont = &Font24; + DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK; +} + +/** + * @brief Initializes the LCD layer in RGB565 format (16 bits per pixel). + * @param LayerIndex: Layer foreground or background + * @param FB_Address: Layer frame buffer + * @retval None + */ +void BSP_LCD_LayerRgb565Init(uint16_t LayerIndex, uint32_t FB_Address) +{ + LCD_LayerCfgTypeDef layer_cfg; + + /* Layer Init */ + layer_cfg.WindowX0 = 0; + layer_cfg.WindowX1 = BSP_LCD_GetXSize(); + layer_cfg.WindowY0 = 0; + layer_cfg.WindowY1 = BSP_LCD_GetYSize(); + layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; + layer_cfg.FBStartAdress = FB_Address; + layer_cfg.Alpha = 255; + layer_cfg.Alpha0 = 0; + layer_cfg.Backcolor.Blue = 0; + layer_cfg.Backcolor.Green = 0; + layer_cfg.Backcolor.Red = 0; + layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + layer_cfg.ImageWidth = BSP_LCD_GetXSize(); + layer_cfg.ImageHeight = BSP_LCD_GetYSize(); + + HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex); + + DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE; + DrawProp[LayerIndex].pFont = &Font24; + DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK; +} + +/** + * @brief Selects the LCD Layer. + * @param LayerIndex: Layer foreground or background + * @retval None + */ +void BSP_LCD_SelectLayer(uint32_t LayerIndex) +{ + ActiveLayer = LayerIndex; +} + +/** + * @brief Sets an LCD Layer visible + * @param LayerIndex: Visible Layer + * @param State: New state of the specified layer + * This parameter can be one of the following values: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void BSP_LCD_SetLayerVisible(uint32_t LayerIndex, FunctionalState State) +{ + if(State == ENABLE) + { + __HAL_LTDC_LAYER_ENABLE(&hLtdcHandler, LayerIndex); + } + else + { + __HAL_LTDC_LAYER_DISABLE(&hLtdcHandler, LayerIndex); + } + __HAL_LTDC_RELOAD_CONFIG(&hLtdcHandler); +} + +/** + * @brief Sets an LCD Layer visible without reloading. + * @param LayerIndex: Visible Layer + * @param State: New state of the specified layer + * This parameter can be one of the following values: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void BSP_LCD_SetLayerVisible_NoReload(uint32_t LayerIndex, FunctionalState State) +{ + if(State == ENABLE) + { + __HAL_LTDC_LAYER_ENABLE(&hLtdcHandler, LayerIndex); + } + else + { + __HAL_LTDC_LAYER_DISABLE(&hLtdcHandler, LayerIndex); + } + /* Do not Sets the Reload */ +} + +/** + * @brief Configures the transparency. + * @param LayerIndex: Layer foreground or background. + * @param Transparency: Transparency + * This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +void BSP_LCD_SetTransparency(uint32_t LayerIndex, uint8_t Transparency) +{ + HAL_LTDC_SetAlpha(&hLtdcHandler, Transparency, LayerIndex); +} + +/** + * @brief Configures the transparency without reloading. + * @param LayerIndex: Layer foreground or background. + * @param Transparency: Transparency + * This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +void BSP_LCD_SetTransparency_NoReload(uint32_t LayerIndex, uint8_t Transparency) +{ + HAL_LTDC_SetAlpha_NoReload(&hLtdcHandler, Transparency, LayerIndex); +} + +/** + * @brief Sets an LCD layer frame buffer address. + * @param LayerIndex: Layer foreground or background + * @param Address: New LCD frame buffer value + * @retval None + */ +void BSP_LCD_SetLayerAddress(uint32_t LayerIndex, uint32_t Address) +{ + HAL_LTDC_SetAddress(&hLtdcHandler, Address, LayerIndex); +} + +/** + * @brief Sets an LCD layer frame buffer address without reloading. + * @param LayerIndex: Layer foreground or background + * @param Address: New LCD frame buffer value + * @retval None + */ +void BSP_LCD_SetLayerAddress_NoReload(uint32_t LayerIndex, uint32_t Address) +{ + HAL_LTDC_SetAddress_NoReload(&hLtdcHandler, Address, LayerIndex); +} + +/** + * @brief Sets display window. + * @param LayerIndex: Layer index + * @param Xpos: LCD X position + * @param Ypos: LCD Y position + * @param Width: LCD window width + * @param Height: LCD window height + * @retval None + */ +void BSP_LCD_SetLayerWindow(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + /* Reconfigure the layer size */ + HAL_LTDC_SetWindowSize(&hLtdcHandler, Width, Height, LayerIndex); + + /* Reconfigure the layer position */ + HAL_LTDC_SetWindowPosition(&hLtdcHandler, Xpos, Ypos, LayerIndex); +} + +/** + * @brief Sets display window without reloading. + * @param LayerIndex: Layer index + * @param Xpos: LCD X position + * @param Ypos: LCD Y position + * @param Width: LCD window width + * @param Height: LCD window height + * @retval None + */ +void BSP_LCD_SetLayerWindow_NoReload(uint16_t LayerIndex, uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + /* Reconfigure the layer size */ + HAL_LTDC_SetWindowSize_NoReload(&hLtdcHandler, Width, Height, LayerIndex); + + /* Reconfigure the layer position */ + HAL_LTDC_SetWindowPosition_NoReload(&hLtdcHandler, Xpos, Ypos, LayerIndex); +} + +/** + * @brief Configures and sets the color keying. + * @param LayerIndex: Layer foreground or background + * @param RGBValue: Color reference + * @retval None + */ +void BSP_LCD_SetColorKeying(uint32_t LayerIndex, uint32_t RGBValue) +{ + /* Configure and Enable the color Keying for LCD Layer */ + HAL_LTDC_ConfigColorKeying(&hLtdcHandler, RGBValue, LayerIndex); + HAL_LTDC_EnableColorKeying(&hLtdcHandler, LayerIndex); +} + +/** + * @brief Configures and sets the color keying without reloading. + * @param LayerIndex: Layer foreground or background + * @param RGBValue: Color reference + * @retval None + */ +void BSP_LCD_SetColorKeying_NoReload(uint32_t LayerIndex, uint32_t RGBValue) +{ + /* Configure and Enable the color Keying for LCD Layer */ + HAL_LTDC_ConfigColorKeying_NoReload(&hLtdcHandler, RGBValue, LayerIndex); + HAL_LTDC_EnableColorKeying_NoReload(&hLtdcHandler, LayerIndex); +} + +/** + * @brief Disables the color keying. + * @param LayerIndex: Layer foreground or background + * @retval None + */ +void BSP_LCD_ResetColorKeying(uint32_t LayerIndex) +{ + /* Disable the color Keying for LCD Layer */ + HAL_LTDC_DisableColorKeying(&hLtdcHandler, LayerIndex); +} + +/** + * @brief Disables the color keying without reloading. + * @param LayerIndex: Layer foreground or background + * @retval None + */ +void BSP_LCD_ResetColorKeying_NoReload(uint32_t LayerIndex) +{ + /* Disable the color Keying for LCD Layer */ + HAL_LTDC_DisableColorKeying_NoReload(&hLtdcHandler, LayerIndex); +} + +/** + * @brief Disables the color keying without reloading. + * @param ReloadType: can be one of the following values + * - LCD_RELOAD_IMMEDIATE + * - LCD_RELOAD_VERTICAL_BLANKING + * @retval None + */ +void BSP_LCD_Reload(uint32_t ReloadType) +{ + HAL_LTDC_Reload (&hLtdcHandler, ReloadType); +} + +/** + * @brief Sets the LCD text color. + * @param Color: Text color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetTextColor(uint32_t Color) +{ + DrawProp[ActiveLayer].TextColor = Color; +} + +/** + * @brief Gets the LCD text color. + * @retval Used text color. + */ +uint32_t BSP_LCD_GetTextColor(void) +{ + return DrawProp[ActiveLayer].TextColor; +} + +/** + * @brief Sets the LCD background color. + * @param Color: Layer background color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetBackColor(uint32_t Color) +{ + DrawProp[ActiveLayer].BackColor = Color; +} + +/** + * @brief Gets the LCD background color. + * @retval Used background colour + */ +uint32_t BSP_LCD_GetBackColor(void) +{ + return DrawProp[ActiveLayer].BackColor; +} + +/** + * @brief Sets the LCD text font. + * @param fonts: Layer font to be used + * @retval None + */ +void BSP_LCD_SetFont(sFONT *fonts) +{ + DrawProp[ActiveLayer].pFont = fonts; +} + +/** + * @brief Gets the LCD text font. + * @retval Used layer font + */ +sFONT *BSP_LCD_GetFont(void) +{ + return DrawProp[ActiveLayer].pFont; +} + +/** + * @brief Reads an LCD pixel. + * @param Xpos: X position + * @param Ypos: Y position + * @retval RGB pixel color + */ +uint32_t BSP_LCD_ReadPixel(uint16_t Xpos, uint16_t Ypos) +{ + uint32_t ret = 0; + + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))); + } + else if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + /* Read data value from SDRAM memory */ + ret = (*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) & 0x00FFFFFF); + } + else if((hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))); + } + else + { + /* Read data value from SDRAM memory */ + ret = *(__IO uint8_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))); + } + + return ret; +} + +/** + * @brief Clears the hole LCD. + * @param Color: Color of the background + * @retval None + */ +void BSP_LCD_Clear(uint32_t Color) +{ + /* Clear the LCD */ + LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color); +} + +/** + * @brief Clears the selected line. + * @param Line: Line to be cleared + * @retval None + */ +void BSP_LCD_ClearStringLine(uint32_t Line) +{ + uint32_t color_backup = DrawProp[ActiveLayer].TextColor; + DrawProp[ActiveLayer].TextColor = DrawProp[ActiveLayer].BackColor; + + /* Draw rectangle with background color */ + BSP_LCD_FillRect(0, (Line * DrawProp[ActiveLayer].pFont->Height), BSP_LCD_GetXSize(), DrawProp[ActiveLayer].pFont->Height); + + DrawProp[ActiveLayer].TextColor = color_backup; + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); +} + +/** + * @brief Displays one character. + * @param Xpos: Start column address + * @param Ypos: Line where to display the character shape. + * @param Ascii: Character ascii code + * This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E + * @retval None + */ +void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii) +{ + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]); +} + +/** + * @brief Displays characters on the LCD. + * @param Xpos: X position (in pixel) + * @param Ypos: Y position (in pixel) + * @param Text: Pointer to string to display on LCD + * @param Mode: Display mode + * This parameter can be one of the following values: + * @arg CENTER_MODE + * @arg RIGHT_MODE + * @arg LEFT_MODE + * @retval None + */ +void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode) +{ + uint16_t ref_column = 1, i = 0; + uint32_t size = 0, xsize = 0; + uint8_t *ptr = Text; + + /* Get the text size */ + while (*ptr++) size ++ ; + + /* Characters number per line */ + xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width); + + switch (Mode) + { + case CENTER_MODE: + { + ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2; + break; + } + case LEFT_MODE: + { + ref_column = Xpos; + break; + } + case RIGHT_MODE: + { + ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width); + break; + } + default: + { + ref_column = Xpos; + break; + } + } + + /* Check that the Start column is located in the screen */ + if ((ref_column < 1) || (ref_column >= 0x8000)) + { + ref_column = 1; + } + + /* Send the string character by character on LCD */ + while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width)) + { + /* Display one character on LCD */ + BSP_LCD_DisplayChar(ref_column, Ypos, *Text); + /* Decrement the column position by 16 */ + ref_column += DrawProp[ActiveLayer].pFont->Width; + /* Point on the next character */ + Text++; + i++; + } +} + +/** + * @brief Displays a maximum of 60 characters on the LCD. + * @param Line: Line where to display the character shape + * @param ptr: Pointer to string to display on LCD + * @retval None + */ +void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr) +{ + BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE); +} + +/** + * @brief Draws an horizontal line. + * @param Xpos: X position + * @param Ypos: Y position + * @param Length: Line length + * @retval None + */ +void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length) +{ + uint32_t Xaddress = 0; + + /* Get the line address */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + { /* RGB565 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + else + { /* ARGB8888 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + + /* Write line */ + LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor); +} + +/** + * @brief Draws a vertical line. + * @param Xpos: X position + * @param Ypos: Y position + * @param Length: Line length + * @retval None + */ +void BSP_LCD_DrawVLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length) +{ + uint32_t Xaddress = 0; + + /* Get the line address */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + { /* RGB565 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + else + { /* ARGB8888 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + + /* Write line */ + LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, 1, Length, (BSP_LCD_GetXSize() - 1), DrawProp[ActiveLayer].TextColor); +} + +/** + * @brief Draws an uni-line (between two points). + * @param x1: Point 1 X position + * @param y1: Point 1 Y position + * @param x2: Point 2 X position + * @param y2: Point 2 Y position + * @retval None + */ +void BSP_LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) +{ + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, num_add = 0, num_pixels = 0, + curpixel = 0; + + deltax = ABS(x2 - x1); /* The difference between the x's */ + deltay = ABS(y2 - y1); /* The difference between the y's */ + x = x1; /* Start x off at the first pixel */ + y = y1; /* Start y off at the first pixel */ + + if (x2 >= x1) /* The x-values are increasing */ + { + xinc1 = 1; + xinc2 = 1; + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + xinc2 = -1; + } + + if (y2 >= y1) /* The y-values are increasing */ + { + yinc1 = 1; + yinc2 = 1; + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = deltax / 2; + num_add = deltay; + num_pixels = deltax; /* There are more x-values than y-values */ + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = deltay / 2; + num_add = deltax; + num_pixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0; curpixel <= num_pixels; curpixel++) + { + BSP_LCD_DrawPixel(x, y, DrawProp[ActiveLayer].TextColor); /* Draw the current pixel */ + num += num_add; /* Increase the numerator by the top of the fraction */ + if (num >= den) /* Check if numerator >= denominator */ + { + num -= den; /* Calculate the new numerator value */ + x += xinc1; /* Change the x as appropriate */ + y += yinc1; /* Change the y as appropriate */ + } + x += xinc2; /* Change the x as appropriate */ + y += yinc2; /* Change the y as appropriate */ + } +} + +/** + * @brief Draws a rectangle. + * @param Xpos: X position + * @param Ypos: Y position + * @param Width: Rectangle width + * @param Height: Rectangle height + * @retval None + */ +void BSP_LCD_DrawRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + /* Draw horizontal lines */ + BSP_LCD_DrawHLine(Xpos, Ypos, Width); + BSP_LCD_DrawHLine(Xpos, (Ypos+ Height), Width); + + /* Draw vertical lines */ + BSP_LCD_DrawVLine(Xpos, Ypos, Height); + BSP_LCD_DrawVLine((Xpos + Width), Ypos, Height); +} + +/** + * @brief Draws a circle. + * @param Xpos: X position + * @param Ypos: Y position + * @param Radius: Circle radius + * @retval None + */ +void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + decision = 3 - (Radius << 1); + current_x = 0; + current_y = Radius; + + while (current_x <= current_y) + { + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + + if (decision < 0) + { + decision += (current_x << 2) + 6; + } + else + { + decision += ((current_x - current_y) << 2) + 10; + current_y--; + } + current_x++; + } +} + +/** + * @brief Draws an poly-line (between many points). + * @param Points: Pointer to the points array + * @param PointCount: Number of points + * @retval None + */ +void BSP_LCD_DrawPolygon(pPoint Points, uint16_t PointCount) +{ + int16_t x = 0, y = 0; + + if(PointCount < 2) + { + return; + } + + BSP_LCD_DrawLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y); + + while(--PointCount) + { + x = Points->X; + y = Points->Y; + Points++; + BSP_LCD_DrawLine(x, y, Points->X, Points->Y); + } +} + +/** + * @brief Draws an ellipse on LCD. + * @param Xpos: X position + * @param Ypos: Y position + * @param XRadius: Ellipse X radius + * @param YRadius: Ellipse Y radius + * @retval None + */ +void BSP_LCD_DrawEllipse(int Xpos, int Ypos, int XRadius, int YRadius) +{ + int x = 0, y = -YRadius, err = 2-2*XRadius, e2; + float k = 0, rad1 = 0, rad2 = 0; + + rad1 = XRadius; + rad2 = YRadius; + + k = (float)(rad2/rad1); + + do { + BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/k)), (Ypos+y), DrawProp[ActiveLayer].TextColor); + BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/k)), (Ypos+y), DrawProp[ActiveLayer].TextColor); + BSP_LCD_DrawPixel((Xpos+(uint16_t)(x/k)), (Ypos-y), DrawProp[ActiveLayer].TextColor); + BSP_LCD_DrawPixel((Xpos-(uint16_t)(x/k)), (Ypos-y), DrawProp[ActiveLayer].TextColor); + + e2 = err; + if (e2 <= x) { + err += ++x*2+1; + if (-y == x && e2 <= y) e2 = 0; + } + if (e2 > y) err += ++y*2+1; + } + while (y <= 0); +} + +/** + * @brief Draws a pixel on LCD. + * @param Xpos: X position + * @param Ypos: Y position + * @param RGB_Code: Pixel color in ARGB mode (8-8-8-8) + * @retval None + */ +void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code) +{ + /* Write data value to all SDRAM memory */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + { /* RGB565 format */ + *(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code; + } + else + { /* ARGB8888 format */ + *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code; + } +} + +/** + * @brief Draws a bitmap picture loaded in the internal Flash in ARGB888 format (32 bits per pixel). + * @param Xpos: Bmp X position in the LCD + * @param Ypos: Bmp Y position in the LCD + * @param pbmp: Pointer to Bmp picture address in the internal Flash + * @retval None + */ +void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp) +{ + uint32_t index = 0, width = 0, height = 0, bit_pixel = 0; + uint32_t address; + uint32_t input_color_mode = 0; + + /* Get bitmap data address offset */ + index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24); + + /* Read bitmap width */ + width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16) + (pbmp[21] << 24); + + /* Read bitmap height */ + height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16) + (pbmp[25] << 24); + + /* Read bit/pixel */ + bit_pixel = pbmp[28] + (pbmp[29] << 8); + + /* Set the address */ + address = hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4)); + + /* Get the layer pixel format */ + if ((bit_pixel/8) == 4) + { + input_color_mode = CM_ARGB8888; + } + else if ((bit_pixel/8) == 2) + { + input_color_mode = CM_RGB565; + } + else + { + input_color_mode = CM_RGB888; + } + + /* Bypass the bitmap header */ + pbmp += (index + (width * (height - 1) * (bit_pixel/8))); + + /* Convert picture to ARGB8888 pixel format */ + for(index=0; index < height; index++) + { + /* Pixel format conversion */ + LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)address, width, input_color_mode); + + /* Increment the source and destination buffers */ + address+= (BSP_LCD_GetXSize()*4); + pbmp -= width*(bit_pixel/8); + } +} + +/** + * @brief Draws a full rectangle. + * @param Xpos: X position + * @param Ypos: Y position + * @param Width: Rectangle width + * @param Height: Rectangle height + * @retval None + */ +void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height) +{ + uint32_t x_address = 0; + + /* Set the text color */ + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); + + /* Get the rectangle start address */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + { /* RGB565 format */ + x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + else + { /* ARGB8888 format */ + x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos); + } + /* Fill the rectangle */ + LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor); +} + +/** + * @brief Draws a full circle. + * @param Xpos: X position + * @param Ypos: Y position + * @param Radius: Circle radius + * @retval None + */ +void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + decision = 3 - (Radius << 1); + + current_x = 0; + current_y = Radius; + + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); + + while (current_x <= current_y) + { + if(current_y > 0) + { + BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y); + BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y); + } + + if(current_x > 0) + { + BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x); + BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x); + } + if (decision < 0) + { + decision += (current_x << 2) + 6; + } + else + { + decision += ((current_x - current_y) << 2) + 10; + current_y--; + } + current_x++; + } + + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); + BSP_LCD_DrawCircle(Xpos, Ypos, Radius); +} + +/** + * @brief Draws a full poly-line (between many points). + * @param Points: Pointer to the points array + * @param PointCount: Number of points + * @retval None + */ +void BSP_LCD_FillPolygon(pPoint Points, uint16_t PointCount) +{ + int16_t X = 0, Y = 0, X2 = 0, Y2 = 0, X_center = 0, Y_center = 0, X_first = 0, Y_first = 0, pixelX = 0, pixelY = 0, counter = 0; + uint16_t image_left = 0, image_right = 0, image_top = 0, image_bottom = 0; + + image_left = image_right = Points->X; + image_top= image_bottom = Points->Y; + + for(counter = 1; counter < PointCount; counter++) + { + pixelX = POLY_X(counter); + if(pixelX < image_left) + { + image_left = pixelX; + } + if(pixelX > image_right) + { + image_right = pixelX; + } + + pixelY = POLY_Y(counter); + if(pixelY < image_top) + { + image_top = pixelY; + } + if(pixelY > image_bottom) + { + image_bottom = pixelY; + } + } + + if(PointCount < 2) + { + return; + } + + X_center = (image_left + image_right)/2; + Y_center = (image_bottom + image_top)/2; + + X_first = Points->X; + Y_first = Points->Y; + + while(--PointCount) + { + X = Points->X; + Y = Points->Y; + Points++; + X2 = Points->X; + Y2 = Points->Y; + + FillTriangle(X, X2, X_center, Y, Y2, Y_center); + FillTriangle(X, X_center, X2, Y, Y_center, Y2); + FillTriangle(X_center, X2, X, Y_center, Y2, Y); + } + + FillTriangle(X_first, X2, X_center, Y_first, Y2, Y_center); + FillTriangle(X_first, X_center, X2, Y_first, Y_center, Y2); + FillTriangle(X_center, X2, X_first, Y_center, Y2, Y_first); +} + +/** + * @brief Draws a full ellipse. + * @param Xpos: X position + * @param Ypos: Y position + * @param XRadius: Ellipse X radius + * @param YRadius: Ellipse Y radius + * @retval None + */ +void BSP_LCD_FillEllipse(int Xpos, int Ypos, int XRadius, int YRadius) +{ + int x = 0, y = -YRadius, err = 2-2*XRadius, e2; + float k = 0, rad1 = 0, rad2 = 0; + + rad1 = XRadius; + rad2 = YRadius; + + k = (float)(rad2/rad1); + + do + { + BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/k)), (Ypos+y), (2*(uint16_t)(x/k) + 1)); + BSP_LCD_DrawHLine((Xpos-(uint16_t)(x/k)), (Ypos-y), (2*(uint16_t)(x/k) + 1)); + + e2 = err; + if (e2 <= x) + { + err += ++x*2+1; + if (-y == x && e2 <= y) e2 = 0; + } + if (e2 > y) err += ++y*2+1; + } + while (y <= 0); +} + +/** + * @brief Enables the display. + * @retval None + */ +void BSP_LCD_DisplayOn(void) +{ + /* Display On */ + __HAL_LTDC_ENABLE(&hLtdcHandler); + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */ +} + +/** + * @brief Disables the display. + * @retval None + */ +void BSP_LCD_DisplayOff(void) +{ + /* Display Off */ + __HAL_LTDC_DISABLE(&hLtdcHandler); + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_RESET); /* De-assert LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_RESET);/* De-assert LCD_BL_CTRL pin */ +} + +/** + * @brief Initializes the LTDC MSP. + * @param hltdc: LTDC handle + * @param Params + * @retval None + */ +__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the LTDC and DMA2D clocks */ + __HAL_RCC_LTDC_CLK_ENABLE(); + __HAL_RCC_DMA2D_CLK_ENABLE(); + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOJ_CLK_ENABLE(); + __HAL_RCC_GPIOK_CLK_ENABLE(); + LCD_DISP_GPIO_CLK_ENABLE(); + LCD_BL_CTRL_GPIO_CLK_ENABLE(); + + /*** LTDC Pins configuration ***/ + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_4; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_12; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOI LTDC alternate configuration */ + gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + + /* GPIOJ configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \ + GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOJ, &gpio_init_structure); + + /* GPIOK configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOK, &gpio_init_structure); + + /* LCD_DISP GPIO configuration */ + gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */ + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure); + + /* LCD_BL_CTRL GPIO configuration */ + gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */ + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure); +} + +/** + * @brief DeInitializes BSP_LCD MSP. + * @param hltdc: LTDC handle + * @param Params + * @retval None + */ +__weak void BSP_LCD_MspDeInit(LTDC_HandleTypeDef *hltdc, void *Params) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Disable LTDC block */ + __HAL_LTDC_DISABLE(hltdc); + + /* LTDC Pins deactivation */ + + /* GPIOE deactivation */ + gpio_init_structure.Pin = GPIO_PIN_4; + HAL_GPIO_DeInit(GPIOE, gpio_init_structure.Pin); + + /* GPIOG deactivation */ + gpio_init_structure.Pin = GPIO_PIN_12; + HAL_GPIO_DeInit(GPIOG, gpio_init_structure.Pin); + + /* GPIOI deactivation */ + gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_12 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_DeInit(GPIOI, gpio_init_structure.Pin); + + /* GPIOJ deactivation */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \ + GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_DeInit(GPIOJ, gpio_init_structure.Pin); + + /* GPIOK deactivation */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + HAL_GPIO_DeInit(GPIOK, gpio_init_structure.Pin); + + /* Disable LTDC clock */ + __HAL_RCC_LTDC_CLK_DISABLE(); + + /* GPIO pins clock can be shut down in the application + by surcharging this __weak function */ +} + +/** + * @brief Clock Config. + * @param hltdc: LTDC handle + * @param Params + * @note This API is called by BSP_LCD_Init() + * Being __weak it can be overwritten by the application + * @retval None + */ +__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params) +{ + static RCC_PeriphCLKInitTypeDef periph_clk_init_struct; + + /* RK043FN48H LCD clock configuration */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */ + /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */ + periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + periph_clk_init_struct.PLLSAI.PLLSAIN = 192; + periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER; + periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4; + HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct); +} + + +/******************************************************************************* + Static Functions +*******************************************************************************/ + +/** + * @brief Draws a character on LCD. + * @param Xpos: Line where to display the character shape + * @param Ypos: Start column address + * @param c: Pointer to the character data + * @retval None + */ +static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c) +{ + uint32_t i = 0, j = 0; + uint16_t height, width; + uint8_t offset; + uint8_t *pchar; + uint32_t line; + + height = DrawProp[ActiveLayer].pFont->Height; + width = DrawProp[ActiveLayer].pFont->Width; + + offset = 8 *((width + 7)/8) - width ; + + for(i = 0; i < height; i++) + { + pchar = ((uint8_t *)c + (width + 7)/8 * i); + + switch(((width + 7)/8)) + { + + case 1: + line = pchar[0]; + break; + + case 2: + line = (pchar[0]<< 8) | pchar[1]; + break; + + case 3: + default: + line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2]; + break; + } + + for (j = 0; j < width; j++) + { + if(line & (1 << (width- j + offset- 1))) + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor); + } + else + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor); + } + } + Ypos++; + } +} + +/** + * @brief Fills a triangle (between 3 points). + * @param x1: Point 1 X position + * @param y1: Point 1 Y position + * @param x2: Point 2 X position + * @param y2: Point 2 Y position + * @param x3: Point 3 X position + * @param y3: Point 3 Y position + * @retval None + */ +static void FillTriangle(uint16_t x1, uint16_t x2, uint16_t x3, uint16_t y1, uint16_t y2, uint16_t y3) +{ + int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0, + yinc1 = 0, yinc2 = 0, den = 0, num = 0, num_add = 0, num_pixels = 0, + curpixel = 0; + + deltax = ABS(x2 - x1); /* The difference between the x's */ + deltay = ABS(y2 - y1); /* The difference between the y's */ + x = x1; /* Start x off at the first pixel */ + y = y1; /* Start y off at the first pixel */ + + if (x2 >= x1) /* The x-values are increasing */ + { + xinc1 = 1; + xinc2 = 1; + } + else /* The x-values are decreasing */ + { + xinc1 = -1; + xinc2 = -1; + } + + if (y2 >= y1) /* The y-values are increasing */ + { + yinc1 = 1; + yinc2 = 1; + } + else /* The y-values are decreasing */ + { + yinc1 = -1; + yinc2 = -1; + } + + if (deltax >= deltay) /* There is at least one x-value for every y-value */ + { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = deltax / 2; + num_add = deltay; + num_pixels = deltax; /* There are more x-values than y-values */ + } + else /* There is at least one y-value for every x-value */ + { + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = deltay / 2; + num_add = deltax; + num_pixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0; curpixel <= num_pixels; curpixel++) + { + BSP_LCD_DrawLine(x, y, x3, y3); + + num += num_add; /* Increase the numerator by the top of the fraction */ + if (num >= den) /* Check if numerator >= denominator */ + { + num -= den; /* Calculate the new numerator value */ + x += xinc1; /* Change the x as appropriate */ + y += yinc1; /* Change the y as appropriate */ + } + x += xinc2; /* Change the x as appropriate */ + y += yinc2; /* Change the y as appropriate */ + } +} + +/** + * @brief Fills a buffer. + * @param LayerIndex: Layer index + * @param pDst: Pointer to destination buffer + * @param xSize: Buffer width + * @param ySize: Buffer height + * @param OffLine: Offset + * @param ColorIndex: Color index + * @retval None + */ +static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex) +{ + /* Register to memory mode with ARGB8888 as color Mode */ + hDma2dHandler.Init.Mode = DMA2D_R2M; + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + { /* RGB565 format */ + hDma2dHandler.Init.ColorMode = DMA2D_RGB565; + } + else + { /* ARGB8888 format */ + hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888; + } + hDma2dHandler.Init.OutputOffset = OffLine; + + hDma2dHandler.Instance = DMA2D; + + /* DMA2D Initialization */ + if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK) + { + if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK) + { + if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK) + { + /* Polling For DMA transfer */ + HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10); + } + } + } +} + +/** + * @brief Converts a line to an ARGB8888 pixel format. + * @param pSrc: Pointer to source buffer + * @param pDst: Output color + * @param xSize: Buffer width + * @param ColorMode: Input color mode + * @retval None + */ +static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode) +{ + /* Configure the DMA2D Mode, Color Mode and output offset */ + hDma2dHandler.Init.Mode = DMA2D_M2M_PFC; + hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888; + hDma2dHandler.Init.OutputOffset = 0; + + /* Foreground Configuration */ + hDma2dHandler.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + hDma2dHandler.LayerCfg[1].InputAlpha = 0xFF; + hDma2dHandler.LayerCfg[1].InputColorMode = ColorMode; + hDma2dHandler.LayerCfg[1].InputOffset = 0; + + hDma2dHandler.Instance = DMA2D; + + /* DMA2D Initialization */ + if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK) + { + if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, 1) == HAL_OK) + { + if (HAL_DMA2D_Start(&hDma2dHandler, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK) + { + /* Polling For DMA transfer */ + HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32746g_discovery_sdram.c b/Core/Src/stm32746g_discovery_sdram.c new file mode 100644 index 0000000..67ad028 --- /dev/null +++ b/Core/Src/stm32746g_discovery_sdram.c @@ -0,0 +1,497 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.c + * @author MCD Application Team + * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory + * device mounted on STM32746G-Discovery board. + @verbatim + 1. How To use this driver: + -------------------------- + - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted + on STM32746G-Discovery board. + - This driver does not need a specific component driver for the SDRAM device + to be included with. + + 2. Driver description: + --------------------- + + Initialization steps: + o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This + function includes the MSP layer hardware resources initialization and the + FMC controller configuration to interface with the external SDRAM memory. + o It contains the SDRAM initialization sequence to program the SDRAM external + device using the function BSP_SDRAM_Initialization_sequence(). Note that this + sequence is standard for all SDRAM devices, but can include some differences + from a device to another. If it is the case, the right sequence should be + implemented separately. + + + SDRAM read/write operations + o SDRAM external memory can be accessed with read/write operations once it is + initialized. + Read/write operation can be performed with AHB access using the functions + BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions + BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). + o The AHB access is performed with 32-bit width transaction, the DMA transfer + configuration is fixed at single (no burst) word transfer (see the + SDRAM_MspInit() static function). + o User can implement his own functions for read/write access with his desired + configurations. + o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() + is called in IRQ handler file, to serve the generated interrupt once the DMA + transfer is complete. + o You can send a command to the SDRAM device in runtime using the function + BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between + the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Dependencies +- stm32f7xx_hal_sdram.c +- stm32f7xx_ll_fmc.c +- stm32f7xx_hal_dma.c +- stm32f7xx_hal_gpio.c +- stm32f7xx_hal_cortex.c +- stm32f7xx_hal_rcc_ex.h +EndDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery_sdram.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables + * @{ + */ +SDRAM_HandleTypeDef sdramHandle; +static FMC_SDRAM_TimingTypeDef Timing; +static FMC_SDRAM_CommandTypeDef Command; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions + * @{ + */ + +/** + * @brief Initializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Init(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device configuration */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ + Timing.LoadToActiveDelay = 2; + Timing.ExitSelfRefreshDelay = 7; + Timing.SelfRefreshTime = 4; + Timing.RowCycleDelay = 7; + Timing.WriteRecoveryTime = 2; + Timing.RPDelay = 2; + Timing.RCDDelay = 2; + + sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; + sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + + /* SDRAM controller initialization */ + + BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + + if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + + return sdramstatus; +} + +/** + * @brief DeInitializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_DeInit(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device de-initialization */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM controller de-initialization */ + BSP_SDRAM_MspDeInit(&sdramHandle, NULL); + + return sdramstatus; +} + +/** + * @brief Programs the SDRAM device. + * @param RefreshCount: SDRAM refresh counter value + * @retval None + */ +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +{ + __IO uint32_t tmpmrd = 0; + + /* Step 1: Configure a clock configuration enable command */ + Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + + /* Step 3: Configure a PALL (precharge all) command */ + Command.CommandMode = FMC_SDRAM_CMD_PALL; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 4: Configure an Auto Refresh command */ + Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 8; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = tmpmrd; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); +} + +/** + * @brief Reads an amount of data from the SDRAM memory in polling mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Reads an amount of data from the SDRAM memory in DMA mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in polling mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in DMA mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Sends command to the SDRAM bank. + * @param SdramCmd: Pointer to SDRAM command structure + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) +{ + if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Initializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF12_FMC; + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + dma_handle.Init.Mode = DMA_NORMAL; + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + + dma_handle.Instance = SDRAM_DMAx_STREAM; + + /* Associate the DMA handle */ + __HAL_LINKDMA(hsdram, hdma, dma_handle); + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); +} + +/** + * @brief DeInitializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + + /* Disable NVIC configuration for DMA interrupt */ + HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); + + /* Deinitialize the stream for new transfer */ + dma_handle.Instance = SDRAM_DMAx_STREAM; + HAL_DMA_DeInit(&dma_handle); + + /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications + by surcharging this __weak function */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32746g_discovery_ts.c b/Core/Src/stm32746g_discovery_ts.c new file mode 100644 index 0000000..4bc8ad4 --- /dev/null +++ b/Core/Src/stm32746g_discovery_ts.c @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_ts.c + * @author MCD Application Team + * @brief This file provides a set of functions needed to manage the Touch + * Screen on STM32746G-Discovery board. + @verbatim + 1. How To use this driver: + -------------------------- + - This driver is used to drive the touch screen module of the STM32746G-Discovery + board on the RK043FN48H-CT672B 480x272 LCD screen with capacitive touch screen. + - The FT5336 component driver must be included in project files according to + the touch screen driver present on this board. + + 2. Driver description: + --------------------- + + Initialization steps: + o Initialize the TS module using the BSP_TS_Init() function. This + function includes the MSP layer hardware resources initialization and the + communication layer configuration to start the TS use. The LCD size properties + (x and y) are passed as parameters. + o If TS interrupt mode is desired, you must configure the TS interrupt mode + by calling the function BSP_TS_ITConfig(). The TS interrupt mode is generated + as an external interrupt whenever a touch is detected. + The interrupt mode internally uses the IO functionalities driver driven by + the IO expander, to configure the IT line. + + + Touch screen use + o The touch screen state is captured whenever the function BSP_TS_GetState() is + used. This function returns information about the last LCD touch occurred + in the TS_StateTypeDef structure. + o If TS interrupt mode is used, the function BSP_TS_ITGetStatus() is needed to get + the interrupt status. To clear the IT pending bits, you should call the + function BSP_TS_ITClear(). + o The IT is handled using the corresponding external interrupt IRQ handler, + the user IT callback treatment is implemented on the same external interrupt + callback. + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Dependencies +- stm32746g_discovery_lcd.c +- ft5336.c +EndDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery_ts.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_TS STM32746G_DISCOVERY_TS + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Private_Types_Definitions STM32746G_DISCOVERY_TS Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Private_Defines STM32746G_DISCOVERY_TS Types Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Private_Macros STM32746G_DISCOVERY_TS Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Imported_Variables STM32746G_DISCOVERY_TS Imported Variables + * @{ + */ + /** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Private_Variables STM32746G_DISCOVERY_TS Private Variables + * @{ + */ +static TS_DrvTypeDef *tsDriver; +static uint16_t tsXBoundary, tsYBoundary; +static uint8_t tsOrientation; +static uint8_t I2cAddress; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Private_Function_Prototypes STM32746G_DISCOVERY_TS Private Function Prototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_TS_Exported_Functions STM32746G_DISCOVERY_TS Exported Functions + * @{ + */ + +/** + * @brief Initializes and configures the touch screen functionalities and + * configures all necessary hardware resources (GPIOs, I2C, clocks..). + * @param ts_SizeX: Maximum X size of the TS area on LCD + * @param ts_SizeY: Maximum Y size of the TS area on LCD + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY) +{ + uint8_t status = TS_OK; + tsXBoundary = ts_SizeX; + tsYBoundary = ts_SizeY; + + /* Read ID and verify if the touch screen driver is ready */ + ft5336_ts_drv.Init(TS_I2C_ADDRESS); + if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE) + { + /* Initialize the TS driver structure */ + tsDriver = &ft5336_ts_drv; + I2cAddress = TS_I2C_ADDRESS; + tsOrientation = TS_SWAP_XY; + + /* Initialize the TS driver */ + tsDriver->Start(I2cAddress); + } + else + { + status = TS_DEVICE_NOT_FOUND; + } + + return status; +} + +/** + * @brief DeInitializes the TouchScreen. + * @retval TS state + */ +uint8_t BSP_TS_DeInit(void) +{ + /* Actually ts_driver does not provide a DeInit function */ + return TS_OK; +} + +/** + * @brief Configures and enables the touch screen interrupts. + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_ITConfig(void) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Configure Interrupt mode for SD detection pin */ + gpio_init_structure.Pin = TS_INT_PIN; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Mode = GPIO_MODE_IT_RISING; + HAL_GPIO_Init(TS_INT_GPIO_PORT, &gpio_init_structure); + + /* Enable and set Touch screen EXTI Interrupt to the lowest priority */ + HAL_NVIC_SetPriority((IRQn_Type)(TS_INT_EXTI_IRQn), 0x0F, 0x00); + HAL_NVIC_EnableIRQ((IRQn_Type)(TS_INT_EXTI_IRQn)); + + /* Enable the TS ITs */ + tsDriver->EnableIT(I2cAddress); + + return TS_OK; +} + +/** + * @brief Gets the touch screen interrupt status. + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_ITGetStatus(void) +{ + /* Return the TS IT status */ + return (tsDriver->GetITStatus(I2cAddress)); +} + +/** + * @brief Returns status and positions of the touch screen. + * @param TS_State: Pointer to touch screen current state structure + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State) +{ + static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0}; + static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0}; + uint8_t ts_status = TS_OK; + uint16_t x[TS_MAX_NB_TOUCH]; + uint16_t y[TS_MAX_NB_TOUCH]; + uint16_t brute_x[TS_MAX_NB_TOUCH]; + uint16_t brute_y[TS_MAX_NB_TOUCH]; + uint16_t x_diff; + uint16_t y_diff; + uint32_t index; +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + uint32_t weight = 0; + uint32_t area = 0; + uint32_t event = 0; +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + + /* Check and update the number of touches active detected */ + TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress); + + if(TS_State->touchDetected) + { + for(index=0; index < TS_State->touchDetected; index++) + { + /* Get each touch coordinates */ + tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index])); + + if(tsOrientation == TS_SWAP_NONE) + { + x[index] = brute_x[index]; + y[index] = brute_y[index]; + } + + if(tsOrientation & TS_SWAP_X) + { + x[index] = 4096 - brute_x[index]; + } + + if(tsOrientation & TS_SWAP_Y) + { + y[index] = 4096 - brute_y[index]; + } + + if(tsOrientation & TS_SWAP_XY) + { + y[index] = brute_x[index]; + x[index] = brute_y[index]; + } + + x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]); + y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]); + + if ((x_diff + y_diff) > 5) + { + _x[index] = x[index]; + _y[index] = y[index]; + } + + if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS) + { + TS_State->touchX[index] = x[index]; + TS_State->touchY[index] = y[index]; + } + else + { + /* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */ + TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12; + TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12; + } + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + + /* Get touch info related to the current touch */ + ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event); + + /* Update TS_State structure */ + TS_State->touchWeight[index] = weight; + TS_State->touchArea[index] = area; + + /* Remap touch event */ + switch(event) + { + case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN : + TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN; + break; + case FT5336_TOUCH_EVT_FLAG_LIFT_UP : + TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP; + break; + case FT5336_TOUCH_EVT_FLAG_CONTACT : + TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT; + break; + case FT5336_TOUCH_EVT_FLAG_NO_EVENT : + TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT; + break; + default : + ts_status = TS_ERROR; + break; + } /* of switch(event) */ + +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + + } /* of for(index=0; index < TS_State->touchDetected; index++) */ + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + /* Get gesture Id */ + ts_status = BSP_TS_Get_GestureId(TS_State); +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + + } /* end of if(TS_State->touchDetected != 0) */ + + return (ts_status); +} + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) +/** + * @brief Update gesture Id following a touch detected. + * @param TS_State: Pointer to touch screen current state structure + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State) +{ + uint32_t gestureId = 0; + uint8_t ts_status = TS_OK; + + /* Get gesture Id */ + ft5336_TS_GetGestureID(I2cAddress, &gestureId); + + /* Remap gesture Id to a TS_GestureIdTypeDef value */ + switch(gestureId) + { + case FT5336_GEST_ID_NO_GESTURE : + TS_State->gestureId = GEST_ID_NO_GESTURE; + break; + case FT5336_GEST_ID_MOVE_UP : + TS_State->gestureId = GEST_ID_MOVE_UP; + break; + case FT5336_GEST_ID_MOVE_RIGHT : + TS_State->gestureId = GEST_ID_MOVE_RIGHT; + break; + case FT5336_GEST_ID_MOVE_DOWN : + TS_State->gestureId = GEST_ID_MOVE_DOWN; + break; + case FT5336_GEST_ID_MOVE_LEFT : + TS_State->gestureId = GEST_ID_MOVE_LEFT; + break; + case FT5336_GEST_ID_ZOOM_IN : + TS_State->gestureId = GEST_ID_ZOOM_IN; + break; + case FT5336_GEST_ID_ZOOM_OUT : + TS_State->gestureId = GEST_ID_ZOOM_OUT; + break; + default : + ts_status = TS_ERROR; + break; + } /* of switch(gestureId) */ + + return(ts_status); +} +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + +/** + * @brief Clears all touch screen interrupts. + */ +void BSP_TS_ITClear(void) +{ + /* Clear TS IT pending bits */ + tsDriver->ClearIT(I2cAddress); +} + + +/** @defgroup STM32756G_DISCOVERY_TS_Private_Functions TS Private Functions + * @{ + */ + + +/** + * @brief Function used to reset all touch data before a new acquisition + * of touch information. + * @param TS_State: Pointer to touch screen current state structure + * @retval TS_OK if OK, TE_ERROR if problem found. + */ +uint8_t BSP_TS_ResetTouchData(TS_StateTypeDef *TS_State) +{ + uint8_t ts_status = TS_ERROR; + uint32_t index; + + if (TS_State != (TS_StateTypeDef *)NULL) + { + TS_State->gestureId = GEST_ID_NO_GESTURE; + TS_State->touchDetected = 0; + + for(index = 0; index < TS_MAX_NB_TOUCH; index++) + { + TS_State->touchX[index] = 0; + TS_State->touchY[index] = 0; + TS_State->touchArea[index] = 0; + TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT; + TS_State->touchWeight[index] = 0; + } + + ts_status = TS_OK; + + } /* of if (TS_State != (TS_StateTypeDef *)NULL) */ + + return (ts_status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f7xx_hal_msp.c b/Core/Src/stm32f7xx_hal_msp.c new file mode 100644 index 0000000..f093a70 --- /dev/null +++ b/Core/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,1253 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA0/WKUP ------> ADC1_IN0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspInit 0 */ + + /* USER CODE END ADC3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC3_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**ADC3 GPIO Configuration + PF10 ------> ADC3_IN8 + PF9 ------> ADC3_IN7 + PF8 ------> ADC3_IN6 + */ + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC3_MspInit 1 */ + + /* USER CODE END ADC3_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA0/WKUP ------> ADC1_IN0 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + else if(hadc->Instance==ADC3) + { + /* USER CODE BEGIN ADC3_MspDeInit 0 */ + + /* USER CODE END ADC3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC3_CLK_DISABLE(); + + /**ADC3 GPIO Configuration + PF10 ------> ADC3_IN8 + PF9 ------> ADC3_IN7 + PF8 ------> ADC3_IN6 + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8); + + /* USER CODE BEGIN ADC3_MspDeInit 1 */ + + /* USER CODE END ADC3_MspDeInit 1 */ + } + +} + +/** +* @brief DAC MSP Initialization +* This function configures the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hdac->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspInit 0 */ + + /* USER CODE END DAC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DAC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* DAC interrupt Init */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* USER CODE BEGIN DAC_MspInit 1 */ + + /* USER CODE END DAC_MspInit 1 */ + } + +} + +/** +* @brief DAC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + if(hdac->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspDeInit 0 */ + + /* USER CODE END DAC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC_CLK_DISABLE(); + + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4); + + /* DAC interrupt DeInit */ + HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn); + /* USER CODE BEGIN DAC_MspDeInit 1 */ + + /* USER CODE END DAC_MspDeInit 1 */ + } + +} + +/** +* @brief DMA2D MSP Initialization +* This function configures the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspInit 0 */ + + /* USER CODE END DMA2D_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DMA2D_CLK_ENABLE(); + /* USER CODE BEGIN DMA2D_MspInit 1 */ + + /* USER CODE END DMA2D_MspInit 1 */ + } + +} + +/** +* @brief DMA2D MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +{ + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspDeInit 0 */ + + /* USER CODE END DMA2D_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DMA2D_CLK_DISABLE(); + /* USER CODE BEGIN DMA2D_MspDeInit 1 */ + + /* USER CODE END DMA2D_MspDeInit 1 */ + } + +} + +/** +* @brief I2C MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + else if(hi2c->Instance==I2C3) + { + /* USER CODE BEGIN I2C3_MspInit 0 */ + + /* USER CODE END I2C3_MspInit 0 */ + + __HAL_RCC_GPIOH_CLK_ENABLE(); + /**I2C3 GPIO Configuration + PH7 ------> I2C3_SCL + PH8 ------> I2C3_SDA + */ + GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C3_CLK_ENABLE(); + /* USER CODE BEGIN I2C3_MspInit 1 */ + + /* USER CODE END I2C3_MspInit 1 */ + } + +} + +/** +* @brief I2C MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(ARDUINO_SCL_D15_GPIO_Port, ARDUINO_SCL_D15_Pin); + + HAL_GPIO_DeInit(ARDUINO_SDA_D14_GPIO_Port, ARDUINO_SDA_D14_Pin); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + else if(hi2c->Instance==I2C3) + { + /* USER CODE BEGIN I2C3_MspDeInit 0 */ + + /* USER CODE END I2C3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C3_CLK_DISABLE(); + + /**I2C3 GPIO Configuration + PH7 ------> I2C3_SCL + PH8 ------> I2C3_SDA + */ + HAL_GPIO_DeInit(LCD_SCL_GPIO_Port, LCD_SCL_Pin); + + HAL_GPIO_DeInit(LCD_SDA_GPIO_Port, LCD_SDA_Pin); + + /* USER CODE BEGIN I2C3_MspDeInit 1 */ + + /* USER CODE END I2C3_MspDeInit 1 */ + } + +} + +/** +* @brief LTDC MSP Initialization +* This function configures the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspInit 0 */ + + /* USER CODE END LTDC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOJ_CLK_ENABLE(); + __HAL_RCC_GPIOK_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PJ13 ------> LTDC_B1 + PK7 ------> LTDC_DE + PK6 ------> LTDC_B7 + PK5 ------> LTDC_B6 + PG12 ------> LTDC_B4 + PJ14 ------> LTDC_B2 + PI10 ------> LTDC_HSYNC + PK4 ------> LTDC_B5 + PJ15 ------> LTDC_B3 + PI9 ------> LTDC_VSYNC + PK1 ------> LTDC_G6 + PK2 ------> LTDC_G7 + PI15 ------> LTDC_R0 + PJ11 ------> LTDC_G4 + PK0 ------> LTDC_G5 + PI14 ------> LTDC_CLK + PJ8 ------> LTDC_G1 + PJ10 ------> LTDC_G3 + PJ7 ------> LTDC_G0 + PJ9 ------> LTDC_G2 + PJ6 ------> LTDC_R7 + PJ4 ------> LTDC_R5 + PJ5 ------> LTDC_R6 + PJ3 ------> LTDC_R4 + PJ2 ------> LTDC_R3 + PJ0 ------> LTDC_R1 + PJ1 ------> LTDC_R2 + */ + GPIO_InitStruct.Pin = LCD_B0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin + |LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin + |LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin + |LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin + |LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LCD_B4_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* LTDC interrupt Init */ + HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(LTDC_IRQn); + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } + +} + +/** +* @brief LTDC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspDeInit 0 */ + + /* USER CODE END LTDC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LTDC_CLK_DISABLE(); + + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PJ13 ------> LTDC_B1 + PK7 ------> LTDC_DE + PK6 ------> LTDC_B7 + PK5 ------> LTDC_B6 + PG12 ------> LTDC_B4 + PJ14 ------> LTDC_B2 + PI10 ------> LTDC_HSYNC + PK4 ------> LTDC_B5 + PJ15 ------> LTDC_B3 + PI9 ------> LTDC_VSYNC + PK1 ------> LTDC_G6 + PK2 ------> LTDC_G7 + PI15 ------> LTDC_R0 + PJ11 ------> LTDC_G4 + PK0 ------> LTDC_G5 + PI14 ------> LTDC_CLK + PJ8 ------> LTDC_G1 + PJ10 ------> LTDC_G3 + PJ7 ------> LTDC_G0 + PJ9 ------> LTDC_G2 + PJ6 ------> LTDC_R7 + PJ4 ------> LTDC_R5 + PJ5 ------> LTDC_R6 + PJ3 ------> LTDC_R4 + PJ2 ------> LTDC_R3 + PJ0 ------> LTDC_R1 + PJ1 ------> LTDC_R2 + */ + HAL_GPIO_DeInit(LCD_B0_GPIO_Port, LCD_B0_Pin); + + HAL_GPIO_DeInit(GPIOJ, LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin + |LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin + |LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin + |LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin); + + HAL_GPIO_DeInit(GPIOK, LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin + |LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin); + + HAL_GPIO_DeInit(LCD_B4_GPIO_Port, LCD_B4_Pin); + + HAL_GPIO_DeInit(GPIOI, LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin); + + /* LTDC interrupt DeInit */ + HAL_NVIC_DisableIRQ(LTDC_IRQn); + /* USER CODE BEGIN LTDC_MspDeInit 1 */ + + /* USER CODE END LTDC_MspDeInit 1 */ + } + +} + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PI1 ------> SPI2_SCK + PI0 ------> SPI2_NSS + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PI1 ------> SPI2_SCK + PI0 ------> SPI2_NSS + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOI, ARDUINO_SCK_D13_Pin|GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + +/** +* @brief TIM_Base MSP Initialization +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspInit 0 */ + + /* USER CODE END TIM5_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM5_CLK_ENABLE(); + /* USER CODE BEGIN TIM5_MspInit 1 */ + + /* USER CODE END TIM5_MspInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspInit 0 */ + + /* USER CODE END TIM8_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM8_CLK_ENABLE(); + /* USER CODE BEGIN TIM8_MspInit 1 */ + + /* USER CODE END TIM8_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(htim->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PB4 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + else if(htim->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspPostInit 0 */ + + /* USER CODE END TIM8_MspPostInit 0 */ + + __HAL_RCC_GPIOI_CLK_ENABLE(); + /**TIM8 GPIO Configuration + PI2 ------> TIM8_CH4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM8; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM8_MspPostInit 1 */ + + /* USER CODE END TIM8_MspPostInit 1 */ + } + +} +/** +* @brief TIM_Base MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM5) + { + /* USER CODE BEGIN TIM5_MspDeInit 0 */ + + /* USER CODE END TIM5_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM5_CLK_DISABLE(); + /* USER CODE BEGIN TIM5_MspDeInit 1 */ + + /* USER CODE END TIM5_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspDeInit 0 */ + + /* USER CODE END TIM8_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM8_CLK_DISABLE(); + /* USER CODE BEGIN TIM8_MspDeInit 1 */ + + /* USER CODE END TIM8_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==UART7) + { + /* USER CODE BEGIN UART7_MspInit 0 */ + + /* USER CODE END UART7_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_UART7_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**UART7 GPIO Configuration + PF7 ------> UART7_TX + PF6 ------> UART7_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART7; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* USER CODE BEGIN UART7_MspInit 1 */ + + /* USER CODE END UART7_MspInit 1 */ + } + else if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = VCP_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = VCP_TX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART6 GPIO Configuration + PC7 ------> USART6_RX + PC6 ------> USART6_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==UART7) + { + /* USER CODE BEGIN UART7_MspDeInit 0 */ + + /* USER CODE END UART7_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART7_CLK_DISABLE(); + + /**UART7 GPIO Configuration + PF7 ------> UART7_TX + PF6 ------> UART7_RX + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_6); + + /* USER CODE BEGIN UART7_MspDeInit 1 */ + + /* USER CODE END UART7_MspDeInit 1 */ + } + else if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + HAL_GPIO_DeInit(VCP_RX_GPIO_Port, VCP_RX_Pin); + + HAL_GPIO_DeInit(VCP_TX_GPIO_Port, VCP_TX_Pin); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspDeInit 0 */ + + /* USER CODE END USART6_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART6_CLK_DISABLE(); + + /**USART6 GPIO Configuration + PC7 ------> USART6_RX + PC6 ------> USART6_TX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7|GPIO_PIN_6); + + /* USER CODE BEGIN USART6_MspDeInit 1 */ + + /* USER CODE END USART6_MspDeInit 1 */ + } + +} + +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + if (FMC_Initialized) { + return; + } + FMC_Initialized = 1; + + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /** FMC GPIO Configuration + PE1 ------> FMC_NBL1 + PE0 ------> FMC_NBL0 + PG15 ------> FMC_SDNCAS + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PG8 ------> FMC_SDCLK + PF4 ------> FMC_A4 + PH5 ------> FMC_SDNWE + PH3 ------> FMC_SDNE0 + PF5 ------> FMC_A5 + PD15 ------> FMC_D1 + PD10 ------> FMC_D15 + PC3 ------> FMC_SDCKE0 + PD14 ------> FMC_D0 + PD9 ------> FMC_D14 + PD8 ------> FMC_D13 + PF12 ------> FMC_A6 + PG1 ------> FMC_A11 + PF15 ------> FMC_A9 + PF13 ------> FMC_A7 + PG0 ------> FMC_A10 + PE8 ------> FMC_D5 + PG5 ------> FMC_BA1 + PG4 ------> FMC_BA0 + PF14 ------> FMC_A8 + PF11 ------> FMC_SDNRAS + PE9 ------> FMC_D6 + PE11 ------> FMC_D8 + PE14 ------> FMC_D11 + PE7 ------> FMC_D4 + PE10 ------> FMC_D7 + PE12 ------> FMC_D9 + PE15 ------> FMC_D12 + PE13 ------> FMC_D10 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + |GPIO_PIN_5|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ + /* USER CODE BEGIN SDRAM_MspInit 0 */ + + /* USER CODE END SDRAM_MspInit 0 */ + HAL_FMC_MspInit(); + /* USER CODE BEGIN SDRAM_MspInit 1 */ + + /* USER CODE END SDRAM_MspInit 1 */ +} + +static uint32_t FMC_DeInitialized = 0; + +static void HAL_FMC_MspDeInit(void){ + /* USER CODE BEGIN FMC_MspDeInit 0 */ + + /* USER CODE END FMC_MspDeInit 0 */ + if (FMC_DeInitialized) { + return; + } + FMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_DISABLE(); + + /** FMC GPIO Configuration + PE1 ------> FMC_NBL1 + PE0 ------> FMC_NBL0 + PG15 ------> FMC_SDNCAS + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PG8 ------> FMC_SDCLK + PF4 ------> FMC_A4 + PH5 ------> FMC_SDNWE + PH3 ------> FMC_SDNE0 + PF5 ------> FMC_A5 + PD15 ------> FMC_D1 + PD10 ------> FMC_D15 + PC3 ------> FMC_SDCKE0 + PD14 ------> FMC_D0 + PD9 ------> FMC_D14 + PD8 ------> FMC_D13 + PF12 ------> FMC_A6 + PG1 ------> FMC_A11 + PF15 ------> FMC_A9 + PF13 ------> FMC_A7 + PG0 ------> FMC_A10 + PE8 ------> FMC_D5 + PG5 ------> FMC_BA1 + PG4 ------> FMC_BA0 + PF14 ------> FMC_A8 + PF11 ------> FMC_SDNRAS + PE9 ------> FMC_D6 + PE11 ------> FMC_D8 + PE14 ------> FMC_D11 + PE7 ------> FMC_D4 + PE10 ------> FMC_D7 + PE12 ------> FMC_D9 + PE15 ------> FMC_D12 + PE13 ------> FMC_D10 + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + |GPIO_PIN_5|GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3); + + /* USER CODE BEGIN FMC_MspDeInit 1 */ + + /* USER CODE END FMC_MspDeInit 1 */ +} + +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){ + /* USER CODE BEGIN SDRAM_MspDeInit 0 */ + + /* USER CODE END SDRAM_MspDeInit 0 */ + HAL_FMC_MspDeInit(); + /* USER CODE BEGIN SDRAM_MspDeInit 1 */ + + /* USER CODE END SDRAM_MspDeInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f7xx_hal_timebase_tim.c b/Core/Src/stm32f7xx_hal_timebase_tim.c new file mode 100644 index 0000000..84ba798 --- /dev/null +++ b/Core/Src/stm32f7xx_hal_timebase_tim.c @@ -0,0 +1,111 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_timebase_TIM.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim6; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock = 0; + uint32_t uwPrescalerValue = 0; + uint32_t pFLatency; + /*Configure the TIM6 IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Compute TIM6 clock */ + uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + if(HAL_TIM_Base_Init(&htim6) == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + return HAL_TIM_Base_Start_IT(&htim6); + } + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/stm32f7xx_it.c b/Core/Src/stm32f7xx_it.c new file mode 100644 index 0000000..f9e65e3 --- /dev/null +++ b/Core/Src/stm32f7xx_it.c @@ -0,0 +1,197 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern DAC_HandleTypeDef hdac; +extern LTDC_HandleTypeDef hltdc; +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_DAC_IRQHandler(&hdac); + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/** + * @brief This function handles LTDC global interrupt. + */ +void LTDC_IRQHandler(void) +{ + /* USER CODE BEGIN LTDC_IRQn 0 */ + + /* USER CODE END LTDC_IRQn 0 */ + HAL_LTDC_IRQHandler(&hltdc); + /* USER CODE BEGIN LTDC_IRQn 1 */ + + /* USER CODE END LTDC_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..4ec9584 --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,159 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char * stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..d7cc52c --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,80 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/system_stm32f7xx.c b/Core/Src/system_stm32f7xx.c new file mode 100644 index 0000000..7282bc8 --- /dev/null +++ b/Core/Src/system_stm32f7xx.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Core/Startup/startup_stm32f746nghx.s b/Core/Startup/startup_stm32f746nghx.s new file mode 100644 index 0000000..0a42af5 --- /dev/null +++ b/Core/Startup/startup_stm32f746nghx.s @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file startup_stm32f746xx.s + * @author MCD Application Team + * @brief STM32F746xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Debug/Core/Src/freertos.d b/Debug/Core/Src/freertos.d new file mode 100644 index 0000000..bc7b019 --- /dev/null +++ b/Debug/Core/Src/freertos.d @@ -0,0 +1,159 @@ +Core/Src/freertos.o: ../Core/Src/freertos.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Core/Inc/main.h ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Core/Inc/main.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/freertos.o b/Debug/Core/Src/freertos.o new file mode 100644 index 0000000..99a0a60 Binary files /dev/null and b/Debug/Core/Src/freertos.o differ diff --git a/Debug/Core/Src/freertos.su b/Debug/Core/Src/freertos.su new file mode 100644 index 0000000..631af39 --- /dev/null +++ b/Debug/Core/Src/freertos.su @@ -0,0 +1,4 @@ +freertos.c:65:13:vApplicationIdleHook 4 static +freertos.c:80:13:vApplicationStackOverflowHook 16 static +freertos.c:89:13:vApplicationMallocFailedHook 4 static +freertos.c:108:6:vApplicationGetIdleTaskMemory 24 static diff --git a/Debug/Core/Src/ft5336.d b/Debug/Core/Src/ft5336.d new file mode 100644 index 0000000..a92d7dc --- /dev/null +++ b/Debug/Core/Src/ft5336.d @@ -0,0 +1,6 @@ +Core/Src/ft5336.o: ../Core/Src/ft5336.c ../Core/Inc/ft5336.h \ + ../Core/Inc/ts.h + +../Core/Inc/ft5336.h: + +../Core/Inc/ts.h: diff --git a/Debug/Core/Src/ft5336.o b/Debug/Core/Src/ft5336.o new file mode 100644 index 0000000..933d3f2 Binary files /dev/null and b/Debug/Core/Src/ft5336.o differ diff --git a/Debug/Core/Src/ft5336.su b/Debug/Core/Src/ft5336.su new file mode 100644 index 0000000..88c19b0 --- /dev/null +++ b/Debug/Core/Src/ft5336.su @@ -0,0 +1,15 @@ +ft5336.c:147:6:ft5336_Init 16 static +ft5336.c:163:6:ft5336_Reset 16 static +ft5336.c:175:10:ft5336_ReadID 24 static +ft5336.c:207:6:ft5336_TS_Start 16 static +ft5336.c:224:9:ft5336_TS_DetectTouch 24 static +ft5336.c:256:6:ft5336_TS_GetXY 32 static +ft5336.c:377:6:ft5336_TS_EnableIT 24 static +ft5336.c:392:6:ft5336_TS_DisableIT 24 static +ft5336.c:409:9:ft5336_TS_ITStatus 16 static +ft5336.c:422:6:ft5336_TS_ClearIT 16 static +ft5336.c:437:6:ft5336_TS_GetGestureID 24 static +ft5336.c:461:6:ft5336_TS_GetTouchInfo 32 static +ft5336.c:570:16:ft5336_Get_I2C_InitializedStatus 4 static +ft5336.c:580:13:ft5336_I2C_InitializeIfRequired 8 static +ft5336.c:597:17:ft5336_TS_Configure 24 static diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d new file mode 100644 index 0000000..a68d336 --- /dev/null +++ b/Debug/Core/Src/main.d @@ -0,0 +1,204 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Core/Inc/stm32746g_discovery_lcd.h ../Core/Inc/rk043fn48h.h \ + ../Core/Inc/stm32746g_discovery_sdram.h \ + ../Core/Inc/stm32746g_discovery.h ../Core/Inc/../../Fonts/fonts.h \ + ../Core/Inc/stm32746g_discovery_ts.h ../Core/Inc/ft5336.h \ + ../Core/Inc/ts.h + +../Core/Inc/main.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: + +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Core/Inc/stm32746g_discovery_lcd.h: + +../Core/Inc/rk043fn48h.h: + +../Core/Inc/stm32746g_discovery_sdram.h: + +../Core/Inc/stm32746g_discovery.h: + +../Core/Inc/../../Fonts/fonts.h: + +../Core/Inc/stm32746g_discovery_ts.h: + +../Core/Inc/ft5336.h: + +../Core/Inc/ts.h: diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o new file mode 100644 index 0000000..f0eed21 Binary files /dev/null and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su new file mode 100644 index 0000000..cd9558b --- /dev/null +++ b/Debug/Core/Src/main.su @@ -0,0 +1,24 @@ +main.c:115:5:main 136 static +main.c:255:6:SystemClock_Config 216 static +main.c:330:13:MX_ADC1_Init 24 static +main.c:380:13:MX_ADC3_Init 24 static +main.c:430:13:MX_DAC_Init 16 static +main.c:468:13:MX_DMA2D_Init 8 static +main.c:505:13:MX_I2C1_Init 8 static +main.c:551:13:MX_I2C3_Init 8 static +main.c:597:13:MX_LTDC_Init 64 static +main.c:659:13:MX_RTC_Init 80 static +main.c:751:13:MX_SPI2_Init 8 static +main.c:791:13:MX_TIM1_Init 40 static +main.c:838:13:MX_TIM2_Init 40 static +main.c:883:13:MX_TIM3_Init 88 static +main.c:949:13:MX_TIM5_Init 40 static +main.c:994:13:MX_TIM8_Init 112 static +main.c:1073:13:MX_UART7_Init 8 static +main.c:1108:13:MX_USART1_UART_Init 8 static +main.c:1143:13:MX_USART6_UART_Init 8 static +main.c:1174:13:MX_FMC_Init 40 static +main.c:1225:13:MX_GPIO_Init 72 static +main.c:1412:6:StartDefaultTask 16 static +main.c:1431:6:HAL_TIM_PeriodElapsedCallback 16 static +main.c:1448:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Debug/Core/Src/stm32746g_discovery.d b/Debug/Core/Src/stm32746g_discovery.d new file mode 100644 index 0000000..1c81ae0 --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery.d @@ -0,0 +1,133 @@ +Core/Src/stm32746g_discovery.o: ../Core/Src/stm32746g_discovery.c \ + ../Core/Inc/stm32746g_discovery.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Core/Inc/stm32746g_discovery.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/stm32746g_discovery.o b/Debug/Core/Src/stm32746g_discovery.o new file mode 100644 index 0000000..d440a2c Binary files /dev/null and b/Debug/Core/Src/stm32746g_discovery.o differ diff --git a/Debug/Core/Src/stm32746g_discovery.su b/Debug/Core/Src/stm32746g_discovery.su new file mode 100644 index 0000000..6c405c3 --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery.su @@ -0,0 +1,34 @@ +stm32746g_discovery.c:178:10:BSP_GetVersion 4 static +stm32746g_discovery.c:190:6:BSP_LED_Init 48 static +stm32746g_discovery.c:222:6:BSP_LED_DeInit 40 static +stm32746g_discovery.c:245:6:BSP_LED_On 24 static +stm32746g_discovery.c:263:6:BSP_LED_Off 24 static +stm32746g_discovery.c:281:6:BSP_LED_Toggle 24 static +stm32746g_discovery.c:309:6:BSP_PB_Init 48 static +stm32746g_discovery.c:363:6:BSP_PB_DeInit 40 static +stm32746g_discovery.c:385:10:BSP_PB_GetState 16 static +stm32746g_discovery.c:400:6:BSP_COM_Init 48 static +stm32746g_discovery.c:440:6:BSP_COM_DeInit 16 static +stm32746g_discovery.c:466:13:I2Cx_MspInit 56 static +stm32746g_discovery.c:553:13:I2Cx_Init 16 static +stm32746g_discovery.c:591:26:I2Cx_ReadMultiple 48 static +stm32746g_discovery.c:621:26:I2Cx_WriteMultiple 48 static +stm32746g_discovery.c:649:26:I2Cx_IsDeviceReady 24 static +stm32746g_discovery.c:660:13:I2Cx_Error 16 static +stm32746g_discovery.c:679:6:AUDIO_IO_Init 8 static +stm32746g_discovery.c:688:6:AUDIO_IO_DeInit 4 static +stm32746g_discovery.c:699:6:AUDIO_IO_Write 32 static +stm32746g_discovery.c:716:10:AUDIO_IO_Read 32 static +stm32746g_discovery.c:736:6:AUDIO_IO_Delay 16 static +stm32746g_discovery.c:747:6:CAMERA_IO_Init 8 static +stm32746g_discovery.c:759:6:CAMERA_IO_Write 24 static +stm32746g_discovery.c:770:9:CAMERA_IO_Read 32 static +stm32746g_discovery.c:784:6:CAMERA_Delay 16 static +stm32746g_discovery.c:795:6:EEPROM_IO_Init 8 static +stm32746g_discovery.c:808:19:EEPROM_IO_WriteData 32 static +stm32746g_discovery.c:821:19:EEPROM_IO_ReadData 32 static +stm32746g_discovery.c:833:19:EEPROM_IO_IsDeviceReady 16 static +stm32746g_discovery.c:844:6:TS_IO_Init 8 static +stm32746g_discovery.c:856:6:TS_IO_Write 24 static +stm32746g_discovery.c:867:9:TS_IO_Read 32 static +stm32746g_discovery.c:881:6:TS_IO_Delay 16 static diff --git a/Debug/Core/Src/stm32746g_discovery_lcd.d b/Debug/Core/Src/stm32746g_discovery_lcd.d new file mode 100644 index 0000000..2e22b6c --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_lcd.d @@ -0,0 +1,161 @@ +Core/Src/stm32746g_discovery_lcd.o: ../Core/Src/stm32746g_discovery_lcd.c \ + ../Core/Inc/stm32746g_discovery_lcd.h ../Core/Inc/rk043fn48h.h \ + ../Core/Inc/stm32746g_discovery_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Core/Inc/stm32746g_discovery.h ../Core/Inc/../../Fonts/fonts.h \ + ../Core/Src/../../Fonts/fonts.h ../Core/Src/../../Fonts/font24.c \ + ../Core/Src/../../Fonts/fonts.h ../Core/Src/../../Fonts/font20.c \ + ../Core/Src/../../Fonts/font16.c ../Core/Src/../../Fonts/font12.c \ + ../Core/Src/../../Fonts/font8.c + +../Core/Inc/stm32746g_discovery_lcd.h: + +../Core/Inc/rk043fn48h.h: + +../Core/Inc/stm32746g_discovery_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: + +../Core/Inc/stm32746g_discovery.h: + +../Core/Inc/../../Fonts/fonts.h: + +../Core/Src/../../Fonts/fonts.h: + +../Core/Src/../../Fonts/font24.c: + +../Core/Src/../../Fonts/fonts.h: + +../Core/Src/../../Fonts/font20.c: + +../Core/Src/../../Fonts/font16.c: + +../Core/Src/../../Fonts/font12.c: + +../Core/Src/../../Fonts/font8.c: diff --git a/Debug/Core/Src/stm32746g_discovery_lcd.o b/Debug/Core/Src/stm32746g_discovery_lcd.o new file mode 100644 index 0000000..637ae9a Binary files /dev/null and b/Debug/Core/Src/stm32746g_discovery_lcd.o differ diff --git a/Debug/Core/Src/stm32746g_discovery_lcd.su b/Debug/Core/Src/stm32746g_discovery_lcd.su new file mode 100644 index 0000000..6a3f22e --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_lcd.su @@ -0,0 +1,56 @@ +stm32746g_discovery_lcd.c:164:9:BSP_LCD_Init 8 static +stm32746g_discovery_lcd.c:226:9:BSP_LCD_DeInit 8 static +stm32746g_discovery_lcd.c:247:10:BSP_LCD_GetXSize 4 static +stm32746g_discovery_lcd.c:256:10:BSP_LCD_GetYSize 4 static +stm32746g_discovery_lcd.c:266:6:BSP_LCD_SetXSize 16 static +stm32746g_discovery_lcd.c:276:6:BSP_LCD_SetYSize 16 static +stm32746g_discovery_lcd.c:287:6:BSP_LCD_LayerDefaultInit 72 static +stm32746g_discovery_lcd.c:321:6:BSP_LCD_LayerRgb565Init 72 static +stm32746g_discovery_lcd.c:354:6:BSP_LCD_SelectLayer 16 static +stm32746g_discovery_lcd.c:368:6:BSP_LCD_SetLayerVisible 16 static +stm32746g_discovery_lcd.c:390:6:BSP_LCD_SetLayerVisible_NoReload 16 static +stm32746g_discovery_lcd.c:410:6:BSP_LCD_SetTransparency 16 static +stm32746g_discovery_lcd.c:422:6:BSP_LCD_SetTransparency_NoReload 16 static +stm32746g_discovery_lcd.c:433:6:BSP_LCD_SetLayerAddress 16 static +stm32746g_discovery_lcd.c:444:6:BSP_LCD_SetLayerAddress_NoReload 16 static +stm32746g_discovery_lcd.c:458:6:BSP_LCD_SetLayerWindow 24 static +stm32746g_discovery_lcd.c:476:6:BSP_LCD_SetLayerWindow_NoReload 24 static +stm32746g_discovery_lcd.c:491:6:BSP_LCD_SetColorKeying 16 static +stm32746g_discovery_lcd.c:504:6:BSP_LCD_SetColorKeying_NoReload 16 static +stm32746g_discovery_lcd.c:516:6:BSP_LCD_ResetColorKeying 16 static +stm32746g_discovery_lcd.c:527:6:BSP_LCD_ResetColorKeying_NoReload 16 static +stm32746g_discovery_lcd.c:540:6:BSP_LCD_Reload 16 static +stm32746g_discovery_lcd.c:550:6:BSP_LCD_SetTextColor 16 static +stm32746g_discovery_lcd.c:559:10:BSP_LCD_GetTextColor 4 static +stm32746g_discovery_lcd.c:569:6:BSP_LCD_SetBackColor 16 static +stm32746g_discovery_lcd.c:578:10:BSP_LCD_GetBackColor 4 static +stm32746g_discovery_lcd.c:588:6:BSP_LCD_SetFont 16 static +stm32746g_discovery_lcd.c:597:8:BSP_LCD_GetFont 4 static +stm32746g_discovery_lcd.c:608:10:BSP_LCD_ReadPixel 32 static +stm32746g_discovery_lcd.c:643:6:BSP_LCD_Clear 40 static +stm32746g_discovery_lcd.c:654:6:BSP_LCD_ClearStringLine 32 static +stm32746g_discovery_lcd.c:674:6:BSP_LCD_DisplayChar 24 static +stm32746g_discovery_lcd.c:692:6:BSP_LCD_DisplayStringAt 48 static +stm32746g_discovery_lcd.c:753:6:BSP_LCD_DisplayStringAtLine 16 static +stm32746g_discovery_lcd.c:765:6:BSP_LCD_DrawHLine 40 static +stm32746g_discovery_lcd.c:790:6:BSP_LCD_DrawVLine 48 static +stm32746g_discovery_lcd.c:816:6:BSP_LCD_DrawLine 56 static +stm32746g_discovery_lcd.c:891:6:BSP_LCD_DrawRect 24 static +stm32746g_discovery_lcd.c:909:6:BSP_LCD_DrawCircle 40 static +stm32746g_discovery_lcd.c:956:6:BSP_LCD_DrawPolygon 32 static +stm32746g_discovery_lcd.c:984:6:BSP_LCD_DrawEllipse 64 static +stm32746g_discovery_lcd.c:1017:6:BSP_LCD_DrawPixel 24 static +stm32746g_discovery_lcd.c:1037:6:BSP_LCD_DrawBitmap 56 static +stm32746g_discovery_lcd.c:1095:6:BSP_LCD_FillRect 48 static +stm32746g_discovery_lcd.c:1122:6:BSP_LCD_FillCircle 32 static +stm32746g_discovery_lcd.c:1170:6:BSP_LCD_FillPolygon 64 static +stm32746g_discovery_lcd.c:1238:6:BSP_LCD_FillEllipse 56 static +stm32746g_discovery_lcd.c:1268:6:BSP_LCD_DisplayOn 8 static +stm32746g_discovery_lcd.c:1280:6:BSP_LCD_DisplayOff 8 static +stm32746g_discovery_lcd.c:1294:13:BSP_LCD_MspInit 72 static +stm32746g_discovery_lcd.c:1366:13:BSP_LCD_MspDeInit 40 static +stm32746g_discovery_lcd.c:1415:13:BSP_LCD_ClockConfig 16 static +stm32746g_discovery_lcd.c:1443:13:DrawChar 40 static +stm32746g_discovery_lcd.c:1502:13:FillTriangle 56 static +stm32746g_discovery_lcd.c:1580:13:LL_FillBuffer 32 static +stm32746g_discovery_lcd.c:1618:13:LL_ConvertLineToARGB8888 32 static diff --git a/Debug/Core/Src/stm32746g_discovery_sdram.d b/Debug/Core/Src/stm32746g_discovery_sdram.d new file mode 100644 index 0000000..80a054d --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_sdram.d @@ -0,0 +1,134 @@ +Core/Src/stm32746g_discovery_sdram.o: \ + ../Core/Src/stm32746g_discovery_sdram.c \ + ../Core/Inc/stm32746g_discovery_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Core/Inc/stm32746g_discovery_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/stm32746g_discovery_sdram.o b/Debug/Core/Src/stm32746g_discovery_sdram.o new file mode 100644 index 0000000..12dbfe2 Binary files /dev/null and b/Debug/Core/Src/stm32746g_discovery_sdram.o differ diff --git a/Debug/Core/Src/stm32746g_discovery_sdram.su b/Debug/Core/Src/stm32746g_discovery_sdram.su new file mode 100644 index 0000000..e0d71e7 --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_sdram.su @@ -0,0 +1,10 @@ +stm32746g_discovery_sdram.c:146:9:BSP_SDRAM_Init 8 static +stm32746g_discovery_sdram.c:195:9:BSP_SDRAM_DeInit 8 static +stm32746g_discovery_sdram.c:221:6:BSP_SDRAM_Initialization_sequence 24 static +stm32746g_discovery_sdram.c:283:9:BSP_SDRAM_ReadData 24 static +stm32746g_discovery_sdram.c:302:9:BSP_SDRAM_ReadData_DMA 24 static +stm32746g_discovery_sdram.c:321:9:BSP_SDRAM_WriteData 24 static +stm32746g_discovery_sdram.c:340:9:BSP_SDRAM_WriteData_DMA 24 static +stm32746g_discovery_sdram.c:357:9:BSP_SDRAM_Sendcmd 16 static +stm32746g_discovery_sdram.c:375:13:BSP_SDRAM_MspInit 72 static +stm32746g_discovery_sdram.c:466:13:BSP_SDRAM_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32746g_discovery_ts.d b/Debug/Core/Src/stm32746g_discovery_ts.d new file mode 100644 index 0000000..85b0c78 --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_ts.d @@ -0,0 +1,140 @@ +Core/Src/stm32746g_discovery_ts.o: ../Core/Src/stm32746g_discovery_ts.c \ + ../Core/Inc/stm32746g_discovery_ts.h ../Core/Inc/stm32746g_discovery.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Core/Inc/ft5336.h ../Core/Inc/ts.h + +../Core/Inc/stm32746g_discovery_ts.h: + +../Core/Inc/stm32746g_discovery.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: + +../Core/Inc/ft5336.h: + +../Core/Inc/ts.h: diff --git a/Debug/Core/Src/stm32746g_discovery_ts.o b/Debug/Core/Src/stm32746g_discovery_ts.o new file mode 100644 index 0000000..8ca6743 Binary files /dev/null and b/Debug/Core/Src/stm32746g_discovery_ts.o differ diff --git a/Debug/Core/Src/stm32746g_discovery_ts.su b/Debug/Core/Src/stm32746g_discovery_ts.su new file mode 100644 index 0000000..4a67c7f --- /dev/null +++ b/Debug/Core/Src/stm32746g_discovery_ts.su @@ -0,0 +1,8 @@ +stm32746g_discovery_ts.c:146:9:BSP_TS_Init 24 static +stm32746g_discovery_ts.c:176:9:BSP_TS_DeInit 4 static +stm32746g_discovery_ts.c:186:9:BSP_TS_ITConfig 32 static +stm32746g_discovery_ts.c:211:9:BSP_TS_ITGetStatus 8 static +stm32746g_discovery_ts.c:222:9:BSP_TS_GetState 104 static +stm32746g_discovery_ts.c:342:9:BSP_TS_Get_GestureId 24 static +stm32746g_discovery_ts.c:386:6:BSP_TS_ITClear 8 static +stm32746g_discovery_ts.c:404:9:BSP_TS_ResetTouchData 24 static diff --git a/Debug/Core/Src/stm32f7xx_hal_msp.d b/Debug/Core/Src/stm32f7xx_hal_msp.d new file mode 100644 index 0000000..0103ec0 --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_hal_msp.d @@ -0,0 +1,132 @@ +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Core/Inc/main.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/stm32f7xx_hal_msp.o b/Debug/Core/Src/stm32f7xx_hal_msp.o new file mode 100644 index 0000000..9ff5c9c Binary files /dev/null and b/Debug/Core/Src/stm32f7xx_hal_msp.o differ diff --git a/Debug/Core/Src/stm32f7xx_hal_msp.su b/Debug/Core/Src/stm32f7xx_hal_msp.su new file mode 100644 index 0000000..ef8ee3e --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_hal_msp.su @@ -0,0 +1,24 @@ +stm32f7xx_hal_msp.c:66:6:HAL_MspInit 16 static +stm32f7xx_hal_msp.c:90:6:HAL_ADC_MspInit 56 static +stm32f7xx_hal_msp.c:146:6:HAL_ADC_MspDeInit 16 static +stm32f7xx_hal_msp.c:193:6:HAL_DAC_MspInit 48 static +stm32f7xx_hal_msp.c:229:6:HAL_DAC_MspDeInit 16 static +stm32f7xx_hal_msp.c:259:6:HAL_DMA2D_MspInit 24 static +stm32f7xx_hal_msp.c:281:6:HAL_DMA2D_MspDeInit 16 static +stm32f7xx_hal_msp.c:303:6:HAL_I2C_MspInit 56 static +stm32f7xx_hal_msp.c:363:6:HAL_I2C_MspDeInit 16 static +stm32f7xx_hal_msp.c:414:6:HAL_LTDC_MspInit 64 static +stm32f7xx_hal_msp.c:515:6:HAL_LTDC_MspDeInit 16 static +stm32f7xx_hal_msp.c:584:6:HAL_RTC_MspInit 16 static +stm32f7xx_hal_msp.c:606:6:HAL_RTC_MspDeInit 16 static +stm32f7xx_hal_msp.c:628:6:HAL_SPI_MspInit 48 static +stm32f7xx_hal_msp.c:681:6:HAL_SPI_MspDeInit 16 static +stm32f7xx_hal_msp.c:714:6:HAL_TIM_Base_MspInit 40 static +stm32f7xx_hal_msp.c:774:6:HAL_TIM_MspPostInit 48 static +stm32f7xx_hal_msp.c:826:6:HAL_TIM_Base_MspDeInit 16 static +stm32f7xx_hal_msp.c:892:6:HAL_UART_MspInit 64 static +stm32f7xx_hal_msp.c:984:6:HAL_UART_MspDeInit 16 static +stm32f7xx_hal_msp.c:1047:13:HAL_FMC_MspInit 32 static +stm32f7xx_hal_msp.c:1153:6:HAL_SDRAM_MspInit 16 static +stm32f7xx_hal_msp.c:1165:13:HAL_FMC_MspDeInit 8 static +stm32f7xx_hal_msp.c:1239:6:HAL_SDRAM_MspDeInit 16 static diff --git a/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d new file mode 100644 index 0000000..7a90751 --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.d @@ -0,0 +1,131 @@ +Core/Src/stm32f7xx_hal_timebase_tim.o: \ + ../Core/Src/stm32f7xx_hal_timebase_tim.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o new file mode 100644 index 0000000..4ed8c41 Binary files /dev/null and b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.o differ diff --git a/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su new file mode 100644 index 0000000..3138172 --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_hal_timebase_tim.su @@ -0,0 +1,3 @@ +stm32f7xx_hal_timebase_tim.c:42:19:HAL_InitTick 56 static +stm32f7xx_hal_timebase_tim.c:93:6:HAL_SuspendTick 4 static +stm32f7xx_hal_timebase_tim.c:105:6:HAL_ResumeTick 4 static diff --git a/Debug/Core/Src/stm32f7xx_it.d b/Debug/Core/Src/stm32f7xx_it.d new file mode 100644 index 0000000..5f20399 --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_it.d @@ -0,0 +1,135 @@ +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + ../Core/Inc/stm32f7xx_it.h + +../Core/Inc/main.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: + +../Core/Inc/stm32f7xx_it.h: diff --git a/Debug/Core/Src/stm32f7xx_it.o b/Debug/Core/Src/stm32f7xx_it.o new file mode 100644 index 0000000..78ce64f Binary files /dev/null and b/Debug/Core/Src/stm32f7xx_it.o differ diff --git a/Debug/Core/Src/stm32f7xx_it.su b/Debug/Core/Src/stm32f7xx_it.su new file mode 100644 index 0000000..7e0660e --- /dev/null +++ b/Debug/Core/Src/stm32f7xx_it.su @@ -0,0 +1,8 @@ +stm32f7xx_it.c:73:6:NMI_Handler 4 static +stm32f7xx_it.c:88:6:HardFault_Handler 4 static +stm32f7xx_it.c:103:6:MemManage_Handler 4 static +stm32f7xx_it.c:118:6:BusFault_Handler 4 static +stm32f7xx_it.c:133:6:UsageFault_Handler 4 static +stm32f7xx_it.c:148:6:DebugMon_Handler 4 static +stm32f7xx_it.c:168:6:TIM6_DAC_IRQHandler 8 static +stm32f7xx_it.c:183:6:LTDC_IRQHandler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..77d6a3c --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,79 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/freertos.c \ +../Core/Src/ft5336.c \ +../Core/Src/main.c \ +../Core/Src/stm32746g_discovery.c \ +../Core/Src/stm32746g_discovery_lcd.c \ +../Core/Src/stm32746g_discovery_sdram.c \ +../Core/Src/stm32746g_discovery_ts.c \ +../Core/Src/stm32f7xx_hal_msp.c \ +../Core/Src/stm32f7xx_hal_timebase_tim.c \ +../Core/Src/stm32f7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32f7xx.c + +OBJS += \ +./Core/Src/freertos.o \ +./Core/Src/ft5336.o \ +./Core/Src/main.o \ +./Core/Src/stm32746g_discovery.o \ +./Core/Src/stm32746g_discovery_lcd.o \ +./Core/Src/stm32746g_discovery_sdram.o \ +./Core/Src/stm32746g_discovery_ts.o \ +./Core/Src/stm32f7xx_hal_msp.o \ +./Core/Src/stm32f7xx_hal_timebase_tim.o \ +./Core/Src/stm32f7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32f7xx.o + +C_DEPS += \ +./Core/Src/freertos.d \ +./Core/Src/ft5336.d \ +./Core/Src/main.d \ +./Core/Src/stm32746g_discovery.d \ +./Core/Src/stm32746g_discovery_lcd.d \ +./Core/Src/stm32746g_discovery_sdram.d \ +./Core/Src/stm32746g_discovery_ts.d \ +./Core/Src/stm32f7xx_hal_msp.d \ +./Core/Src/stm32f7xx_hal_timebase_tim.d \ +./Core/Src/stm32f7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32f7xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/freertos.o: ../Core/Src/freertos.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/freertos.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/ft5336.o: ../Core/Src/ft5336.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/ft5336.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/main.o: ../Core/Src/main.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32746g_discovery.o: ../Core/Src/stm32746g_discovery.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32746g_discovery.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32746g_discovery_lcd.o: ../Core/Src/stm32746g_discovery_lcd.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32746g_discovery_lcd.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32746g_discovery_sdram.o: ../Core/Src/stm32746g_discovery_sdram.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32746g_discovery_sdram.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32746g_discovery_ts.o: ../Core/Src/stm32746g_discovery_ts.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32746g_discovery_ts.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_hal_msp.o: ../Core/Src/stm32f7xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_hal_timebase_tim.o: ../Core/Src/stm32f7xx_hal_timebase_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_hal_timebase_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f7xx_it.o: ../Core/Src/stm32f7xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f7xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f7xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..b1f3a2e Binary files /dev/null and b/Debug/Core/Src/syscalls.o differ diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..492a785 --- /dev/null +++ b/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +syscalls.c:48:6:initialise_monitor_handles 4 static +syscalls.c:52:5:_getpid 4 static +syscalls.c:57:5:_kill 16 static +syscalls.c:63:6:_exit 16 static +syscalls.c:69:27:_read 32 static +syscalls.c:81:27:_write 32 static +syscalls.c:92:5:_close 16 static +syscalls.c:98:5:_fstat 16 static +syscalls.c:104:5:_isatty 16 static +syscalls.c:109:5:_lseek 24 static +syscalls.c:114:5:_open 12 static +syscalls.c:120:5:_wait 16 static +syscalls.c:126:5:_unlink 16 static +syscalls.c:132:5:_times 16 static +syscalls.c:137:5:_stat 16 static +syscalls.c:143:5:_link 16 static +syscalls.c:149:5:_fork 8 static +syscalls.c:155:5:_execve 24 static diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..394553a Binary files /dev/null and b/Debug/Core/Src/sysmem.o differ diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..4474c68 --- /dev/null +++ b/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +sysmem.c:54:7:_sbrk 32 static diff --git a/Debug/Core/Src/system_stm32f7xx.d b/Debug/Core/Src/system_stm32f7xx.d new file mode 100644 index 0000000..5bb8f64 --- /dev/null +++ b/Debug/Core/Src/system_stm32f7xx.d @@ -0,0 +1,130 @@ +Core/Src/system_stm32f7xx.o: ../Core/Src/system_stm32f7xx.c \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Core/Src/system_stm32f7xx.o b/Debug/Core/Src/system_stm32f7xx.o new file mode 100644 index 0000000..ba14dc2 Binary files /dev/null and b/Debug/Core/Src/system_stm32f7xx.o differ diff --git a/Debug/Core/Src/system_stm32f7xx.su b/Debug/Core/Src/system_stm32f7xx.su new file mode 100644 index 0000000..4f5210b --- /dev/null +++ b/Debug/Core/Src/system_stm32f7xx.su @@ -0,0 +1,2 @@ +system_stm32f7xx.c:134:6:SystemInit 4 static +system_stm32f7xx.c:185:6:SystemCoreClockUpdate 32 static diff --git a/Debug/Core/Startup/startup_stm32f746nghx.d b/Debug/Core/Startup/startup_stm32f746nghx.d new file mode 100644 index 0000000..d288a1a --- /dev/null +++ b/Debug/Core/Startup/startup_stm32f746nghx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32f746nghx.o: \ + ../Core/Startup/startup_stm32f746nghx.s diff --git a/Debug/Core/Startup/startup_stm32f746nghx.o b/Debug/Core/Startup/startup_stm32f746nghx.o new file mode 100644 index 0000000..a1997ea Binary files /dev/null and b/Debug/Core/Startup/startup_stm32f746nghx.o differ diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..165f761 --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32f746nghx.s + +OBJS += \ +./Core/Startup/startup_stm32f746nghx.o + +S_DEPS += \ +./Core/Startup/startup_stm32f746nghx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/startup_stm32f746nghx.o: ../Core/Startup/startup_stm32f746nghx.s + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32f746nghx.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d new file mode 100644 index 0000000..eee271e --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o new file mode 100644 index 0000000..520107a Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su new file mode 100644 index 0000000..832be7c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.su @@ -0,0 +1,29 @@ +stm32f7xx_hal.c:138:19:HAL_Init 8 static +stm32f7xx_hal.c:168:19:HAL_DeInit 8 static +stm32f7xx_hal.c:197:13:HAL_MspInit 4 static +stm32f7xx_hal.c:208:13:HAL_MspDeInit 4 static +stm32f7xx_hal.c:231:26:HAL_InitTick 16 static +stm32f7xx_hal.c:290:13:HAL_IncTick 4 static +stm32f7xx_hal.c:301:17:HAL_GetTick 4 static +stm32f7xx_hal.c:310:10:HAL_GetTickPrio 4 static +stm32f7xx_hal.c:319:19:HAL_SetTickFreq 24 static +stm32f7xx_hal.c:351:21:HAL_GetTickFreq 4 static +stm32f7xx_hal.c:367:13:HAL_Delay 24 static +stm32f7xx_hal.c:393:13:HAL_SuspendTick 4 static +stm32f7xx_hal.c:409:13:HAL_ResumeTick 4 static +stm32f7xx_hal.c:419:10:HAL_GetHalVersion 4 static +stm32f7xx_hal.c:428:10:HAL_GetREVID 4 static +stm32f7xx_hal.c:437:10:HAL_GetDEVID 4 static +stm32f7xx_hal.c:446:10:HAL_GetUIDw0 4 static +stm32f7xx_hal.c:455:10:HAL_GetUIDw1 4 static +stm32f7xx_hal.c:464:10:HAL_GetUIDw2 4 static +stm32f7xx_hal.c:473:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +stm32f7xx_hal.c:482:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +stm32f7xx_hal.c:491:6:HAL_DBGMCU_EnableDBGStopMode 4 static +stm32f7xx_hal.c:500:6:HAL_DBGMCU_DisableDBGStopMode 4 static +stm32f7xx_hal.c:509:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +stm32f7xx_hal.c:518:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static +stm32f7xx_hal.c:529:6:HAL_EnableCompensationCell 4 static +stm32f7xx_hal.c:540:6:HAL_DisableCompensationCell 4 static +stm32f7xx_hal.c:553:6:HAL_EnableFMCMemorySwapping 4 static +stm32f7xx_hal.c:566:6:HAL_DisableFMCMemorySwapping 4 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.d new file mode 100644 index 0000000..076962c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o new file mode 100644 index 0000000..b150667 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.su new file mode 100644 index 0000000..1dc1d4d --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.su @@ -0,0 +1,26 @@ +stm32f7xx_hal_adc.c:322:19:HAL_ADC_Init 24 static +stm32f7xx_hal_adc.c:416:19:HAL_ADC_DeInit 24 static +stm32f7xx_hal_adc.c:473:13:HAL_ADC_MspInit 16 static +stm32f7xx_hal_adc.c:488:13:HAL_ADC_MspDeInit 16 static +stm32f7xx_hal_adc.c:730:19:HAL_ADC_Start 24 static +stm32f7xx_hal_adc.c:843:19:HAL_ADC_Stop 16 static +stm32f7xx_hal_adc.c:886:19:HAL_ADC_PollForConversion 24 static +stm32f7xx_hal_adc.c:971:19:HAL_ADC_PollForEvent 32 static +stm32f7xx_hal_adc.c:1033:19:HAL_ADC_Start_IT 24 static +stm32f7xx_hal_adc.c:1148:19:HAL_ADC_Stop_IT 16 static +stm32f7xx_hal_adc.c:1185:6:HAL_ADC_IRQHandler 24 static +stm32f7xx_hal_adc.c:1347:19:HAL_ADC_Start_DMA 32 static +stm32f7xx_hal_adc.c:1477:19:HAL_ADC_Stop_DMA 24 static +stm32f7xx_hal_adc.c:1523:10:HAL_ADC_GetValue 16 static +stm32f7xx_hal_adc.c:1535:13:HAL_ADC_ConvCpltCallback 16 static +stm32f7xx_hal_adc.c:1550:13:HAL_ADC_ConvHalfCpltCallback 16 static +stm32f7xx_hal_adc.c:1565:13:HAL_ADC_LevelOutOfWindowCallback 16 static +stm32f7xx_hal_adc.c:1586:13:HAL_ADC_ErrorCallback 16 static +stm32f7xx_hal_adc.c:1624:19:HAL_ADC_ConfigChannel 24 static +stm32f7xx_hal_adc.c:1745:19:HAL_ADC_AnalogWDGConfig 16 static +stm32f7xx_hal_adc.c:1827:10:HAL_ADC_GetState 16 static +stm32f7xx_hal_adc.c:1839:10:HAL_ADC_GetError 16 static +stm32f7xx_hal_adc.c:1865:13:ADC_Init 16 static +stm32f7xx_hal_adc.c:1946:13:ADC_DMAConvCplt 24 static +stm32f7xx_hal_adc.c:2015:13:ADC_DMAHalfConvCplt 24 static +stm32f7xx_hal_adc.c:2032:13:ADC_DMAError 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.d new file mode 100644 index 0000000..0f98675 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o new file mode 100644 index 0000000..5c46197 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.su new file mode 100644 index 0000000..30b1698 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.su @@ -0,0 +1,15 @@ +stm32f7xx_hal_adc_ex.c:147:19:HAL_ADCEx_InjectedStart 32 static +stm32f7xx_hal_adc_ex.c:236:19:HAL_ADCEx_InjectedStart_IT 32 static +stm32f7xx_hal_adc_ex.c:333:19:HAL_ADCEx_InjectedStop 24 static +stm32f7xx_hal_adc_ex.c:387:19:HAL_ADCEx_InjectedPollForConversion 24 static +stm32f7xx_hal_adc_ex.c:454:19:HAL_ADCEx_InjectedStop_IT 24 static +stm32f7xx_hal_adc_ex.c:516:10:HAL_ADCEx_InjectedGetValue 24 static +stm32f7xx_hal_adc_ex.c:567:19:HAL_ADCEx_MultiModeStart_DMA 32 static +stm32f7xx_hal_adc_ex.c:680:19:HAL_ADCEx_MultiModeStop_DMA 24 static +stm32f7xx_hal_adc_ex.c:727:10:HAL_ADCEx_MultiModeGetValue 16 static +stm32f7xx_hal_adc_ex.c:739:13:HAL_ADCEx_InjectedConvCpltCallback 16 static +stm32f7xx_hal_adc_ex.c:756:19:HAL_ADCEx_InjectedConfigChannel 16 static +stm32f7xx_hal_adc_ex.c:912:19:HAL_ADCEx_MultiModeConfigChannel 16 static +stm32f7xx_hal_adc_ex.c:951:13:ADC_MultiModeDMAConvCplt 24 static +stm32f7xx_hal_adc_ex.c:1004:13:ADC_MultiModeDMAHalfConvCplt 24 static +stm32f7xx_hal_adc_ex.c:1017:13:ADC_MultiModeDMAError 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d new file mode 100644 index 0000000..1891e19 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o new file mode 100644 index 0000000..ffaef6f Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su new file mode 100644 index 0000000..1eb1222 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.su @@ -0,0 +1,32 @@ +core_cm7.h:1865:22:__NVIC_SetPriorityGrouping 24 static +core_cm7.h:1884:26:__NVIC_GetPriorityGrouping 4 static +core_cm7.h:1896:22:__NVIC_EnableIRQ 16 static +core_cm7.h:1932:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +core_cm7.h:1951:26:__NVIC_GetPendingIRQ 16 static +core_cm7.h:1970:22:__NVIC_SetPendingIRQ 16 static +core_cm7.h:1985:22:__NVIC_ClearPendingIRQ 16 static +core_cm7.h:2002:26:__NVIC_GetActive 16 static +core_cm7.h:2024:22:__NVIC_SetPriority 16 static +core_cm7.h:2046:26:__NVIC_GetPriority 16 static +core_cm7.h:2071:26:NVIC_EncodePriority 40 static +core_cm7.h:2098:22:NVIC_DecodePriority 40 static +core_cm7.h:2147:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +core_cm7.h:2564:26:SysTick_Config 16 static +stm32f7xx_hal_cortex.c:143:6:HAL_NVIC_SetPriorityGrouping 16 static +stm32f7xx_hal_cortex.c:165:6:HAL_NVIC_SetPriority 32 static +stm32f7xx_hal_cortex.c:187:6:HAL_NVIC_EnableIRQ 16 static +stm32f7xx_hal_cortex.c:203:6:HAL_NVIC_DisableIRQ 16 static +stm32f7xx_hal_cortex.c:216:6:HAL_NVIC_SystemReset 8 static +stm32f7xx_hal_cortex.c:229:10:HAL_SYSTICK_Config 16 static +stm32f7xx_hal_cortex.c:258:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +stm32f7xx_hal_cortex.c:281:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +stm32f7xx_hal_cortex.c:300:6:HAL_MPU_ConfigRegion 16 static +stm32f7xx_hal_cortex.c:344:10:HAL_NVIC_GetPriorityGrouping 8 static +stm32f7xx_hal_cortex.c:371:6:HAL_NVIC_GetPriority 24 static +stm32f7xx_hal_cortex.c:386:6:HAL_NVIC_SetPendingIRQ 16 static +stm32f7xx_hal_cortex.c:404:10:HAL_NVIC_GetPendingIRQ 16 static +stm32f7xx_hal_cortex.c:420:6:HAL_NVIC_ClearPendingIRQ 16 static +stm32f7xx_hal_cortex.c:437:10:HAL_NVIC_GetActive 16 static +stm32f7xx_hal_cortex.c:454:6:HAL_SYSTICK_CLKSourceConfig 16 static +stm32f7xx_hal_cortex.c:472:6:HAL_SYSTICK_IRQHandler 8 static +stm32f7xx_hal_cortex.c:481:13:HAL_SYSTICK_Callback 4 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.d new file mode 100644 index 0000000..8a46bcb --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o new file mode 100644 index 0000000..6ce0f51 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.su new file mode 100644 index 0000000..fb39254 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.su @@ -0,0 +1,21 @@ +stm32f7xx_hal_dac.c:267:19:HAL_DAC_Init 16 static +stm32f7xx_hal_dac.c:326:19:HAL_DAC_DeInit 16 static +stm32f7xx_hal_dac.c:371:13:HAL_DAC_MspInit 16 static +stm32f7xx_hal_dac.c:387:13:HAL_DAC_MspDeInit 16 static +stm32f7xx_hal_dac.c:429:19:HAL_DAC_Start 24 static +stm32f7xx_hal_dac.c:488:19:HAL_DAC_Stop 16 static +stm32f7xx_hal_dac.c:520:19:HAL_DAC_Start_DMA 32 static +stm32f7xx_hal_dac.c:639:19:HAL_DAC_Stop_DMA 24 static +stm32f7xx_hal_dac.c:689:10:HAL_DAC_GetValue 16 static +stm32f7xx_hal_dac.c:711:6:HAL_DAC_IRQHandler 16 static +stm32f7xx_hal_dac.c:765:13:HAL_DAC_ConvCpltCallbackCh1 16 static +stm32f7xx_hal_dac.c:781:13:HAL_DAC_ConvHalfCpltCallbackCh1 16 static +stm32f7xx_hal_dac.c:797:13:HAL_DAC_ErrorCallbackCh1 16 static +stm32f7xx_hal_dac.c:813:13:HAL_DAC_DMAUnderrunCallbackCh1 16 static +stm32f7xx_hal_dac.c:853:19:HAL_DAC_ConfigChannel 32 static +stm32f7xx_hal_dac.c:909:19:HAL_DAC_SetValue 32 static +stm32f7xx_hal_dac.c:961:22:HAL_DAC_GetState 16 static +stm32f7xx_hal_dac.c:974:10:HAL_DAC_GetError 16 static +stm32f7xx_hal_dac.c:1233:13:DAC_DMAConvCpltCh1 24 static +stm32f7xx_hal_dac.c:1252:13:DAC_DMAHalfConvCpltCh1 24 static +stm32f7xx_hal_dac.c:1269:13:DAC_DMAErrorCh1 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.d new file mode 100644 index 0000000..ddfb40c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o new file mode 100644 index 0000000..8c1dde8 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.su new file mode 100644 index 0000000..9b9e2b1 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.su @@ -0,0 +1,11 @@ +stm32f7xx_hal_dac_ex.c:88:10:HAL_DACEx_DualGetValue 24 static +stm32f7xx_hal_dac_ex.c:124:19:HAL_DACEx_TriangleWaveGenerate 24 static +stm32f7xx_hal_dac_ex.c:173:19:HAL_DACEx_NoiseWaveGenerate 24 static +stm32f7xx_hal_dac_ex.c:213:19:HAL_DACEx_DualSetValue 32 static +stm32f7xx_hal_dac_ex.c:252:13:HAL_DACEx_ConvCpltCallbackCh2 16 static +stm32f7xx_hal_dac_ex.c:268:13:HAL_DACEx_ConvHalfCpltCallbackCh2 16 static +stm32f7xx_hal_dac_ex.c:284:13:HAL_DACEx_ErrorCallbackCh2 16 static +stm32f7xx_hal_dac_ex.c:300:13:HAL_DACEx_DMAUnderrunCallbackCh2 16 static +stm32f7xx_hal_dac_ex.c:316:6:DAC_DMAConvCpltCh2 24 static +stm32f7xx_hal_dac_ex.c:335:6:DAC_DMAHalfConvCpltCh2 24 static +stm32f7xx_hal_dac_ex.c:352:6:DAC_DMAErrorCh2 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d new file mode 100644 index 0000000..07250e3 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o new file mode 100644 index 0000000..0d48878 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su new file mode 100644 index 0000000..79059b0 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.su @@ -0,0 +1,15 @@ +stm32f7xx_hal_dma.c:172:19:HAL_DMA_Init 32 static +stm32f7xx_hal_dma.c:311:19:HAL_DMA_DeInit 24 static +stm32f7xx_hal_dma.c:409:19:HAL_DMA_Start 32 static +stm32f7xx_hal_dma.c:453:19:HAL_DMA_Start_IT 32 static +stm32f7xx_hal_dma.c:516:19:HAL_DMA_Abort 24 static +stm32f7xx_hal_dma.c:583:19:HAL_DMA_Abort_IT 16 static +stm32f7xx_hal_dma.c:613:19:HAL_DMA_PollForTransfer 48 static +stm32f7xx_hal_dma.c:749:6:HAL_DMA_IRQHandler 32 static +stm32f7xx_hal_dma.c:970:19:HAL_DMA_RegisterCallback 32 static +stm32f7xx_hal_dma.c:1030:19:HAL_DMA_UnRegisterCallback 24 static +stm32f7xx_hal_dma.c:1115:22:HAL_DMA_GetState 16 static +stm32f7xx_hal_dma.c:1126:10:HAL_DMA_GetError 16 static +stm32f7xx_hal_dma.c:1152:13:DMA_SetConfig 24 static +stm32f7xx_hal_dma.c:1186:17:DMA_CalcBaseAndBitshift 24 static +stm32f7xx_hal_dma.c:1214:26:DMA_CheckFifoParam 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d new file mode 100644 index 0000000..0d2c657 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o new file mode 100644 index 0000000..5a98bc3 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su new file mode 100644 index 0000000..b98e7b3 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.su @@ -0,0 +1,30 @@ +stm32f7xx_hal_dma2d.c:237:19:HAL_DMA2D_Init 16 static +stm32f7xx_hal_dma2d.c:313:19:HAL_DMA2D_DeInit 16 static +stm32f7xx_hal_dma2d.c:403:13:HAL_DMA2D_MspInit 16 static +stm32f7xx_hal_dma2d.c:419:13:HAL_DMA2D_MspDeInit 16 static +stm32f7xx_hal_dma2d.c:673:19:HAL_DMA2D_Start 32 static +stm32f7xx_hal_dma2d.c:707:19:HAL_DMA2D_Start_IT 32 static +stm32f7xx_hal_dma2d.c:742:19:HAL_DMA2D_BlendingStart 32 static +stm32f7xx_hal_dma2d.c:777:19:HAL_DMA2D_BlendingStart_IT 32 static +stm32f7xx_hal_dma2d.c:810:19:HAL_DMA2D_Abort 24 static +stm32f7xx_hal_dma2d.c:859:19:HAL_DMA2D_Suspend 24 static +stm32f7xx_hal_dma2d.c:908:19:HAL_DMA2D_Resume 16 static +stm32f7xx_hal_dma2d.c:936:19:HAL_DMA2D_EnableCLUT 16 static +stm32f7xx_hal_dma2d.c:974:19:HAL_DMA2D_CLUTLoad 24 static +stm32f7xx_hal_dma2d.c:1028:19:HAL_DMA2D_CLUTLoad_IT 24 static +stm32f7xx_hal_dma2d.c:1086:19:HAL_DMA2D_CLUTLoading_Abort 24 static +stm32f7xx_hal_dma2d.c:1143:19:HAL_DMA2D_CLUTLoading_Suspend 32 static +stm32f7xx_hal_dma2d.c:1204:19:HAL_DMA2D_CLUTLoading_Resume 16 static +stm32f7xx_hal_dma2d.c:1247:19:HAL_DMA2D_PollForTransfer 32 static +stm32f7xx_hal_dma2d.c:1375:6:HAL_DMA2D_IRQHandler 24 static +stm32f7xx_hal_dma2d.c:1545:13:HAL_DMA2D_LineEventCallback 16 static +stm32f7xx_hal_dma2d.c:1561:13:HAL_DMA2D_CLUTLoadingCpltCallback 16 static +stm32f7xx_hal_dma2d.c:1604:19:HAL_DMA2D_ConfigLayer 32 static +stm32f7xx_hal_dma2d.c:1705:19:HAL_DMA2D_ConfigCLUT 24 static +stm32f7xx_hal_dma2d.c:1759:19:HAL_DMA2D_ProgramLineEvent 16 static +stm32f7xx_hal_dma2d.c:1797:19:HAL_DMA2D_EnableDeadTime 16 static +stm32f7xx_hal_dma2d.c:1820:19:HAL_DMA2D_DisableDeadTime 16 static +stm32f7xx_hal_dma2d.c:1846:19:HAL_DMA2D_ConfigDeadTime 16 static +stm32f7xx_hal_dma2d.c:1891:24:HAL_DMA2D_GetState 16 static +stm32f7xx_hal_dma2d.c:1902:10:HAL_DMA2D_GetError 16 static +stm32f7xx_hal_dma2d.c:1930:13:DMA2D_SetConfig 48 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d new file mode 100644 index 0000000..376258d --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o new file mode 100644 index 0000000..62af2df Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su new file mode 100644 index 0000000..de9991e --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.su @@ -0,0 +1,4 @@ +stm32f7xx_hal_dma_ex.c:103:19:HAL_DMAEx_MultiBufferStart 32 static +stm32f7xx_hal_dma_ex.c:157:19:HAL_DMAEx_MultiBufferStart_IT 32 static +stm32f7xx_hal_dma_ex.c:235:19:HAL_DMAEx_ChangeMemory 24 static +stm32f7xx_hal_dma_ex.c:272:13:DMA_MultiBufferSetConfig 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d new file mode 100644 index 0000000..f5e4b44 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o new file mode 100644 index 0000000..88b0546 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d new file mode 100644 index 0000000..3cb0c14 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o new file mode 100644 index 0000000..cb7d4d3 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su new file mode 100644 index 0000000..cf1fd86 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.su @@ -0,0 +1,9 @@ +stm32f7xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 32 static +stm32f7xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 32 static +stm32f7xx_hal_exti.c:327:19:HAL_EXTI_ClearConfigLine 32 static +stm32f7xx_hal_exti.c:380:19:HAL_EXTI_RegisterCallback 32 static +stm32f7xx_hal_exti.c:405:19:HAL_EXTI_GetHandle 16 static +stm32f7xx_hal_exti.c:445:6:HAL_EXTI_IRQHandler 24 static +stm32f7xx_hal_exti.c:477:10:HAL_EXTI_GetPending 32 static +stm32f7xx_hal_exti.c:506:6:HAL_EXTI_ClearPending 24 static +stm32f7xx_hal_exti.c:527:6:HAL_EXTI_GenerateSWI 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d new file mode 100644 index 0000000..3d88d5c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o new file mode 100644 index 0000000..9cf73c1 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su new file mode 100644 index 0000000..aef0f1a --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.su @@ -0,0 +1,17 @@ +stm32f7xx_hal_flash.c:164:19:HAL_FLASH_Program 32 static +stm32f7xx_hal_flash.c:233:19:HAL_FLASH_Program_IT 32 static +stm32f7xx_hal_flash.c:295:6:HAL_FLASH_IRQHandler 16 static +stm32f7xx_hal_flash.c:430:13:HAL_FLASH_EndOfOperationCallback 16 static +stm32f7xx_hal_flash.c:448:13:HAL_FLASH_OperationErrorCallback 16 static +stm32f7xx_hal_flash.c:480:19:HAL_FLASH_Unlock 16 static +stm32f7xx_hal_flash.c:504:19:HAL_FLASH_Lock 4 static +stm32f7xx_hal_flash.c:516:19:HAL_FLASH_OB_Unlock 4 static +stm32f7xx_hal_flash.c:536:19:HAL_FLASH_OB_Lock 4 static +stm32f7xx_hal_flash.c:548:19:HAL_FLASH_OB_Launch 8 static +stm32f7xx_hal_flash.c:584:10:HAL_FLASH_GetError 4 static +stm32f7xx_hal_flash.c:598:19:FLASH_WaitForLastOperation 24 static +stm32f7xx_hal_flash.c:653:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +stm32f7xx_hal_flash.c:685:13:FLASH_Program_Word 16 static,ignoring_inline_asm +stm32f7xx_hal_flash.c:714:13:FLASH_Program_HalfWord 16 static,ignoring_inline_asm +stm32f7xx_hal_flash.c:744:13:FLASH_Program_Byte 16 static,ignoring_inline_asm +stm32f7xx_hal_flash.c:765:13:FLASH_SetErrorCode 4 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d new file mode 100644 index 0000000..1c83120 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o new file mode 100644 index 0000000..8cf8275 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su new file mode 100644 index 0000000..6706d24 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.su @@ -0,0 +1,17 @@ +stm32f7xx_hal_flash_ex.c:158:19:HAL_FLASHEx_Erase 24 static +stm32f7xx_hal_flash_ex.c:231:19:HAL_FLASHEx_Erase_IT 24 static +stm32f7xx_hal_flash_ex.c:287:19:HAL_FLASHEx_OBProgram 40 static +stm32f7xx_hal_flash_ex.c:386:6:HAL_FLASHEx_OBGetConfig 16 static +stm32f7xx_hal_flash_ex.c:641:13:FLASH_MassErase 16 static,ignoring_inline_asm +stm32f7xx_hal_flash_ex.c:672:6:FLASH_Erase_Sector 24 static,ignoring_inline_asm +stm32f7xx_hal_flash_ex.c:713:17:FLASH_OB_GetWRP 4 static +stm32f7xx_hal_flash_ex.c:747:26:FLASH_OB_UserConfig 40 static +stm32f7xx_hal_flash_ex.c:785:17:FLASH_OB_GetUser 4 static +stm32f7xx_hal_flash_ex.c:808:26:FLASH_OB_EnableWRP 24 static +stm32f7xx_hal_flash_ex.c:844:26:FLASH_OB_DisableWRP 24 static +stm32f7xx_hal_flash_ex.c:875:26:FLASH_OB_RDP_LevelConfig 24 static +stm32f7xx_hal_flash_ex.c:903:26:FLASH_OB_BOR_LevelConfig 16 static +stm32f7xx_hal_flash_ex.c:934:26:FLASH_OB_BootAddressConfig 24 static +stm32f7xx_hal_flash_ex.c:967:16:FLASH_OB_GetRDP 16 static +stm32f7xx_hal_flash_ex.c:995:17:FLASH_OB_GetBOR 4 static +stm32f7xx_hal_flash_ex.c:1018:17:FLASH_OB_GetBootAddress 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d new file mode 100644 index 0000000..5fd667b --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o new file mode 100644 index 0000000..1c0951d Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su new file mode 100644 index 0000000..0b90ac4 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.su @@ -0,0 +1,8 @@ +stm32f7xx_hal_gpio.c:169:6:HAL_GPIO_Init 40 static +stm32f7xx_hal_gpio.c:294:6:HAL_GPIO_DeInit 32 static +stm32f7xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 24 static +stm32f7xx_hal_gpio.c:407:6:HAL_GPIO_WritePin 16 static +stm32f7xx_hal_gpio.c:429:6:HAL_GPIO_TogglePin 16 static +stm32f7xx_hal_gpio.c:455:19:HAL_GPIO_LockPin 24 static +stm32f7xx_hal_gpio.c:489:6:HAL_GPIO_EXTI_IRQHandler 16 static +stm32f7xx_hal_gpio.c:504:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d new file mode 100644 index 0000000..6c30600 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o new file mode 100644 index 0000000..0c9312d Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su new file mode 100644 index 0000000..85ae89c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.su @@ -0,0 +1,78 @@ +stm32f7xx_hal_i2c.c:469:19:HAL_I2C_Init 16 static +stm32f7xx_hal_i2c.c:578:19:HAL_I2C_DeInit 16 static +stm32f7xx_hal_i2c.c:624:13:HAL_I2C_MspInit 16 static +stm32f7xx_hal_i2c.c:640:13:HAL_I2C_MspDeInit 16 static +stm32f7xx_hal_i2c.c:1060:19:HAL_I2C_Master_Transmit 40 static +stm32f7xx_hal_i2c.c:1174:19:HAL_I2C_Master_Receive 40 static +stm32f7xx_hal_i2c.c:1287:19:HAL_I2C_Slave_Transmit 40 static +stm32f7xx_hal_i2c.c:1424:19:HAL_I2C_Slave_Receive 40 static +stm32f7xx_hal_i2c.c:1550:19:HAL_I2C_Master_Transmit_IT 40 static +stm32f7xx_hal_i2c.c:1619:19:HAL_I2C_Master_Receive_IT 40 static +stm32f7xx_hal_i2c.c:1686:19:HAL_I2C_Slave_Transmit_IT 24 static +stm32f7xx_hal_i2c.c:1735:19:HAL_I2C_Slave_Receive_IT 24 static +stm32f7xx_hal_i2c.c:1786:19:HAL_I2C_Master_Transmit_DMA 40 static +stm32f7xx_hal_i2c.c:1929:19:HAL_I2C_Master_Receive_DMA 40 static +stm32f7xx_hal_i2c.c:2070:19:HAL_I2C_Slave_Transmit_DMA 32 static +stm32f7xx_hal_i2c.c:2173:19:HAL_I2C_Slave_Receive_DMA 32 static +stm32f7xx_hal_i2c.c:2280:19:HAL_I2C_Mem_Write 40 static +stm32f7xx_hal_i2c.c:2415:19:HAL_I2C_Mem_Read 40 static +stm32f7xx_hal_i2c.c:2548:19:HAL_I2C_Mem_Write_IT 40 static +stm32f7xx_hal_i2c.c:2639:19:HAL_I2C_Mem_Read_IT 40 static +stm32f7xx_hal_i2c.c:2729:19:HAL_I2C_Mem_Write_DMA 48 static +stm32f7xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_DMA 48 static +stm32f7xx_hal_i2c.c:3014:19:HAL_I2C_IsDeviceReady 48 static +stm32f7xx_hal_i2c.c:3156:19:HAL_I2C_Master_Seq_Transmit_IT 40 static +stm32f7xx_hal_i2c.c:3240:19:HAL_I2C_Master_Seq_Transmit_DMA 48 static +stm32f7xx_hal_i2c.c:3402:19:HAL_I2C_Master_Seq_Receive_IT 40 static +stm32f7xx_hal_i2c.c:3486:19:HAL_I2C_Master_Seq_Receive_DMA 48 static +stm32f7xx_hal_i2c.c:3646:19:HAL_I2C_Slave_Seq_Transmit_IT 24 static +stm32f7xx_hal_i2c.c:3741:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static +stm32f7xx_hal_i2c.c:3920:19:HAL_I2C_Slave_Seq_Receive_IT 24 static +stm32f7xx_hal_i2c.c:4015:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static +stm32f7xx_hal_i2c.c:4190:19:HAL_I2C_EnableListen_IT 16 static +stm32f7xx_hal_i2c.c:4214:19:HAL_I2C_DisableListen_IT 24 static +stm32f7xx_hal_i2c.c:4247:19:HAL_I2C_Master_Abort_IT 24 static +stm32f7xx_hal_i2c.c:4297:6:HAL_I2C_EV_IRQHandler 24 static +stm32f7xx_hal_i2c.c:4316:6:HAL_I2C_ER_IRQHandler 32 static +stm32f7xx_hal_i2c.c:4365:13:HAL_I2C_MasterTxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4381:13:HAL_I2C_MasterRxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4396:13:HAL_I2C_SlaveTxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4412:13:HAL_I2C_SlaveRxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4430:13:HAL_I2C_AddrCallback 16 static +stm32f7xx_hal_i2c.c:4448:13:HAL_I2C_ListenCpltCallback 16 static +stm32f7xx_hal_i2c.c:4464:13:HAL_I2C_MemTxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4480:13:HAL_I2C_MemRxCpltCallback 16 static +stm32f7xx_hal_i2c.c:4496:13:HAL_I2C_ErrorCallback 16 static +stm32f7xx_hal_i2c.c:4512:13:HAL_I2C_AbortCpltCallback 16 static +stm32f7xx_hal_i2c.c:4547:22:HAL_I2C_GetState 16 static +stm32f7xx_hal_i2c.c:4559:21:HAL_I2C_GetMode 16 static +stm32f7xx_hal_i2c.c:4570:10:HAL_I2C_GetError 16 static +stm32f7xx_hal_i2c.c:4595:26:I2C_Master_ISR_IT 40 static +stm32f7xx_hal_i2c.c:4732:26:I2C_Slave_ISR_IT 32 static +stm32f7xx_hal_i2c.c:4865:26:I2C_Master_ISR_DMA 40 static +stm32f7xx_hal_i2c.c:5000:26:I2C_Slave_ISR_DMA 32 static +stm32f7xx_hal_i2c.c:5122:26:I2C_RequestMemoryWrite 32 static +stm32f7xx_hal_i2c.c:5175:26:I2C_RequestMemoryRead 32 static +stm32f7xx_hal_i2c.c:5222:13:I2C_ITAddrCplt 24 static +stm32f7xx_hal_i2c.c:5317:13:I2C_ITMasterSeqCplt 16 static +stm32f7xx_hal_i2c.c:5370:13:I2C_ITSlaveSeqCplt 16 static +stm32f7xx_hal_i2c.c:5426:13:I2C_ITMasterCplt 24 static +stm32f7xx_hal_i2c.c:5545:13:I2C_ITSlaveCplt 24 static +stm32f7xx_hal_i2c.c:5682:13:I2C_ITListenCplt 16 static +stm32f7xx_hal_i2c.c:5733:13:I2C_ITError 24 static +stm32f7xx_hal_i2c.c:5851:13:I2C_Flush_TXDR 16 static +stm32f7xx_hal_i2c.c:5872:13:I2C_DMAMasterTransmitCplt 24 static +stm32f7xx_hal_i2c.c:5920:13:I2C_DMASlaveTransmitCplt 24 static +stm32f7xx_hal_i2c.c:5947:13:I2C_DMAMasterReceiveCplt 24 static +stm32f7xx_hal_i2c.c:5995:13:I2C_DMASlaveReceiveCplt 24 static +stm32f7xx_hal_i2c.c:6022:13:I2C_DMAError 24 static +stm32f7xx_hal_i2c.c:6060:13:I2C_DMAAbort 24 static +stm32f7xx_hal_i2c.c:6101:26:I2C_WaitOnFlagUntilTimeout 24 static +stm32f7xx_hal_i2c.c:6131:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +stm32f7xx_hal_i2c.c:6168:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +stm32f7xx_hal_i2c.c:6202:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +stm32f7xx_hal_i2c.c:6265:26:I2C_IsAcknowledgeFailed 24 static +stm32f7xx_hal_i2c.c:6333:13:I2C_TransferConfig 24 static +stm32f7xx_hal_i2c.c:6352:13:I2C_Enable_IRQ 24 static +stm32f7xx_hal_i2c.c:6423:13:I2C_Disable_IRQ 24 static +stm32f7xx_hal_i2c.c:6486:13:I2C_ConvertOtherXferOptions 16 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d new file mode 100644 index 0000000..7e9d67c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o new file mode 100644 index 0000000..3b35ecf Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su new file mode 100644 index 0000000..1f2efdc --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.su @@ -0,0 +1,2 @@ +stm32f7xx_hal_i2c_ex.c:92:19:HAL_I2CEx_ConfigAnalogFilter 16 static +stm32f7xx_hal_i2c_ex.c:136:19:HAL_I2CEx_ConfigDigitalFilter 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d new file mode 100644 index 0000000..298d926 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o new file mode 100644 index 0000000..bc7c2a9 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su new file mode 100644 index 0000000..d19386d --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.su @@ -0,0 +1,40 @@ +stm32f7xx_hal_ltdc.c:191:19:HAL_LTDC_Init 24 static +stm32f7xx_hal_ltdc.c:300:19:HAL_LTDC_DeInit 16 static +stm32f7xx_hal_ltdc.c:332:13:HAL_LTDC_MspInit 16 static +stm32f7xx_hal_ltdc.c:348:13:HAL_LTDC_MspDeInit 16 static +stm32f7xx_hal_ltdc.c:563:6:HAL_LTDC_IRQHandler 24 static +stm32f7xx_hal_ltdc.c:681:13:HAL_LTDC_ErrorCallback 16 static +stm32f7xx_hal_ltdc.c:697:13:HAL_LTDC_LineEventCallback 16 static +stm32f7xx_hal_ltdc.c:713:13:HAL_LTDC_ReloadEventCallback 16 static +stm32f7xx_hal_ltdc.c:763:19:HAL_LTDC_ConfigLayer 32 static +stm32f7xx_hal_ltdc.c:813:19:HAL_LTDC_ConfigColorKeying 24 static +stm32f7xx_hal_ltdc.c:851:19:HAL_LTDC_ConfigCLUT 40 static +stm32f7xx_hal_ltdc.c:900:19:HAL_LTDC_EnableColorKeying 16 static +stm32f7xx_hal_ltdc.c:935:19:HAL_LTDC_DisableColorKeying 16 static +stm32f7xx_hal_ltdc.c:970:19:HAL_LTDC_EnableCLUT 16 static +stm32f7xx_hal_ltdc.c:1005:19:HAL_LTDC_DisableCLUT 16 static +stm32f7xx_hal_ltdc.c:1038:19:HAL_LTDC_EnableDither 16 static +stm32f7xx_hal_ltdc.c:1065:19:HAL_LTDC_DisableDither 16 static +stm32f7xx_hal_ltdc.c:1096:19:HAL_LTDC_SetWindowSize 32 static +stm32f7xx_hal_ltdc.c:1152:19:HAL_LTDC_SetWindowPosition 32 static +stm32f7xx_hal_ltdc.c:1203:19:HAL_LTDC_SetPixelFormat 32 static +stm32f7xx_hal_ltdc.c:1248:19:HAL_LTDC_SetAlpha 32 static +stm32f7xx_hal_ltdc.c:1292:19:HAL_LTDC_SetAddress 32 static +stm32f7xx_hal_ltdc.c:1339:19:HAL_LTDC_SetPitch 40 static +stm32f7xx_hal_ltdc.c:1408:19:HAL_LTDC_ProgramLineEvent 16 static +stm32f7xx_hal_ltdc.c:1447:20:HAL_LTDC_Reload 16 static +stm32f7xx_hal_ltdc.c:1486:19:HAL_LTDC_ConfigLayer_NoReload 32 static +stm32f7xx_hal_ltdc.c:1535:19:HAL_LTDC_SetWindowSize_NoReload 32 static +stm32f7xx_hal_ltdc.c:1589:19:HAL_LTDC_SetWindowPosition_NoReload 32 static +stm32f7xx_hal_ltdc.c:1638:19:HAL_LTDC_SetPixelFormat_NoReload 32 static +stm32f7xx_hal_ltdc.c:1681:19:HAL_LTDC_SetAlpha_NoReload 32 static +stm32f7xx_hal_ltdc.c:1724:19:HAL_LTDC_SetAddress_NoReload 32 static +stm32f7xx_hal_ltdc.c:1769:19:HAL_LTDC_SetPitch_NoReload 40 static +stm32f7xx_hal_ltdc.c:1836:19:HAL_LTDC_ConfigColorKeying_NoReload 24 static +stm32f7xx_hal_ltdc.c:1870:19:HAL_LTDC_EnableColorKeying_NoReload 16 static +stm32f7xx_hal_ltdc.c:1903:19:HAL_LTDC_DisableColorKeying_NoReload 16 static +stm32f7xx_hal_ltdc.c:1936:19:HAL_LTDC_EnableCLUT_NoReload 16 static +stm32f7xx_hal_ltdc.c:1969:19:HAL_LTDC_DisableCLUT_NoReload 16 static +stm32f7xx_hal_ltdc.c:2018:23:HAL_LTDC_GetState 16 static +stm32f7xx_hal_ltdc.c:2029:10:HAL_LTDC_GetError 16 static +stm32f7xx_hal_ltdc.c:2055:13:LTDC_SetConfig 40 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d new file mode 100644 index 0000000..40fabae --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o new file mode 100644 index 0000000..4e0b819 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d new file mode 100644 index 0000000..ac0be5e --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o new file mode 100644 index 0000000..d5d624a Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su new file mode 100644 index 0000000..f0a4f07 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.su @@ -0,0 +1,17 @@ +stm32f7xx_hal_pwr.c:100:6:HAL_PWR_DeInit 4 static +stm32f7xx_hal_pwr.c:113:6:HAL_PWR_EnableBkUpAccess 4 static +stm32f7xx_hal_pwr.c:126:6:HAL_PWR_DisableBkUpAccess 4 static +stm32f7xx_hal_pwr.c:260:6:HAL_PWR_ConfigPVD 16 static +stm32f7xx_hal_pwr.c:303:6:HAL_PWR_EnablePVD 4 static +stm32f7xx_hal_pwr.c:313:6:HAL_PWR_DisablePVD 4 static +stm32f7xx_hal_pwr.c:336:6:HAL_PWR_EnableWakeUpPin 16 static +stm32f7xx_hal_pwr.c:360:6:HAL_PWR_DisableWakeUpPin 16 static +stm32f7xx_hal_pwr.c:387:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +stm32f7xx_hal_pwr.c:434:6:HAL_PWR_EnterSTOPMode 24 static,ignoring_inline_asm +stm32f7xx_hal_pwr.c:487:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +stm32f7xx_hal_pwr.c:508:6:HAL_PWR_PVD_IRQHandler 8 static +stm32f7xx_hal_pwr.c:525:13:HAL_PWR_PVDCallback 4 static +stm32f7xx_hal_pwr.c:540:6:HAL_PWR_EnableSleepOnExit 4 static +stm32f7xx_hal_pwr.c:552:6:HAL_PWR_DisableSleepOnExit 4 static +stm32f7xx_hal_pwr.c:564:6:HAL_PWR_EnableSEVOnPend 4 static +stm32f7xx_hal_pwr.c:576:6:HAL_PWR_DisableSEVOnPend 4 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d new file mode 100644 index 0000000..91f87f9 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o new file mode 100644 index 0000000..4eec0f7 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su new file mode 100644 index 0000000..78228e9 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.su @@ -0,0 +1,13 @@ +stm32f7xx_hal_pwr_ex.c:135:19:HAL_PWREx_EnableBkUpReg 16 static +stm32f7xx_hal_pwr_ex.c:164:19:HAL_PWREx_DisableBkUpReg 16 static +stm32f7xx_hal_pwr_ex.c:193:6:HAL_PWREx_EnableFlashPowerDown 4 static +stm32f7xx_hal_pwr_ex.c:203:6:HAL_PWREx_DisableFlashPowerDown 4 static +stm32f7xx_hal_pwr_ex.c:213:6:HAL_PWREx_EnableMainRegulatorLowVoltage 4 static +stm32f7xx_hal_pwr_ex.c:223:6:HAL_PWREx_DisableMainRegulatorLowVoltage 4 static +stm32f7xx_hal_pwr_ex.c:233:6:HAL_PWREx_EnableLowRegulatorLowVoltage 4 static +stm32f7xx_hal_pwr_ex.c:243:6:HAL_PWREx_DisableLowRegulatorLowVoltage 4 static +stm32f7xx_hal_pwr_ex.c:259:19:HAL_PWREx_EnableOverDrive 16 static +stm32f7xx_hal_pwr_ex.c:305:19:HAL_PWREx_DisableOverDrive 16 static +stm32f7xx_hal_pwr_ex.c:379:19:HAL_PWREx_EnterUnderDriveSTOPMode 32 static,ignoring_inline_asm +stm32f7xx_hal_pwr_ex.c:445:10:HAL_PWREx_GetVoltageRange 4 static +stm32f7xx_hal_pwr_ex.c:477:19:HAL_PWREx_ControlVoltageScaling 32 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d new file mode 100644 index 0000000..5bfe437 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o new file mode 100644 index 0000000..44fa0de Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su new file mode 100644 index 0000000..08db9c5 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.su @@ -0,0 +1,14 @@ +stm32f7xx_hal_rcc.c:198:19:HAL_RCC_DeInit 16 static +stm32f7xx_hal_rcc.c:344:19:HAL_RCC_OscConfig 32 static +stm32f7xx_hal_rcc.c:724:19:HAL_RCC_ClockConfig 24 static +stm32f7xx_hal_rcc.c:905:6:HAL_RCC_MCOConfig 56 static +stm32f7xx_hal_rcc.c:959:6:HAL_RCC_EnableCSS 4 static +stm32f7xx_hal_rcc.c:968:6:HAL_RCC_DisableCSS 4 static +stm32f7xx_hal_rcc.c:1003:10:HAL_RCC_GetSysClockFreq 40 static +stm32f7xx_hal_rcc.c:1057:10:HAL_RCC_GetHCLKFreq 4 static +stm32f7xx_hal_rcc.c:1068:10:HAL_RCC_GetPCLK1Freq 8 static +stm32f7xx_hal_rcc.c:1080:10:HAL_RCC_GetPCLK2Freq 8 static +stm32f7xx_hal_rcc.c:1093:6:HAL_RCC_GetOscConfig 16 static +stm32f7xx_hal_rcc.c:1175:6:HAL_RCC_GetClockConfig 16 static +stm32f7xx_hal_rcc.c:1201:6:HAL_RCC_NMI_IRQHandler 8 static +stm32f7xx_hal_rcc.c:1218:13:HAL_RCC_CSSCallback 4 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d new file mode 100644 index 0000000..ca300b5 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o new file mode 100644 index 0000000..dfa837a Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su new file mode 100644 index 0000000..7f47fad --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.su @@ -0,0 +1,7 @@ +stm32f7xx_hal_rcc_ex.c:107:19:HAL_RCCEx_PeriphCLKConfig 40 static +stm32f7xx_hal_rcc_ex.c:667:6:HAL_RCCEx_GetPeriphCLKConfig 24 static +stm32f7xx_hal_rcc_ex.c:1385:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +stm32f7xx_hal_rcc_ex.c:1588:19:HAL_RCCEx_EnablePLLI2S 24 static +stm32f7xx_hal_rcc_ex.c:1649:19:HAL_RCCEx_DisablePLLI2S 16 static +stm32f7xx_hal_rcc_ex.c:1676:19:HAL_RCCEx_EnablePLLSAI 24 static +stm32f7xx_hal_rcc_ex.c:1738:19:HAL_RCCEx_DisablePLLSAI 16 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d new file mode 100644 index 0000000..62c7973 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o new file mode 100644 index 0000000..1cbb03e Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su new file mode 100644 index 0000000..f6da9cc --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.su @@ -0,0 +1,20 @@ +stm32f7xx_hal_rtc.c:242:19:HAL_RTC_Init 16 static +stm32f7xx_hal_rtc.c:347:19:HAL_RTC_DeInit 24 static +stm32f7xx_hal_rtc.c:671:13:HAL_RTC_MspInit 16 static +stm32f7xx_hal_rtc.c:687:13:HAL_RTC_MspDeInit 16 static +stm32f7xx_hal_rtc.c:726:19:HAL_RTC_SetTime 40 static +stm32f7xx_hal_rtc.c:860:19:HAL_RTC_GetTime 32 static +stm32f7xx_hal_rtc.c:905:19:HAL_RTC_SetDate 40 static +stm32f7xx_hal_rtc.c:1015:19:HAL_RTC_GetDate 32 static +stm32f7xx_hal_rtc.c:1070:19:HAL_RTC_SetAlarm 48 static +stm32f7xx_hal_rtc.c:1256:19:HAL_RTC_SetAlarm_IT 48 static +stm32f7xx_hal_rtc.c:1439:19:HAL_RTC_DeactivateAlarm 24 static +stm32f7xx_hal_rtc.c:1536:19:HAL_RTC_GetAlarm 32 static +stm32f7xx_hal_rtc.c:1587:6:HAL_RTC_AlarmIRQHandler 16 static +stm32f7xx_hal_rtc.c:1638:13:HAL_RTC_AlarmAEventCallback 16 static +stm32f7xx_hal_rtc.c:1655:19:HAL_RTC_PollForAlarmAEvent 24 static +stm32f7xx_hal_rtc.c:1717:19:HAL_RTC_WaitForSynchro 24 static +stm32f7xx_hal_rtc.c:1763:21:HAL_RTC_GetState 16 static +stm32f7xx_hal_rtc.c:1780:19:RTC_EnterInitMode 24 static +stm32f7xx_hal_rtc.c:1812:9:RTC_ByteToBcd2 24 static +stm32f7xx_hal_rtc.c:1830:9:RTC_Bcd2ToByte 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d new file mode 100644 index 0000000..d051e05 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o new file mode 100644 index 0000000..b4293f0 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su new file mode 100644 index 0000000..4c9e18c --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.su @@ -0,0 +1,37 @@ +stm32f7xx_hal_rtc_ex.c:141:19:HAL_RTCEx_SetTimeStamp 32 static +stm32f7xx_hal_rtc_ex.c:201:19:HAL_RTCEx_SetTimeStamp_IT 32 static +stm32f7xx_hal_rtc_ex.c:258:19:HAL_RTCEx_DeactivateTimeStamp 24 static +stm32f7xx_hal_rtc_ex.c:297:19:HAL_RTCEx_SetInternalTimeStamp 16 static +stm32f7xx_hal_rtc_ex.c:328:19:HAL_RTCEx_DeactivateInternalTimeStamp 16 static +stm32f7xx_hal_rtc_ex.c:364:19:HAL_RTCEx_GetTimeStamp 32 static +stm32f7xx_hal_rtc_ex.c:416:19:HAL_RTCEx_SetTamper 24 static +stm32f7xx_hal_rtc_ex.c:504:19:HAL_RTCEx_SetTamper_IT 24 static +stm32f7xx_hal_rtc_ex.c:615:19:HAL_RTCEx_DeactivateTamper 16 static +stm32f7xx_hal_rtc_ex.c:657:6:HAL_RTCEx_TamperTimeStampIRQHandler 16 static +stm32f7xx_hal_rtc_ex.c:744:13:HAL_RTCEx_TimeStampEventCallback 16 static +stm32f7xx_hal_rtc_ex.c:760:13:HAL_RTCEx_Tamper1EventCallback 16 static +stm32f7xx_hal_rtc_ex.c:776:13:HAL_RTCEx_Tamper2EventCallback 16 static +stm32f7xx_hal_rtc_ex.c:791:13:HAL_RTCEx_Tamper3EventCallback 16 static +stm32f7xx_hal_rtc_ex.c:808:19:HAL_RTCEx_PollForTimeStampEvent 24 static +stm32f7xx_hal_rtc_ex.c:851:19:HAL_RTCEx_PollForTamper1Event 24 static +stm32f7xx_hal_rtc_ex.c:887:19:HAL_RTCEx_PollForTamper2Event 24 static +stm32f7xx_hal_rtc_ex.c:922:19:HAL_RTCEx_PollForTamper3Event 24 static +stm32f7xx_hal_rtc_ex.c:974:19:HAL_RTCEx_SetWakeUpTimer 32 static +stm32f7xx_hal_rtc_ex.c:1047:19:HAL_RTCEx_SetWakeUpTimer_IT 32 static +stm32f7xx_hal_rtc_ex.c:1149:10:HAL_RTCEx_DeactivateWakeUpTimer 24 static +stm32f7xx_hal_rtc_ex.c:1204:10:HAL_RTCEx_GetWakeUpTimer 16 static +stm32f7xx_hal_rtc_ex.c:1221:6:HAL_RTCEx_WakeUpTimerIRQHandler 16 static +stm32f7xx_hal_rtc_ex.c:1250:13:HAL_RTCEx_WakeUpTimerEventCallback 16 static +stm32f7xx_hal_rtc_ex.c:1267:19:HAL_RTCEx_PollForWakeUpTimerEvent 24 static +stm32f7xx_hal_rtc_ex.c:1337:6:HAL_RTCEx_BKUPWrite 32 static +stm32f7xx_hal_rtc_ex.c:1360:10:HAL_RTCEx_BKUPRead 24 static +stm32f7xx_hal_rtc_ex.c:1394:19:HAL_RTCEx_SetSmoothCalib 32 static +stm32f7xx_hal_rtc_ex.c:1464:19:HAL_RTCEx_SetSynchroShift 32 static +stm32f7xx_hal_rtc_ex.c:1559:19:HAL_RTCEx_SetCalibrationOutPut 16 static +stm32f7xx_hal_rtc_ex.c:1598:19:HAL_RTCEx_DeactivateCalibrationOutPut 16 static +stm32f7xx_hal_rtc_ex.c:1628:19:HAL_RTCEx_SetRefClock 16 static +stm32f7xx_hal_rtc_ex.c:1678:19:HAL_RTCEx_DeactivateRefClock 16 static +stm32f7xx_hal_rtc_ex.c:1730:19:HAL_RTCEx_EnableBypassShadow 16 static +stm32f7xx_hal_rtc_ex.c:1763:19:HAL_RTCEx_DisableBypassShadow 16 static +stm32f7xx_hal_rtc_ex.c:1813:13:HAL_RTCEx_AlarmBEventCallback 16 static +stm32f7xx_hal_rtc_ex.c:1830:19:HAL_RTCEx_PollForAlarmBEvent 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d new file mode 100644 index 0000000..de90529 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o new file mode 100644 index 0000000..c95bcb9 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su new file mode 100644 index 0000000..4b11836 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.su @@ -0,0 +1,23 @@ +stm32f7xx_hal_sdram.c:159:19:HAL_SDRAM_Init 16 static +stm32f7xx_hal_sdram.c:209:19:HAL_SDRAM_DeInit 16 static +stm32f7xx_hal_sdram.c:242:13:HAL_SDRAM_MspInit 16 static +stm32f7xx_hal_sdram.c:258:13:HAL_SDRAM_MspDeInit 16 static +stm32f7xx_hal_sdram.c:274:6:HAL_SDRAM_IRQHandler 16 static +stm32f7xx_hal_sdram.c:297:13:HAL_SDRAM_RefreshErrorCallback 16 static +stm32f7xx_hal_sdram.c:313:13:HAL_SDRAM_DMA_XferCpltCallback 16 static +stm32f7xx_hal_sdram.c:328:13:HAL_SDRAM_DMA_XferErrorCallback 16 static +stm32f7xx_hal_sdram.c:365:19:HAL_SDRAM_Read_8b 32 static +stm32f7xx_hal_sdram.c:406:19:HAL_SDRAM_Write_8b 32 static +stm32f7xx_hal_sdram.c:450:19:HAL_SDRAM_Read_16b 32 static +stm32f7xx_hal_sdram.c:490:19:HAL_SDRAM_Write_16b 32 static +stm32f7xx_hal_sdram.c:533:19:HAL_SDRAM_Read_32b 32 static +stm32f7xx_hal_sdram.c:573:19:HAL_SDRAM_Write_32b 32 static +stm32f7xx_hal_sdram.c:616:19:HAL_SDRAM_Read_DMA 32 static +stm32f7xx_hal_sdram.c:657:19:HAL_SDRAM_Write_DMA 32 static +stm32f7xx_hal_sdram.c:912:19:HAL_SDRAM_WriteProtection_Enable 16 static +stm32f7xx_hal_sdram.c:938:19:HAL_SDRAM_WriteProtection_Disable 16 static +stm32f7xx_hal_sdram.c:966:19:HAL_SDRAM_SendCommand 24 static +stm32f7xx_hal_sdram.c:1000:19:HAL_SDRAM_ProgramRefreshRate 16 static +stm32f7xx_hal_sdram.c:1027:19:HAL_SDRAM_SetAutoRefreshNumber 16 static +stm32f7xx_hal_sdram.c:1053:10:HAL_SDRAM_GetModeStatus 16 static +stm32f7xx_hal_sdram.c:1084:24:HAL_SDRAM_GetState 16 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.d new file mode 100644 index 0000000..21fde23 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o new file mode 100644 index 0000000..94aead9 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.su new file mode 100644 index 0000000..2ed09bc --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.su @@ -0,0 +1,56 @@ +stm32f7xx_hal_spi.c:313:19:HAL_SPI_Init 24 static +stm32f7xx_hal_spi.c:458:19:HAL_SPI_DeInit 16 static +stm32f7xx_hal_spi.c:502:13:HAL_SPI_MspInit 16 static +stm32f7xx_hal_spi.c:518:13:HAL_SPI_MspDeInit 16 static +stm32f7xx_hal_spi.c:789:19:HAL_SPI_Transmit 40 static +stm32f7xx_hal_spi.c:972:19:HAL_SPI_Receive 40 static +stm32f7xx_hal_spi.c:1197:19:HAL_SPI_TransmitReceive 48 static +stm32f7xx_hal_spi.c:1495:19:HAL_SPI_Transmit_IT 32 static +stm32f7xx_hal_spi.c:1578:19:HAL_SPI_Receive_IT 32 static +stm32f7xx_hal_spi.c:1683:19:HAL_SPI_TransmitReceive_IT 32 static +stm32f7xx_hal_spi.c:1792:19:HAL_SPI_Transmit_DMA 32 static +stm32f7xx_hal_spi.c:1914:19:HAL_SPI_Receive_DMA 32 static +stm32f7xx_hal_spi.c:2056:19:HAL_SPI_TransmitReceive_DMA 32 static +stm32f7xx_hal_spi.c:2246:19:HAL_SPI_Abort 48 static +stm32f7xx_hal_spi.c:2407:19:HAL_SPI_Abort_IT 40 static +stm32f7xx_hal_spi.c:2569:19:HAL_SPI_DMAPause 16 static +stm32f7xx_hal_spi.c:2589:19:HAL_SPI_DMAResume 16 static +stm32f7xx_hal_spi.c:2609:19:HAL_SPI_DMAStop 24 static +stm32f7xx_hal_spi.c:2649:6:HAL_SPI_IRQHandler 40 static +stm32f7xx_hal_spi.c:2755:13:HAL_SPI_TxCpltCallback 16 static +stm32f7xx_hal_spi.c:2771:13:HAL_SPI_RxCpltCallback 16 static +stm32f7xx_hal_spi.c:2787:13:HAL_SPI_TxRxCpltCallback 16 static +stm32f7xx_hal_spi.c:2803:13:HAL_SPI_TxHalfCpltCallback 16 static +stm32f7xx_hal_spi.c:2819:13:HAL_SPI_RxHalfCpltCallback 16 static +stm32f7xx_hal_spi.c:2835:13:HAL_SPI_TxRxHalfCpltCallback 16 static +stm32f7xx_hal_spi.c:2851:13:HAL_SPI_ErrorCallback 16 static +stm32f7xx_hal_spi.c:2869:13:HAL_SPI_AbortCpltCallback 16 static +stm32f7xx_hal_spi.c:2904:22:HAL_SPI_GetState 16 static +stm32f7xx_hal_spi.c:2916:10:HAL_SPI_GetError 16 static +stm32f7xx_hal_spi.c:2941:13:SPI_DMATransmitCplt 32 static +stm32f7xx_hal_spi.c:2998:13:SPI_DMAReceiveCplt 24 static +stm32f7xx_hal_spi.c:3093:13:SPI_DMATransmitReceiveCplt 24 static +stm32f7xx_hal_spi.c:3182:13:SPI_DMAHalfTransmitCplt 24 static +stm32f7xx_hal_spi.c:3200:13:SPI_DMAHalfReceiveCplt 24 static +stm32f7xx_hal_spi.c:3218:13:SPI_DMAHalfTransmitReceiveCplt 24 static +stm32f7xx_hal_spi.c:3236:13:SPI_DMAError 24 static +stm32f7xx_hal_spi.c:3259:13:SPI_DMAAbortOnError 24 static +stm32f7xx_hal_spi.c:3281:13:SPI_DMATxAbortCallback 40 static +stm32f7xx_hal_spi.c:3347:13:SPI_DMARxAbortCallback 40 static +stm32f7xx_hal_spi.c:3412:13:SPI_2linesRxISR_8BIT 16 static +stm32f7xx_hal_spi.c:3490:13:SPI_2linesTxISR_8BIT 16 static +stm32f7xx_hal_spi.c:3537:13:SPI_2linesRxISR_16BIT 16 static +stm32f7xx_hal_spi.c:3589:13:SPI_2linesTxISR_16BIT 16 static +stm32f7xx_hal_spi.c:3647:13:SPI_RxISR_8BIT 16 static +stm32f7xx_hal_spi.c:3699:13:SPI_RxISR_16BIT 16 static +stm32f7xx_hal_spi.c:3732:13:SPI_TxISR_8BIT 16 static +stm32f7xx_hal_spi.c:3757:13:SPI_TxISR_16BIT 16 static +stm32f7xx_hal_spi.c:3787:26:SPI_WaitFlagStateUntilTimeout 24 static +stm32f7xx_hal_spi.c:3839:26:SPI_WaitFifoStateUntilTimeout 24 static +stm32f7xx_hal_spi.c:3895:26:SPI_EndRxTransaction 32 static +stm32f7xx_hal_spi.c:3931:26:SPI_EndRxTxTransaction 32 static +stm32f7xx_hal_spi.c:3963:13:SPI_CloseRxTx_ISR 24 static +stm32f7xx_hal_spi.c:4040:13:SPI_CloseRx_ISR 16 static +stm32f7xx_hal_spi.c:4097:13:SPI_CloseTx_ISR 24 static +stm32f7xx_hal_spi.c:4146:13:SPI_AbortRx_ISR 32 static +stm32f7xx_hal_spi.c:4191:13:SPI_AbortTx_ISR 32 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.d new file mode 100644 index 0000000..5713560 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o new file mode 100644 index 0000000..d76cd9f Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.su new file mode 100644 index 0000000..cb120f4 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.su @@ -0,0 +1 @@ +stm32f7xx_hal_spi_ex.c:80:19:HAL_SPIEx_FlushRxFifo 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d new file mode 100644 index 0000000..180a271 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o new file mode 100644 index 0000000..655b7db Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su new file mode 100644 index 0000000..963cd5e --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.su @@ -0,0 +1,116 @@ +stm32f7xx_hal_tim.c:268:19:HAL_TIM_Base_Init 16 static +stm32f7xx_hal_tim.c:320:19:HAL_TIM_Base_DeInit 16 static +stm32f7xx_hal_tim.c:356:13:HAL_TIM_Base_MspInit 16 static +stm32f7xx_hal_tim.c:371:13:HAL_TIM_Base_MspDeInit 16 static +stm32f7xx_hal_tim.c:387:19:HAL_TIM_Base_Start 24 static +stm32f7xx_hal_tim.c:416:19:HAL_TIM_Base_Stop 16 static +stm32f7xx_hal_tim.c:439:19:HAL_TIM_Base_Start_IT 24 static +stm32f7xx_hal_tim.c:465:19:HAL_TIM_Base_Stop_IT 16 static +stm32f7xx_hal_tim.c:486:19:HAL_TIM_Base_Start_DMA 32 static +stm32f7xx_hal_tim.c:545:19:HAL_TIM_Base_Stop_DMA 16 static +stm32f7xx_hal_tim.c:600:19:HAL_TIM_OC_Init 16 static +stm32f7xx_hal_tim.c:652:19:HAL_TIM_OC_DeInit 16 static +stm32f7xx_hal_tim.c:688:13:HAL_TIM_OC_MspInit 16 static +stm32f7xx_hal_tim.c:703:13:HAL_TIM_OC_MspDeInit 16 static +stm32f7xx_hal_tim.c:726:19:HAL_TIM_OC_Start 24 static +stm32f7xx_hal_tim.c:766:19:HAL_TIM_OC_Stop 16 static +stm32f7xx_hal_tim.c:798:19:HAL_TIM_OC_Start_IT 24 static +stm32f7xx_hal_tim.c:870:19:HAL_TIM_OC_Stop_IT 16 static +stm32f7xx_hal_tim.c:938:19:HAL_TIM_OC_Start_DMA 32 static +stm32f7xx_hal_tim.c:1080:19:HAL_TIM_OC_Stop_DMA 16 static +stm32f7xx_hal_tim.c:1177:19:HAL_TIM_PWM_Init 16 static +stm32f7xx_hal_tim.c:1229:19:HAL_TIM_PWM_DeInit 16 static +stm32f7xx_hal_tim.c:1265:13:HAL_TIM_PWM_MspInit 16 static +stm32f7xx_hal_tim.c:1280:13:HAL_TIM_PWM_MspDeInit 16 static +stm32f7xx_hal_tim.c:1303:19:HAL_TIM_PWM_Start 24 static +stm32f7xx_hal_tim.c:1343:19:HAL_TIM_PWM_Stop 16 static +stm32f7xx_hal_tim.c:1378:19:HAL_TIM_PWM_Start_IT 24 static +stm32f7xx_hal_tim.c:1449:19:HAL_TIM_PWM_Stop_IT 16 static +stm32f7xx_hal_tim.c:1517:19:HAL_TIM_PWM_Start_DMA 32 static +stm32f7xx_hal_tim.c:1658:19:HAL_TIM_PWM_Stop_DMA 16 static +stm32f7xx_hal_tim.c:1755:19:HAL_TIM_IC_Init 16 static +stm32f7xx_hal_tim.c:1807:19:HAL_TIM_IC_DeInit 16 static +stm32f7xx_hal_tim.c:1843:13:HAL_TIM_IC_MspInit 16 static +stm32f7xx_hal_tim.c:1858:13:HAL_TIM_IC_MspDeInit 16 static +stm32f7xx_hal_tim.c:1879:19:HAL_TIM_IC_Start 24 static +stm32f7xx_hal_tim.c:1911:19:HAL_TIM_IC_Stop 16 static +stm32f7xx_hal_tim.c:1937:19:HAL_TIM_IC_Start_IT 24 static +stm32f7xx_hal_tim.c:2002:19:HAL_TIM_IC_Stop_IT 16 static +stm32f7xx_hal_tim.c:2064:19:HAL_TIM_IC_Start_DMA 32 static +stm32f7xx_hal_tim.c:2199:19:HAL_TIM_IC_Stop_DMA 16 static +stm32f7xx_hal_tim.c:2294:19:HAL_TIM_OnePulse_Init 16 static +stm32f7xx_hal_tim.c:2353:19:HAL_TIM_OnePulse_DeInit 16 static +stm32f7xx_hal_tim.c:2389:13:HAL_TIM_OnePulse_MspInit 16 static +stm32f7xx_hal_tim.c:2404:13:HAL_TIM_OnePulse_MspDeInit 16 static +stm32f7xx_hal_tim.c:2423:19:HAL_TIM_OnePulse_Start 16 static +stm32f7xx_hal_tim.c:2459:19:HAL_TIM_OnePulse_Stop 16 static +stm32f7xx_hal_tim.c:2495:19:HAL_TIM_OnePulse_Start_IT 16 static +stm32f7xx_hal_tim.c:2537:19:HAL_TIM_OnePulse_Stop_IT 16 static +stm32f7xx_hal_tim.c:2607:19:HAL_TIM_Encoder_Init 32 static +stm32f7xx_hal_tim.c:2712:19:HAL_TIM_Encoder_DeInit 16 static +stm32f7xx_hal_tim.c:2748:13:HAL_TIM_Encoder_MspInit 16 static +stm32f7xx_hal_tim.c:2763:13:HAL_TIM_Encoder_MspDeInit 16 static +stm32f7xx_hal_tim.c:2783:19:HAL_TIM_Encoder_Start 16 static +stm32f7xx_hal_tim.c:2827:19:HAL_TIM_Encoder_Stop 16 static +stm32f7xx_hal_tim.c:2873:19:HAL_TIM_Encoder_Start_IT 16 static +stm32f7xx_hal_tim.c:2923:19:HAL_TIM_Encoder_Stop_IT 16 static +stm32f7xx_hal_tim.c:2977:19:HAL_TIM_Encoder_Start_DMA 24 static +stm32f7xx_hal_tim.c:3112:19:HAL_TIM_Encoder_Stop_DMA 16 static +stm32f7xx_hal_tim.c:3178:6:HAL_TIM_IRQHandler 16 static +stm32f7xx_hal_tim.c:3408:19:HAL_TIM_OC_ConfigChannel 24 static +stm32f7xx_hal_tim.c:3508:19:HAL_TIM_IC_ConfigChannel 24 static +stm32f7xx_hal_tim.c:3607:19:HAL_TIM_PWM_ConfigChannel 24 static +stm32f7xx_hal_tim.c:3756:19:HAL_TIM_OnePulse_ConfigChannel 56 static +stm32f7xx_hal_tim.c:3902:19:HAL_TIM_DMABurst_WriteStart 24 static +stm32f7xx_hal_tim.c:4071:19:HAL_TIM_DMABurst_WriteStop 24 static +stm32f7xx_hal_tim.c:4174:19:HAL_TIM_DMABurst_ReadStart 24 static +stm32f7xx_hal_tim.c:4338:19:HAL_TIM_DMABurst_ReadStop 24 static +stm32f7xx_hal_tim.c:4417:19:HAL_TIM_GenerateEvent 16 static +stm32f7xx_hal_tim.c:4456:19:HAL_TIM_ConfigOCrefClear 24 static +stm32f7xx_hal_tim.c:4608:19:HAL_TIM_ConfigClockSource 24 static +stm32f7xx_hal_tim.c:4760:19:HAL_TIM_ConfigTI1Input 24 static +stm32f7xx_hal_tim.c:4792:19:HAL_TIM_SlaveConfigSynchro 16 static +stm32f7xx_hal_tim.c:4832:19:HAL_TIM_SlaveConfigSynchro_IT 16 static +stm32f7xx_hal_tim.c:4875:10:HAL_TIM_ReadCapturedValue 24 static +stm32f7xx_hal_tim.c:4959:13:HAL_TIM_PeriodElapsedCallback 16 static +stm32f7xx_hal_tim.c:4974:13:HAL_TIM_PeriodElapsedHalfCpltCallback 16 static +stm32f7xx_hal_tim.c:4989:13:HAL_TIM_OC_DelayElapsedCallback 16 static +stm32f7xx_hal_tim.c:5004:13:HAL_TIM_IC_CaptureCallback 16 static +stm32f7xx_hal_tim.c:5019:13:HAL_TIM_IC_CaptureHalfCpltCallback 16 static +stm32f7xx_hal_tim.c:5034:13:HAL_TIM_PWM_PulseFinishedCallback 16 static +stm32f7xx_hal_tim.c:5049:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 16 static +stm32f7xx_hal_tim.c:5064:13:HAL_TIM_TriggerCallback 16 static +stm32f7xx_hal_tim.c:5079:13:HAL_TIM_TriggerHalfCpltCallback 16 static +stm32f7xx_hal_tim.c:5094:13:HAL_TIM_ErrorCallback 16 static +stm32f7xx_hal_tim.c:5621:22:HAL_TIM_Base_GetState 16 static +stm32f7xx_hal_tim.c:5631:22:HAL_TIM_OC_GetState 16 static +stm32f7xx_hal_tim.c:5641:22:HAL_TIM_PWM_GetState 16 static +stm32f7xx_hal_tim.c:5651:22:HAL_TIM_IC_GetState 16 static +stm32f7xx_hal_tim.c:5661:22:HAL_TIM_OnePulse_GetState 16 static +stm32f7xx_hal_tim.c:5671:22:HAL_TIM_Encoder_GetState 16 static +stm32f7xx_hal_tim.c:5693:6:TIM_DMAError 24 static +stm32f7xx_hal_tim.c:5711:6:TIM_DMADelayPulseCplt 24 static +stm32f7xx_hal_tim.c:5752:6:TIM_DMADelayPulseHalfCplt 24 static +stm32f7xx_hal_tim.c:5793:6:TIM_DMACaptureCplt 24 static +stm32f7xx_hal_tim.c:5834:6:TIM_DMACaptureHalfCplt 24 static +stm32f7xx_hal_tim.c:5875:13:TIM_DMAPeriodElapsedCplt 24 static +stm32f7xx_hal_tim.c:5893:13:TIM_DMAPeriodElapsedHalfCplt 24 static +stm32f7xx_hal_tim.c:5911:13:TIM_DMATriggerCplt 24 static +stm32f7xx_hal_tim.c:5929:13:TIM_DMATriggerHalfCplt 24 static +stm32f7xx_hal_tim.c:5948:6:TIM_Base_SetConfig 24 static +stm32f7xx_hal_tim.c:5996:13:TIM_OC1_SetConfig 32 static +stm32f7xx_hal_tim.c:6071:6:TIM_OC2_SetConfig 32 static +stm32f7xx_hal_tim.c:6147:13:TIM_OC3_SetConfig 32 static +stm32f7xx_hal_tim.c:6221:13:TIM_OC4_SetConfig 32 static +stm32f7xx_hal_tim.c:6281:13:TIM_OC5_SetConfig 32 static +stm32f7xx_hal_tim.c:6334:13:TIM_OC6_SetConfig 32 static +stm32f7xx_hal_tim.c:6388:26:TIM_SlaveTimer_SetConfig 32 static +stm32f7xx_hal_tim.c:6519:6:TIM_TI1_SetConfig 32 static +stm32f7xx_hal_tim.c:6566:13:TIM_TI1_ConfigInputStage 32 static +stm32f7xx_hal_tim.c:6609:13:TIM_TI2_SetConfig 32 static +stm32f7xx_hal_tim.c:6649:13:TIM_TI2_ConfigInputStage 32 static +stm32f7xx_hal_tim.c:6692:13:TIM_TI3_SetConfig 32 static +stm32f7xx_hal_tim.c:6740:13:TIM_TI4_SetConfig 32 static +stm32f7xx_hal_tim.c:6783:13:TIM_ITRx_SetConfig 24 static +stm32f7xx_hal_tim.c:6813:6:TIM_ETR_SetConfig 32 static +stm32f7xx_hal_tim.c:6845:6:TIM_CCxChannelCmd 32 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d new file mode 100644 index 0000000..2112b64 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o new file mode 100644 index 0000000..b8041f2 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su new file mode 100644 index 0000000..c3f050e --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.su @@ -0,0 +1,41 @@ +stm32f7xx_hal_tim_ex.c:131:19:HAL_TIMEx_HallSensor_Init 48 static +stm32f7xx_hal_tim_ex.c:223:19:HAL_TIMEx_HallSensor_DeInit 16 static +stm32f7xx_hal_tim_ex.c:259:13:HAL_TIMEx_HallSensor_MspInit 16 static +stm32f7xx_hal_tim_ex.c:274:13:HAL_TIMEx_HallSensor_MspDeInit 16 static +stm32f7xx_hal_tim_ex.c:289:19:HAL_TIMEx_HallSensor_Start 24 static +stm32f7xx_hal_tim_ex.c:316:19:HAL_TIMEx_HallSensor_Stop 16 static +stm32f7xx_hal_tim_ex.c:337:19:HAL_TIMEx_HallSensor_Start_IT 24 static +stm32f7xx_hal_tim_ex.c:367:19:HAL_TIMEx_HallSensor_Stop_IT 16 static +stm32f7xx_hal_tim_ex.c:393:19:HAL_TIMEx_HallSensor_Start_DMA 32 static +stm32f7xx_hal_tim_ex.c:453:19:HAL_TIMEx_HallSensor_Stop_DMA 16 static +stm32f7xx_hal_tim_ex.c:509:19:HAL_TIMEx_OCN_Start 24 static +stm32f7xx_hal_tim_ex.c:544:19:HAL_TIMEx_OCN_Stop 16 static +stm32f7xx_hal_tim_ex.c:573:19:HAL_TIMEx_OCN_Start_IT 24 static +stm32f7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Stop_IT 24 static +stm32f7xx_hal_tim_ex.c:705:19:HAL_TIMEx_OCN_Start_DMA 32 static +stm32f7xx_hal_tim_ex.c:823:19:HAL_TIMEx_OCN_Stop_DMA 16 static +stm32f7xx_hal_tim_ex.c:918:19:HAL_TIMEx_PWMN_Start 24 static +stm32f7xx_hal_tim_ex.c:952:19:HAL_TIMEx_PWMN_Stop 16 static +stm32f7xx_hal_tim_ex.c:981:19:HAL_TIMEx_PWMN_Start_IT 24 static +stm32f7xx_hal_tim_ex.c:1046:19:HAL_TIMEx_PWMN_Stop_IT 24 static +stm32f7xx_hal_tim_ex.c:1113:19:HAL_TIMEx_PWMN_Start_DMA 32 static +stm32f7xx_hal_tim_ex.c:1230:19:HAL_TIMEx_PWMN_Stop_DMA 16 static +stm32f7xx_hal_tim_ex.c:1313:19:HAL_TIMEx_OnePulseN_Start 16 static +stm32f7xx_hal_tim_ex.c:1338:19:HAL_TIMEx_OnePulseN_Stop 16 static +stm32f7xx_hal_tim_ex.c:1367:19:HAL_TIMEx_OnePulseN_Start_IT 16 static +stm32f7xx_hal_tim_ex.c:1398:19:HAL_TIMEx_OnePulseN_Stop_IT 16 static +stm32f7xx_hal_tim_ex.c:1469:19:HAL_TIMEx_ConfigCommutEvent 24 static +stm32f7xx_hal_tim_ex.c:1525:19:HAL_TIMEx_ConfigCommutEvent_IT 24 static +stm32f7xx_hal_tim_ex.c:1582:19:HAL_TIMEx_ConfigCommutEvent_DMA 24 static +stm32f7xx_hal_tim_ex.c:1631:19:HAL_TIMEx_MasterConfigSynchronization 24 static +stm32f7xx_hal_tim_ex.c:1704:19:HAL_TIMEx_ConfigBreakDeadTime 24 static +stm32f7xx_hal_tim_ex.c:1904:19:HAL_TIMEx_RemapConfig 16 static +stm32f7xx_hal_tim_ex.c:1933:19:HAL_TIMEx_GroupChannel5 16 static +stm32f7xx_hal_tim_ex.c:1983:13:HAL_TIMEx_CommutCallback 16 static +stm32f7xx_hal_tim_ex.c:1997:13:HAL_TIMEx_CommutHalfCpltCallback 16 static +stm32f7xx_hal_tim_ex.c:2012:13:HAL_TIMEx_BreakCallback 16 static +stm32f7xx_hal_tim_ex.c:2027:13:HAL_TIMEx_Break2Callback 16 static +stm32f7xx_hal_tim_ex.c:2060:22:HAL_TIMEx_HallSensor_GetState 16 static +stm32f7xx_hal_tim_ex.c:2083:6:TIMEx_DMACommutationCplt 24 static +stm32f7xx_hal_tim_ex.c:2102:6:TIMEx_DMACommutationHalfCplt 24 static +stm32f7xx_hal_tim_ex.c:2129:13:TIM_CCxNChannelCmd 32 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d new file mode 100644 index 0000000..f8207f6 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o new file mode 100644 index 0000000..490f5fe Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su new file mode 100644 index 0000000..8880719 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.su @@ -0,0 +1,63 @@ +stm32f7xx_hal_uart.c:287:19:HAL_UART_Init 16 static +stm32f7xx_hal_uart.c:360:19:HAL_HalfDuplex_Init 16 static +stm32f7xx_hal_uart.c:433:19:HAL_LIN_Init 16 static +stm32f7xx_hal_uart.c:530:19:HAL_MultiProcessor_Init 24 static +stm32f7xx_hal_uart.c:604:19:HAL_UART_DeInit 16 static +stm32f7xx_hal_uart.c:649:13:HAL_UART_MspInit 16 static +stm32f7xx_hal_uart.c:664:13:HAL_UART_MspDeInit 16 static +stm32f7xx_hal_uart.c:1011:19:HAL_UART_Transmit 48 static +stm32f7xx_hal_uart.c:1096:19:HAL_UART_Receive 48 static +stm32f7xx_hal_uart.c:1181:19:HAL_UART_Transmit_IT 24 static +stm32f7xx_hal_uart.c:1234:19:HAL_UART_Receive_IT 24 static +stm32f7xx_hal_uart.c:1293:19:HAL_UART_Transmit_DMA 24 static +stm32f7xx_hal_uart.c:1369:19:HAL_UART_Receive_DMA 24 static +stm32f7xx_hal_uart.c:1440:19:HAL_UART_DMAPause 24 static +stm32f7xx_hal_uart.c:1474:19:HAL_UART_DMAResume 16 static +stm32f7xx_hal_uart.c:1506:19:HAL_UART_DMAStop 24 static +stm32f7xx_hal_uart.c:1581:19:HAL_UART_Abort 16 static +stm32f7xx_hal_uart.c:1669:19:HAL_UART_AbortTransmit 16 static +stm32f7xx_hal_uart.c:1721:19:HAL_UART_AbortReceive 16 static +stm32f7xx_hal_uart.c:1781:19:HAL_UART_Abort_IT 24 static +stm32f7xx_hal_uart.c:1920:19:HAL_UART_AbortTransmit_IT 16 static +stm32f7xx_hal_uart.c:2004:19:HAL_UART_AbortReceive_IT 16 static +stm32f7xx_hal_uart.c:2088:6:HAL_UART_IRQHandler 40 static +stm32f7xx_hal_uart.c:2294:13:HAL_UART_TxCpltCallback 16 static +stm32f7xx_hal_uart.c:2309:13:HAL_UART_TxHalfCpltCallback 16 static +stm32f7xx_hal_uart.c:2324:13:HAL_UART_RxCpltCallback 16 static +stm32f7xx_hal_uart.c:2339:13:HAL_UART_RxHalfCpltCallback 16 static +stm32f7xx_hal_uart.c:2354:13:HAL_UART_ErrorCallback 16 static +stm32f7xx_hal_uart.c:2369:13:HAL_UART_AbortCpltCallback 16 static +stm32f7xx_hal_uart.c:2384:13:HAL_UART_AbortTransmitCpltCallback 16 static +stm32f7xx_hal_uart.c:2399:13:HAL_UART_AbortReceiveCpltCallback 16 static +stm32f7xx_hal_uart.c:2463:6:HAL_UART_ReceiverTimeout_Config 16 static +stm32f7xx_hal_uart.c:2475:19:HAL_UART_EnableReceiverTimeout 16 static +stm32f7xx_hal_uart.c:2506:19:HAL_UART_DisableReceiverTimeout 16 static +stm32f7xx_hal_uart.c:2537:19:HAL_MultiProcessor_EnableMuteMode 16 static +stm32f7xx_hal_uart.c:2557:19:HAL_MultiProcessor_DisableMuteMode 16 static +stm32f7xx_hal_uart.c:2577:6:HAL_MultiProcessor_EnterMuteMode 16 static +stm32f7xx_hal_uart.c:2587:19:HAL_HalfDuplex_EnableTransmitter 16 static +stm32f7xx_hal_uart.c:2610:19:HAL_HalfDuplex_EnableReceiver 16 static +stm32f7xx_hal_uart.c:2634:19:HAL_LIN_SendBreak 16 static +stm32f7xx_hal_uart.c:2679:23:HAL_UART_GetState 24 static +stm32f7xx_hal_uart.c:2695:10:HAL_UART_GetError 16 static +stm32f7xx_hal_uart.c:2740:19:UART_SetConfig 40 static +stm32f7xx_hal_uart.c:2880:6:UART_AdvFeatureConfig 16 static +stm32f7xx_hal_uart.c:2954:19:UART_CheckIdleState 32 static +stm32f7xx_hal_uart.c:3006:19:UART_WaitOnFlagUntilTimeout 24 static +stm32f7xx_hal_uart.c:3061:13:UART_EndTxTransfer 16 static +stm32f7xx_hal_uart.c:3076:13:UART_EndRxTransfer 16 static +stm32f7xx_hal_uart.c:3095:13:UART_DMATransmitCplt 24 static +stm32f7xx_hal_uart.c:3129:13:UART_DMATxHalfCplt 24 static +stm32f7xx_hal_uart.c:3147:13:UART_DMAReceiveCplt 24 static +stm32f7xx_hal_uart.c:3182:13:UART_DMARxHalfCplt 24 static +stm32f7xx_hal_uart.c:3200:13:UART_DMAError 32 static +stm32f7xx_hal_uart.c:3240:13:UART_DMAAbortOnError 24 static +stm32f7xx_hal_uart.c:3263:13:UART_DMATxAbortCallback 24 static +stm32f7xx_hal_uart.c:3312:13:UART_DMARxAbortCallback 24 static +stm32f7xx_hal_uart.c:3363:13:UART_DMATxOnlyAbortCallback 24 static +stm32f7xx_hal_uart.c:3391:13:UART_DMARxOnlyAbortCallback 24 static +stm32f7xx_hal_uart.c:3423:13:UART_TxISR_8BIT 16 static +stm32f7xx_hal_uart.c:3452:13:UART_TxISR_16BIT 24 static +stm32f7xx_hal_uart.c:3484:13:UART_EndTransmit_IT 16 static +stm32f7xx_hal_uart.c:3509:13:UART_RxISR_8BIT 24 static +stm32f7xx_hal_uart.c:3559:13:UART_RxISR_16BIT 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d new file mode 100644 index 0000000..55929c1 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o new file mode 100644 index 0000000..131f79d Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su new file mode 100644 index 0000000..ef60486 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.su @@ -0,0 +1,2 @@ +stm32f7xx_hal_uart_ex.c:150:19:HAL_RS485Ex_Init 32 static +stm32f7xx_hal_uart_ex.c:312:19:HAL_MultiProcessorEx_AddressLength_Set 16 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d new file mode 100644 index 0000000..ab32145 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d @@ -0,0 +1,131 @@ +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o: \ + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + ../Core/Inc/stm32f7xx_hal_conf.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + ../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: + +../Core/Inc/stm32f7xx_hal_conf.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h: + +../Drivers/CMSIS/Include/core_cm7.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Include/mpu_armv7.h: + +../Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: + +../Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o new file mode 100644 index 0000000..56a03f5 Binary files /dev/null and b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o differ diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su new file mode 100644 index 0000000..e7c6b34 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.su @@ -0,0 +1,22 @@ +stm32f7xx_ll_fmc.c:132:20:FMC_NORSRAM_Init 24 static +stm32f7xx_ll_fmc.c:209:19:FMC_NORSRAM_DeInit 24 static +stm32f7xx_ll_fmc.c:246:19:FMC_NORSRAM_Timing_Init 32 static +stm32f7xx_ll_fmc.c:300:20:FMC_NORSRAM_Extended_Timing_Init 32 static +stm32f7xx_ll_fmc.c:368:19:FMC_NORSRAM_WriteOperation_Enable 16 static +stm32f7xx_ll_fmc.c:386:19:FMC_NORSRAM_WriteOperation_Disable 16 static +stm32f7xx_ll_fmc.c:455:19:FMC_NAND_Init 24 static +stm32f7xx_ll_fmc.c:500:19:FMC_NAND_CommonSpace_Timing_Init 32 static +stm32f7xx_ll_fmc.c:539:19:FMC_NAND_AttributeSpace_Timing_Init 32 static +stm32f7xx_ll_fmc.c:575:19:FMC_NAND_DeInit 16 static +stm32f7xx_ll_fmc.c:619:19:FMC_NAND_ECC_Enable 16 static +stm32f7xx_ll_fmc.c:638:19:FMC_NAND_ECC_Disable 16 static +stm32f7xx_ll_fmc.c:658:19:FMC_NAND_GetECC 32 static +stm32f7xx_ll_fmc.c:742:19:FMC_SDRAM_Init 24 static +stm32f7xx_ll_fmc.c:823:19:FMC_SDRAM_Timing_Init 32 static +stm32f7xx_ll_fmc.c:893:19:FMC_SDRAM_DeInit 16 static +stm32f7xx_ll_fmc.c:934:19:FMC_SDRAM_WriteProtection_Enable 16 static +stm32f7xx_ll_fmc.c:951:19:FMC_SDRAM_WriteProtection_Disable 16 static +stm32f7xx_ll_fmc.c:971:19:FMC_SDRAM_SendCommand 32 static +stm32f7xx_ll_fmc.c:1000:19:FMC_SDRAM_ProgramRefreshRate 16 static +stm32f7xx_ll_fmc.c:1018:19:FMC_SDRAM_SetAutoRefreshNumber 16 static +stm32f7xx_ll_fmc.c:1039:10:FMC_SDRAM_GetModeStatus 24 static diff --git a/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..10e9774 --- /dev/null +++ b/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,174 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c + +OBJS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + +C_DEPS += \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o: ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d new file mode 100644 index 0000000..858af67 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d @@ -0,0 +1,56 @@ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h + +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o new file mode 100644 index 0000000..8fdcb6f Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su new file mode 100644 index 0000000..5fabf54 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.su @@ -0,0 +1,56 @@ +cmsis_os.c:103:31:makeFreeRtosPriority 24 static +cmsis_os.c:116:19:makeCmsisPriority 24 static +cmsis_os.c:130:12:inHandlerMode 16 static,ignoring_inline_asm +cmsis_os.c:150:10:osKernelStart 8 static +cmsis_os.c:165:9:osKernelRunning 8 static +cmsis_os.c:184:10:osKernelSysTick 8 static +cmsis_os.c:202:12:osThreadCreate 56 static +cmsis_os.c:240:12:osThreadGetId 8 static +cmsis_os.c:255:10:osThreadTerminate 16 static +cmsis_os.c:270:10:osThreadYield 4 static,ignoring_inline_asm +cmsis_os.c:284:10:osThreadSetPriority 16 static +cmsis_os.c:300:12:osThreadGetPriority 16 static +cmsis_os.c:322:10:osDelay 24 static +cmsis_os.c:357:11:osTimerCreate 24 static +cmsis_os.c:404:10:osTimerStart 24 static +cmsis_os.c:443:10:osTimerStop 24 static +cmsis_os.c:472:10:osTimerDelete 24 static +cmsis_os.c:502:9:osSignalSet 32 static,ignoring_inline_asm +cmsis_os.c:543:9:osSignalWait 48 static +cmsis_os.c:597:11:osMutexCreate 16 static +cmsis_os.c:626:10:osMutexWait 24 static,ignoring_inline_asm +cmsis_os.c:666:10:osMutexRelease 24 static,ignoring_inline_asm +cmsis_os.c:690:10:osMutexDelete 16 static +cmsis_os.c:712:15:osSemaphoreCreate 32 static +cmsis_os.c:779:9:osSemaphoreWait 24 static,ignoring_inline_asm +cmsis_os.c:819:10:osSemaphoreRelease 24 static,ignoring_inline_asm +cmsis_os.c:846:10:osSemaphoreDelete 16 static +cmsis_os.c:883:10:osPoolCreate 32 static +cmsis_os.c:936:7:osPoolAlloc 48 static,ignoring_inline_asm +cmsis_os.c:977:7:osPoolCAlloc 24 static +cmsis_os.c:996:10:osPoolFree 24 static +cmsis_os.c:1040:14:osMessageCreate 32 static +cmsis_os.c:1067:10:osMessagePut 32 static,ignoring_inline_asm +cmsis_os.c:1099:9:osMessageGet 56 static,ignoring_inline_asm +cmsis_os.c:1168:11:osMailCreate 40 static +cmsis_os.c:1214:7:osMailAlloc 24 static +cmsis_os.c:1236:7:osMailCAlloc 24 static +cmsis_os.c:1257:10:osMailPut 24 static,ignoring_inline_asm +cmsis_os.c:1290:9:osMailGet 56 static,ignoring_inline_asm +cmsis_os.c:1346:10:osMailFree 16 static +cmsis_os.c:1362:6:osSystickHandler 8 static +cmsis_os.c:1432:10:osThreadSuspend 16 static +cmsis_os.c:1448:10:osThreadResume 16 static,ignoring_inline_asm +cmsis_os.c:1472:10:osThreadSuspendAll 8 static +cmsis_os.c:1483:10:osThreadResumeAll 8 static +cmsis_os.c:1500:10:osDelayUntil 16 static +cmsis_os.c:1520:10:osAbortDelay 16 static +cmsis_os.c:1541:10:osThreadList 16 static +cmsis_os.c:1555:9:osMessagePeek 48 static +cmsis_os.c:1596:10:osMessageWaiting 16 static +cmsis_os.c:1612:10:osMessageAvailableSpace 16 static +cmsis_os.c:1622:10:osMessageDelete 16 static +cmsis_os.c:1638:11:osRecursiveMutexCreate 16 static +cmsis_os.c:1664:10:osRecursiveMutexRelease 24 static +cmsis_os.c:1685:10:osRecursiveMutexWait 24 static +cmsis_os.c:1724:10:osSemaphoreGetCount 16 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk new file mode 100644 index 0000000..f302221 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o: ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d new file mode 100644 index 0000000..e4d64ba --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.d @@ -0,0 +1,32 @@ +Middlewares/Third_Party/FreeRTOS/Source/croutine.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o new file mode 100644 index 0000000..ba6096c Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/croutine.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d new file mode 100644 index 0000000..20b16f1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.d @@ -0,0 +1,41 @@ +Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o new file mode 100644 index 0000000..a1d1b62 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su new file mode 100644 index 0000000..620af88 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/event_groups.su @@ -0,0 +1,11 @@ +event_groups.c:93:21:xEventGroupCreateStatic 32 static,ignoring_inline_asm +event_groups.c:145:21:xEventGroupCreate 16 static +event_groups.c:191:13:xEventGroupSync 56 static,ignoring_inline_asm +event_groups.c:311:13:xEventGroupWaitBits 72 static,ignoring_inline_asm +event_groups.c:461:13:xEventGroupClearBits 32 static,ignoring_inline_asm +event_groups.c:503:13:xEventGroupGetBitsFromISR 40 static,ignoring_inline_asm +event_groups.c:519:13:xEventGroupSetBits 64 static,ignoring_inline_asm +event_groups.c:613:6:vEventGroupDelete 32 static,ignoring_inline_asm +event_groups.c:657:6:vEventGroupSetBitsCallback 16 static +event_groups.c:665:6:vEventGroupClearBitsCallback 16 static +event_groups.c:671:19:prvTestWaitCondition 32 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d new file mode 100644 index 0000000..8e95ed0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.d @@ -0,0 +1,26 @@ +Middlewares/Third_Party/FreeRTOS/Source/list.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/list.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o new file mode 100644 index 0000000..453b1ce Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su new file mode 100644 index 0000000..e840c82 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/list.su @@ -0,0 +1,5 @@ +list.c:37:6:vListInitialise 16 static +list.c:62:6:vListInitialiseItem 16 static +list.c:74:6:vListInsertEnd 24 static +list.c:103:6:vListInsert 24 static +list.c:170:13:uxListRemove 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d new file mode 100644 index 0000000..ed07ebe --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d @@ -0,0 +1,29 @@ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o new file mode 100644 index 0000000..31498bd Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su new file mode 100644 index 0000000..05c947b --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.su @@ -0,0 +1,13 @@ +port.c:181:14:pxPortInitialiseStack 24 static +port.c:211:13:prvTaskExitError 24 static,ignoring_inline_asm +port.c:236:6:SVC_Handler 0 static,ignoring_inline_asm +port.c:255:13:prvPortStartFirstTask 0 static,ignoring_inline_asm +port.c:281:12:xPortStartScheduler 24 static,ignoring_inline_asm +port.c:383:6:vPortEndScheduler 16 static,ignoring_inline_asm +port.c:391:6:vPortEnterCritical 16 static,ignoring_inline_asm +port.c:408:6:vPortExitCritical 16 static,ignoring_inline_asm +port.c:419:6:PendSV_Handler 0 static,ignoring_inline_asm +port.c:478:6:SysTick_Handler 16 static,ignoring_inline_asm +port.c:669:30:vPortSetupTimerInterrupt 4 static +port.c:691:13:vPortEnableVFP 0 static,ignoring_inline_asm +port.c:707:7:vPortValidateInterruptPriority 24 static,ignoring_inline_asm diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk new file mode 100644 index 0000000..b5f124f --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d new file mode 100644 index 0000000..a2ec253 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d @@ -0,0 +1,29 @@ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o new file mode 100644 index 0000000..b34ce18 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su new file mode 100644 index 0000000..5f8251a --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.su @@ -0,0 +1,7 @@ +heap_4.c:113:7:pvPortMalloc 48 static,ignoring_inline_asm +heap_4.c:263:6:vPortFree 32 static,ignoring_inline_asm +heap_4.c:311:8:xPortGetFreeHeapSize 4 static +heap_4.c:317:8:xPortGetMinimumEverFreeHeapSize 4 static +heap_4.c:323:6:vPortInitialiseBlocks 4 static +heap_4.c:329:13:prvHeapInit 24 static +heap_4.c:377:13:prvInsertBlockIntoFreeList 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk new file mode 100644 index 0000000..4312653 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk @@ -0,0 +1,19 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o: ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d new file mode 100644 index 0000000..c2323dc --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.d @@ -0,0 +1,35 @@ +Middlewares/Third_Party/FreeRTOS/Source/queue.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o new file mode 100644 index 0000000..c2e8255 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su new file mode 100644 index 0000000..eadc524 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/queue.su @@ -0,0 +1,34 @@ +queue.c:255:12:xQueueGenericReset 24 static,ignoring_inline_asm +queue.c:310:16:xQueueGenericCreateStatic 64 static,ignoring_inline_asm +queue.c:368:16:xQueueGenericCreate 48 static,ignoring_inline_asm +queue.c:429:13:prvInitialiseNewQueue 24 static +queue.c:473:14:prvInitialiseMutex 16 static +queue.c:503:16:xQueueCreateMutex 32 static +queue.c:519:16:xQueueCreateMutexStatic 40 static +queue.c:596:13:xQueueGiveMutexRecursive 40 static,ignoring_inline_asm +queue.c:651:13:xQueueTakeMutexRecursive 40 static,ignoring_inline_asm +queue.c:693:16:xQueueCreateCountingSemaphoreStatic 48 static,ignoring_inline_asm +queue.c:721:16:xQueueCreateCountingSemaphore 32 static,ignoring_inline_asm +queue.c:747:12:xQueueGenericSend 64 static,ignoring_inline_asm +queue.c:957:12:xQueueGenericSendFromISR 64 static,ignoring_inline_asm +queue.c:1108:12:xQueueGiveFromISR 64 static,ignoring_inline_asm +queue.c:1273:12:xQueueReceive 56 static,ignoring_inline_asm +queue.c:1414:12:xQueueSemaphoreTake 64 static,ignoring_inline_asm +queue.c:1632:12:xQueuePeek 64 static,ignoring_inline_asm +queue.c:1781:12:xQueueReceiveFromISR 64 static,ignoring_inline_asm +queue.c:1872:12:xQueuePeekFromISR 56 static,ignoring_inline_asm +queue.c:1926:13:uxQueueMessagesWaiting 24 static,ignoring_inline_asm +queue.c:1942:13:uxQueueSpacesAvailable 32 static,ignoring_inline_asm +queue.c:1959:13:uxQueueMessagesWaitingFromISR 32 static,ignoring_inline_asm +queue.c:1971:6:vQueueDelete 24 static,ignoring_inline_asm +queue.c:2045:21:prvGetDisinheritPriorityAfterTimeout 24 static +queue.c:2070:19:prvCopyDataToQueue 32 static +queue.c:2149:13:prvCopyDataFromQueue 16 static +queue.c:2167:13:prvUnlockQueue 24 static +queue.c:2287:19:prvIsQueueEmpty 24 static +queue.c:2308:12:xQueueIsQueueEmptyFromISR 32 static,ignoring_inline_asm +queue.c:2327:19:prvIsQueueFull 24 static +queue.c:2348:12:xQueueIsQueueFullFromISR 32 static,ignoring_inline_asm +queue.c:2644:7:vQueueAddToRegistry 24 static +queue.c:2673:14:pcQueueGetName 24 static +queue.c:2701:7:vQueueUnregisterQueue 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d new file mode 100644 index 0000000..191afe8 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d @@ -0,0 +1,32 @@ +Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o new file mode 100644 index 0000000..4482606 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su new file mode 100644 index 0000000..1899fa0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.su @@ -0,0 +1,22 @@ +stream_buffer.c:219:23:xStreamBufferGenericCreate 56 static,ignoring_inline_asm +stream_buffer.c:283:23:xStreamBufferGenericCreateStatic 72 static,ignoring_inline_asm +stream_buffer.c:359:6:vStreamBufferDelete 24 static,ignoring_inline_asm +stream_buffer.c:392:12:xStreamBufferReset 40 static,ignoring_inline_asm +stream_buffer.c:441:12:xStreamBufferSetTriggerLevel 32 static,ignoring_inline_asm +stream_buffer.c:470:8:xStreamBufferSpacesAvailable 32 static,ignoring_inline_asm +stream_buffer.c:494:8:xStreamBufferBytesAvailable 32 static,ignoring_inline_asm +stream_buffer.c:506:8:xStreamBufferSend 72 static,ignoring_inline_asm +stream_buffer.c:610:8:xStreamBufferSendFromISR 72 static,ignoring_inline_asm +stream_buffer.c:661:15:prvWriteMessageToBuffer 32 static +stream_buffer.c:713:8:xStreamBufferReceive 64 static,ignoring_inline_asm +stream_buffer.c:817:8:xStreamBufferNextMessageLengthBytes 48 static,ignoring_inline_asm +stream_buffer.c:861:8:xStreamBufferReceiveFromISR 72 static,ignoring_inline_asm +stream_buffer.c:918:15:prvReadMessageFromBuffer 40 static +stream_buffer.c:970:12:xStreamBufferIsEmpty 32 static,ignoring_inline_asm +stream_buffer.c:993:12:xStreamBufferIsFull 32 static,ignoring_inline_asm +stream_buffer.c:1028:12:xStreamBufferSendCompletedFromISR 56 static,ignoring_inline_asm +stream_buffer.c:1058:12:xStreamBufferReceiveCompletedFromISR 56 static,ignoring_inline_asm +stream_buffer.c:1088:15:prvWriteBytesToBuffer 48 static,ignoring_inline_asm +stream_buffer.c:1134:15:prvReadBytesFromBuffer 48 static,ignoring_inline_asm +stream_buffer.c:1189:15:prvBytesInBuffer 24 static +stream_buffer.c:1209:13:prvInitialiseNewStreamBuffer 32 static,ignoring_inline_asm diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk new file mode 100644 index 0000000..e0613a5 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/subdir.mk @@ -0,0 +1,49 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ +../Middlewares/Third_Party/FreeRTOS/Source/list.c \ +../Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \ +../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +../Middlewares/Third_Party/FreeRTOS/Source/timers.c + +OBJS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.o \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o \ +./Middlewares/Third_Party/FreeRTOS/Source/list.o \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.o \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.o \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.o + +C_DEPS += \ +./Middlewares/Third_Party/FreeRTOS/Source/croutine.d \ +./Middlewares/Third_Party/FreeRTOS/Source/event_groups.d \ +./Middlewares/Third_Party/FreeRTOS/Source/list.d \ +./Middlewares/Third_Party/FreeRTOS/Source/queue.d \ +./Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d \ +./Middlewares/Third_Party/FreeRTOS/Source/tasks.d \ +./Middlewares/Third_Party/FreeRTOS/Source/timers.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/FreeRTOS/Source/croutine.o: ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/croutine.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/event_groups.o: ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/event_groups.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/list.o: ../Middlewares/Third_Party/FreeRTOS/Source/list.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/list.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/queue.o: ../Middlewares/Third_Party/FreeRTOS/Source/queue.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/queue.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o: ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/tasks.o: ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/tasks.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Middlewares/Third_Party/FreeRTOS/Source/timers.o: ../Middlewares/Third_Party/FreeRTOS/Source/timers.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F746xx -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc -I../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy -I../Middlewares/Third_Party/FreeRTOS/Source/include -I../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS -I../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 -I../Drivers/CMSIS/Device/ST/STM32F7xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Middlewares/Third_Party/FreeRTOS/Source/timers.d" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" + diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d new file mode 100644 index 0000000..894bbfd --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.d @@ -0,0 +1,38 @@ +Middlewares/Third_Party/FreeRTOS/Source/tasks.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o new file mode 100644 index 0000000..529081b Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su new file mode 100644 index 0000000..c9c96fa --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/tasks.su @@ -0,0 +1,54 @@ +tasks.c:578:15:xTaskCreateStatic 64 static,ignoring_inline_asm +tasks.c:730:13:xTaskCreate 56 static +tasks.c:821:13:prvInitialiseNewTask 40 static,ignoring_inline_asm +tasks.c:1072:13:prvAddNewTaskToReadyList 16 static,ignoring_inline_asm +tasks.c:1157:7:vTaskDelete 24 static,ignoring_inline_asm +tasks.c:1333:7:vTaskDelay 24 static,ignoring_inline_asm +tasks.c:1470:14:uxTaskPriorityGet 24 static +tasks.c:1492:14:uxTaskPriorityGetFromISR 40 static,ignoring_inline_asm +tasks.c:1532:7:vTaskPrioritySet 40 static,ignoring_inline_asm +tasks.c:1696:7:vTaskSuspend 24 static,ignoring_inline_asm +tasks.c:1797:20:prvTaskIsTaskSuspended 32 static,ignoring_inline_asm +tasks.c:1843:7:vTaskResume 24 static,ignoring_inline_asm +tasks.c:1897:13:xTaskResumeFromISR 48 static,ignoring_inline_asm +tasks.c:1967:6:vTaskStartScheduler 48 static,ignoring_inline_asm +tasks.c:2089:6:vTaskEndScheduler 16 static,ignoring_inline_asm +tasks.c:2100:6:vTaskSuspendAll 4 static,ignoring_inline_asm +tasks.c:2174:12:xTaskResumeAll 24 static,ignoring_inline_asm +tasks.c:2284:12:xTaskGetTickCount 16 static +tasks.c:2299:12:xTaskGetTickCountFromISR 16 static +tasks.c:2330:13:uxTaskGetNumberOfTasks 4 static +tasks.c:2338:7:pcTaskGetName 24 static,ignoring_inline_asm +tasks.c:2665:12:xTaskIncrementTick 32 static,ignoring_inline_asm +tasks.c:2839:7:vTaskSetApplicationTaskTag 24 static +tasks.c:2868:21:xTaskGetApplicationTaskTag 24 static +tasks.c:2892:21:xTaskGetApplicationTaskTagFromISR 40 static,ignoring_inline_asm +tasks.c:2917:13:xTaskCallApplicationTaskHook 24 static +tasks.c:2947:6:vTaskSwitchContext 40 static,ignoring_inline_asm +tasks.c:3020:6:vTaskPlaceOnEventList 24 static,ignoring_inline_asm +tasks.c:3037:6:vTaskPlaceOnUnorderedEventList 32 static,ignoring_inline_asm +tasks.c:3094:12:xTaskRemoveFromEventList 32 static,ignoring_inline_asm +tasks.c:3162:6:vTaskRemoveFromUnorderedEventList 32 static,ignoring_inline_asm +tasks.c:3196:6:vTaskSetTimeOutState 24 static,ignoring_inline_asm +tasks.c:3208:6:vTaskInternalSetTimeOutState 16 static +tasks.c:3216:12:xTaskCheckForTimeOut 40 static,ignoring_inline_asm +tasks.c:3279:6:vTaskMissedYield 4 static +tasks.c:3334:8:prvIdleTask 16 static,ignoring_inline_asm +tasks.c:3546:13:prvInitialiseTaskLists 16 static +tasks.c:3578:13:prvCheckTasksWaitingTermination 16 static +tasks.c:3826:14:prvDeleteTCB 24 static,ignoring_inline_asm +tasks.c:3880:13:prvResetNextTaskUnblockTime 16 static +tasks.c:3906:15:xTaskGetCurrentTaskHandle 16 static +tasks.c:3923:13:xTaskGetSchedulerState 16 static +tasks.c:3951:13:xTaskPriorityInherit 24 static +tasks.c:4038:13:xTaskPriorityDisinherit 32 static,ignoring_inline_asm +tasks.c:4118:7:vTaskPriorityDisinheritAfterTimeout 40 static,ignoring_inline_asm +tasks.c:4533:12:uxTaskResetEventItemValue 16 static +tasks.c:4549:15:pvTaskIncrementMutexHeldCount 4 static +tasks.c:4566:11:ulTaskNotifyTake 24 static,ignoring_inline_asm +tasks.c:4634:13:xTaskNotifyWait 32 static,ignoring_inline_asm +tasks.c:4714:13:xTaskGenericNotify 48 static,ignoring_inline_asm +tasks.c:4828:13:xTaskGenericNotifyFromISR 64 static,ignoring_inline_asm +tasks.c:4957:7:vTaskNotifyGiveFromISR 48 static,ignoring_inline_asm +tasks.c:5044:13:xTaskNotifyStateClear 24 static +tasks.c:5081:13:prvAddCurrentTaskToDelayedList 24 static diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d new file mode 100644 index 0000000..9597af0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.d @@ -0,0 +1,38 @@ +Middlewares/Third_Party/FreeRTOS/Source/timers.o: \ + ../Middlewares/Third_Party/FreeRTOS/Source/timers.c \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h \ + ../Core/Inc/FreeRTOSConfig.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/list.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/task.h \ + ../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h + +../Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h: + +../Core/Inc/FreeRTOSConfig.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/portable.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h: + +../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/list.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/queue.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/task.h: + +../Middlewares/Third_Party/FreeRTOS/Source/include/timers.h: diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o new file mode 100644 index 0000000..cfad288 Binary files /dev/null and b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.o differ diff --git a/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su b/Debug/Middlewares/Third_Party/FreeRTOS/Source/timers.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..93072c6 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,98 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/subdir.mk +-include Middlewares/Third_Party/FreeRTOS/Source/subdir.mk +-include Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +BUILD_ARTIFACT_NAME := prog_demo_2021 +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +prog_demo_2021.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +prog_demo_2021.list \ + +OBJCOPY_BIN += \ +prog_demo_2021.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: prog_demo_2021.elf secondary-outputs + +# Tool invocations +prog_demo_2021.elf: $(OBJS) $(USER_OBJS) /home/ajuton/Documents/STM32CubeIDE/workspace_1.5.1/test_/STM32F746NGHX_FLASH.ld + arm-none-eabi-gcc -o "prog_demo_2021.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"/home/ajuton/Documents/STM32CubeIDE/workspace_1.5.1/test_/STM32F746NGHX_FLASH.ld" --specs=nosys.specs -Wl,-Map="prog_demo_2021.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +prog_demo_2021.list: $(EXECUTABLES) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "prog_demo_2021.list" + @echo 'Finished building: $@' + @echo ' ' + +prog_demo_2021.bin: $(EXECUTABLES) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "prog_demo_2021.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..3fe03b2 --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,56 @@ +"Core/Src/freertos.o" +"Core/Src/ft5336.o" +"Core/Src/main.o" +"Core/Src/stm32746g_discovery.o" +"Core/Src/stm32746g_discovery_lcd.o" +"Core/Src/stm32746g_discovery_sdram.o" +"Core/Src/stm32746g_discovery_ts.o" +"Core/Src/stm32f7xx_hal_msp.o" +"Core/Src/stm32f7xx_hal_timebase_tim.o" +"Core/Src/stm32f7xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32f7xx.o" +"Core/Startup/startup_stm32f746nghx.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o" +"Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o" +"Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o" +"Middlewares/Third_Party/FreeRTOS/Source/croutine.o" +"Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" +"Middlewares/Third_Party/FreeRTOS/Source/list.o" +"Middlewares/Third_Party/FreeRTOS/Source/queue.o" +"Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o" +"Middlewares/Third_Party/FreeRTOS/Source/tasks.o" +"Middlewares/Third_Party/FreeRTOS/Source/timers.o" +"Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o" +"Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/prog_demo_2021.bin b/Debug/prog_demo_2021.bin new file mode 100644 index 0000000..7aaaa20 Binary files /dev/null and b/Debug/prog_demo_2021.bin differ diff --git a/Debug/prog_demo_2021.elf b/Debug/prog_demo_2021.elf new file mode 100644 index 0000000..a455f3c Binary files /dev/null and b/Debug/prog_demo_2021.elf differ diff --git a/Debug/prog_demo_2021.list b/Debug/prog_demo_2021.list new file mode 100644 index 0000000..83e8075 --- /dev/null +++ b/Debug/prog_demo_2021.list @@ -0,0 +1,33288 @@ + +prog_demo_2021.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000001c8 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000c210 080001d0 080001d0 000101d0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00001fe4 0800c3e0 0800c3e0 0001c3e0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800e3c4 0800e3c4 000200b0 2**0 + CONTENTS + 4 .ARM 00000008 0800e3c4 0800e3c4 0001e3c4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800e3cc 0800e3cc 000200b0 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800e3cc 0800e3cc 0001e3cc 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 0800e3d0 0800e3d0 0001e3d0 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 000000b0 20000000 0800e3d4 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00008a4c 200000b0 0800e484 000200b0 2**2 + ALLOC + 10 ._user_heap_stack 00000604 20008afc 0800e484 00028afc 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 000200b0 2**0 + CONTENTS, READONLY + 12 .debug_info 00029de5 00000000 00000000 000200e0 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_abbrev 000051ee 00000000 00000000 00049ec5 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_aranges 00002490 00000000 00000000 0004f0b8 2**3 + CONTENTS, READONLY, DEBUGGING + 15 .debug_ranges 00002208 00000000 00000000 00051548 2**3 + CONTENTS, READONLY, DEBUGGING + 16 .debug_macro 0002df43 00000000 00000000 00053750 2**0 + CONTENTS, READONLY, DEBUGGING + 17 .debug_line 0001dc92 00000000 00000000 00081693 2**0 + CONTENTS, READONLY, DEBUGGING + 18 .debug_str 00114119 00000000 00000000 0009f325 2**0 + CONTENTS, READONLY, DEBUGGING + 19 .comment 0000007b 00000000 00000000 001b343e 2**0 + CONTENTS, READONLY + 20 .debug_frame 00009d9c 00000000 00000000 001b34bc 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +080001d0 <__do_global_dtors_aux>: + 80001d0: b510 push {r4, lr} + 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) + 80001d4: 7823 ldrb r3, [r4, #0] + 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> + 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) + 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> + 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) + 80001de: f3af 8000 nop.w + 80001e2: 2301 movs r3, #1 + 80001e4: 7023 strb r3, [r4, #0] + 80001e6: bd10 pop {r4, pc} + 80001e8: 200000b0 .word 0x200000b0 + 80001ec: 00000000 .word 0x00000000 + 80001f0: 0800c3c8 .word 0x0800c3c8 + +080001f4 : + 80001f4: b508 push {r3, lr} + 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) + 80001f8: b11b cbz r3, 8000202 + 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) + 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) + 80001fe: f3af 8000 nop.w + 8000202: bd08 pop {r3, pc} + 8000204: 00000000 .word 0x00000000 + 8000208: 200000b4 .word 0x200000b4 + 800020c: 0800c3c8 .word 0x0800c3c8 + +08000210 : + 8000210: f001 01ff and.w r1, r1, #255 ; 0xff + 8000214: 2a10 cmp r2, #16 + 8000216: db2b blt.n 8000270 + 8000218: f010 0f07 tst.w r0, #7 + 800021c: d008 beq.n 8000230 + 800021e: f810 3b01 ldrb.w r3, [r0], #1 + 8000222: 3a01 subs r2, #1 + 8000224: 428b cmp r3, r1 + 8000226: d02d beq.n 8000284 + 8000228: f010 0f07 tst.w r0, #7 + 800022c: b342 cbz r2, 8000280 + 800022e: d1f6 bne.n 800021e + 8000230: b4f0 push {r4, r5, r6, r7} + 8000232: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000236: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800023a: f022 0407 bic.w r4, r2, #7 + 800023e: f07f 0700 mvns.w r7, #0 + 8000242: 2300 movs r3, #0 + 8000244: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000248: 3c08 subs r4, #8 + 800024a: ea85 0501 eor.w r5, r5, r1 + 800024e: ea86 0601 eor.w r6, r6, r1 + 8000252: fa85 f547 uadd8 r5, r5, r7 + 8000256: faa3 f587 sel r5, r3, r7 + 800025a: fa86 f647 uadd8 r6, r6, r7 + 800025e: faa5 f687 sel r6, r5, r7 + 8000262: b98e cbnz r6, 8000288 + 8000264: d1ee bne.n 8000244 + 8000266: bcf0 pop {r4, r5, r6, r7} + 8000268: f001 01ff and.w r1, r1, #255 ; 0xff + 800026c: f002 0207 and.w r2, r2, #7 + 8000270: b132 cbz r2, 8000280 + 8000272: f810 3b01 ldrb.w r3, [r0], #1 + 8000276: 3a01 subs r2, #1 + 8000278: ea83 0301 eor.w r3, r3, r1 + 800027c: b113 cbz r3, 8000284 + 800027e: d1f8 bne.n 8000272 + 8000280: 2000 movs r0, #0 + 8000282: 4770 bx lr + 8000284: 3801 subs r0, #1 + 8000286: 4770 bx lr + 8000288: 2d00 cmp r5, #0 + 800028a: bf06 itte eq + 800028c: 4635 moveq r5, r6 + 800028e: 3803 subeq r0, #3 + 8000290: 3807 subne r0, #7 + 8000292: f015 0f01 tst.w r5, #1 + 8000296: d107 bne.n 80002a8 + 8000298: 3001 adds r0, #1 + 800029a: f415 7f80 tst.w r5, #256 ; 0x100 + 800029e: bf02 ittt eq + 80002a0: 3001 addeq r0, #1 + 80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 80002a6: 3001 addeq r0, #1 + 80002a8: bcf0 pop {r4, r5, r6, r7} + 80002aa: 3801 subs r0, #1 + 80002ac: 4770 bx lr + 80002ae: bf00 nop + +080002b0 <__aeabi_uldivmod>: + 80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18> + 80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18> + 80002b4: 2900 cmp r1, #0 + 80002b6: bf08 it eq + 80002b8: 2800 cmpeq r0, #0 + 80002ba: bf1c itt ne + 80002bc: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 80002c0: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 80002c4: f000 b972 b.w 80005ac <__aeabi_idiv0> + 80002c8: f1ad 0c08 sub.w ip, sp, #8 + 80002cc: e96d ce04 strd ip, lr, [sp, #-16]! + 80002d0: f000 f806 bl 80002e0 <__udivmoddi4> + 80002d4: f8dd e004 ldr.w lr, [sp, #4] + 80002d8: e9dd 2302 ldrd r2, r3, [sp, #8] + 80002dc: b004 add sp, #16 + 80002de: 4770 bx lr + +080002e0 <__udivmoddi4>: + 80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80002e4: 9e08 ldr r6, [sp, #32] + 80002e6: 4604 mov r4, r0 + 80002e8: 4688 mov r8, r1 + 80002ea: 2b00 cmp r3, #0 + 80002ec: d14b bne.n 8000386 <__udivmoddi4+0xa6> + 80002ee: 428a cmp r2, r1 + 80002f0: 4615 mov r5, r2 + 80002f2: d967 bls.n 80003c4 <__udivmoddi4+0xe4> + 80002f4: fab2 f282 clz r2, r2 + 80002f8: b14a cbz r2, 800030e <__udivmoddi4+0x2e> + 80002fa: f1c2 0720 rsb r7, r2, #32 + 80002fe: fa01 f302 lsl.w r3, r1, r2 + 8000302: fa20 f707 lsr.w r7, r0, r7 + 8000306: 4095 lsls r5, r2 + 8000308: ea47 0803 orr.w r8, r7, r3 + 800030c: 4094 lsls r4, r2 + 800030e: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000312: 0c23 lsrs r3, r4, #16 + 8000314: fbb8 f7fe udiv r7, r8, lr + 8000318: fa1f fc85 uxth.w ip, r5 + 800031c: fb0e 8817 mls r8, lr, r7, r8 + 8000320: ea43 4308 orr.w r3, r3, r8, lsl #16 + 8000324: fb07 f10c mul.w r1, r7, ip + 8000328: 4299 cmp r1, r3 + 800032a: d909 bls.n 8000340 <__udivmoddi4+0x60> + 800032c: 18eb adds r3, r5, r3 + 800032e: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff + 8000332: f080 811b bcs.w 800056c <__udivmoddi4+0x28c> + 8000336: 4299 cmp r1, r3 + 8000338: f240 8118 bls.w 800056c <__udivmoddi4+0x28c> + 800033c: 3f02 subs r7, #2 + 800033e: 442b add r3, r5 + 8000340: 1a5b subs r3, r3, r1 + 8000342: b2a4 uxth r4, r4 + 8000344: fbb3 f0fe udiv r0, r3, lr + 8000348: fb0e 3310 mls r3, lr, r0, r3 + 800034c: ea44 4403 orr.w r4, r4, r3, lsl #16 + 8000350: fb00 fc0c mul.w ip, r0, ip + 8000354: 45a4 cmp ip, r4 + 8000356: d909 bls.n 800036c <__udivmoddi4+0x8c> + 8000358: 192c adds r4, r5, r4 + 800035a: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 800035e: f080 8107 bcs.w 8000570 <__udivmoddi4+0x290> + 8000362: 45a4 cmp ip, r4 + 8000364: f240 8104 bls.w 8000570 <__udivmoddi4+0x290> + 8000368: 3802 subs r0, #2 + 800036a: 442c add r4, r5 + 800036c: ea40 4007 orr.w r0, r0, r7, lsl #16 + 8000370: eba4 040c sub.w r4, r4, ip + 8000374: 2700 movs r7, #0 + 8000376: b11e cbz r6, 8000380 <__udivmoddi4+0xa0> + 8000378: 40d4 lsrs r4, r2 + 800037a: 2300 movs r3, #0 + 800037c: e9c6 4300 strd r4, r3, [r6] + 8000380: 4639 mov r1, r7 + 8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000386: 428b cmp r3, r1 + 8000388: d909 bls.n 800039e <__udivmoddi4+0xbe> + 800038a: 2e00 cmp r6, #0 + 800038c: f000 80eb beq.w 8000566 <__udivmoddi4+0x286> + 8000390: 2700 movs r7, #0 + 8000392: e9c6 0100 strd r0, r1, [r6] + 8000396: 4638 mov r0, r7 + 8000398: 4639 mov r1, r7 + 800039a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800039e: fab3 f783 clz r7, r3 + 80003a2: 2f00 cmp r7, #0 + 80003a4: d147 bne.n 8000436 <__udivmoddi4+0x156> + 80003a6: 428b cmp r3, r1 + 80003a8: d302 bcc.n 80003b0 <__udivmoddi4+0xd0> + 80003aa: 4282 cmp r2, r0 + 80003ac: f200 80fa bhi.w 80005a4 <__udivmoddi4+0x2c4> + 80003b0: 1a84 subs r4, r0, r2 + 80003b2: eb61 0303 sbc.w r3, r1, r3 + 80003b6: 2001 movs r0, #1 + 80003b8: 4698 mov r8, r3 + 80003ba: 2e00 cmp r6, #0 + 80003bc: d0e0 beq.n 8000380 <__udivmoddi4+0xa0> + 80003be: e9c6 4800 strd r4, r8, [r6] + 80003c2: e7dd b.n 8000380 <__udivmoddi4+0xa0> + 80003c4: b902 cbnz r2, 80003c8 <__udivmoddi4+0xe8> + 80003c6: deff udf #255 ; 0xff + 80003c8: fab2 f282 clz r2, r2 + 80003cc: 2a00 cmp r2, #0 + 80003ce: f040 808f bne.w 80004f0 <__udivmoddi4+0x210> + 80003d2: 1b49 subs r1, r1, r5 + 80003d4: ea4f 4e15 mov.w lr, r5, lsr #16 + 80003d8: fa1f f885 uxth.w r8, r5 + 80003dc: 2701 movs r7, #1 + 80003de: fbb1 fcfe udiv ip, r1, lr + 80003e2: 0c23 lsrs r3, r4, #16 + 80003e4: fb0e 111c mls r1, lr, ip, r1 + 80003e8: ea43 4301 orr.w r3, r3, r1, lsl #16 + 80003ec: fb08 f10c mul.w r1, r8, ip + 80003f0: 4299 cmp r1, r3 + 80003f2: d907 bls.n 8000404 <__udivmoddi4+0x124> + 80003f4: 18eb adds r3, r5, r3 + 80003f6: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff + 80003fa: d202 bcs.n 8000402 <__udivmoddi4+0x122> + 80003fc: 4299 cmp r1, r3 + 80003fe: f200 80cd bhi.w 800059c <__udivmoddi4+0x2bc> + 8000402: 4684 mov ip, r0 + 8000404: 1a59 subs r1, r3, r1 + 8000406: b2a3 uxth r3, r4 + 8000408: fbb1 f0fe udiv r0, r1, lr + 800040c: fb0e 1410 mls r4, lr, r0, r1 + 8000410: ea43 4404 orr.w r4, r3, r4, lsl #16 + 8000414: fb08 f800 mul.w r8, r8, r0 + 8000418: 45a0 cmp r8, r4 + 800041a: d907 bls.n 800042c <__udivmoddi4+0x14c> + 800041c: 192c adds r4, r5, r4 + 800041e: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 8000422: d202 bcs.n 800042a <__udivmoddi4+0x14a> + 8000424: 45a0 cmp r8, r4 + 8000426: f200 80b6 bhi.w 8000596 <__udivmoddi4+0x2b6> + 800042a: 4618 mov r0, r3 + 800042c: eba4 0408 sub.w r4, r4, r8 + 8000430: ea40 400c orr.w r0, r0, ip, lsl #16 + 8000434: e79f b.n 8000376 <__udivmoddi4+0x96> + 8000436: f1c7 0c20 rsb ip, r7, #32 + 800043a: 40bb lsls r3, r7 + 800043c: fa22 fe0c lsr.w lr, r2, ip + 8000440: ea4e 0e03 orr.w lr, lr, r3 + 8000444: fa01 f407 lsl.w r4, r1, r7 + 8000448: fa20 f50c lsr.w r5, r0, ip + 800044c: fa21 f30c lsr.w r3, r1, ip + 8000450: ea4f 481e mov.w r8, lr, lsr #16 + 8000454: 4325 orrs r5, r4 + 8000456: fbb3 f9f8 udiv r9, r3, r8 + 800045a: 0c2c lsrs r4, r5, #16 + 800045c: fb08 3319 mls r3, r8, r9, r3 + 8000460: fa1f fa8e uxth.w sl, lr + 8000464: ea44 4303 orr.w r3, r4, r3, lsl #16 + 8000468: fb09 f40a mul.w r4, r9, sl + 800046c: 429c cmp r4, r3 + 800046e: fa02 f207 lsl.w r2, r2, r7 + 8000472: fa00 f107 lsl.w r1, r0, r7 + 8000476: d90b bls.n 8000490 <__udivmoddi4+0x1b0> + 8000478: eb1e 0303 adds.w r3, lr, r3 + 800047c: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff + 8000480: f080 8087 bcs.w 8000592 <__udivmoddi4+0x2b2> + 8000484: 429c cmp r4, r3 + 8000486: f240 8084 bls.w 8000592 <__udivmoddi4+0x2b2> + 800048a: f1a9 0902 sub.w r9, r9, #2 + 800048e: 4473 add r3, lr + 8000490: 1b1b subs r3, r3, r4 + 8000492: b2ad uxth r5, r5 + 8000494: fbb3 f0f8 udiv r0, r3, r8 + 8000498: fb08 3310 mls r3, r8, r0, r3 + 800049c: ea45 4403 orr.w r4, r5, r3, lsl #16 + 80004a0: fb00 fa0a mul.w sl, r0, sl + 80004a4: 45a2 cmp sl, r4 + 80004a6: d908 bls.n 80004ba <__udivmoddi4+0x1da> + 80004a8: eb1e 0404 adds.w r4, lr, r4 + 80004ac: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 80004b0: d26b bcs.n 800058a <__udivmoddi4+0x2aa> + 80004b2: 45a2 cmp sl, r4 + 80004b4: d969 bls.n 800058a <__udivmoddi4+0x2aa> + 80004b6: 3802 subs r0, #2 + 80004b8: 4474 add r4, lr + 80004ba: ea40 4009 orr.w r0, r0, r9, lsl #16 + 80004be: fba0 8902 umull r8, r9, r0, r2 + 80004c2: eba4 040a sub.w r4, r4, sl + 80004c6: 454c cmp r4, r9 + 80004c8: 46c2 mov sl, r8 + 80004ca: 464b mov r3, r9 + 80004cc: d354 bcc.n 8000578 <__udivmoddi4+0x298> + 80004ce: d051 beq.n 8000574 <__udivmoddi4+0x294> + 80004d0: 2e00 cmp r6, #0 + 80004d2: d069 beq.n 80005a8 <__udivmoddi4+0x2c8> + 80004d4: ebb1 050a subs.w r5, r1, sl + 80004d8: eb64 0403 sbc.w r4, r4, r3 + 80004dc: fa04 fc0c lsl.w ip, r4, ip + 80004e0: 40fd lsrs r5, r7 + 80004e2: 40fc lsrs r4, r7 + 80004e4: ea4c 0505 orr.w r5, ip, r5 + 80004e8: e9c6 5400 strd r5, r4, [r6] + 80004ec: 2700 movs r7, #0 + 80004ee: e747 b.n 8000380 <__udivmoddi4+0xa0> + 80004f0: f1c2 0320 rsb r3, r2, #32 + 80004f4: fa20 f703 lsr.w r7, r0, r3 + 80004f8: 4095 lsls r5, r2 + 80004fa: fa01 f002 lsl.w r0, r1, r2 + 80004fe: fa21 f303 lsr.w r3, r1, r3 + 8000502: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000506: 4338 orrs r0, r7 + 8000508: 0c01 lsrs r1, r0, #16 + 800050a: fbb3 f7fe udiv r7, r3, lr + 800050e: fa1f f885 uxth.w r8, r5 + 8000512: fb0e 3317 mls r3, lr, r7, r3 + 8000516: ea41 4103 orr.w r1, r1, r3, lsl #16 + 800051a: fb07 f308 mul.w r3, r7, r8 + 800051e: 428b cmp r3, r1 + 8000520: fa04 f402 lsl.w r4, r4, r2 + 8000524: d907 bls.n 8000536 <__udivmoddi4+0x256> + 8000526: 1869 adds r1, r5, r1 + 8000528: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff + 800052c: d22f bcs.n 800058e <__udivmoddi4+0x2ae> + 800052e: 428b cmp r3, r1 + 8000530: d92d bls.n 800058e <__udivmoddi4+0x2ae> + 8000532: 3f02 subs r7, #2 + 8000534: 4429 add r1, r5 + 8000536: 1acb subs r3, r1, r3 + 8000538: b281 uxth r1, r0 + 800053a: fbb3 f0fe udiv r0, r3, lr + 800053e: fb0e 3310 mls r3, lr, r0, r3 + 8000542: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000546: fb00 f308 mul.w r3, r0, r8 + 800054a: 428b cmp r3, r1 + 800054c: d907 bls.n 800055e <__udivmoddi4+0x27e> + 800054e: 1869 adds r1, r5, r1 + 8000550: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff + 8000554: d217 bcs.n 8000586 <__udivmoddi4+0x2a6> + 8000556: 428b cmp r3, r1 + 8000558: d915 bls.n 8000586 <__udivmoddi4+0x2a6> + 800055a: 3802 subs r0, #2 + 800055c: 4429 add r1, r5 + 800055e: 1ac9 subs r1, r1, r3 + 8000560: ea40 4707 orr.w r7, r0, r7, lsl #16 + 8000564: e73b b.n 80003de <__udivmoddi4+0xfe> + 8000566: 4637 mov r7, r6 + 8000568: 4630 mov r0, r6 + 800056a: e709 b.n 8000380 <__udivmoddi4+0xa0> + 800056c: 4607 mov r7, r0 + 800056e: e6e7 b.n 8000340 <__udivmoddi4+0x60> + 8000570: 4618 mov r0, r3 + 8000572: e6fb b.n 800036c <__udivmoddi4+0x8c> + 8000574: 4541 cmp r1, r8 + 8000576: d2ab bcs.n 80004d0 <__udivmoddi4+0x1f0> + 8000578: ebb8 0a02 subs.w sl, r8, r2 + 800057c: eb69 020e sbc.w r2, r9, lr + 8000580: 3801 subs r0, #1 + 8000582: 4613 mov r3, r2 + 8000584: e7a4 b.n 80004d0 <__udivmoddi4+0x1f0> + 8000586: 4660 mov r0, ip + 8000588: e7e9 b.n 800055e <__udivmoddi4+0x27e> + 800058a: 4618 mov r0, r3 + 800058c: e795 b.n 80004ba <__udivmoddi4+0x1da> + 800058e: 4667 mov r7, ip + 8000590: e7d1 b.n 8000536 <__udivmoddi4+0x256> + 8000592: 4681 mov r9, r0 + 8000594: e77c b.n 8000490 <__udivmoddi4+0x1b0> + 8000596: 3802 subs r0, #2 + 8000598: 442c add r4, r5 + 800059a: e747 b.n 800042c <__udivmoddi4+0x14c> + 800059c: f1ac 0c02 sub.w ip, ip, #2 + 80005a0: 442b add r3, r5 + 80005a2: e72f b.n 8000404 <__udivmoddi4+0x124> + 80005a4: 4638 mov r0, r7 + 80005a6: e708 b.n 80003ba <__udivmoddi4+0xda> + 80005a8: 4637 mov r7, r6 + 80005aa: e6e9 b.n 8000380 <__udivmoddi4+0xa0> + +080005ac <__aeabi_idiv0>: + 80005ac: 4770 bx lr + 80005ae: bf00 nop + +080005b0 : +} +/* USER CODE END 2 */ + +/* USER CODE BEGIN 4 */ +__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) +{ + 80005b0: b480 push {r7} + 80005b2: b083 sub sp, #12 + 80005b4: af00 add r7, sp, #0 + 80005b6: 6078 str r0, [r7, #4] + 80005b8: 6039 str r1, [r7, #0] + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is + called if a stack overflow is detected. */ +} + 80005ba: bf00 nop + 80005bc: 370c adds r7, #12 + 80005be: 46bd mov sp, r7 + 80005c0: f85d 7b04 ldr.w r7, [sp], #4 + 80005c4: 4770 bx lr + +080005c6 : +/* USER CODE END 4 */ + +/* USER CODE BEGIN 5 */ +__weak void vApplicationMallocFailedHook(void) +{ + 80005c6: b480 push {r7} + 80005c8: af00 add r7, sp, #0 + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ +} + 80005ca: bf00 nop + 80005cc: 46bd mov sp, r7 + 80005ce: f85d 7b04 ldr.w r7, [sp], #4 + 80005d2: 4770 bx lr + +080005d4 : + * from MCU to FT5336 : ie I2C channel initialization (if required). + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Init(uint16_t DeviceAddr) +{ + 80005d4: b580 push {r7, lr} + 80005d6: b082 sub sp, #8 + 80005d8: af00 add r7, sp, #0 + 80005da: 4603 mov r3, r0 + 80005dc: 80fb strh r3, [r7, #6] + /* Wait at least 200ms after power up before accessing registers + * Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */ + TS_IO_Delay(200); + 80005de: 20c8 movs r0, #200 ; 0xc8 + 80005e0: f001 fe16 bl 8002210 + + /* Initialize I2C link if needed */ + ft5336_I2C_InitializeIfRequired(); + 80005e4: f000 fa7a bl 8000adc +} + 80005e8: bf00 nop + 80005ea: 3708 adds r7, #8 + 80005ec: 46bd mov sp, r7 + 80005ee: bd80 pop {r7, pc} + +080005f0 : + * @note : Not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_Reset(uint16_t DeviceAddr) +{ + 80005f0: b480 push {r7} + 80005f2: b083 sub sp, #12 + 80005f4: af00 add r7, sp, #0 + 80005f6: 4603 mov r3, r0 + 80005f8: 80fb strh r3, [r7, #6] + /* Do nothing */ + /* No software reset sequence available in FT5336 IC */ +} + 80005fa: bf00 nop + 80005fc: 370c adds r7, #12 + 80005fe: 46bd mov sp, r7 + 8000600: f85d 7b04 ldr.w r7, [sp], #4 + 8000604: 4770 bx lr + +08000606 : + * able to read the FT5336 device ID, and verify this is a FT5336. + * @param DeviceAddr: I2C FT5336 Slave address. + * @retval The Device ID (two bytes). + */ +uint16_t ft5336_ReadID(uint16_t DeviceAddr) +{ + 8000606: b580 push {r7, lr} + 8000608: b084 sub sp, #16 + 800060a: af00 add r7, sp, #0 + 800060c: 4603 mov r3, r0 + 800060e: 80fb strh r3, [r7, #6] + volatile uint8_t ucReadId = 0; + 8000610: 2300 movs r3, #0 + 8000612: 737b strb r3, [r7, #13] + uint8_t nbReadAttempts = 0; + 8000614: 2300 movs r3, #0 + 8000616: 73fb strb r3, [r7, #15] + uint8_t bFoundDevice = 0; /* Device not found by default */ + 8000618: 2300 movs r3, #0 + 800061a: 73bb strb r3, [r7, #14] + + /* Initialize I2C link if needed */ + ft5336_I2C_InitializeIfRequired(); + 800061c: f000 fa5e bl 8000adc + + /* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */ + for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++) + 8000620: 2300 movs r3, #0 + 8000622: 73fb strb r3, [r7, #15] + 8000624: e010 b.n 8000648 + { + /* Read register FT5336_CHIP_ID_REG as DeviceID detection */ + ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG); + 8000626: 88fb ldrh r3, [r7, #6] + 8000628: b2db uxtb r3, r3 + 800062a: 21a8 movs r1, #168 ; 0xa8 + 800062c: 4618 mov r0, r3 + 800062e: f001 fdd1 bl 80021d4 + 8000632: 4603 mov r3, r0 + 8000634: 737b strb r3, [r7, #13] + + /* Found the searched device ID ? */ + if(ucReadId == FT5336_ID_VALUE) + 8000636: 7b7b ldrb r3, [r7, #13] + 8000638: b2db uxtb r3, r3 + 800063a: 2b51 cmp r3, #81 ; 0x51 + 800063c: d101 bne.n 8000642 + { + /* Set device as found */ + bFoundDevice = 1; + 800063e: 2301 movs r3, #1 + 8000640: 73bb strb r3, [r7, #14] + for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++) + 8000642: 7bfb ldrb r3, [r7, #15] + 8000644: 3301 adds r3, #1 + 8000646: 73fb strb r3, [r7, #15] + 8000648: 7bfb ldrb r3, [r7, #15] + 800064a: 2b02 cmp r3, #2 + 800064c: d802 bhi.n 8000654 + 800064e: 7bbb ldrb r3, [r7, #14] + 8000650: 2b00 cmp r3, #0 + 8000652: d0e8 beq.n 8000626 + } + } + + /* Return the device ID value */ + return (ucReadId); + 8000654: 7b7b ldrb r3, [r7, #13] + 8000656: b2db uxtb r3, r3 + 8000658: b29b uxth r3, r3 +} + 800065a: 4618 mov r0, r3 + 800065c: 3710 adds r7, #16 + 800065e: 46bd mov sp, r7 + 8000660: bd80 pop {r7, pc} + +08000662 : + * @brief Configures the touch Screen IC device to start detecting touches + * @param DeviceAddr: Device address on communication Bus (I2C slave address). + * @retval None. + */ +void ft5336_TS_Start(uint16_t DeviceAddr) +{ + 8000662: b580 push {r7, lr} + 8000664: b082 sub sp, #8 + 8000666: af00 add r7, sp, #0 + 8000668: 4603 mov r3, r0 + 800066a: 80fb strh r3, [r7, #6] + /* Minimum static configuration of FT5336 */ + FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr)); + 800066c: 88fb ldrh r3, [r7, #6] + 800066e: 4618 mov r0, r3 + 8000670: f000 fa44 bl 8000afc + + /* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */ + /* Note TS_INT is active low */ + ft5336_TS_DisableIT(DeviceAddr); + 8000674: 88fb ldrh r3, [r7, #6] + 8000676: 4618 mov r0, r3 + 8000678: f000 f932 bl 80008e0 +} + 800067c: bf00 nop + 800067e: 3708 adds r7, #8 + 8000680: 46bd mov sp, r7 + 8000682: bd80 pop {r7, pc} + +08000684 : + * variables). + * @param DeviceAddr: Device address on communication Bus. + * @retval : Number of active touches detected (can be 0, 1 or 2). + */ +uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr) +{ + 8000684: b580 push {r7, lr} + 8000686: b084 sub sp, #16 + 8000688: af00 add r7, sp, #0 + 800068a: 4603 mov r3, r0 + 800068c: 80fb strh r3, [r7, #6] + volatile uint8_t nbTouch = 0; + 800068e: 2300 movs r3, #0 + 8000690: 73fb strb r3, [r7, #15] + + /* Read register FT5336_TD_STAT_REG to check number of touches detection */ + nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG); + 8000692: 88fb ldrh r3, [r7, #6] + 8000694: b2db uxtb r3, r3 + 8000696: 2102 movs r1, #2 + 8000698: 4618 mov r0, r3 + 800069a: f001 fd9b bl 80021d4 + 800069e: 4603 mov r3, r0 + 80006a0: 73fb strb r3, [r7, #15] + nbTouch &= FT5336_TD_STAT_MASK; + 80006a2: 7bfb ldrb r3, [r7, #15] + 80006a4: b2db uxtb r3, r3 + 80006a6: f003 030f and.w r3, r3, #15 + 80006aa: b2db uxtb r3, r3 + 80006ac: 73fb strb r3, [r7, #15] + + if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH) + 80006ae: 7bfb ldrb r3, [r7, #15] + 80006b0: b2db uxtb r3, r3 + 80006b2: 2b05 cmp r3, #5 + 80006b4: d901 bls.n 80006ba + { + /* If invalid number of touch detected, set it to zero */ + nbTouch = 0; + 80006b6: 2300 movs r3, #0 + 80006b8: 73fb strb r3, [r7, #15] + } + + /* Update ft5336 driver internal global : current number of active touches */ + ft5336_handle.currActiveTouchNb = nbTouch; + 80006ba: 7bfb ldrb r3, [r7, #15] + 80006bc: b2da uxtb r2, r3 + 80006be: 4b05 ldr r3, [pc, #20] ; (80006d4 ) + 80006c0: 705a strb r2, [r3, #1] + + /* Reset current active touch index on which to work on */ + ft5336_handle.currActiveTouchIdx = 0; + 80006c2: 4b04 ldr r3, [pc, #16] ; (80006d4 ) + 80006c4: 2200 movs r2, #0 + 80006c6: 709a strb r2, [r3, #2] + + return(nbTouch); + 80006c8: 7bfb ldrb r3, [r7, #15] + 80006ca: b2db uxtb r3, r3 +} + 80006cc: 4618 mov r0, r3 + 80006ce: 3710 adds r7, #16 + 80006d0: 46bd mov sp, r7 + 80006d2: bd80 pop {r7, pc} + 80006d4: 200000cc .word 0x200000cc + +080006d8 : + * @param X: Pointer to X position value + * @param Y: Pointer to Y position value + * @retval None. + */ +void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y) +{ + 80006d8: b580 push {r7, lr} + 80006da: b086 sub sp, #24 + 80006dc: af00 add r7, sp, #0 + 80006de: 4603 mov r3, r0 + 80006e0: 60b9 str r1, [r7, #8] + 80006e2: 607a str r2, [r7, #4] + 80006e4: 81fb strh r3, [r7, #14] + volatile uint8_t ucReadData = 0; + 80006e6: 2300 movs r3, #0 + 80006e8: 74fb strb r3, [r7, #19] + static uint16_t coord; + uint8_t regAddressXLow = 0; + 80006ea: 2300 movs r3, #0 + 80006ec: 75fb strb r3, [r7, #23] + uint8_t regAddressXHigh = 0; + 80006ee: 2300 movs r3, #0 + 80006f0: 75bb strb r3, [r7, #22] + uint8_t regAddressYLow = 0; + 80006f2: 2300 movs r3, #0 + 80006f4: 757b strb r3, [r7, #21] + uint8_t regAddressYHigh = 0; + 80006f6: 2300 movs r3, #0 + 80006f8: 753b strb r3, [r7, #20] + + if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) + 80006fa: 4b6d ldr r3, [pc, #436] ; (80008b0 ) + 80006fc: 789a ldrb r2, [r3, #2] + 80006fe: 4b6c ldr r3, [pc, #432] ; (80008b0 ) + 8000700: 785b ldrb r3, [r3, #1] + 8000702: 429a cmp r2, r3 + 8000704: f080 80cf bcs.w 80008a6 + { + switch(ft5336_handle.currActiveTouchIdx) + 8000708: 4b69 ldr r3, [pc, #420] ; (80008b0 ) + 800070a: 789b ldrb r3, [r3, #2] + 800070c: 2b09 cmp r3, #9 + 800070e: d871 bhi.n 80007f4 + 8000710: a201 add r2, pc, #4 ; (adr r2, 8000718 ) + 8000712: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8000716: bf00 nop + 8000718: 08000741 .word 0x08000741 + 800071c: 08000753 .word 0x08000753 + 8000720: 08000765 .word 0x08000765 + 8000724: 08000777 .word 0x08000777 + 8000728: 08000789 .word 0x08000789 + 800072c: 0800079b .word 0x0800079b + 8000730: 080007ad .word 0x080007ad + 8000734: 080007bf .word 0x080007bf + 8000738: 080007d1 .word 0x080007d1 + 800073c: 080007e3 .word 0x080007e3 + { + case 0 : + regAddressXLow = FT5336_P1_XL_REG; + 8000740: 2304 movs r3, #4 + 8000742: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P1_XH_REG; + 8000744: 2303 movs r3, #3 + 8000746: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P1_YL_REG; + 8000748: 2306 movs r3, #6 + 800074a: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P1_YH_REG; + 800074c: 2305 movs r3, #5 + 800074e: 753b strb r3, [r7, #20] + break; + 8000750: e051 b.n 80007f6 + + case 1 : + regAddressXLow = FT5336_P2_XL_REG; + 8000752: 230a movs r3, #10 + 8000754: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P2_XH_REG; + 8000756: 2309 movs r3, #9 + 8000758: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P2_YL_REG; + 800075a: 230c movs r3, #12 + 800075c: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P2_YH_REG; + 800075e: 230b movs r3, #11 + 8000760: 753b strb r3, [r7, #20] + break; + 8000762: e048 b.n 80007f6 + + case 2 : + regAddressXLow = FT5336_P3_XL_REG; + 8000764: 2310 movs r3, #16 + 8000766: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P3_XH_REG; + 8000768: 230f movs r3, #15 + 800076a: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P3_YL_REG; + 800076c: 2312 movs r3, #18 + 800076e: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P3_YH_REG; + 8000770: 2311 movs r3, #17 + 8000772: 753b strb r3, [r7, #20] + break; + 8000774: e03f b.n 80007f6 + + case 3 : + regAddressXLow = FT5336_P4_XL_REG; + 8000776: 2316 movs r3, #22 + 8000778: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P4_XH_REG; + 800077a: 2315 movs r3, #21 + 800077c: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P4_YL_REG; + 800077e: 2318 movs r3, #24 + 8000780: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P4_YH_REG; + 8000782: 2317 movs r3, #23 + 8000784: 753b strb r3, [r7, #20] + break; + 8000786: e036 b.n 80007f6 + + case 4 : + regAddressXLow = FT5336_P5_XL_REG; + 8000788: 231c movs r3, #28 + 800078a: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P5_XH_REG; + 800078c: 231b movs r3, #27 + 800078e: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P5_YL_REG; + 8000790: 231e movs r3, #30 + 8000792: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P5_YH_REG; + 8000794: 231d movs r3, #29 + 8000796: 753b strb r3, [r7, #20] + break; + 8000798: e02d b.n 80007f6 + + case 5 : + regAddressXLow = FT5336_P6_XL_REG; + 800079a: 2322 movs r3, #34 ; 0x22 + 800079c: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P6_XH_REG; + 800079e: 2321 movs r3, #33 ; 0x21 + 80007a0: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P6_YL_REG; + 80007a2: 2324 movs r3, #36 ; 0x24 + 80007a4: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P6_YH_REG; + 80007a6: 2323 movs r3, #35 ; 0x23 + 80007a8: 753b strb r3, [r7, #20] + break; + 80007aa: e024 b.n 80007f6 + + case 6 : + regAddressXLow = FT5336_P7_XL_REG; + 80007ac: 2328 movs r3, #40 ; 0x28 + 80007ae: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P7_XH_REG; + 80007b0: 2327 movs r3, #39 ; 0x27 + 80007b2: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P7_YL_REG; + 80007b4: 232a movs r3, #42 ; 0x2a + 80007b6: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P7_YH_REG; + 80007b8: 2329 movs r3, #41 ; 0x29 + 80007ba: 753b strb r3, [r7, #20] + break; + 80007bc: e01b b.n 80007f6 + + case 7 : + regAddressXLow = FT5336_P8_XL_REG; + 80007be: 232e movs r3, #46 ; 0x2e + 80007c0: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P8_XH_REG; + 80007c2: 232d movs r3, #45 ; 0x2d + 80007c4: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P8_YL_REG; + 80007c6: 2330 movs r3, #48 ; 0x30 + 80007c8: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P8_YH_REG; + 80007ca: 232f movs r3, #47 ; 0x2f + 80007cc: 753b strb r3, [r7, #20] + break; + 80007ce: e012 b.n 80007f6 + + case 8 : + regAddressXLow = FT5336_P9_XL_REG; + 80007d0: 2334 movs r3, #52 ; 0x34 + 80007d2: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P9_XH_REG; + 80007d4: 2333 movs r3, #51 ; 0x33 + 80007d6: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P9_YL_REG; + 80007d8: 2336 movs r3, #54 ; 0x36 + 80007da: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P9_YH_REG; + 80007dc: 2335 movs r3, #53 ; 0x35 + 80007de: 753b strb r3, [r7, #20] + break; + 80007e0: e009 b.n 80007f6 + + case 9 : + regAddressXLow = FT5336_P10_XL_REG; + 80007e2: 233a movs r3, #58 ; 0x3a + 80007e4: 75fb strb r3, [r7, #23] + regAddressXHigh = FT5336_P10_XH_REG; + 80007e6: 2339 movs r3, #57 ; 0x39 + 80007e8: 75bb strb r3, [r7, #22] + regAddressYLow = FT5336_P10_YL_REG; + 80007ea: 233c movs r3, #60 ; 0x3c + 80007ec: 757b strb r3, [r7, #21] + regAddressYHigh = FT5336_P10_YH_REG; + 80007ee: 233b movs r3, #59 ; 0x3b + 80007f0: 753b strb r3, [r7, #20] + break; + 80007f2: e000 b.n 80007f6 + + default : + break; + 80007f4: bf00 nop + + } /* end switch(ft5336_handle.currActiveTouchIdx) */ + + /* Read low part of X position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow); + 80007f6: 89fb ldrh r3, [r7, #14] + 80007f8: b2db uxtb r3, r3 + 80007fa: 7dfa ldrb r2, [r7, #23] + 80007fc: 4611 mov r1, r2 + 80007fe: 4618 mov r0, r3 + 8000800: f001 fce8 bl 80021d4 + 8000804: 4603 mov r3, r0 + 8000806: 74fb strb r3, [r7, #19] + coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT; + 8000808: 7cfb ldrb r3, [r7, #19] + 800080a: b2db uxtb r3, r3 + 800080c: b29a uxth r2, r3 + 800080e: 4b29 ldr r3, [pc, #164] ; (80008b4 ) + 8000810: 801a strh r2, [r3, #0] + + /* Read high part of X position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh); + 8000812: 89fb ldrh r3, [r7, #14] + 8000814: b2db uxtb r3, r3 + 8000816: 7dba ldrb r2, [r7, #22] + 8000818: 4611 mov r1, r2 + 800081a: 4618 mov r0, r3 + 800081c: f001 fcda bl 80021d4 + 8000820: 4603 mov r3, r0 + 8000822: 74fb strb r3, [r7, #19] + coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8; + 8000824: 7cfb ldrb r3, [r7, #19] + 8000826: b2db uxtb r3, r3 + 8000828: 021b lsls r3, r3, #8 + 800082a: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 800082e: b21a sxth r2, r3 + 8000830: 4b20 ldr r3, [pc, #128] ; (80008b4 ) + 8000832: 881b ldrh r3, [r3, #0] + 8000834: b21b sxth r3, r3 + 8000836: 4313 orrs r3, r2 + 8000838: b21b sxth r3, r3 + 800083a: b29a uxth r2, r3 + 800083c: 4b1d ldr r3, [pc, #116] ; (80008b4 ) + 800083e: 801a strh r2, [r3, #0] + + /* Send back ready X position to caller */ + *X = coord; + 8000840: 4b1c ldr r3, [pc, #112] ; (80008b4 ) + 8000842: 881a ldrh r2, [r3, #0] + 8000844: 68bb ldr r3, [r7, #8] + 8000846: 801a strh r2, [r3, #0] + + /* Read low part of Y position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow); + 8000848: 89fb ldrh r3, [r7, #14] + 800084a: b2db uxtb r3, r3 + 800084c: 7d7a ldrb r2, [r7, #21] + 800084e: 4611 mov r1, r2 + 8000850: 4618 mov r0, r3 + 8000852: f001 fcbf bl 80021d4 + 8000856: 4603 mov r3, r0 + 8000858: 74fb strb r3, [r7, #19] + coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT; + 800085a: 7cfb ldrb r3, [r7, #19] + 800085c: b2db uxtb r3, r3 + 800085e: b29a uxth r2, r3 + 8000860: 4b14 ldr r3, [pc, #80] ; (80008b4 ) + 8000862: 801a strh r2, [r3, #0] + + /* Read high part of Y position */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh); + 8000864: 89fb ldrh r3, [r7, #14] + 8000866: b2db uxtb r3, r3 + 8000868: 7d3a ldrb r2, [r7, #20] + 800086a: 4611 mov r1, r2 + 800086c: 4618 mov r0, r3 + 800086e: f001 fcb1 bl 80021d4 + 8000872: 4603 mov r3, r0 + 8000874: 74fb strb r3, [r7, #19] + coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8; + 8000876: 7cfb ldrb r3, [r7, #19] + 8000878: b2db uxtb r3, r3 + 800087a: 021b lsls r3, r3, #8 + 800087c: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 8000880: b21a sxth r2, r3 + 8000882: 4b0c ldr r3, [pc, #48] ; (80008b4 ) + 8000884: 881b ldrh r3, [r3, #0] + 8000886: b21b sxth r3, r3 + 8000888: 4313 orrs r3, r2 + 800088a: b21b sxth r3, r3 + 800088c: b29a uxth r2, r3 + 800088e: 4b09 ldr r3, [pc, #36] ; (80008b4 ) + 8000890: 801a strh r2, [r3, #0] + + /* Send back ready Y position to caller */ + *Y = coord; + 8000892: 4b08 ldr r3, [pc, #32] ; (80008b4 ) + 8000894: 881a ldrh r2, [r3, #0] + 8000896: 687b ldr r3, [r7, #4] + 8000898: 801a strh r2, [r3, #0] + + ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */ + 800089a: 4b05 ldr r3, [pc, #20] ; (80008b0 ) + 800089c: 789b ldrb r3, [r3, #2] + 800089e: 3301 adds r3, #1 + 80008a0: b2da uxtb r2, r3 + 80008a2: 4b03 ldr r3, [pc, #12] ; (80008b0 ) + 80008a4: 709a strb r2, [r3, #2] + + } /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */ +} + 80008a6: bf00 nop + 80008a8: 3718 adds r7, #24 + 80008aa: 46bd mov sp, r7 + 80008ac: bd80 pop {r7, pc} + 80008ae: bf00 nop + 80008b0: 200000cc .word 0x200000cc + 80008b4: 200000d0 .word 0x200000d0 + +080008b8 : + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_EnableIT(uint16_t DeviceAddr) +{ + 80008b8: b580 push {r7, lr} + 80008ba: b084 sub sp, #16 + 80008bc: af00 add r7, sp, #0 + 80008be: 4603 mov r3, r0 + 80008c0: 80fb strh r3, [r7, #6] + uint8_t regValue = 0; + 80008c2: 2300 movs r3, #0 + 80008c4: 73fb strb r3, [r7, #15] + regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT; + 80008c6: 2301 movs r3, #1 + 80008c8: 73fb strb r3, [r7, #15] + + /* Set interrupt trigger mode in FT5336_GMODE_REG */ + TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue); + 80008ca: 88fb ldrh r3, [r7, #6] + 80008cc: b2db uxtb r3, r3 + 80008ce: 7bfa ldrb r2, [r7, #15] + 80008d0: 21a4 movs r1, #164 ; 0xa4 + 80008d2: 4618 mov r0, r3 + 80008d4: f001 fc64 bl 80021a0 +} + 80008d8: bf00 nop + 80008da: 3710 adds r7, #16 + 80008dc: 46bd mov sp, r7 + 80008de: bd80 pop {r7, pc} + +080008e0 : + * connected to MCU as EXTI. + * @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336). + * @retval None + */ +void ft5336_TS_DisableIT(uint16_t DeviceAddr) +{ + 80008e0: b580 push {r7, lr} + 80008e2: b084 sub sp, #16 + 80008e4: af00 add r7, sp, #0 + 80008e6: 4603 mov r3, r0 + 80008e8: 80fb strh r3, [r7, #6] + uint8_t regValue = 0; + 80008ea: 2300 movs r3, #0 + 80008ec: 73fb strb r3, [r7, #15] + regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT; + 80008ee: 2300 movs r3, #0 + 80008f0: 73fb strb r3, [r7, #15] + + /* Set interrupt polling mode in FT5336_GMODE_REG */ + TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue); + 80008f2: 88fb ldrh r3, [r7, #6] + 80008f4: b2db uxtb r3, r3 + 80008f6: 7bfa ldrb r2, [r7, #15] + 80008f8: 21a4 movs r1, #164 ; 0xa4 + 80008fa: 4618 mov r0, r3 + 80008fc: f001 fc50 bl 80021a0 +} + 8000900: bf00 nop + 8000902: 3710 adds r7, #16 + 8000904: 46bd mov sp, r7 + 8000906: bd80 pop {r7, pc} + +08000908 : + * @note : This feature is not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval TS interrupts status : always return 0 here + */ +uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr) +{ + 8000908: b480 push {r7} + 800090a: b083 sub sp, #12 + 800090c: af00 add r7, sp, #0 + 800090e: 4603 mov r3, r0 + 8000910: 80fb strh r3, [r7, #6] + /* Always return 0 as feature not applicable to FT5336 */ + return 0; + 8000912: 2300 movs r3, #0 +} + 8000914: 4618 mov r0, r3 + 8000916: 370c adds r7, #12 + 8000918: 46bd mov sp, r7 + 800091a: f85d 7b04 ldr.w r7, [sp], #4 + 800091e: 4770 bx lr + +08000920 : + * @note : This feature is not applicable to FT5336. + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @retval None + */ +void ft5336_TS_ClearIT(uint16_t DeviceAddr) +{ + 8000920: b480 push {r7} + 8000922: b083 sub sp, #12 + 8000924: af00 add r7, sp, #0 + 8000926: 4603 mov r3, r0 + 8000928: 80fb strh r3, [r7, #6] + /* Nothing to be done here for FT5336 */ +} + 800092a: bf00 nop + 800092c: 370c adds r7, #12 + 800092e: 46bd mov sp, r7 + 8000930: f85d 7b04 ldr.w r7, [sp], #4 + 8000934: 4770 bx lr + +08000936 : + * @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336). + * @param pGestureId : Pointer to get last touch gesture Identification. + * @retval None. + */ +void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId) +{ + 8000936: b580 push {r7, lr} + 8000938: b084 sub sp, #16 + 800093a: af00 add r7, sp, #0 + 800093c: 4603 mov r3, r0 + 800093e: 6039 str r1, [r7, #0] + 8000940: 80fb strh r3, [r7, #6] + volatile uint8_t ucReadData = 0; + 8000942: 2300 movs r3, #0 + 8000944: 73fb strb r3, [r7, #15] + + ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG); + 8000946: 88fb ldrh r3, [r7, #6] + 8000948: b2db uxtb r3, r3 + 800094a: 2101 movs r1, #1 + 800094c: 4618 mov r0, r3 + 800094e: f001 fc41 bl 80021d4 + 8000952: 4603 mov r3, r0 + 8000954: 73fb strb r3, [r7, #15] + + * pGestureId = ucReadData; + 8000956: 7bfb ldrb r3, [r7, #15] + 8000958: b2db uxtb r3, r3 + 800095a: 461a mov r2, r3 + 800095c: 683b ldr r3, [r7, #0] + 800095e: 601a str r2, [r3, #0] +} + 8000960: bf00 nop + 8000962: 3710 adds r7, #16 + 8000964: 46bd mov sp, r7 + 8000966: bd80 pop {r7, pc} + +08000968 : +void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr, + uint32_t touchIdx, + uint32_t * pWeight, + uint32_t * pArea, + uint32_t * pEvent) +{ + 8000968: b580 push {r7, lr} + 800096a: b086 sub sp, #24 + 800096c: af00 add r7, sp, #0 + 800096e: 60b9 str r1, [r7, #8] + 8000970: 607a str r2, [r7, #4] + 8000972: 603b str r3, [r7, #0] + 8000974: 4603 mov r3, r0 + 8000976: 81fb strh r3, [r7, #14] + volatile uint8_t ucReadData = 0; + 8000978: 2300 movs r3, #0 + 800097a: 753b strb r3, [r7, #20] + uint8_t regAddressXHigh = 0; + 800097c: 2300 movs r3, #0 + 800097e: 75fb strb r3, [r7, #23] + uint8_t regAddressPWeight = 0; + 8000980: 2300 movs r3, #0 + 8000982: 75bb strb r3, [r7, #22] + uint8_t regAddressPMisc = 0; + 8000984: 2300 movs r3, #0 + 8000986: 757b strb r3, [r7, #21] + + if(touchIdx < ft5336_handle.currActiveTouchNb) + 8000988: 4b4d ldr r3, [pc, #308] ; (8000ac0 ) + 800098a: 785b ldrb r3, [r3, #1] + 800098c: 461a mov r2, r3 + 800098e: 68bb ldr r3, [r7, #8] + 8000990: 4293 cmp r3, r2 + 8000992: f080 8090 bcs.w 8000ab6 + { + switch(touchIdx) + 8000996: 68bb ldr r3, [r7, #8] + 8000998: 2b09 cmp r3, #9 + 800099a: d85d bhi.n 8000a58 + 800099c: a201 add r2, pc, #4 ; (adr r2, 80009a4 ) + 800099e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80009a2: bf00 nop + 80009a4: 080009cd .word 0x080009cd + 80009a8: 080009db .word 0x080009db + 80009ac: 080009e9 .word 0x080009e9 + 80009b0: 080009f7 .word 0x080009f7 + 80009b4: 08000a05 .word 0x08000a05 + 80009b8: 08000a13 .word 0x08000a13 + 80009bc: 08000a21 .word 0x08000a21 + 80009c0: 08000a2f .word 0x08000a2f + 80009c4: 08000a3d .word 0x08000a3d + 80009c8: 08000a4b .word 0x08000a4b + { + case 0 : + regAddressXHigh = FT5336_P1_XH_REG; + 80009cc: 2303 movs r3, #3 + 80009ce: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P1_WEIGHT_REG; + 80009d0: 2307 movs r3, #7 + 80009d2: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P1_MISC_REG; + 80009d4: 2308 movs r3, #8 + 80009d6: 757b strb r3, [r7, #21] + break; + 80009d8: e03f b.n 8000a5a + + case 1 : + regAddressXHigh = FT5336_P2_XH_REG; + 80009da: 2309 movs r3, #9 + 80009dc: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P2_WEIGHT_REG; + 80009de: 230d movs r3, #13 + 80009e0: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P2_MISC_REG; + 80009e2: 230e movs r3, #14 + 80009e4: 757b strb r3, [r7, #21] + break; + 80009e6: e038 b.n 8000a5a + + case 2 : + regAddressXHigh = FT5336_P3_XH_REG; + 80009e8: 230f movs r3, #15 + 80009ea: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P3_WEIGHT_REG; + 80009ec: 2313 movs r3, #19 + 80009ee: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P3_MISC_REG; + 80009f0: 2314 movs r3, #20 + 80009f2: 757b strb r3, [r7, #21] + break; + 80009f4: e031 b.n 8000a5a + + case 3 : + regAddressXHigh = FT5336_P4_XH_REG; + 80009f6: 2315 movs r3, #21 + 80009f8: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P4_WEIGHT_REG; + 80009fa: 2319 movs r3, #25 + 80009fc: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P4_MISC_REG; + 80009fe: 231a movs r3, #26 + 8000a00: 757b strb r3, [r7, #21] + break; + 8000a02: e02a b.n 8000a5a + + case 4 : + regAddressXHigh = FT5336_P5_XH_REG; + 8000a04: 231b movs r3, #27 + 8000a06: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P5_WEIGHT_REG; + 8000a08: 231f movs r3, #31 + 8000a0a: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P5_MISC_REG; + 8000a0c: 2320 movs r3, #32 + 8000a0e: 757b strb r3, [r7, #21] + break; + 8000a10: e023 b.n 8000a5a + + case 5 : + regAddressXHigh = FT5336_P6_XH_REG; + 8000a12: 2321 movs r3, #33 ; 0x21 + 8000a14: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P6_WEIGHT_REG; + 8000a16: 2325 movs r3, #37 ; 0x25 + 8000a18: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P6_MISC_REG; + 8000a1a: 2326 movs r3, #38 ; 0x26 + 8000a1c: 757b strb r3, [r7, #21] + break; + 8000a1e: e01c b.n 8000a5a + + case 6 : + regAddressXHigh = FT5336_P7_XH_REG; + 8000a20: 2327 movs r3, #39 ; 0x27 + 8000a22: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P7_WEIGHT_REG; + 8000a24: 232b movs r3, #43 ; 0x2b + 8000a26: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P7_MISC_REG; + 8000a28: 232c movs r3, #44 ; 0x2c + 8000a2a: 757b strb r3, [r7, #21] + break; + 8000a2c: e015 b.n 8000a5a + + case 7 : + regAddressXHigh = FT5336_P8_XH_REG; + 8000a2e: 232d movs r3, #45 ; 0x2d + 8000a30: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P8_WEIGHT_REG; + 8000a32: 2331 movs r3, #49 ; 0x31 + 8000a34: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P8_MISC_REG; + 8000a36: 2332 movs r3, #50 ; 0x32 + 8000a38: 757b strb r3, [r7, #21] + break; + 8000a3a: e00e b.n 8000a5a + + case 8 : + regAddressXHigh = FT5336_P9_XH_REG; + 8000a3c: 2333 movs r3, #51 ; 0x33 + 8000a3e: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P9_WEIGHT_REG; + 8000a40: 2337 movs r3, #55 ; 0x37 + 8000a42: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P9_MISC_REG; + 8000a44: 2338 movs r3, #56 ; 0x38 + 8000a46: 757b strb r3, [r7, #21] + break; + 8000a48: e007 b.n 8000a5a + + case 9 : + regAddressXHigh = FT5336_P10_XH_REG; + 8000a4a: 2339 movs r3, #57 ; 0x39 + 8000a4c: 75fb strb r3, [r7, #23] + regAddressPWeight = FT5336_P10_WEIGHT_REG; + 8000a4e: 233d movs r3, #61 ; 0x3d + 8000a50: 75bb strb r3, [r7, #22] + regAddressPMisc = FT5336_P10_MISC_REG; + 8000a52: 233e movs r3, #62 ; 0x3e + 8000a54: 757b strb r3, [r7, #21] + break; + 8000a56: e000 b.n 8000a5a + + default : + break; + 8000a58: bf00 nop + + } /* end switch(touchIdx) */ + + /* Read Event Id of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh); + 8000a5a: 89fb ldrh r3, [r7, #14] + 8000a5c: b2db uxtb r3, r3 + 8000a5e: 7dfa ldrb r2, [r7, #23] + 8000a60: 4611 mov r1, r2 + 8000a62: 4618 mov r0, r3 + 8000a64: f001 fbb6 bl 80021d4 + 8000a68: 4603 mov r3, r0 + 8000a6a: 753b strb r3, [r7, #20] + * pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT; + 8000a6c: 7d3b ldrb r3, [r7, #20] + 8000a6e: b2db uxtb r3, r3 + 8000a70: 119b asrs r3, r3, #6 + 8000a72: f003 0203 and.w r2, r3, #3 + 8000a76: 6a3b ldr r3, [r7, #32] + 8000a78: 601a str r2, [r3, #0] + + /* Read weight of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight); + 8000a7a: 89fb ldrh r3, [r7, #14] + 8000a7c: b2db uxtb r3, r3 + 8000a7e: 7dba ldrb r2, [r7, #22] + 8000a80: 4611 mov r1, r2 + 8000a82: 4618 mov r0, r3 + 8000a84: f001 fba6 bl 80021d4 + 8000a88: 4603 mov r3, r0 + 8000a8a: 753b strb r3, [r7, #20] + * pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT; + 8000a8c: 7d3b ldrb r3, [r7, #20] + 8000a8e: b2db uxtb r3, r3 + 8000a90: 461a mov r2, r3 + 8000a92: 687b ldr r3, [r7, #4] + 8000a94: 601a str r2, [r3, #0] + + /* Read area of touch index */ + ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc); + 8000a96: 89fb ldrh r3, [r7, #14] + 8000a98: b2db uxtb r3, r3 + 8000a9a: 7d7a ldrb r2, [r7, #21] + 8000a9c: 4611 mov r1, r2 + 8000a9e: 4618 mov r0, r3 + 8000aa0: f001 fb98 bl 80021d4 + 8000aa4: 4603 mov r3, r0 + 8000aa6: 753b strb r3, [r7, #20] + * pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT; + 8000aa8: 7d3b ldrb r3, [r7, #20] + 8000aaa: b2db uxtb r3, r3 + 8000aac: 111b asrs r3, r3, #4 + 8000aae: f003 0204 and.w r2, r3, #4 + 8000ab2: 683b ldr r3, [r7, #0] + 8000ab4: 601a str r2, [r3, #0] + + } /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */ +} + 8000ab6: bf00 nop + 8000ab8: 3718 adds r7, #24 + 8000aba: 46bd mov sp, r7 + 8000abc: bd80 pop {r7, pc} + 8000abe: bf00 nop + 8000ac0: 200000cc .word 0x200000cc + +08000ac4 : + * @brief Return the status of I2C was initialized or not. + * @param None. + * @retval : I2C initialization status. + */ +static uint8_t ft5336_Get_I2C_InitializedStatus(void) +{ + 8000ac4: b480 push {r7} + 8000ac6: af00 add r7, sp, #0 + return(ft5336_handle.i2cInitialized); + 8000ac8: 4b03 ldr r3, [pc, #12] ; (8000ad8 ) + 8000aca: 781b ldrb r3, [r3, #0] +} + 8000acc: 4618 mov r0, r3 + 8000ace: 46bd mov sp, r7 + 8000ad0: f85d 7b04 ldr.w r7, [sp], #4 + 8000ad4: 4770 bx lr + 8000ad6: bf00 nop + 8000ad8: 200000cc .word 0x200000cc + +08000adc : + * @brief I2C initialize if needed. + * @param None. + * @retval : None. + */ +static void ft5336_I2C_InitializeIfRequired(void) +{ + 8000adc: b580 push {r7, lr} + 8000ade: af00 add r7, sp, #0 + if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED) + 8000ae0: f7ff fff0 bl 8000ac4 + 8000ae4: 4603 mov r3, r0 + 8000ae6: 2b00 cmp r3, #0 + 8000ae8: d104 bne.n 8000af4 + { + /* Initialize TS IO BUS layer (I2C) */ + TS_IO_Init(); + 8000aea: f001 fb4f bl 800218c + + /* Set state to initialized */ + ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED; + 8000aee: 4b02 ldr r3, [pc, #8] ; (8000af8 ) + 8000af0: 2201 movs r2, #1 + 8000af2: 701a strb r2, [r3, #0] + } +} + 8000af4: bf00 nop + 8000af6: bd80 pop {r7, pc} + 8000af8: 200000cc .word 0x200000cc + +08000afc : + * @brief Basic static configuration of TouchScreen + * @param DeviceAddr: FT5336 Device address for communication on I2C Bus. + * @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK. + */ +static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr) +{ + 8000afc: b480 push {r7} + 8000afe: b085 sub sp, #20 + 8000b00: af00 add r7, sp, #0 + 8000b02: 4603 mov r3, r0 + 8000b04: 80fb strh r3, [r7, #6] + uint32_t status = FT5336_STATUS_OK; + 8000b06: 2300 movs r3, #0 + 8000b08: 60fb str r3, [r7, #12] + + /* Nothing special to be done for FT5336 */ + + return(status); + 8000b0a: 68fb ldr r3, [r7, #12] +} + 8000b0c: 4618 mov r0, r3 + 8000b0e: 3714 adds r7, #20 + 8000b10: 46bd mov sp, r7 + 8000b12: f85d 7b04 ldr.w r7, [sp], #4 + 8000b16: 4770 bx lr + +08000b18
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000b18: b5b0 push {r4, r5, r7, lr} + 8000b1a: b09e sub sp, #120 ; 0x78 + 8000b1c: af02 add r7, sp, #8 + /* USER CODE BEGIN 1 */ + char text[50]={}; + 8000b1e: f107 032c add.w r3, r7, #44 ; 0x2c + 8000b22: 2232 movs r2, #50 ; 0x32 + 8000b24: 2100 movs r1, #0 + 8000b26: 4618 mov r0, r3 + 8000b28: f00b f849 bl 800bbbe + static TS_StateTypeDef TS_State; + uint32_t potl,potr,joystick_h, joystick_v; + ADC_ChannelConfTypeDef sConfig = {0}; + 8000b2c: f107 031c add.w r3, r7, #28 + 8000b30: 2200 movs r2, #0 + 8000b32: 601a str r2, [r3, #0] + 8000b34: 605a str r2, [r3, #4] + 8000b36: 609a str r2, [r3, #8] + 8000b38: 60da str r2, [r3, #12] + sConfig.Rank = ADC_REGULAR_RANK_1; + 8000b3a: 2301 movs r3, #1 + 8000b3c: 623b str r3, [r7, #32] + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 8000b3e: 2300 movs r3, #0 + 8000b40: 627b str r3, [r7, #36] ; 0x24 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000b42: f003 fcb4 bl 80044ae + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8000b46: f000 f925 bl 8000d94 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000b4a: f000 ffbf bl 8001acc + MX_ADC3_Init(); + 8000b4e: f000 fa23 bl 8000f98 + MX_I2C1_Init(); + 8000b52: f000 facf bl 80010f4 + MX_I2C3_Init(); + 8000b56: f000 fb0d bl 8001174 + MX_LTDC_Init(); + 8000b5a: f000 fb4b bl 80011f4 + MX_RTC_Init(); + 8000b5e: f000 fbcb bl 80012f8 + MX_SPI2_Init(); + 8000b62: f000 fc6f bl 8001444 + MX_TIM1_Init(); + 8000b66: f000 fcab bl 80014c0 + MX_TIM2_Init(); + 8000b6a: f000 fcfd bl 8001568 + MX_TIM3_Init(); + 8000b6e: f000 fd49 bl 8001604 + MX_TIM5_Init(); + 8000b72: f000 fdd5 bl 8001720 + MX_TIM8_Init(); + 8000b76: f000 fe21 bl 80017bc + MX_USART1_UART_Init(); + 8000b7a: f000 fef9 bl 8001970 + MX_USART6_UART_Init(); + 8000b7e: f000 ff27 bl 80019d0 + MX_ADC1_Init(); + 8000b82: f000 f9b7 bl 8000ef4 + MX_DAC_Init(); + 8000b86: f000 fa59 bl 800103c + MX_UART7_Init(); + 8000b8a: f000 fec1 bl 8001910 + MX_FMC_Init(); + 8000b8e: f000 ff4f bl 8001a30 + MX_DMA2D_Init(); + 8000b92: f000 fa7d bl 8001090 + /* USER CODE BEGIN 2 */ + BSP_LCD_Init(); + 8000b96: f001 fb47 bl 8002228 + BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS); + 8000b9a: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000 + 8000b9e: 2000 movs r0, #0 + 8000ba0: f001 fbda bl 8002358 + BSP_LCD_LayerDefaultInit(1, LCD_FB_START_ADDRESS+ BSP_LCD_GetXSize()*BSP_LCD_GetYSize()*4); + 8000ba4: f001 fbb0 bl 8002308 + 8000ba8: 4604 mov r4, r0 + 8000baa: f001 fbc1 bl 8002330 + 8000bae: 4603 mov r3, r0 + 8000bb0: fb03 f304 mul.w r3, r3, r4 + 8000bb4: f103 5340 add.w r3, r3, #805306368 ; 0x30000000 + 8000bb8: 009b lsls r3, r3, #2 + 8000bba: 4619 mov r1, r3 + 8000bbc: 2001 movs r0, #1 + 8000bbe: f001 fbcb bl 8002358 + BSP_LCD_DisplayOn(); + 8000bc2: f002 f819 bl 8002bf8 + BSP_LCD_SelectLayer(1); + 8000bc6: 2001 movs r0, #1 + 8000bc8: f001 fc26 bl 8002418 + BSP_LCD_Clear(LCD_COLOR_LIGHTGREEN); + 8000bcc: f06f 107f mvn.w r0, #8323199 ; 0x7f007f + 8000bd0: f001 fc94 bl 80024fc + BSP_LCD_SetFont(&Font12); + 8000bd4: 4863 ldr r0, [pc, #396] ; (8000d64 ) + 8000bd6: f001 fc61 bl 800249c + BSP_LCD_SetTextColor(LCD_COLOR_BLUE); + 8000bda: 4863 ldr r0, [pc, #396] ; (8000d68 ) + 8000bdc: f001 fc2c bl 8002438 + BSP_LCD_SetBackColor(LCD_COLOR_LIGHTGREEN); + 8000be0: f06f 107f mvn.w r0, #8323199 ; 0x7f007f + 8000be4: f001 fc40 bl 8002468 + + BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize()); + 8000be8: f001 fb8e bl 8002308 + 8000bec: 4603 mov r3, r0 + 8000bee: b29c uxth r4, r3 + 8000bf0: f001 fb9e bl 8002330 + 8000bf4: 4603 mov r3, r0 + 8000bf6: b29b uxth r3, r3 + 8000bf8: 4619 mov r1, r3 + 8000bfa: 4620 mov r0, r4 + 8000bfc: f002 fbca bl 8003394 + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* definition and creation of defaultTask */ + osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096); + 8000c00: 4b5a ldr r3, [pc, #360] ; (8000d6c ) + 8000c02: 463c mov r4, r7 + 8000c04: 461d mov r5, r3 + 8000c06: cd0f ldmia r5!, {r0, r1, r2, r3} + 8000c08: c40f stmia r4!, {r0, r1, r2, r3} + 8000c0a: e895 0007 ldmia.w r5, {r0, r1, r2} + 8000c0e: e884 0007 stmia.w r4, {r0, r1, r2} + defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL); + 8000c12: 463b mov r3, r7 + 8000c14: 2100 movs r1, #0 + 8000c16: 4618 mov r0, r3 + 8000c18: f009 fef2 bl 800aa00 + 8000c1c: 4602 mov r2, r0 + 8000c1e: 4b54 ldr r3, [pc, #336] ; (8000d70 ) + 8000c20: 601a str r2, [r3, #0] + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + HAL_GPIO_WritePin(LED13_GPIO_Port,LED13_Pin,HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin)); + 8000c22: f44f 7180 mov.w r1, #256 ; 0x100 + 8000c26: 4853 ldr r0, [pc, #332] ; (8000d74 ) + 8000c28: f005 f916 bl 8005e58 + 8000c2c: 4603 mov r3, r0 + 8000c2e: 461a mov r2, r3 + 8000c30: f44f 4180 mov.w r1, #16384 ; 0x4000 + 8000c34: 4850 ldr r0, [pc, #320] ; (8000d78 ) + 8000c36: f005 f927 bl 8005e88 + HAL_GPIO_WritePin(LED14_GPIO_Port,LED14_Pin,HAL_GPIO_ReadPin(BP2_GPIO_Port,BP2_Pin)); + 8000c3a: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8000c3e: 484d ldr r0, [pc, #308] ; (8000d74 ) + 8000c40: f005 f90a bl 8005e58 + 8000c44: 4603 mov r3, r0 + 8000c46: 461a mov r2, r3 + 8000c48: 2120 movs r1, #32 + 8000c4a: 484c ldr r0, [pc, #304] ; (8000d7c ) + 8000c4c: f005 f91c bl 8005e88 + sprintf(text,"BP1 : %d",HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin)); + 8000c50: f44f 7180 mov.w r1, #256 ; 0x100 + 8000c54: 4847 ldr r0, [pc, #284] ; (8000d74 ) + 8000c56: f005 f8ff bl 8005e58 + 8000c5a: 4603 mov r3, r0 + 8000c5c: 461a mov r2, r3 + 8000c5e: f107 032c add.w r3, r7, #44 ; 0x2c + 8000c62: 4947 ldr r1, [pc, #284] ; (8000d80 ) + 8000c64: 4618 mov r0, r3 + 8000c66: f00a ffb3 bl 800bbd0 + BSP_LCD_DisplayStringAtLine(5,(uint8_t*) text); + 8000c6a: f107 032c add.w r3, r7, #44 ; 0x2c + 8000c6e: 4619 mov r1, r3 + 8000c70: 2005 movs r0, #5 + 8000c72: f001 fd73 bl 800275c + + sConfig.Channel = ADC_CHANNEL_6; + 8000c76: 2306 movs r3, #6 + 8000c78: 61fb str r3, [r7, #28] + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + 8000c7a: f107 031c add.w r3, r7, #28 + 8000c7e: 4619 mov r1, r3 + 8000c80: 4840 ldr r0, [pc, #256] ; (8000d84 ) + 8000c82: f003 fdf9 bl 8004878 + HAL_ADC_Start(&hadc3); + 8000c86: 483f ldr r0, [pc, #252] ; (8000d84 ) + 8000c88: f003 fca4 bl 80045d4 + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + 8000c8c: bf00 nop + 8000c8e: 2164 movs r1, #100 ; 0x64 + 8000c90: 483c ldr r0, [pc, #240] ; (8000d84 ) + 8000c92: f003 fd5f bl 8004754 + 8000c96: 4603 mov r3, r0 + 8000c98: 2b00 cmp r3, #0 + 8000c9a: d1f8 bne.n 8000c8e + potr = HAL_ADC_GetValue(&hadc3); + 8000c9c: 4839 ldr r0, [pc, #228] ; (8000d84 ) + 8000c9e: f003 fddd bl 800485c + 8000ca2: 66f8 str r0, [r7, #108] ; 0x6c + + sConfig.Channel = ADC_CHANNEL_7; + 8000ca4: 2307 movs r3, #7 + 8000ca6: 61fb str r3, [r7, #28] + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + 8000ca8: f107 031c add.w r3, r7, #28 + 8000cac: 4619 mov r1, r3 + 8000cae: 4835 ldr r0, [pc, #212] ; (8000d84 ) + 8000cb0: f003 fde2 bl 8004878 + HAL_ADC_Start(&hadc3); + 8000cb4: 4833 ldr r0, [pc, #204] ; (8000d84 ) + 8000cb6: f003 fc8d bl 80045d4 + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + 8000cba: bf00 nop + 8000cbc: 2164 movs r1, #100 ; 0x64 + 8000cbe: 4831 ldr r0, [pc, #196] ; (8000d84 ) + 8000cc0: f003 fd48 bl 8004754 + 8000cc4: 4603 mov r3, r0 + 8000cc6: 2b00 cmp r3, #0 + 8000cc8: d1f8 bne.n 8000cbc + potl = HAL_ADC_GetValue(&hadc3); + 8000cca: 482e ldr r0, [pc, #184] ; (8000d84 ) + 8000ccc: f003 fdc6 bl 800485c + 8000cd0: 66b8 str r0, [r7, #104] ; 0x68 + + sConfig.Channel = ADC_CHANNEL_8; + 8000cd2: 2308 movs r3, #8 + 8000cd4: 61fb str r3, [r7, #28] + HAL_ADC_ConfigChannel(&hadc3, &sConfig); + 8000cd6: f107 031c add.w r3, r7, #28 + 8000cda: 4619 mov r1, r3 + 8000cdc: 4829 ldr r0, [pc, #164] ; (8000d84 ) + 8000cde: f003 fdcb bl 8004878 + HAL_ADC_Start(&hadc3); + 8000ce2: 4828 ldr r0, [pc, #160] ; (8000d84 ) + 8000ce4: f003 fc76 bl 80045d4 + while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK); + 8000ce8: bf00 nop + 8000cea: 2164 movs r1, #100 ; 0x64 + 8000cec: 4825 ldr r0, [pc, #148] ; (8000d84 ) + 8000cee: f003 fd31 bl 8004754 + 8000cf2: 4603 mov r3, r0 + 8000cf4: 2b00 cmp r3, #0 + 8000cf6: d1f8 bne.n 8000cea + joystick_v = HAL_ADC_GetValue(&hadc3); + 8000cf8: 4822 ldr r0, [pc, #136] ; (8000d84 ) + 8000cfa: f003 fdaf bl 800485c + 8000cfe: 6678 str r0, [r7, #100] ; 0x64 + + HAL_ADC_Start(&hadc1); + 8000d00: 4821 ldr r0, [pc, #132] ; (8000d88 ) + 8000d02: f003 fc67 bl 80045d4 + while(HAL_ADC_PollForConversion(&hadc1, 100)!=HAL_OK); + 8000d06: bf00 nop + 8000d08: 2164 movs r1, #100 ; 0x64 + 8000d0a: 481f ldr r0, [pc, #124] ; (8000d88 ) + 8000d0c: f003 fd22 bl 8004754 + 8000d10: 4603 mov r3, r0 + 8000d12: 2b00 cmp r3, #0 + 8000d14: d1f8 bne.n 8000d08 + joystick_h = HAL_ADC_GetValue(&hadc1); + 8000d16: 481c ldr r0, [pc, #112] ; (8000d88 ) + 8000d18: f003 fda0 bl 800485c + 8000d1c: 6638 str r0, [r7, #96] ; 0x60 + + sprintf(text,"POTL : %4u POTR : %4u joy_v : %4u joy_h : %4u",(uint)potl,(uint)potr,(uint)joystick_v,(uint)joystick_h); + 8000d1e: f107 002c add.w r0, r7, #44 ; 0x2c + 8000d22: 6e3b ldr r3, [r7, #96] ; 0x60 + 8000d24: 9301 str r3, [sp, #4] + 8000d26: 6e7b ldr r3, [r7, #100] ; 0x64 + 8000d28: 9300 str r3, [sp, #0] + 8000d2a: 6efb ldr r3, [r7, #108] ; 0x6c + 8000d2c: 6eba ldr r2, [r7, #104] ; 0x68 + 8000d2e: 4917 ldr r1, [pc, #92] ; (8000d8c ) + 8000d30: f00a ff4e bl 800bbd0 + BSP_LCD_DisplayStringAtLine(9,(uint8_t*) text); + 8000d34: f107 032c add.w r3, r7, #44 ; 0x2c + 8000d38: 4619 mov r1, r3 + 8000d3a: 2009 movs r0, #9 + 8000d3c: f001 fd0e bl 800275c + + BSP_TS_GetState(&TS_State); + 8000d40: 4813 ldr r0, [pc, #76] ; (8000d90 ) + 8000d42: f002 fb67 bl 8003414 + if(TS_State.touchDetected){ + 8000d46: 4b12 ldr r3, [pc, #72] ; (8000d90 ) + 8000d48: 781b ldrb r3, [r3, #0] + 8000d4a: 2b00 cmp r3, #0 + 8000d4c: f43f af69 beq.w 8000c22 + BSP_LCD_FillCircle(TS_State.touchX[0],TS_State.touchY[0],4); + 8000d50: 4b0f ldr r3, [pc, #60] ; (8000d90 ) + 8000d52: 8858 ldrh r0, [r3, #2] + 8000d54: 4b0e ldr r3, [pc, #56] ; (8000d90 ) + 8000d56: 899b ldrh r3, [r3, #12] + 8000d58: 2204 movs r2, #4 + 8000d5a: 4619 mov r1, r3 + 8000d5c: f001 feac bl 8002ab8 + HAL_GPIO_WritePin(LED13_GPIO_Port,LED13_Pin,HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin)); + 8000d60: e75f b.n 8000c22 + 8000d62: bf00 nop + 8000d64: 20000030 .word 0x20000030 + 8000d68: ff0000ff .word 0xff0000ff + 8000d6c: 0800c428 .word 0x0800c428 + 8000d70: 20008438 .word 0x20008438 + 8000d74: 40020000 .word 0x40020000 + 8000d78: 40021c00 .word 0x40021c00 + 8000d7c: 40021000 .word 0x40021000 + 8000d80: 0800c3e0 .word 0x0800c3e0 + 8000d84: 20008768 .word 0x20008768 + 8000d88: 20008720 .word 0x20008720 + 8000d8c: 0800c3ec .word 0x0800c3ec + 8000d90: 200000d4 .word 0x200000d4 + +08000d94 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000d94: b580 push {r7, lr} + 8000d96: b0b4 sub sp, #208 ; 0xd0 + 8000d98: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000d9a: f107 03a0 add.w r3, r7, #160 ; 0xa0 + 8000d9e: 2230 movs r2, #48 ; 0x30 + 8000da0: 2100 movs r1, #0 + 8000da2: 4618 mov r0, r3 + 8000da4: f00a ff0b bl 800bbbe + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000da8: f107 038c add.w r3, r7, #140 ; 0x8c + 8000dac: 2200 movs r2, #0 + 8000dae: 601a str r2, [r3, #0] + 8000db0: 605a str r2, [r3, #4] + 8000db2: 609a str r2, [r3, #8] + 8000db4: 60da str r2, [r3, #12] + 8000db6: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8000db8: f107 0308 add.w r3, r7, #8 + 8000dbc: 2284 movs r2, #132 ; 0x84 + 8000dbe: 2100 movs r1, #0 + 8000dc0: 4618 mov r0, r3 + 8000dc2: f00a fefc bl 800bbbe + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 8000dc6: f006 f9a1 bl 800710c + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 8000dca: 4b47 ldr r3, [pc, #284] ; (8000ee8 ) + 8000dcc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000dce: 4a46 ldr r2, [pc, #280] ; (8000ee8 ) + 8000dd0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000dd4: 6413 str r3, [r2, #64] ; 0x40 + 8000dd6: 4b44 ldr r3, [pc, #272] ; (8000ee8 ) + 8000dd8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000dda: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000dde: 607b str r3, [r7, #4] + 8000de0: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000de2: 4b42 ldr r3, [pc, #264] ; (8000eec ) + 8000de4: 681b ldr r3, [r3, #0] + 8000de6: 4a41 ldr r2, [pc, #260] ; (8000eec ) + 8000de8: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 8000dec: 6013 str r3, [r2, #0] + 8000dee: 4b3f ldr r3, [pc, #252] ; (8000eec ) + 8000df0: 681b ldr r3, [r3, #0] + 8000df2: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000df6: 603b str r3, [r7, #0] + 8000df8: 683b ldr r3, [r7, #0] + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + 8000dfa: 2309 movs r3, #9 + 8000dfc: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8000e00: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8000e04: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + 8000e08: 2301 movs r3, #1 + 8000e0a: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000e0e: 2302 movs r3, #2 + 8000e10: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8000e14: f44f 0380 mov.w r3, #4194304 ; 0x400000 + 8000e18: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + RCC_OscInitStruct.PLL.PLLM = 25; + 8000e1c: 2319 movs r3, #25 + 8000e1e: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + RCC_OscInitStruct.PLL.PLLN = 400; + 8000e22: f44f 73c8 mov.w r3, #400 ; 0x190 + 8000e26: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 8000e2a: 2302 movs r3, #2 + 8000e2c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + RCC_OscInitStruct.PLL.PLLQ = 9; + 8000e30: 2309 movs r3, #9 + 8000e32: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000e36: f107 03a0 add.w r3, r7, #160 ; 0xa0 + 8000e3a: 4618 mov r0, r3 + 8000e3c: f006 f9c6 bl 80071cc + 8000e40: 4603 mov r3, r0 + 8000e42: 2b00 cmp r3, #0 + 8000e44: d001 beq.n 8000e4a + { + Error_Handler(); + 8000e46: f001 f847 bl 8001ed8 + } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + 8000e4a: f006 f96f bl 800712c + 8000e4e: 4603 mov r3, r0 + 8000e50: 2b00 cmp r3, #0 + 8000e52: d001 beq.n 8000e58 + { + Error_Handler(); + 8000e54: f001 f840 bl 8001ed8 + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000e58: 230f movs r3, #15 + 8000e5a: f8c7 308c str.w r3, [r7, #140] ; 0x8c + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000e5e: 2302 movs r3, #2 + 8000e60: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000e64: 2300 movs r3, #0 + 8000e66: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 8000e6a: f44f 53a0 mov.w r3, #5120 ; 0x1400 + 8000e6e: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 8000e72: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8000e76: f8c7 309c str.w r3, [r7, #156] ; 0x9c + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) + 8000e7a: f107 038c add.w r3, r7, #140 ; 0x8c + 8000e7e: 2106 movs r1, #6 + 8000e80: 4618 mov r0, r3 + 8000e82: f006 fc47 bl 8007714 + 8000e86: 4603 mov r3, r0 + 8000e88: 2b00 cmp r3, #0 + 8000e8a: d001 beq.n 8000e90 + { + Error_Handler(); + 8000e8c: f001 f824 bl 8001ed8 + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_RTC + 8000e90: 4b17 ldr r3, [pc, #92] ; (8000ef0 ) + 8000e92: 60bb str r3, [r7, #8] + |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART6 + |RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_I2C1 + |RCC_PERIPHCLK_I2C3; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 384; + 8000e94: f44f 73c0 mov.w r3, #384 ; 0x180 + 8000e98: 61fb str r3, [r7, #28] + PeriphClkInitStruct.PLLSAI.PLLSAIR = 5; + 8000e9a: 2305 movs r3, #5 + 8000e9c: 627b str r3, [r7, #36] ; 0x24 + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + 8000e9e: 2302 movs r3, #2 + 8000ea0: 623b str r3, [r7, #32] + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8; + 8000ea2: 2303 movs r3, #3 + 8000ea4: 62bb str r3, [r7, #40] ; 0x28 + PeriphClkInitStruct.PLLSAIDivQ = 1; + 8000ea6: 2301 movs r3, #1 + 8000ea8: 633b str r3, [r7, #48] ; 0x30 + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8; + 8000eaa: f44f 3300 mov.w r3, #131072 ; 0x20000 + 8000eae: 637b str r3, [r7, #52] ; 0x34 + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + 8000eb0: f44f 7300 mov.w r3, #512 ; 0x200 + 8000eb4: 63bb str r3, [r7, #56] ; 0x38 + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 8000eb6: 2300 movs r3, #0 + 8000eb8: 64fb str r3, [r7, #76] ; 0x4c + PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2; + 8000eba: 2300 movs r3, #0 + 8000ebc: 663b str r3, [r7, #96] ; 0x60 + PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1; + 8000ebe: 2300 movs r3, #0 + 8000ec0: 667b str r3, [r7, #100] ; 0x64 + PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 8000ec2: 2300 movs r3, #0 + 8000ec4: 66fb str r3, [r7, #108] ; 0x6c + PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1; + 8000ec6: 2300 movs r3, #0 + 8000ec8: 677b str r3, [r7, #116] ; 0x74 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000eca: f107 0308 add.w r3, r7, #8 + 8000ece: 4618 mov r0, r3 + 8000ed0: f006 fe24 bl 8007b1c + 8000ed4: 4603 mov r3, r0 + 8000ed6: 2b00 cmp r3, #0 + 8000ed8: d001 beq.n 8000ede + { + Error_Handler(); + 8000eda: f000 fffd bl 8001ed8 + } +} + 8000ede: bf00 nop + 8000ee0: 37d0 adds r7, #208 ; 0xd0 + 8000ee2: 46bd mov sp, r7 + 8000ee4: bd80 pop {r7, pc} + 8000ee6: bf00 nop + 8000ee8: 40023800 .word 0x40023800 + 8000eec: 40007000 .word 0x40007000 + 8000ef0: 00015868 .word 0x00015868 + +08000ef4 : + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + 8000ef4: b580 push {r7, lr} + 8000ef6: b084 sub sp, #16 + 8000ef8: af00 add r7, sp, #0 + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + 8000efa: 463b mov r3, r7 + 8000efc: 2200 movs r2, #0 + 8000efe: 601a str r2, [r3, #0] + 8000f00: 605a str r2, [r3, #4] + 8000f02: 609a str r2, [r3, #8] + 8000f04: 60da str r2, [r3, #12] + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + 8000f06: 4b21 ldr r3, [pc, #132] ; (8000f8c ) + 8000f08: 4a21 ldr r2, [pc, #132] ; (8000f90 ) + 8000f0a: 601a str r2, [r3, #0] + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 8000f0c: 4b1f ldr r3, [pc, #124] ; (8000f8c ) + 8000f0e: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8000f12: 605a str r2, [r3, #4] + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 8000f14: 4b1d ldr r3, [pc, #116] ; (8000f8c ) + 8000f16: 2200 movs r2, #0 + 8000f18: 609a str r2, [r3, #8] + hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; + 8000f1a: 4b1c ldr r3, [pc, #112] ; (8000f8c ) + 8000f1c: 2200 movs r2, #0 + 8000f1e: 611a str r2, [r3, #16] + hadc1.Init.ContinuousConvMode = DISABLE; + 8000f20: 4b1a ldr r3, [pc, #104] ; (8000f8c ) + 8000f22: 2200 movs r2, #0 + 8000f24: 619a str r2, [r3, #24] + hadc1.Init.DiscontinuousConvMode = DISABLE; + 8000f26: 4b19 ldr r3, [pc, #100] ; (8000f8c ) + 8000f28: 2200 movs r2, #0 + 8000f2a: f883 2020 strb.w r2, [r3, #32] + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 8000f2e: 4b17 ldr r3, [pc, #92] ; (8000f8c ) + 8000f30: 2200 movs r2, #0 + 8000f32: 62da str r2, [r3, #44] ; 0x2c + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 8000f34: 4b15 ldr r3, [pc, #84] ; (8000f8c ) + 8000f36: 4a17 ldr r2, [pc, #92] ; (8000f94 ) + 8000f38: 629a str r2, [r3, #40] ; 0x28 + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 8000f3a: 4b14 ldr r3, [pc, #80] ; (8000f8c ) + 8000f3c: 2200 movs r2, #0 + 8000f3e: 60da str r2, [r3, #12] + hadc1.Init.NbrOfConversion = 1; + 8000f40: 4b12 ldr r3, [pc, #72] ; (8000f8c ) + 8000f42: 2201 movs r2, #1 + 8000f44: 61da str r2, [r3, #28] + hadc1.Init.DMAContinuousRequests = DISABLE; + 8000f46: 4b11 ldr r3, [pc, #68] ; (8000f8c ) + 8000f48: 2200 movs r2, #0 + 8000f4a: f883 2030 strb.w r2, [r3, #48] ; 0x30 + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 8000f4e: 4b0f ldr r3, [pc, #60] ; (8000f8c ) + 8000f50: 2201 movs r2, #1 + 8000f52: 615a str r2, [r3, #20] + if (HAL_ADC_Init(&hadc1) != HAL_OK) + 8000f54: 480d ldr r0, [pc, #52] ; (8000f8c ) + 8000f56: f003 faf9 bl 800454c + 8000f5a: 4603 mov r3, r0 + 8000f5c: 2b00 cmp r3, #0 + 8000f5e: d001 beq.n 8000f64 + { + Error_Handler(); + 8000f60: f000 ffba bl 8001ed8 + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_0; + 8000f64: 2300 movs r3, #0 + 8000f66: 603b str r3, [r7, #0] + sConfig.Rank = ADC_REGULAR_RANK_1; + 8000f68: 2301 movs r3, #1 + 8000f6a: 607b str r3, [r7, #4] + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 8000f6c: 2300 movs r3, #0 + 8000f6e: 60bb str r3, [r7, #8] + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 8000f70: 463b mov r3, r7 + 8000f72: 4619 mov r1, r3 + 8000f74: 4805 ldr r0, [pc, #20] ; (8000f8c ) + 8000f76: f003 fc7f bl 8004878 + 8000f7a: 4603 mov r3, r0 + 8000f7c: 2b00 cmp r3, #0 + 8000f7e: d001 beq.n 8000f84 + { + Error_Handler(); + 8000f80: f000 ffaa bl 8001ed8 + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + 8000f84: bf00 nop + 8000f86: 3710 adds r7, #16 + 8000f88: 46bd mov sp, r7 + 8000f8a: bd80 pop {r7, pc} + 8000f8c: 20008720 .word 0x20008720 + 8000f90: 40012000 .word 0x40012000 + 8000f94: 0f000001 .word 0x0f000001 + +08000f98 : + * @brief ADC3 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC3_Init(void) +{ + 8000f98: b580 push {r7, lr} + 8000f9a: b084 sub sp, #16 + 8000f9c: af00 add r7, sp, #0 + + /* USER CODE BEGIN ADC3_Init 0 */ + + /* USER CODE END ADC3_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + 8000f9e: 463b mov r3, r7 + 8000fa0: 2200 movs r2, #0 + 8000fa2: 601a str r2, [r3, #0] + 8000fa4: 605a str r2, [r3, #4] + 8000fa6: 609a str r2, [r3, #8] + 8000fa8: 60da str r2, [r3, #12] + /* USER CODE BEGIN ADC3_Init 1 */ + + /* USER CODE END ADC3_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc3.Instance = ADC3; + 8000faa: 4b21 ldr r3, [pc, #132] ; (8001030 ) + 8000fac: 4a21 ldr r2, [pc, #132] ; (8001034 ) + 8000fae: 601a str r2, [r3, #0] + hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 8000fb0: 4b1f ldr r3, [pc, #124] ; (8001030 ) + 8000fb2: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8000fb6: 605a str r2, [r3, #4] + hadc3.Init.Resolution = ADC_RESOLUTION_12B; + 8000fb8: 4b1d ldr r3, [pc, #116] ; (8001030 ) + 8000fba: 2200 movs r2, #0 + 8000fbc: 609a str r2, [r3, #8] + hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + 8000fbe: 4b1c ldr r3, [pc, #112] ; (8001030 ) + 8000fc0: 2200 movs r2, #0 + 8000fc2: 611a str r2, [r3, #16] + hadc3.Init.ContinuousConvMode = DISABLE; + 8000fc4: 4b1a ldr r3, [pc, #104] ; (8001030 ) + 8000fc6: 2200 movs r2, #0 + 8000fc8: 619a str r2, [r3, #24] + hadc3.Init.DiscontinuousConvMode = DISABLE; + 8000fca: 4b19 ldr r3, [pc, #100] ; (8001030 ) + 8000fcc: 2200 movs r2, #0 + 8000fce: f883 2020 strb.w r2, [r3, #32] + hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 8000fd2: 4b17 ldr r3, [pc, #92] ; (8001030 ) + 8000fd4: 2200 movs r2, #0 + 8000fd6: 62da str r2, [r3, #44] ; 0x2c + hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 8000fd8: 4b15 ldr r3, [pc, #84] ; (8001030 ) + 8000fda: 4a17 ldr r2, [pc, #92] ; (8001038 ) + 8000fdc: 629a str r2, [r3, #40] ; 0x28 + hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 8000fde: 4b14 ldr r3, [pc, #80] ; (8001030 ) + 8000fe0: 2200 movs r2, #0 + 8000fe2: 60da str r2, [r3, #12] + hadc3.Init.NbrOfConversion = 1; + 8000fe4: 4b12 ldr r3, [pc, #72] ; (8001030 ) + 8000fe6: 2201 movs r2, #1 + 8000fe8: 61da str r2, [r3, #28] + hadc3.Init.DMAContinuousRequests = DISABLE; + 8000fea: 4b11 ldr r3, [pc, #68] ; (8001030 ) + 8000fec: 2200 movs r2, #0 + 8000fee: f883 2030 strb.w r2, [r3, #48] ; 0x30 + hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 8000ff2: 4b0f ldr r3, [pc, #60] ; (8001030 ) + 8000ff4: 2201 movs r2, #1 + 8000ff6: 615a str r2, [r3, #20] + if (HAL_ADC_Init(&hadc3) != HAL_OK) + 8000ff8: 480d ldr r0, [pc, #52] ; (8001030 ) + 8000ffa: f003 faa7 bl 800454c + 8000ffe: 4603 mov r3, r0 + 8001000: 2b00 cmp r3, #0 + 8001002: d001 beq.n 8001008 + { + Error_Handler(); + 8001004: f000 ff68 bl 8001ed8 + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_6; + 8001008: 2306 movs r3, #6 + 800100a: 603b str r3, [r7, #0] + sConfig.Rank = ADC_REGULAR_RANK_1; + 800100c: 2301 movs r3, #1 + 800100e: 607b str r3, [r7, #4] + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 8001010: 2300 movs r3, #0 + 8001012: 60bb str r3, [r7, #8] + if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + 8001014: 463b mov r3, r7 + 8001016: 4619 mov r1, r3 + 8001018: 4805 ldr r0, [pc, #20] ; (8001030 ) + 800101a: f003 fc2d bl 8004878 + 800101e: 4603 mov r3, r0 + 8001020: 2b00 cmp r3, #0 + 8001022: d001 beq.n 8001028 + { + Error_Handler(); + 8001024: f000 ff58 bl 8001ed8 + } + /* USER CODE BEGIN ADC3_Init 2 */ + + /* USER CODE END ADC3_Init 2 */ + +} + 8001028: bf00 nop + 800102a: 3710 adds r7, #16 + 800102c: 46bd mov sp, r7 + 800102e: bd80 pop {r7, pc} + 8001030: 20008768 .word 0x20008768 + 8001034: 40012200 .word 0x40012200 + 8001038: 0f000001 .word 0x0f000001 + +0800103c : + * @brief DAC Initialization Function + * @param None + * @retval None + */ +static void MX_DAC_Init(void) +{ + 800103c: b580 push {r7, lr} + 800103e: b082 sub sp, #8 + 8001040: af00 add r7, sp, #0 + + /* USER CODE BEGIN DAC_Init 0 */ + + /* USER CODE END DAC_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + 8001042: 463b mov r3, r7 + 8001044: 2200 movs r2, #0 + 8001046: 601a str r2, [r3, #0] + 8001048: 605a str r2, [r3, #4] + /* USER CODE BEGIN DAC_Init 1 */ + + /* USER CODE END DAC_Init 1 */ + /** DAC Initialization + */ + hdac.Instance = DAC; + 800104a: 4b0f ldr r3, [pc, #60] ; (8001088 ) + 800104c: 4a0f ldr r2, [pc, #60] ; (800108c ) + 800104e: 601a str r2, [r3, #0] + if (HAL_DAC_Init(&hdac) != HAL_OK) + 8001050: 480d ldr r0, [pc, #52] ; (8001088 ) + 8001052: f003 ff37 bl 8004ec4 + 8001056: 4603 mov r3, r0 + 8001058: 2b00 cmp r3, #0 + 800105a: d001 beq.n 8001060 + { + Error_Handler(); + 800105c: f000 ff3c bl 8001ed8 + } + /** DAC channel OUT1 config + */ + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + 8001060: 2300 movs r3, #0 + 8001062: 603b str r3, [r7, #0] + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + 8001064: 2300 movs r3, #0 + 8001066: 607b str r3, [r7, #4] + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK) + 8001068: 463b mov r3, r7 + 800106a: 2200 movs r2, #0 + 800106c: 4619 mov r1, r3 + 800106e: 4806 ldr r0, [pc, #24] ; (8001088 ) + 8001070: f003 ff9e bl 8004fb0 + 8001074: 4603 mov r3, r0 + 8001076: 2b00 cmp r3, #0 + 8001078: d001 beq.n 800107e + { + Error_Handler(); + 800107a: f000 ff2d bl 8001ed8 + } + /* USER CODE BEGIN DAC_Init 2 */ + + /* USER CODE END DAC_Init 2 */ + +} + 800107e: bf00 nop + 8001080: 3708 adds r7, #8 + 8001082: 46bd mov sp, r7 + 8001084: bd80 pop {r7, pc} + 8001086: bf00 nop + 8001088: 20008830 .word 0x20008830 + 800108c: 40007400 .word 0x40007400 + +08001090 : + * @brief DMA2D Initialization Function + * @param None + * @retval None + */ +static void MX_DMA2D_Init(void) +{ + 8001090: b580 push {r7, lr} + 8001092: af00 add r7, sp, #0 + /* USER CODE END DMA2D_Init 0 */ + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + hdma2d.Instance = DMA2D; + 8001094: 4b15 ldr r3, [pc, #84] ; (80010ec ) + 8001096: 4a16 ldr r2, [pc, #88] ; (80010f0 ) + 8001098: 601a str r2, [r3, #0] + hdma2d.Init.Mode = DMA2D_M2M; + 800109a: 4b14 ldr r3, [pc, #80] ; (80010ec ) + 800109c: 2200 movs r2, #0 + 800109e: 605a str r2, [r3, #4] + hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; + 80010a0: 4b12 ldr r3, [pc, #72] ; (80010ec ) + 80010a2: 2200 movs r2, #0 + 80010a4: 609a str r2, [r3, #8] + hdma2d.Init.OutputOffset = 0; + 80010a6: 4b11 ldr r3, [pc, #68] ; (80010ec ) + 80010a8: 2200 movs r2, #0 + 80010aa: 60da str r2, [r3, #12] + hdma2d.LayerCfg[1].InputOffset = 0; + 80010ac: 4b0f ldr r3, [pc, #60] ; (80010ec ) + 80010ae: 2200 movs r2, #0 + 80010b0: 629a str r2, [r3, #40] ; 0x28 + hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + 80010b2: 4b0e ldr r3, [pc, #56] ; (80010ec ) + 80010b4: 2200 movs r2, #0 + 80010b6: 62da str r2, [r3, #44] ; 0x2c + hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + 80010b8: 4b0c ldr r3, [pc, #48] ; (80010ec ) + 80010ba: 2200 movs r2, #0 + 80010bc: 631a str r2, [r3, #48] ; 0x30 + hdma2d.LayerCfg[1].InputAlpha = 0; + 80010be: 4b0b ldr r3, [pc, #44] ; (80010ec ) + 80010c0: 2200 movs r2, #0 + 80010c2: 635a str r2, [r3, #52] ; 0x34 + if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) + 80010c4: 4809 ldr r0, [pc, #36] ; (80010ec ) + 80010c6: f004 f987 bl 80053d8 + 80010ca: 4603 mov r3, r0 + 80010cc: 2b00 cmp r3, #0 + 80010ce: d001 beq.n 80010d4 + { + Error_Handler(); + 80010d0: f000 ff02 bl 8001ed8 + } + if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) + 80010d4: 2101 movs r1, #1 + 80010d6: 4805 ldr r0, [pc, #20] ; (80010ec ) + 80010d8: f004 fadc bl 8005694 + 80010dc: 4603 mov r3, r0 + 80010de: 2b00 cmp r3, #0 + 80010e0: d001 beq.n 80010e6 + { + Error_Handler(); + 80010e2: f000 fef9 bl 8001ed8 + } + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + 80010e6: bf00 nop + 80010e8: bd80 pop {r7, pc} + 80010ea: bf00 nop + 80010ec: 20008924 .word 0x20008924 + 80010f0: 4002b000 .word 0x4002b000 + +080010f4 : + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 80010f4: b580 push {r7, lr} + 80010f6: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 80010f8: 4b1b ldr r3, [pc, #108] ; (8001168 ) + 80010fa: 4a1c ldr r2, [pc, #112] ; (800116c ) + 80010fc: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x00C0EAFF; + 80010fe: 4b1a ldr r3, [pc, #104] ; (8001168 ) + 8001100: 4a1b ldr r2, [pc, #108] ; (8001170 ) + 8001102: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 8001104: 4b18 ldr r3, [pc, #96] ; (8001168 ) + 8001106: 2200 movs r2, #0 + 8001108: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 800110a: 4b17 ldr r3, [pc, #92] ; (8001168 ) + 800110c: 2201 movs r2, #1 + 800110e: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001110: 4b15 ldr r3, [pc, #84] ; (8001168 ) + 8001112: 2200 movs r2, #0 + 8001114: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 8001116: 4b14 ldr r3, [pc, #80] ; (8001168 ) + 8001118: 2200 movs r2, #0 + 800111a: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 800111c: 4b12 ldr r3, [pc, #72] ; (8001168 ) + 800111e: 2200 movs r2, #0 + 8001120: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001122: 4b11 ldr r3, [pc, #68] ; (8001168 ) + 8001124: 2200 movs r2, #0 + 8001126: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001128: 4b0f ldr r3, [pc, #60] ; (8001168 ) + 800112a: 2200 movs r2, #0 + 800112c: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 800112e: 480e ldr r0, [pc, #56] ; (8001168 ) + 8001130: f004 fec4 bl 8005ebc + 8001134: 4603 mov r3, r0 + 8001136: 2b00 cmp r3, #0 + 8001138: d001 beq.n 800113e + { + Error_Handler(); + 800113a: f000 fecd bl 8001ed8 + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 800113e: 2100 movs r1, #0 + 8001140: 4809 ldr r0, [pc, #36] ; (8001168 ) + 8001142: f005 fbd3 bl 80068ec + 8001146: 4603 mov r3, r0 + 8001148: 2b00 cmp r3, #0 + 800114a: d001 beq.n 8001150 + { + Error_Handler(); + 800114c: f000 fec4 bl 8001ed8 + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 8001150: 2100 movs r1, #0 + 8001152: 4805 ldr r0, [pc, #20] ; (8001168 ) + 8001154: f005 fc15 bl 8006982 + 8001158: 4603 mov r3, r0 + 800115a: 2b00 cmp r3, #0 + 800115c: d001 beq.n 8001162 + { + Error_Handler(); + 800115e: f000 febb bl 8001ed8 + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8001162: bf00 nop + 8001164: bd80 pop {r7, pc} + 8001166: bf00 nop + 8001168: 200085ac .word 0x200085ac + 800116c: 40005400 .word 0x40005400 + 8001170: 00c0eaff .word 0x00c0eaff + +08001174 : + * @brief I2C3 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C3_Init(void) +{ + 8001174: b580 push {r7, lr} + 8001176: af00 add r7, sp, #0 + /* USER CODE END I2C3_Init 0 */ + + /* USER CODE BEGIN I2C3_Init 1 */ + + /* USER CODE END I2C3_Init 1 */ + hi2c3.Instance = I2C3; + 8001178: 4b1b ldr r3, [pc, #108] ; (80011e8 ) + 800117a: 4a1c ldr r2, [pc, #112] ; (80011ec ) + 800117c: 601a str r2, [r3, #0] + hi2c3.Init.Timing = 0x00C0EAFF; + 800117e: 4b1a ldr r3, [pc, #104] ; (80011e8 ) + 8001180: 4a1b ldr r2, [pc, #108] ; (80011f0 ) + 8001182: 605a str r2, [r3, #4] + hi2c3.Init.OwnAddress1 = 0; + 8001184: 4b18 ldr r3, [pc, #96] ; (80011e8 ) + 8001186: 2200 movs r2, #0 + 8001188: 609a str r2, [r3, #8] + hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 800118a: 4b17 ldr r3, [pc, #92] ; (80011e8 ) + 800118c: 2201 movs r2, #1 + 800118e: 60da str r2, [r3, #12] + hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001190: 4b15 ldr r3, [pc, #84] ; (80011e8 ) + 8001192: 2200 movs r2, #0 + 8001194: 611a str r2, [r3, #16] + hi2c3.Init.OwnAddress2 = 0; + 8001196: 4b14 ldr r3, [pc, #80] ; (80011e8 ) + 8001198: 2200 movs r2, #0 + 800119a: 615a str r2, [r3, #20] + hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 800119c: 4b12 ldr r3, [pc, #72] ; (80011e8 ) + 800119e: 2200 movs r2, #0 + 80011a0: 619a str r2, [r3, #24] + hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 80011a2: 4b11 ldr r3, [pc, #68] ; (80011e8 ) + 80011a4: 2200 movs r2, #0 + 80011a6: 61da str r2, [r3, #28] + hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 80011a8: 4b0f ldr r3, [pc, #60] ; (80011e8 ) + 80011aa: 2200 movs r2, #0 + 80011ac: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c3) != HAL_OK) + 80011ae: 480e ldr r0, [pc, #56] ; (80011e8 ) + 80011b0: f004 fe84 bl 8005ebc + 80011b4: 4603 mov r3, r0 + 80011b6: 2b00 cmp r3, #0 + 80011b8: d001 beq.n 80011be + { + Error_Handler(); + 80011ba: f000 fe8d bl 8001ed8 + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 80011be: 2100 movs r1, #0 + 80011c0: 4809 ldr r0, [pc, #36] ; (80011e8 ) + 80011c2: f005 fb93 bl 80068ec + 80011c6: 4603 mov r3, r0 + 80011c8: 2b00 cmp r3, #0 + 80011ca: d001 beq.n 80011d0 + { + Error_Handler(); + 80011cc: f000 fe84 bl 8001ed8 + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) + 80011d0: 2100 movs r1, #0 + 80011d2: 4805 ldr r0, [pc, #20] ; (80011e8 ) + 80011d4: f005 fbd5 bl 8006982 + 80011d8: 4603 mov r3, r0 + 80011da: 2b00 cmp r3, #0 + 80011dc: d001 beq.n 80011e2 + { + Error_Handler(); + 80011de: f000 fe7b bl 8001ed8 + } + /* USER CODE BEGIN I2C3_Init 2 */ + + /* USER CODE END I2C3_Init 2 */ + +} + 80011e2: bf00 nop + 80011e4: bd80 pop {r7, pc} + 80011e6: bf00 nop + 80011e8: 2000843c .word 0x2000843c + 80011ec: 40005c00 .word 0x40005c00 + 80011f0: 00c0eaff .word 0x00c0eaff + +080011f4 : + * @brief LTDC Initialization Function + * @param None + * @retval None + */ +static void MX_LTDC_Init(void) +{ + 80011f4: b580 push {r7, lr} + 80011f6: b08e sub sp, #56 ; 0x38 + 80011f8: af00 add r7, sp, #0 + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + 80011fa: 1d3b adds r3, r7, #4 + 80011fc: 2234 movs r2, #52 ; 0x34 + 80011fe: 2100 movs r1, #0 + 8001200: 4618 mov r0, r3 + 8001202: f00a fcdc bl 800bbbe + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + 8001206: 4b3a ldr r3, [pc, #232] ; (80012f0 ) + 8001208: 4a3a ldr r2, [pc, #232] ; (80012f4 ) + 800120a: 601a str r2, [r3, #0] + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + 800120c: 4b38 ldr r3, [pc, #224] ; (80012f0 ) + 800120e: 2200 movs r2, #0 + 8001210: 605a str r2, [r3, #4] + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + 8001212: 4b37 ldr r3, [pc, #220] ; (80012f0 ) + 8001214: 2200 movs r2, #0 + 8001216: 609a str r2, [r3, #8] + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + 8001218: 4b35 ldr r3, [pc, #212] ; (80012f0 ) + 800121a: 2200 movs r2, #0 + 800121c: 60da str r2, [r3, #12] + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + 800121e: 4b34 ldr r3, [pc, #208] ; (80012f0 ) + 8001220: 2200 movs r2, #0 + 8001222: 611a str r2, [r3, #16] + hltdc.Init.HorizontalSync = 40; + 8001224: 4b32 ldr r3, [pc, #200] ; (80012f0 ) + 8001226: 2228 movs r2, #40 ; 0x28 + 8001228: 615a str r2, [r3, #20] + hltdc.Init.VerticalSync = 9; + 800122a: 4b31 ldr r3, [pc, #196] ; (80012f0 ) + 800122c: 2209 movs r2, #9 + 800122e: 619a str r2, [r3, #24] + hltdc.Init.AccumulatedHBP = 53; + 8001230: 4b2f ldr r3, [pc, #188] ; (80012f0 ) + 8001232: 2235 movs r2, #53 ; 0x35 + 8001234: 61da str r2, [r3, #28] + hltdc.Init.AccumulatedVBP = 11; + 8001236: 4b2e ldr r3, [pc, #184] ; (80012f0 ) + 8001238: 220b movs r2, #11 + 800123a: 621a str r2, [r3, #32] + hltdc.Init.AccumulatedActiveW = 533; + 800123c: 4b2c ldr r3, [pc, #176] ; (80012f0 ) + 800123e: f240 2215 movw r2, #533 ; 0x215 + 8001242: 625a str r2, [r3, #36] ; 0x24 + hltdc.Init.AccumulatedActiveH = 283; + 8001244: 4b2a ldr r3, [pc, #168] ; (80012f0 ) + 8001246: f240 121b movw r2, #283 ; 0x11b + 800124a: 629a str r2, [r3, #40] ; 0x28 + hltdc.Init.TotalWidth = 565; + 800124c: 4b28 ldr r3, [pc, #160] ; (80012f0 ) + 800124e: f240 2235 movw r2, #565 ; 0x235 + 8001252: 62da str r2, [r3, #44] ; 0x2c + hltdc.Init.TotalHeigh = 285; + 8001254: 4b26 ldr r3, [pc, #152] ; (80012f0 ) + 8001256: f240 121d movw r2, #285 ; 0x11d + 800125a: 631a str r2, [r3, #48] ; 0x30 + hltdc.Init.Backcolor.Blue = 0; + 800125c: 4b24 ldr r3, [pc, #144] ; (80012f0 ) + 800125e: 2200 movs r2, #0 + 8001260: f883 2034 strb.w r2, [r3, #52] ; 0x34 + hltdc.Init.Backcolor.Green = 0; + 8001264: 4b22 ldr r3, [pc, #136] ; (80012f0 ) + 8001266: 2200 movs r2, #0 + 8001268: f883 2035 strb.w r2, [r3, #53] ; 0x35 + hltdc.Init.Backcolor.Red = 0; + 800126c: 4b20 ldr r3, [pc, #128] ; (80012f0 ) + 800126e: 2200 movs r2, #0 + 8001270: f883 2036 strb.w r2, [r3, #54] ; 0x36 + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + 8001274: 481e ldr r0, [pc, #120] ; (80012f0 ) + 8001276: f005 fbd1 bl 8006a1c + 800127a: 4603 mov r3, r0 + 800127c: 2b00 cmp r3, #0 + 800127e: d001 beq.n 8001284 + { + Error_Handler(); + 8001280: f000 fe2a bl 8001ed8 + } + pLayerCfg.WindowX0 = 0; + 8001284: 2300 movs r3, #0 + 8001286: 607b str r3, [r7, #4] + pLayerCfg.WindowX1 = 480; + 8001288: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 800128c: 60bb str r3, [r7, #8] + pLayerCfg.WindowY0 = 0; + 800128e: 2300 movs r3, #0 + 8001290: 60fb str r3, [r7, #12] + pLayerCfg.WindowY1 = 272; + 8001292: f44f 7388 mov.w r3, #272 ; 0x110 + 8001296: 613b str r3, [r7, #16] + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; + 8001298: 2302 movs r3, #2 + 800129a: 617b str r3, [r7, #20] + pLayerCfg.Alpha = 255; + 800129c: 23ff movs r3, #255 ; 0xff + 800129e: 61bb str r3, [r7, #24] + pLayerCfg.Alpha0 = 0; + 80012a0: 2300 movs r3, #0 + 80012a2: 61fb str r3, [r7, #28] + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + 80012a4: f44f 63c0 mov.w r3, #1536 ; 0x600 + 80012a8: 623b str r3, [r7, #32] + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + 80012aa: 2307 movs r3, #7 + 80012ac: 627b str r3, [r7, #36] ; 0x24 + pLayerCfg.FBStartAdress = 0xC0000000; + 80012ae: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000 + 80012b2: 62bb str r3, [r7, #40] ; 0x28 + pLayerCfg.ImageWidth = 480; + 80012b4: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 80012b8: 62fb str r3, [r7, #44] ; 0x2c + pLayerCfg.ImageHeight = 272; + 80012ba: f44f 7388 mov.w r3, #272 ; 0x110 + 80012be: 633b str r3, [r7, #48] ; 0x30 + pLayerCfg.Backcolor.Blue = 0; + 80012c0: 2300 movs r3, #0 + 80012c2: f887 3034 strb.w r3, [r7, #52] ; 0x34 + pLayerCfg.Backcolor.Green = 0; + 80012c6: 2300 movs r3, #0 + 80012c8: f887 3035 strb.w r3, [r7, #53] ; 0x35 + pLayerCfg.Backcolor.Red = 0; + 80012cc: 2300 movs r3, #0 + 80012ce: f887 3036 strb.w r3, [r7, #54] ; 0x36 + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + 80012d2: 1d3b adds r3, r7, #4 + 80012d4: 2200 movs r2, #0 + 80012d6: 4619 mov r1, r3 + 80012d8: 4805 ldr r0, [pc, #20] ; (80012f0 ) + 80012da: f005 fd31 bl 8006d40 + 80012de: 4603 mov r3, r0 + 80012e0: 2b00 cmp r3, #0 + 80012e2: d001 beq.n 80012e8 + { + Error_Handler(); + 80012e4: f000 fdf8 bl 8001ed8 + } + /* USER CODE BEGIN LTDC_Init 2 */ + + /* USER CODE END LTDC_Init 2 */ + +} + 80012e8: bf00 nop + 80012ea: 3738 adds r7, #56 ; 0x38 + 80012ec: 46bd mov sp, r7 + 80012ee: bd80 pop {r7, pc} + 80012f0: 20008678 .word 0x20008678 + 80012f4: 40016800 .word 0x40016800 + +080012f8 : + * @brief RTC Initialization Function + * @param None + * @retval None + */ +static void MX_RTC_Init(void) +{ + 80012f8: b580 push {r7, lr} + 80012fa: b092 sub sp, #72 ; 0x48 + 80012fc: af00 add r7, sp, #0 + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + RTC_TimeTypeDef sTime = {0}; + 80012fe: f107 0330 add.w r3, r7, #48 ; 0x30 + 8001302: 2200 movs r2, #0 + 8001304: 601a str r2, [r3, #0] + 8001306: 605a str r2, [r3, #4] + 8001308: 609a str r2, [r3, #8] + 800130a: 60da str r2, [r3, #12] + 800130c: 611a str r2, [r3, #16] + 800130e: 615a str r2, [r3, #20] + RTC_DateTypeDef sDate = {0}; + 8001310: 2300 movs r3, #0 + 8001312: 62fb str r3, [r7, #44] ; 0x2c + RTC_AlarmTypeDef sAlarm = {0}; + 8001314: 463b mov r3, r7 + 8001316: 222c movs r2, #44 ; 0x2c + 8001318: 2100 movs r1, #0 + 800131a: 4618 mov r0, r3 + 800131c: f00a fc4f bl 800bbbe + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 8001320: 4b46 ldr r3, [pc, #280] ; (800143c ) + 8001322: 4a47 ldr r2, [pc, #284] ; (8001440 ) + 8001324: 601a str r2, [r3, #0] + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + 8001326: 4b45 ldr r3, [pc, #276] ; (800143c ) + 8001328: 2200 movs r2, #0 + 800132a: 605a str r2, [r3, #4] + hrtc.Init.AsynchPrediv = 127; + 800132c: 4b43 ldr r3, [pc, #268] ; (800143c ) + 800132e: 227f movs r2, #127 ; 0x7f + 8001330: 609a str r2, [r3, #8] + hrtc.Init.SynchPrediv = 255; + 8001332: 4b42 ldr r3, [pc, #264] ; (800143c ) + 8001334: 22ff movs r2, #255 ; 0xff + 8001336: 60da str r2, [r3, #12] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 8001338: 4b40 ldr r3, [pc, #256] ; (800143c ) + 800133a: 2200 movs r2, #0 + 800133c: 611a str r2, [r3, #16] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 800133e: 4b3f ldr r3, [pc, #252] ; (800143c ) + 8001340: 2200 movs r2, #0 + 8001342: 615a str r2, [r3, #20] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 8001344: 4b3d ldr r3, [pc, #244] ; (800143c ) + 8001346: 2200 movs r2, #0 + 8001348: 619a str r2, [r3, #24] + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 800134a: 483c ldr r0, [pc, #240] ; (800143c ) + 800134c: f006 ffd4 bl 80082f8 + 8001350: 4603 mov r3, r0 + 8001352: 2b00 cmp r3, #0 + 8001354: d001 beq.n 800135a + { + Error_Handler(); + 8001356: f000 fdbf bl 8001ed8 + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + sTime.Hours = 0x0; + 800135a: 2300 movs r3, #0 + 800135c: f887 3030 strb.w r3, [r7, #48] ; 0x30 + sTime.Minutes = 0x0; + 8001360: 2300 movs r3, #0 + 8001362: f887 3031 strb.w r3, [r7, #49] ; 0x31 + sTime.Seconds = 0x0; + 8001366: 2300 movs r3, #0 + 8001368: f887 3032 strb.w r3, [r7, #50] ; 0x32 + sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 800136c: 2300 movs r3, #0 + 800136e: 643b str r3, [r7, #64] ; 0x40 + sTime.StoreOperation = RTC_STOREOPERATION_RESET; + 8001370: 2300 movs r3, #0 + 8001372: 647b str r3, [r7, #68] ; 0x44 + if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) + 8001374: f107 0330 add.w r3, r7, #48 ; 0x30 + 8001378: 2201 movs r2, #1 + 800137a: 4619 mov r1, r3 + 800137c: 482f ldr r0, [pc, #188] ; (800143c ) + 800137e: f007 f837 bl 80083f0 + 8001382: 4603 mov r3, r0 + 8001384: 2b00 cmp r3, #0 + 8001386: d001 beq.n 800138c + { + Error_Handler(); + 8001388: f000 fda6 bl 8001ed8 + } + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + 800138c: 2301 movs r3, #1 + 800138e: f887 302c strb.w r3, [r7, #44] ; 0x2c + sDate.Month = RTC_MONTH_JANUARY; + 8001392: 2301 movs r3, #1 + 8001394: f887 302d strb.w r3, [r7, #45] ; 0x2d + sDate.Date = 0x1; + 8001398: 2301 movs r3, #1 + 800139a: f887 302e strb.w r3, [r7, #46] ; 0x2e + sDate.Year = 0x0; + 800139e: 2300 movs r3, #0 + 80013a0: f887 302f strb.w r3, [r7, #47] ; 0x2f + if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) + 80013a4: f107 032c add.w r3, r7, #44 ; 0x2c + 80013a8: 2201 movs r2, #1 + 80013aa: 4619 mov r1, r3 + 80013ac: 4823 ldr r0, [pc, #140] ; (800143c ) + 80013ae: f007 f8dd bl 800856c + 80013b2: 4603 mov r3, r0 + 80013b4: 2b00 cmp r3, #0 + 80013b6: d001 beq.n 80013bc + { + Error_Handler(); + 80013b8: f000 fd8e bl 8001ed8 + } + /** Enable the Alarm A + */ + sAlarm.AlarmTime.Hours = 0x0; + 80013bc: 2300 movs r3, #0 + 80013be: 703b strb r3, [r7, #0] + sAlarm.AlarmTime.Minutes = 0x0; + 80013c0: 2300 movs r3, #0 + 80013c2: 707b strb r3, [r7, #1] + sAlarm.AlarmTime.Seconds = 0x0; + 80013c4: 2300 movs r3, #0 + 80013c6: 70bb strb r3, [r7, #2] + sAlarm.AlarmTime.SubSeconds = 0x0; + 80013c8: 2300 movs r3, #0 + 80013ca: 607b str r3, [r7, #4] + sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 80013cc: 2300 movs r3, #0 + 80013ce: 613b str r3, [r7, #16] + sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + 80013d0: 2300 movs r3, #0 + 80013d2: 617b str r3, [r7, #20] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 80013d4: 2300 movs r3, #0 + 80013d6: 61bb str r3, [r7, #24] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL; + 80013d8: 2300 movs r3, #0 + 80013da: 61fb str r3, [r7, #28] + sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE; + 80013dc: 2300 movs r3, #0 + 80013de: 623b str r3, [r7, #32] + sAlarm.AlarmDateWeekDay = 0x1; + 80013e0: 2301 movs r3, #1 + 80013e2: f887 3024 strb.w r3, [r7, #36] ; 0x24 + sAlarm.Alarm = RTC_ALARM_A; + 80013e6: f44f 7380 mov.w r3, #256 ; 0x100 + 80013ea: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + 80013ec: 463b mov r3, r7 + 80013ee: 2201 movs r2, #1 + 80013f0: 4619 mov r1, r3 + 80013f2: 4812 ldr r0, [pc, #72] ; (800143c ) + 80013f4: f007 f962 bl 80086bc + 80013f8: 4603 mov r3, r0 + 80013fa: 2b00 cmp r3, #0 + 80013fc: d001 beq.n 8001402 + { + Error_Handler(); + 80013fe: f000 fd6b bl 8001ed8 + } + /** Enable the Alarm B + */ + sAlarm.Alarm = RTC_ALARM_B; + 8001402: f44f 7300 mov.w r3, #512 ; 0x200 + 8001406: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + 8001408: 463b mov r3, r7 + 800140a: 2201 movs r2, #1 + 800140c: 4619 mov r1, r3 + 800140e: 480b ldr r0, [pc, #44] ; (800143c ) + 8001410: f007 f954 bl 80086bc + 8001414: 4603 mov r3, r0 + 8001416: 2b00 cmp r3, #0 + 8001418: d001 beq.n 800141e + { + Error_Handler(); + 800141a: f000 fd5d bl 8001ed8 + } + /** Enable the TimeStamp + */ + if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_POS1) != HAL_OK) + 800141e: 2202 movs r2, #2 + 8001420: 2100 movs r1, #0 + 8001422: 4806 ldr r0, [pc, #24] ; (800143c ) + 8001424: f007 fad4 bl 80089d0 + 8001428: 4603 mov r3, r0 + 800142a: 2b00 cmp r3, #0 + 800142c: d001 beq.n 8001432 + { + Error_Handler(); + 800142e: f000 fd53 bl 8001ed8 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 8001432: bf00 nop + 8001434: 3748 adds r7, #72 ; 0x48 + 8001436: 46bd mov sp, r7 + 8001438: bd80 pop {r7, pc} + 800143a: bf00 nop + 800143c: 20008844 .word 0x20008844 + 8001440: 40002800 .word 0x40002800 + +08001444 : + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + 8001444: b580 push {r7, lr} + 8001446: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + 8001448: 4b1b ldr r3, [pc, #108] ; (80014b8 ) + 800144a: 4a1c ldr r2, [pc, #112] ; (80014bc ) + 800144c: 601a str r2, [r3, #0] + hspi2.Init.Mode = SPI_MODE_MASTER; + 800144e: 4b1a ldr r3, [pc, #104] ; (80014b8 ) + 8001450: f44f 7282 mov.w r2, #260 ; 0x104 + 8001454: 605a str r2, [r3, #4] + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + 8001456: 4b18 ldr r3, [pc, #96] ; (80014b8 ) + 8001458: 2200 movs r2, #0 + 800145a: 609a str r2, [r3, #8] + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + 800145c: 4b16 ldr r3, [pc, #88] ; (80014b8 ) + 800145e: f44f 7240 mov.w r2, #768 ; 0x300 + 8001462: 60da str r2, [r3, #12] + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + 8001464: 4b14 ldr r3, [pc, #80] ; (80014b8 ) + 8001466: 2200 movs r2, #0 + 8001468: 611a str r2, [r3, #16] + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + 800146a: 4b13 ldr r3, [pc, #76] ; (80014b8 ) + 800146c: 2200 movs r2, #0 + 800146e: 615a str r2, [r3, #20] + hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT; + 8001470: 4b11 ldr r3, [pc, #68] ; (80014b8 ) + 8001472: f44f 2280 mov.w r2, #262144 ; 0x40000 + 8001476: 619a str r2, [r3, #24] + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8001478: 4b0f ldr r3, [pc, #60] ; (80014b8 ) + 800147a: 2200 movs r2, #0 + 800147c: 61da str r2, [r3, #28] + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + 800147e: 4b0e ldr r3, [pc, #56] ; (80014b8 ) + 8001480: 2200 movs r2, #0 + 8001482: 621a str r2, [r3, #32] + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + 8001484: 4b0c ldr r3, [pc, #48] ; (80014b8 ) + 8001486: 2200 movs r2, #0 + 8001488: 625a str r2, [r3, #36] ; 0x24 + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 800148a: 4b0b ldr r3, [pc, #44] ; (80014b8 ) + 800148c: 2200 movs r2, #0 + 800148e: 629a str r2, [r3, #40] ; 0x28 + hspi2.Init.CRCPolynomial = 7; + 8001490: 4b09 ldr r3, [pc, #36] ; (80014b8 ) + 8001492: 2207 movs r2, #7 + 8001494: 62da str r2, [r3, #44] ; 0x2c + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 8001496: 4b08 ldr r3, [pc, #32] ; (80014b8 ) + 8001498: 2200 movs r2, #0 + 800149a: 631a str r2, [r3, #48] ; 0x30 + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 800149c: 4b06 ldr r3, [pc, #24] ; (80014b8 ) + 800149e: 2208 movs r2, #8 + 80014a0: 635a str r2, [r3, #52] ; 0x34 + if (HAL_SPI_Init(&hspi2) != HAL_OK) + 80014a2: 4805 ldr r0, [pc, #20] ; (80014b8 ) + 80014a4: f007 fb69 bl 8008b7a + 80014a8: 4603 mov r3, r0 + 80014aa: 2b00 cmp r3, #0 + 80014ac: d001 beq.n 80014b2 + { + Error_Handler(); + 80014ae: f000 fd13 bl 8001ed8 + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + 80014b2: bf00 nop + 80014b4: bd80 pop {r7, pc} + 80014b6: bf00 nop + 80014b8: 20008488 .word 0x20008488 + 80014bc: 40003800 .word 0x40003800 + +080014c0 : + * @brief TIM1 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM1_Init(void) +{ + 80014c0: b580 push {r7, lr} + 80014c2: b088 sub sp, #32 + 80014c4: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM1_Init 0 */ + + /* USER CODE END TIM1_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 80014c6: f107 0310 add.w r3, r7, #16 + 80014ca: 2200 movs r2, #0 + 80014cc: 601a str r2, [r3, #0] + 80014ce: 605a str r2, [r3, #4] + 80014d0: 609a str r2, [r3, #8] + 80014d2: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80014d4: 1d3b adds r3, r7, #4 + 80014d6: 2200 movs r2, #0 + 80014d8: 601a str r2, [r3, #0] + 80014da: 605a str r2, [r3, #4] + 80014dc: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM1_Init 1 */ + + /* USER CODE END TIM1_Init 1 */ + htim1.Instance = TIM1; + 80014de: 4b20 ldr r3, [pc, #128] ; (8001560 ) + 80014e0: 4a20 ldr r2, [pc, #128] ; (8001564 ) + 80014e2: 601a str r2, [r3, #0] + htim1.Init.Prescaler = 0; + 80014e4: 4b1e ldr r3, [pc, #120] ; (8001560 ) + 80014e6: 2200 movs r2, #0 + 80014e8: 605a str r2, [r3, #4] + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + 80014ea: 4b1d ldr r3, [pc, #116] ; (8001560 ) + 80014ec: 2200 movs r2, #0 + 80014ee: 609a str r2, [r3, #8] + htim1.Init.Period = 65535; + 80014f0: 4b1b ldr r3, [pc, #108] ; (8001560 ) + 80014f2: f64f 72ff movw r2, #65535 ; 0xffff + 80014f6: 60da str r2, [r3, #12] + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80014f8: 4b19 ldr r3, [pc, #100] ; (8001560 ) + 80014fa: 2200 movs r2, #0 + 80014fc: 611a str r2, [r3, #16] + htim1.Init.RepetitionCounter = 0; + 80014fe: 4b18 ldr r3, [pc, #96] ; (8001560 ) + 8001500: 2200 movs r2, #0 + 8001502: 615a str r2, [r3, #20] + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001504: 4b16 ldr r3, [pc, #88] ; (8001560 ) + 8001506: 2200 movs r2, #0 + 8001508: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + 800150a: 4815 ldr r0, [pc, #84] ; (8001560 ) + 800150c: f007 fbc7 bl 8008c9e + 8001510: 4603 mov r3, r0 + 8001512: 2b00 cmp r3, #0 + 8001514: d001 beq.n 800151a + { + Error_Handler(); + 8001516: f000 fcdf bl 8001ed8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800151a: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800151e: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + 8001520: f107 0310 add.w r3, r7, #16 + 8001524: 4619 mov r1, r3 + 8001526: 480e ldr r0, [pc, #56] ; (8001560 ) + 8001528: f007 fe7a bl 8009220 + 800152c: 4603 mov r3, r0 + 800152e: 2b00 cmp r3, #0 + 8001530: d001 beq.n 8001536 + { + Error_Handler(); + 8001532: f000 fcd1 bl 8001ed8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001536: 2300 movs r3, #0 + 8001538: 607b str r3, [r7, #4] + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + 800153a: 2300 movs r3, #0 + 800153c: 60bb str r3, [r7, #8] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800153e: 2300 movs r3, #0 + 8001540: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + 8001542: 1d3b adds r3, r7, #4 + 8001544: 4619 mov r1, r3 + 8001546: 4806 ldr r0, [pc, #24] ; (8001560 ) + 8001548: f008 fbae bl 8009ca8 + 800154c: 4603 mov r3, r0 + 800154e: 2b00 cmp r3, #0 + 8001550: d001 beq.n 8001556 + { + Error_Handler(); + 8001552: f000 fcc1 bl 8001ed8 + } + /* USER CODE BEGIN TIM1_Init 2 */ + + /* USER CODE END TIM1_Init 2 */ + +} + 8001556: bf00 nop + 8001558: 3720 adds r7, #32 + 800155a: 46bd mov sp, r7 + 800155c: bd80 pop {r7, pc} + 800155e: bf00 nop + 8001560: 20008864 .word 0x20008864 + 8001564: 40010000 .word 0x40010000 + +08001568 : + * @brief TIM2 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM2_Init(void) +{ + 8001568: b580 push {r7, lr} + 800156a: b088 sub sp, #32 + 800156c: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800156e: f107 0310 add.w r3, r7, #16 + 8001572: 2200 movs r2, #0 + 8001574: 601a str r2, [r3, #0] + 8001576: 605a str r2, [r3, #4] + 8001578: 609a str r2, [r3, #8] + 800157a: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 800157c: 1d3b adds r3, r7, #4 + 800157e: 2200 movs r2, #0 + 8001580: 601a str r2, [r3, #0] + 8001582: 605a str r2, [r3, #4] + 8001584: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + 8001586: 4b1e ldr r3, [pc, #120] ; (8001600 ) + 8001588: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 800158c: 601a str r2, [r3, #0] + htim2.Init.Prescaler = 0; + 800158e: 4b1c ldr r3, [pc, #112] ; (8001600 ) + 8001590: 2200 movs r2, #0 + 8001592: 605a str r2, [r3, #4] + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001594: 4b1a ldr r3, [pc, #104] ; (8001600 ) + 8001596: 2200 movs r2, #0 + 8001598: 609a str r2, [r3, #8] + htim2.Init.Period = 4294967295; + 800159a: 4b19 ldr r3, [pc, #100] ; (8001600 ) + 800159c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80015a0: 60da str r2, [r3, #12] + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 80015a2: 4b17 ldr r3, [pc, #92] ; (8001600 ) + 80015a4: 2200 movs r2, #0 + 80015a6: 611a str r2, [r3, #16] + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 80015a8: 4b15 ldr r3, [pc, #84] ; (8001600 ) + 80015aa: 2200 movs r2, #0 + 80015ac: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + 80015ae: 4814 ldr r0, [pc, #80] ; (8001600 ) + 80015b0: f007 fb75 bl 8008c9e + 80015b4: 4603 mov r3, r0 + 80015b6: 2b00 cmp r3, #0 + 80015b8: d001 beq.n 80015be + { + Error_Handler(); + 80015ba: f000 fc8d bl 8001ed8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 80015be: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80015c2: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) + 80015c4: f107 0310 add.w r3, r7, #16 + 80015c8: 4619 mov r1, r3 + 80015ca: 480d ldr r0, [pc, #52] ; (8001600 ) + 80015cc: f007 fe28 bl 8009220 + 80015d0: 4603 mov r3, r0 + 80015d2: 2b00 cmp r3, #0 + 80015d4: d001 beq.n 80015da + { + Error_Handler(); + 80015d6: f000 fc7f bl 8001ed8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80015da: 2300 movs r3, #0 + 80015dc: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80015de: 2300 movs r3, #0 + 80015e0: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 80015e2: 1d3b adds r3, r7, #4 + 80015e4: 4619 mov r1, r3 + 80015e6: 4806 ldr r0, [pc, #24] ; (8001600 ) + 80015e8: f008 fb5e bl 8009ca8 + 80015ec: 4603 mov r3, r0 + 80015ee: 2b00 cmp r3, #0 + 80015f0: d001 beq.n 80015f6 + { + Error_Handler(); + 80015f2: f000 fc71 bl 8001ed8 + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + +} + 80015f6: bf00 nop + 80015f8: 3720 adds r7, #32 + 80015fa: 46bd mov sp, r7 + 80015fc: bd80 pop {r7, pc} + 80015fe: bf00 nop + 8001600: 20008964 .word 0x20008964 + +08001604 : + * @brief TIM3 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM3_Init(void) +{ + 8001604: b580 push {r7, lr} + 8001606: b094 sub sp, #80 ; 0x50 + 8001608: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 800160a: f107 0340 add.w r3, r7, #64 ; 0x40 + 800160e: 2200 movs r2, #0 + 8001610: 601a str r2, [r3, #0] + 8001612: 605a str r2, [r3, #4] + 8001614: 609a str r2, [r3, #8] + 8001616: 60da str r2, [r3, #12] + TIM_SlaveConfigTypeDef sSlaveConfig = {0}; + 8001618: f107 032c add.w r3, r7, #44 ; 0x2c + 800161c: 2200 movs r2, #0 + 800161e: 601a str r2, [r3, #0] + 8001620: 605a str r2, [r3, #4] + 8001622: 609a str r2, [r3, #8] + 8001624: 60da str r2, [r3, #12] + 8001626: 611a str r2, [r3, #16] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8001628: f107 0320 add.w r3, r7, #32 + 800162c: 2200 movs r2, #0 + 800162e: 601a str r2, [r3, #0] + 8001630: 605a str r2, [r3, #4] + 8001632: 609a str r2, [r3, #8] + TIM_OC_InitTypeDef sConfigOC = {0}; + 8001634: 1d3b adds r3, r7, #4 + 8001636: 2200 movs r2, #0 + 8001638: 601a str r2, [r3, #0] + 800163a: 605a str r2, [r3, #4] + 800163c: 609a str r2, [r3, #8] + 800163e: 60da str r2, [r3, #12] + 8001640: 611a str r2, [r3, #16] + 8001642: 615a str r2, [r3, #20] + 8001644: 619a str r2, [r3, #24] + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + 8001646: 4b34 ldr r3, [pc, #208] ; (8001718 ) + 8001648: 4a34 ldr r2, [pc, #208] ; (800171c ) + 800164a: 601a str r2, [r3, #0] + htim3.Init.Prescaler = 0; + 800164c: 4b32 ldr r3, [pc, #200] ; (8001718 ) + 800164e: 2200 movs r2, #0 + 8001650: 605a str r2, [r3, #4] + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001652: 4b31 ldr r3, [pc, #196] ; (8001718 ) + 8001654: 2200 movs r2, #0 + 8001656: 609a str r2, [r3, #8] + htim3.Init.Period = 65535; + 8001658: 4b2f ldr r3, [pc, #188] ; (8001718 ) + 800165a: f64f 72ff movw r2, #65535 ; 0xffff + 800165e: 60da str r2, [r3, #12] + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001660: 4b2d ldr r3, [pc, #180] ; (8001718 ) + 8001662: 2200 movs r2, #0 + 8001664: 611a str r2, [r3, #16] + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001666: 4b2c ldr r3, [pc, #176] ; (8001718 ) + 8001668: 2200 movs r2, #0 + 800166a: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + 800166c: 482a ldr r0, [pc, #168] ; (8001718 ) + 800166e: f007 fb16 bl 8008c9e + 8001672: 4603 mov r3, r0 + 8001674: 2b00 cmp r3, #0 + 8001676: d001 beq.n 800167c + { + Error_Handler(); + 8001678: f000 fc2e bl 8001ed8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 800167c: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001680: 643b str r3, [r7, #64] ; 0x40 + if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) + 8001682: f107 0340 add.w r3, r7, #64 ; 0x40 + 8001686: 4619 mov r1, r3 + 8001688: 4823 ldr r0, [pc, #140] ; (8001718 ) + 800168a: f007 fdc9 bl 8009220 + 800168e: 4603 mov r3, r0 + 8001690: 2b00 cmp r3, #0 + 8001692: d001 beq.n 8001698 + { + Error_Handler(); + 8001694: f000 fc20 bl 8001ed8 + } + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 8001698: 481f ldr r0, [pc, #124] ; (8001718 ) + 800169a: f007 fb55 bl 8008d48 + 800169e: 4603 mov r3, r0 + 80016a0: 2b00 cmp r3, #0 + 80016a2: d001 beq.n 80016a8 + { + Error_Handler(); + 80016a4: f000 fc18 bl 8001ed8 + } + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE; + 80016a8: 2300 movs r3, #0 + 80016aa: 62fb str r3, [r7, #44] ; 0x2c + sSlaveConfig.InputTrigger = TIM_TS_ITR0; + 80016ac: 2300 movs r3, #0 + 80016ae: 633b str r3, [r7, #48] ; 0x30 + if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK) + 80016b0: f107 032c add.w r3, r7, #44 ; 0x2c + 80016b4: 4619 mov r1, r3 + 80016b6: 4818 ldr r0, [pc, #96] ; (8001718 ) + 80016b8: f007 fe6c bl 8009394 + 80016bc: 4603 mov r3, r0 + 80016be: 2b00 cmp r3, #0 + 80016c0: d001 beq.n 80016c6 + { + Error_Handler(); + 80016c2: f000 fc09 bl 8001ed8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 80016c6: 2300 movs r3, #0 + 80016c8: 623b str r3, [r7, #32] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 80016ca: 2300 movs r3, #0 + 80016cc: 62bb str r3, [r7, #40] ; 0x28 + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 80016ce: f107 0320 add.w r3, r7, #32 + 80016d2: 4619 mov r1, r3 + 80016d4: 4810 ldr r0, [pc, #64] ; (8001718 ) + 80016d6: f008 fae7 bl 8009ca8 + 80016da: 4603 mov r3, r0 + 80016dc: 2b00 cmp r3, #0 + 80016de: d001 beq.n 80016e4 + { + Error_Handler(); + 80016e0: f000 fbfa bl 8001ed8 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 80016e4: 2360 movs r3, #96 ; 0x60 + 80016e6: 607b str r3, [r7, #4] + sConfigOC.Pulse = 0; + 80016e8: 2300 movs r3, #0 + 80016ea: 60bb str r3, [r7, #8] + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 80016ec: 2300 movs r3, #0 + 80016ee: 60fb str r3, [r7, #12] + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 80016f0: 2300 movs r3, #0 + 80016f2: 617b str r3, [r7, #20] + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 80016f4: 1d3b adds r3, r7, #4 + 80016f6: 2200 movs r2, #0 + 80016f8: 4619 mov r1, r3 + 80016fa: 4807 ldr r0, [pc, #28] ; (8001718 ) + 80016fc: f007 fc78 bl 8008ff0 + 8001700: 4603 mov r3, r0 + 8001702: 2b00 cmp r3, #0 + 8001704: d001 beq.n 800170a + { + Error_Handler(); + 8001706: f000 fbe7 bl 8001ed8 + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + 800170a: 4803 ldr r0, [pc, #12] ; (8001718 ) + 800170c: f002 fc16 bl 8003f3c + +} + 8001710: bf00 nop + 8001712: 3750 adds r7, #80 ; 0x50 + 8001714: 46bd mov sp, r7 + 8001716: bd80 pop {r7, pc} + 8001718: 20008638 .word 0x20008638 + 800171c: 40000400 .word 0x40000400 + +08001720 : + * @brief TIM5 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM5_Init(void) +{ + 8001720: b580 push {r7, lr} + 8001722: b088 sub sp, #32 + 8001724: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM5_Init 0 */ + + /* USER CODE END TIM5_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 8001726: f107 0310 add.w r3, r7, #16 + 800172a: 2200 movs r2, #0 + 800172c: 601a str r2, [r3, #0] + 800172e: 605a str r2, [r3, #4] + 8001730: 609a str r2, [r3, #8] + 8001732: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 8001734: 1d3b adds r3, r7, #4 + 8001736: 2200 movs r2, #0 + 8001738: 601a str r2, [r3, #0] + 800173a: 605a str r2, [r3, #4] + 800173c: 609a str r2, [r3, #8] + + /* USER CODE BEGIN TIM5_Init 1 */ + + /* USER CODE END TIM5_Init 1 */ + htim5.Instance = TIM5; + 800173e: 4b1d ldr r3, [pc, #116] ; (80017b4 ) + 8001740: 4a1d ldr r2, [pc, #116] ; (80017b8 ) + 8001742: 601a str r2, [r3, #0] + htim5.Init.Prescaler = 0; + 8001744: 4b1b ldr r3, [pc, #108] ; (80017b4 ) + 8001746: 2200 movs r2, #0 + 8001748: 605a str r2, [r3, #4] + htim5.Init.CounterMode = TIM_COUNTERMODE_UP; + 800174a: 4b1a ldr r3, [pc, #104] ; (80017b4 ) + 800174c: 2200 movs r2, #0 + 800174e: 609a str r2, [r3, #8] + htim5.Init.Period = 4294967295; + 8001750: 4b18 ldr r3, [pc, #96] ; (80017b4 ) + 8001752: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8001756: 60da str r2, [r3, #12] + htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001758: 4b16 ldr r3, [pc, #88] ; (80017b4 ) + 800175a: 2200 movs r2, #0 + 800175c: 611a str r2, [r3, #16] + htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 800175e: 4b15 ldr r3, [pc, #84] ; (80017b4 ) + 8001760: 2200 movs r2, #0 + 8001762: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim5) != HAL_OK) + 8001764: 4813 ldr r0, [pc, #76] ; (80017b4 ) + 8001766: f007 fa9a bl 8008c9e + 800176a: 4603 mov r3, r0 + 800176c: 2b00 cmp r3, #0 + 800176e: d001 beq.n 8001774 + { + Error_Handler(); + 8001770: f000 fbb2 bl 8001ed8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8001774: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001778: 613b str r3, [r7, #16] + if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK) + 800177a: f107 0310 add.w r3, r7, #16 + 800177e: 4619 mov r1, r3 + 8001780: 480c ldr r0, [pc, #48] ; (80017b4 ) + 8001782: f007 fd4d bl 8009220 + 8001786: 4603 mov r3, r0 + 8001788: 2b00 cmp r3, #0 + 800178a: d001 beq.n 8001790 + { + Error_Handler(); + 800178c: f000 fba4 bl 8001ed8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001790: 2300 movs r3, #0 + 8001792: 607b str r3, [r7, #4] + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 8001794: 2300 movs r3, #0 + 8001796: 60fb str r3, [r7, #12] + if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK) + 8001798: 1d3b adds r3, r7, #4 + 800179a: 4619 mov r1, r3 + 800179c: 4805 ldr r0, [pc, #20] ; (80017b4 ) + 800179e: f008 fa83 bl 8009ca8 + 80017a2: 4603 mov r3, r0 + 80017a4: 2b00 cmp r3, #0 + 80017a6: d001 beq.n 80017ac + { + Error_Handler(); + 80017a8: f000 fb96 bl 8001ed8 + } + /* USER CODE BEGIN TIM5_Init 2 */ + + /* USER CODE END TIM5_Init 2 */ + +} + 80017ac: bf00 nop + 80017ae: 3720 adds r7, #32 + 80017b0: 46bd mov sp, r7 + 80017b2: bd80 pop {r7, pc} + 80017b4: 200085f8 .word 0x200085f8 + 80017b8: 40000c00 .word 0x40000c00 + +080017bc : + * @brief TIM8 Initialization Function + * @param None + * @retval None + */ +static void MX_TIM8_Init(void) +{ + 80017bc: b580 push {r7, lr} + 80017be: b09a sub sp, #104 ; 0x68 + 80017c0: af00 add r7, sp, #0 + + /* USER CODE BEGIN TIM8_Init 0 */ + + /* USER CODE END TIM8_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + 80017c2: f107 0358 add.w r3, r7, #88 ; 0x58 + 80017c6: 2200 movs r2, #0 + 80017c8: 601a str r2, [r3, #0] + 80017ca: 605a str r2, [r3, #4] + 80017cc: 609a str r2, [r3, #8] + 80017ce: 60da str r2, [r3, #12] + TIM_MasterConfigTypeDef sMasterConfig = {0}; + 80017d0: f107 034c add.w r3, r7, #76 ; 0x4c + 80017d4: 2200 movs r2, #0 + 80017d6: 601a str r2, [r3, #0] + 80017d8: 605a str r2, [r3, #4] + 80017da: 609a str r2, [r3, #8] + TIM_OC_InitTypeDef sConfigOC = {0}; + 80017dc: f107 0330 add.w r3, r7, #48 ; 0x30 + 80017e0: 2200 movs r2, #0 + 80017e2: 601a str r2, [r3, #0] + 80017e4: 605a str r2, [r3, #4] + 80017e6: 609a str r2, [r3, #8] + 80017e8: 60da str r2, [r3, #12] + 80017ea: 611a str r2, [r3, #16] + 80017ec: 615a str r2, [r3, #20] + 80017ee: 619a str r2, [r3, #24] + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; + 80017f0: 1d3b adds r3, r7, #4 + 80017f2: 222c movs r2, #44 ; 0x2c + 80017f4: 2100 movs r1, #0 + 80017f6: 4618 mov r0, r3 + 80017f8: f00a f9e1 bl 800bbbe + + /* USER CODE BEGIN TIM8_Init 1 */ + + /* USER CODE END TIM8_Init 1 */ + htim8.Instance = TIM8; + 80017fc: 4b42 ldr r3, [pc, #264] ; (8001908 ) + 80017fe: 4a43 ldr r2, [pc, #268] ; (800190c ) + 8001800: 601a str r2, [r3, #0] + htim8.Init.Prescaler = 0; + 8001802: 4b41 ldr r3, [pc, #260] ; (8001908 ) + 8001804: 2200 movs r2, #0 + 8001806: 605a str r2, [r3, #4] + htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + 8001808: 4b3f ldr r3, [pc, #252] ; (8001908 ) + 800180a: 2200 movs r2, #0 + 800180c: 609a str r2, [r3, #8] + htim8.Init.Period = 65535; + 800180e: 4b3e ldr r3, [pc, #248] ; (8001908 ) + 8001810: f64f 72ff movw r2, #65535 ; 0xffff + 8001814: 60da str r2, [r3, #12] + htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 8001816: 4b3c ldr r3, [pc, #240] ; (8001908 ) + 8001818: 2200 movs r2, #0 + 800181a: 611a str r2, [r3, #16] + htim8.Init.RepetitionCounter = 0; + 800181c: 4b3a ldr r3, [pc, #232] ; (8001908 ) + 800181e: 2200 movs r2, #0 + 8001820: 615a str r2, [r3, #20] + htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 8001822: 4b39 ldr r3, [pc, #228] ; (8001908 ) + 8001824: 2200 movs r2, #0 + 8001826: 619a str r2, [r3, #24] + if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + 8001828: 4837 ldr r0, [pc, #220] ; (8001908 ) + 800182a: f007 fa38 bl 8008c9e + 800182e: 4603 mov r3, r0 + 8001830: 2b00 cmp r3, #0 + 8001832: d001 beq.n 8001838 + { + Error_Handler(); + 8001834: f000 fb50 bl 8001ed8 + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + 8001838: f44f 5380 mov.w r3, #4096 ; 0x1000 + 800183c: 65bb str r3, [r7, #88] ; 0x58 + if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) + 800183e: f107 0358 add.w r3, r7, #88 ; 0x58 + 8001842: 4619 mov r1, r3 + 8001844: 4830 ldr r0, [pc, #192] ; (8001908 ) + 8001846: f007 fceb bl 8009220 + 800184a: 4603 mov r3, r0 + 800184c: 2b00 cmp r3, #0 + 800184e: d001 beq.n 8001854 + { + Error_Handler(); + 8001850: f000 fb42 bl 8001ed8 + } + if (HAL_TIM_PWM_Init(&htim8) != HAL_OK) + 8001854: 482c ldr r0, [pc, #176] ; (8001908 ) + 8001856: f007 fa77 bl 8008d48 + 800185a: 4603 mov r3, r0 + 800185c: 2b00 cmp r3, #0 + 800185e: d001 beq.n 8001864 + { + Error_Handler(); + 8001860: f000 fb3a bl 8001ed8 + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 8001864: 2300 movs r3, #0 + 8001866: 64fb str r3, [r7, #76] ; 0x4c + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + 8001868: 2300 movs r3, #0 + 800186a: 653b str r3, [r7, #80] ; 0x50 + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 800186c: 2300 movs r3, #0 + 800186e: 657b str r3, [r7, #84] ; 0x54 + if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + 8001870: f107 034c add.w r3, r7, #76 ; 0x4c + 8001874: 4619 mov r1, r3 + 8001876: 4824 ldr r0, [pc, #144] ; (8001908 ) + 8001878: f008 fa16 bl 8009ca8 + 800187c: 4603 mov r3, r0 + 800187e: 2b00 cmp r3, #0 + 8001880: d001 beq.n 8001886 + { + Error_Handler(); + 8001882: f000 fb29 bl 8001ed8 + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + 8001886: 2360 movs r3, #96 ; 0x60 + 8001888: 633b str r3, [r7, #48] ; 0x30 + sConfigOC.Pulse = 0; + 800188a: 2300 movs r3, #0 + 800188c: 637b str r3, [r7, #52] ; 0x34 + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 800188e: 2300 movs r3, #0 + 8001890: 63bb str r3, [r7, #56] ; 0x38 + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 8001892: 2300 movs r3, #0 + 8001894: 643b str r3, [r7, #64] ; 0x40 + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + 8001896: 2300 movs r3, #0 + 8001898: 647b str r3, [r7, #68] ; 0x44 + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 800189a: 2300 movs r3, #0 + 800189c: 64bb str r3, [r7, #72] ; 0x48 + if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 800189e: f107 0330 add.w r3, r7, #48 ; 0x30 + 80018a2: 220c movs r2, #12 + 80018a4: 4619 mov r1, r3 + 80018a6: 4818 ldr r0, [pc, #96] ; (8001908 ) + 80018a8: f007 fba2 bl 8008ff0 + 80018ac: 4603 mov r3, r0 + 80018ae: 2b00 cmp r3, #0 + 80018b0: d001 beq.n 80018b6 + { + Error_Handler(); + 80018b2: f000 fb11 bl 8001ed8 + } + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + 80018b6: 2300 movs r3, #0 + 80018b8: 607b str r3, [r7, #4] + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + 80018ba: 2300 movs r3, #0 + 80018bc: 60bb str r3, [r7, #8] + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + 80018be: 2300 movs r3, #0 + 80018c0: 60fb str r3, [r7, #12] + sBreakDeadTimeConfig.DeadTime = 0; + 80018c2: 2300 movs r3, #0 + 80018c4: 613b str r3, [r7, #16] + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + 80018c6: 2300 movs r3, #0 + 80018c8: 617b str r3, [r7, #20] + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + 80018ca: f44f 5300 mov.w r3, #8192 ; 0x2000 + 80018ce: 61bb str r3, [r7, #24] + sBreakDeadTimeConfig.BreakFilter = 0; + 80018d0: 2300 movs r3, #0 + 80018d2: 61fb str r3, [r7, #28] + sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; + 80018d4: 2300 movs r3, #0 + 80018d6: 623b str r3, [r7, #32] + sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; + 80018d8: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80018dc: 627b str r3, [r7, #36] ; 0x24 + sBreakDeadTimeConfig.Break2Filter = 0; + 80018de: 2300 movs r3, #0 + 80018e0: 62bb str r3, [r7, #40] ; 0x28 + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + 80018e2: 2300 movs r3, #0 + 80018e4: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK) + 80018e6: 1d3b adds r3, r7, #4 + 80018e8: 4619 mov r1, r3 + 80018ea: 4807 ldr r0, [pc, #28] ; (8001908 ) + 80018ec: f008 fa6a bl 8009dc4 + 80018f0: 4603 mov r3, r0 + 80018f2: 2b00 cmp r3, #0 + 80018f4: d001 beq.n 80018fa + { + Error_Handler(); + 80018f6: f000 faef bl 8001ed8 + } + /* USER CODE BEGIN TIM8_Init 2 */ + + /* USER CODE END TIM8_Init 2 */ + HAL_TIM_MspPostInit(&htim8); + 80018fa: 4803 ldr r0, [pc, #12] ; (8001908 ) + 80018fc: f002 fb1e bl 8003f3c + +} + 8001900: bf00 nop + 8001902: 3768 adds r7, #104 ; 0x68 + 8001904: 46bd mov sp, r7 + 8001906: bd80 pop {r7, pc} + 8001908: 2000856c .word 0x2000856c + 800190c: 40010400 .word 0x40010400 + +08001910 : + * @brief UART7 Initialization Function + * @param None + * @retval None + */ +static void MX_UART7_Init(void) +{ + 8001910: b580 push {r7, lr} + 8001912: af00 add r7, sp, #0 + /* USER CODE END UART7_Init 0 */ + + /* USER CODE BEGIN UART7_Init 1 */ + + /* USER CODE END UART7_Init 1 */ + huart7.Instance = UART7; + 8001914: 4b14 ldr r3, [pc, #80] ; (8001968 ) + 8001916: 4a15 ldr r2, [pc, #84] ; (800196c ) + 8001918: 601a str r2, [r3, #0] + huart7.Init.BaudRate = 115200; + 800191a: 4b13 ldr r3, [pc, #76] ; (8001968 ) + 800191c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001920: 605a str r2, [r3, #4] + huart7.Init.WordLength = UART_WORDLENGTH_8B; + 8001922: 4b11 ldr r3, [pc, #68] ; (8001968 ) + 8001924: 2200 movs r2, #0 + 8001926: 609a str r2, [r3, #8] + huart7.Init.StopBits = UART_STOPBITS_1; + 8001928: 4b0f ldr r3, [pc, #60] ; (8001968 ) + 800192a: 2200 movs r2, #0 + 800192c: 60da str r2, [r3, #12] + huart7.Init.Parity = UART_PARITY_NONE; + 800192e: 4b0e ldr r3, [pc, #56] ; (8001968 ) + 8001930: 2200 movs r2, #0 + 8001932: 611a str r2, [r3, #16] + huart7.Init.Mode = UART_MODE_TX_RX; + 8001934: 4b0c ldr r3, [pc, #48] ; (8001968 ) + 8001936: 220c movs r2, #12 + 8001938: 615a str r2, [r3, #20] + huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800193a: 4b0b ldr r3, [pc, #44] ; (8001968 ) + 800193c: 2200 movs r2, #0 + 800193e: 619a str r2, [r3, #24] + huart7.Init.OverSampling = UART_OVERSAMPLING_16; + 8001940: 4b09 ldr r3, [pc, #36] ; (8001968 ) + 8001942: 2200 movs r2, #0 + 8001944: 61da str r2, [r3, #28] + huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8001946: 4b08 ldr r3, [pc, #32] ; (8001968 ) + 8001948: 2200 movs r2, #0 + 800194a: 621a str r2, [r3, #32] + huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 800194c: 4b06 ldr r3, [pc, #24] ; (8001968 ) + 800194e: 2200 movs r2, #0 + 8001950: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart7) != HAL_OK) + 8001952: 4805 ldr r0, [pc, #20] ; (8001968 ) + 8001954: f008 fad2 bl 8009efc + 8001958: 4603 mov r3, r0 + 800195a: 2b00 cmp r3, #0 + 800195c: d001 beq.n 8001962 + { + Error_Handler(); + 800195e: f000 fabb bl 8001ed8 + } + /* USER CODE BEGIN UART7_Init 2 */ + + /* USER CODE END UART7_Init 2 */ + +} + 8001962: bf00 nop + 8001964: bd80 pop {r7, pc} + 8001966: bf00 nop + 8001968: 200084ec .word 0x200084ec + 800196c: 40007800 .word 0x40007800 + +08001970 : + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + 8001970: b580 push {r7, lr} + 8001972: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 8001974: 4b14 ldr r3, [pc, #80] ; (80019c8 ) + 8001976: 4a15 ldr r2, [pc, #84] ; (80019cc ) + 8001978: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 800197a: 4b13 ldr r3, [pc, #76] ; (80019c8 ) + 800197c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001980: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 8001982: 4b11 ldr r3, [pc, #68] ; (80019c8 ) + 8001984: 2200 movs r2, #0 + 8001986: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 8001988: 4b0f ldr r3, [pc, #60] ; (80019c8 ) + 800198a: 2200 movs r2, #0 + 800198c: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 800198e: 4b0e ldr r3, [pc, #56] ; (80019c8 ) + 8001990: 2200 movs r2, #0 + 8001992: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8001994: 4b0c ldr r3, [pc, #48] ; (80019c8 ) + 8001996: 220c movs r2, #12 + 8001998: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800199a: 4b0b ldr r3, [pc, #44] ; (80019c8 ) + 800199c: 2200 movs r2, #0 + 800199e: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 80019a0: 4b09 ldr r3, [pc, #36] ; (80019c8 ) + 80019a2: 2200 movs r2, #0 + 80019a4: 61da str r2, [r3, #28] + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 80019a6: 4b08 ldr r3, [pc, #32] ; (80019c8 ) + 80019a8: 2200 movs r2, #0 + 80019aa: 621a str r2, [r3, #32] + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 80019ac: 4b06 ldr r3, [pc, #24] ; (80019c8 ) + 80019ae: 2200 movs r2, #0 + 80019b0: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart1) != HAL_OK) + 80019b2: 4805 ldr r0, [pc, #20] ; (80019c8 ) + 80019b4: f008 faa2 bl 8009efc + 80019b8: 4603 mov r3, r0 + 80019ba: 2b00 cmp r3, #0 + 80019bc: d001 beq.n 80019c2 + { + Error_Handler(); + 80019be: f000 fa8b bl 8001ed8 + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 80019c2: bf00 nop + 80019c4: bd80 pop {r7, pc} + 80019c6: bf00 nop + 80019c8: 200087b0 .word 0x200087b0 + 80019cc: 40011000 .word 0x40011000 + +080019d0 : + * @brief USART6 Initialization Function + * @param None + * @retval None + */ +static void MX_USART6_UART_Init(void) +{ + 80019d0: b580 push {r7, lr} + 80019d2: af00 add r7, sp, #0 + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + 80019d4: 4b14 ldr r3, [pc, #80] ; (8001a28 ) + 80019d6: 4a15 ldr r2, [pc, #84] ; (8001a2c ) + 80019d8: 601a str r2, [r3, #0] + huart6.Init.BaudRate = 115200; + 80019da: 4b13 ldr r3, [pc, #76] ; (8001a28 ) + 80019dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 80019e0: 605a str r2, [r3, #4] + huart6.Init.WordLength = UART_WORDLENGTH_8B; + 80019e2: 4b11 ldr r3, [pc, #68] ; (8001a28 ) + 80019e4: 2200 movs r2, #0 + 80019e6: 609a str r2, [r3, #8] + huart6.Init.StopBits = UART_STOPBITS_1; + 80019e8: 4b0f ldr r3, [pc, #60] ; (8001a28 ) + 80019ea: 2200 movs r2, #0 + 80019ec: 60da str r2, [r3, #12] + huart6.Init.Parity = UART_PARITY_NONE; + 80019ee: 4b0e ldr r3, [pc, #56] ; (8001a28 ) + 80019f0: 2200 movs r2, #0 + 80019f2: 611a str r2, [r3, #16] + huart6.Init.Mode = UART_MODE_TX_RX; + 80019f4: 4b0c ldr r3, [pc, #48] ; (8001a28 ) + 80019f6: 220c movs r2, #12 + 80019f8: 615a str r2, [r3, #20] + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 80019fa: 4b0b ldr r3, [pc, #44] ; (8001a28 ) + 80019fc: 2200 movs r2, #0 + 80019fe: 619a str r2, [r3, #24] + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + 8001a00: 4b09 ldr r3, [pc, #36] ; (8001a28 ) + 8001a02: 2200 movs r2, #0 + 8001a04: 61da str r2, [r3, #28] + huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 8001a06: 4b08 ldr r3, [pc, #32] ; (8001a28 ) + 8001a08: 2200 movs r2, #0 + 8001a0a: 621a str r2, [r3, #32] + huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8001a0c: 4b06 ldr r3, [pc, #24] ; (8001a28 ) + 8001a0e: 2200 movs r2, #0 + 8001a10: 625a str r2, [r3, #36] ; 0x24 + if (HAL_UART_Init(&huart6) != HAL_OK) + 8001a12: 4805 ldr r0, [pc, #20] ; (8001a28 ) + 8001a14: f008 fa72 bl 8009efc + 8001a18: 4603 mov r3, r0 + 8001a1a: 2b00 cmp r3, #0 + 8001a1c: d001 beq.n 8001a22 + { + Error_Handler(); + 8001a1e: f000 fa5b bl 8001ed8 + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + 8001a22: bf00 nop + 8001a24: bd80 pop {r7, pc} + 8001a26: bf00 nop + 8001a28: 200088a4 .word 0x200088a4 + 8001a2c: 40011400 .word 0x40011400 + +08001a30 : + +/* FMC initialization function */ +static void MX_FMC_Init(void) +{ + 8001a30: b580 push {r7, lr} + 8001a32: b088 sub sp, #32 + 8001a34: af00 add r7, sp, #0 + + /* USER CODE BEGIN FMC_Init 0 */ + + /* USER CODE END FMC_Init 0 */ + + FMC_SDRAM_TimingTypeDef SdramTiming = {0}; + 8001a36: 1d3b adds r3, r7, #4 + 8001a38: 2200 movs r2, #0 + 8001a3a: 601a str r2, [r3, #0] + 8001a3c: 605a str r2, [r3, #4] + 8001a3e: 609a str r2, [r3, #8] + 8001a40: 60da str r2, [r3, #12] + 8001a42: 611a str r2, [r3, #16] + 8001a44: 615a str r2, [r3, #20] + 8001a46: 619a str r2, [r3, #24] + + /* USER CODE END FMC_Init 1 */ + + /** Perform the SDRAM1 memory initialization sequence + */ + hsdram1.Instance = FMC_SDRAM_DEVICE; + 8001a48: 4b1e ldr r3, [pc, #120] ; (8001ac4 ) + 8001a4a: 4a1f ldr r2, [pc, #124] ; (8001ac8 ) + 8001a4c: 601a str r2, [r3, #0] + /* hsdram1.Init */ + hsdram1.Init.SDBank = FMC_SDRAM_BANK1; + 8001a4e: 4b1d ldr r3, [pc, #116] ; (8001ac4 ) + 8001a50: 2200 movs r2, #0 + 8001a52: 605a str r2, [r3, #4] + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + 8001a54: 4b1b ldr r3, [pc, #108] ; (8001ac4 ) + 8001a56: 2200 movs r2, #0 + 8001a58: 609a str r2, [r3, #8] + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + 8001a5a: 4b1a ldr r3, [pc, #104] ; (8001ac4 ) + 8001a5c: 2204 movs r2, #4 + 8001a5e: 60da str r2, [r3, #12] + hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; + 8001a60: 4b18 ldr r3, [pc, #96] ; (8001ac4 ) + 8001a62: 2210 movs r2, #16 + 8001a64: 611a str r2, [r3, #16] + hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + 8001a66: 4b17 ldr r3, [pc, #92] ; (8001ac4 ) + 8001a68: 2240 movs r2, #64 ; 0x40 + 8001a6a: 615a str r2, [r3, #20] + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; + 8001a6c: 4b15 ldr r3, [pc, #84] ; (8001ac4 ) + 8001a6e: 2280 movs r2, #128 ; 0x80 + 8001a70: 619a str r2, [r3, #24] + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + 8001a72: 4b14 ldr r3, [pc, #80] ; (8001ac4 ) + 8001a74: 2200 movs r2, #0 + 8001a76: 61da str r2, [r3, #28] + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; + 8001a78: 4b12 ldr r3, [pc, #72] ; (8001ac4 ) + 8001a7a: 2200 movs r2, #0 + 8001a7c: 621a str r2, [r3, #32] + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; + 8001a7e: 4b11 ldr r3, [pc, #68] ; (8001ac4 ) + 8001a80: 2200 movs r2, #0 + 8001a82: 625a str r2, [r3, #36] ; 0x24 + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + 8001a84: 4b0f ldr r3, [pc, #60] ; (8001ac4 ) + 8001a86: 2200 movs r2, #0 + 8001a88: 629a str r2, [r3, #40] ; 0x28 + /* SdramTiming */ + SdramTiming.LoadToActiveDelay = 16; + 8001a8a: 2310 movs r3, #16 + 8001a8c: 607b str r3, [r7, #4] + SdramTiming.ExitSelfRefreshDelay = 16; + 8001a8e: 2310 movs r3, #16 + 8001a90: 60bb str r3, [r7, #8] + SdramTiming.SelfRefreshTime = 16; + 8001a92: 2310 movs r3, #16 + 8001a94: 60fb str r3, [r7, #12] + SdramTiming.RowCycleDelay = 16; + 8001a96: 2310 movs r3, #16 + 8001a98: 613b str r3, [r7, #16] + SdramTiming.WriteRecoveryTime = 16; + 8001a9a: 2310 movs r3, #16 + 8001a9c: 617b str r3, [r7, #20] + SdramTiming.RPDelay = 16; + 8001a9e: 2310 movs r3, #16 + 8001aa0: 61bb str r3, [r7, #24] + SdramTiming.RCDDelay = 16; + 8001aa2: 2310 movs r3, #16 + 8001aa4: 61fb str r3, [r7, #28] + + if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + 8001aa6: 1d3b adds r3, r7, #4 + 8001aa8: 4619 mov r1, r3 + 8001aaa: 4806 ldr r0, [pc, #24] ; (8001ac4 ) + 8001aac: f006 ffe6 bl 8008a7c + 8001ab0: 4603 mov r3, r0 + 8001ab2: 2b00 cmp r3, #0 + 8001ab4: d001 beq.n 8001aba + { + Error_Handler( ); + 8001ab6: f000 fa0f bl 8001ed8 + } + + /* USER CODE BEGIN FMC_Init 2 */ + + /* USER CODE END FMC_Init 2 */ +} + 8001aba: bf00 nop + 8001abc: 3720 adds r7, #32 + 8001abe: 46bd mov sp, r7 + 8001ac0: bd80 pop {r7, pc} + 8001ac2: bf00 nop + 8001ac4: 200089a4 .word 0x200089a4 + 8001ac8: a0000140 .word 0xa0000140 + +08001acc : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8001acc: b580 push {r7, lr} + 8001ace: b090 sub sp, #64 ; 0x40 + 8001ad0: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001ad2: f107 032c add.w r3, r7, #44 ; 0x2c + 8001ad6: 2200 movs r2, #0 + 8001ad8: 601a str r2, [r3, #0] + 8001ada: 605a str r2, [r3, #4] + 8001adc: 609a str r2, [r3, #8] + 8001ade: 60da str r2, [r3, #12] + 8001ae0: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8001ae2: 4bb0 ldr r3, [pc, #704] ; (8001da4 ) + 8001ae4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001ae6: 4aaf ldr r2, [pc, #700] ; (8001da4 ) + 8001ae8: f043 0310 orr.w r3, r3, #16 + 8001aec: 6313 str r3, [r2, #48] ; 0x30 + 8001aee: 4bad ldr r3, [pc, #692] ; (8001da4 ) + 8001af0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001af2: f003 0310 and.w r3, r3, #16 + 8001af6: 62bb str r3, [r7, #40] ; 0x28 + 8001af8: 6abb ldr r3, [r7, #40] ; 0x28 + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001afa: 4baa ldr r3, [pc, #680] ; (8001da4 ) + 8001afc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001afe: 4aa9 ldr r2, [pc, #676] ; (8001da4 ) + 8001b00: f043 0302 orr.w r3, r3, #2 + 8001b04: 6313 str r3, [r2, #48] ; 0x30 + 8001b06: 4ba7 ldr r3, [pc, #668] ; (8001da4 ) + 8001b08: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b0a: f003 0302 and.w r3, r3, #2 + 8001b0e: 627b str r3, [r7, #36] ; 0x24 + 8001b10: 6a7b ldr r3, [r7, #36] ; 0x24 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001b12: 4ba4 ldr r3, [pc, #656] ; (8001da4 ) + 8001b14: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b16: 4aa3 ldr r2, [pc, #652] ; (8001da4 ) + 8001b18: f043 0301 orr.w r3, r3, #1 + 8001b1c: 6313 str r3, [r2, #48] ; 0x30 + 8001b1e: 4ba1 ldr r3, [pc, #644] ; (8001da4 ) + 8001b20: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b22: f003 0301 and.w r3, r3, #1 + 8001b26: 623b str r3, [r7, #32] + 8001b28: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8001b2a: 4b9e ldr r3, [pc, #632] ; (8001da4 ) + 8001b2c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b2e: 4a9d ldr r2, [pc, #628] ; (8001da4 ) + 8001b30: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8001b34: 6313 str r3, [r2, #48] ; 0x30 + 8001b36: 4b9b ldr r3, [pc, #620] ; (8001da4 ) + 8001b38: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b3a: f003 0340 and.w r3, r3, #64 ; 0x40 + 8001b3e: 61fb str r3, [r7, #28] + 8001b40: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8001b42: 4b98 ldr r3, [pc, #608] ; (8001da4 ) + 8001b44: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b46: 4a97 ldr r2, [pc, #604] ; (8001da4 ) + 8001b48: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8001b4c: 6313 str r3, [r2, #48] ; 0x30 + 8001b4e: 4b95 ldr r3, [pc, #596] ; (8001da4 ) + 8001b50: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b52: f403 7300 and.w r3, r3, #512 ; 0x200 + 8001b56: 61bb str r3, [r7, #24] + 8001b58: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 8001b5a: 4b92 ldr r3, [pc, #584] ; (8001da4 ) + 8001b5c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b5e: 4a91 ldr r2, [pc, #580] ; (8001da4 ) + 8001b60: f043 0308 orr.w r3, r3, #8 + 8001b64: 6313 str r3, [r2, #48] ; 0x30 + 8001b66: 4b8f ldr r3, [pc, #572] ; (8001da4 ) + 8001b68: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b6a: f003 0308 and.w r3, r3, #8 + 8001b6e: 617b str r3, [r7, #20] + 8001b70: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8001b72: 4b8c ldr r3, [pc, #560] ; (8001da4 ) + 8001b74: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b76: 4a8b ldr r2, [pc, #556] ; (8001da4 ) + 8001b78: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8001b7c: 6313 str r3, [r2, #48] ; 0x30 + 8001b7e: 4b89 ldr r3, [pc, #548] ; (8001da4 ) + 8001b80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b82: f403 7380 and.w r3, r3, #256 ; 0x100 + 8001b86: 613b str r3, [r7, #16] + 8001b88: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 8001b8a: 4b86 ldr r3, [pc, #536] ; (8001da4 ) + 8001b8c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b8e: 4a85 ldr r2, [pc, #532] ; (8001da4 ) + 8001b90: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8001b94: 6313 str r3, [r2, #48] ; 0x30 + 8001b96: 4b83 ldr r3, [pc, #524] ; (8001da4 ) + 8001b98: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001b9a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8001b9e: 60fb str r3, [r7, #12] + 8001ba0: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8001ba2: 4b80 ldr r3, [pc, #512] ; (8001da4 ) + 8001ba4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001ba6: 4a7f ldr r2, [pc, #508] ; (8001da4 ) + 8001ba8: f043 0304 orr.w r3, r3, #4 + 8001bac: 6313 str r3, [r2, #48] ; 0x30 + 8001bae: 4b7d ldr r3, [pc, #500] ; (8001da4 ) + 8001bb0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001bb2: f003 0304 and.w r3, r3, #4 + 8001bb6: 60bb str r3, [r7, #8] + 8001bb8: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8001bba: 4b7a ldr r3, [pc, #488] ; (8001da4 ) + 8001bbc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001bbe: 4a79 ldr r2, [pc, #484] ; (8001da4 ) + 8001bc0: f043 0320 orr.w r3, r3, #32 + 8001bc4: 6313 str r3, [r2, #48] ; 0x30 + 8001bc6: 4b77 ldr r3, [pc, #476] ; (8001da4 ) + 8001bc8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001bca: f003 0320 and.w r3, r3, #32 + 8001bce: 607b str r3, [r7, #4] + 8001bd0: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8001bd2: 4b74 ldr r3, [pc, #464] ; (8001da4 ) + 8001bd4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001bd6: 4a73 ldr r2, [pc, #460] ; (8001da4 ) + 8001bd8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001bdc: 6313 str r3, [r2, #48] ; 0x30 + 8001bde: 4b71 ldr r3, [pc, #452] ; (8001da4 ) + 8001be0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001be2: f003 0380 and.w r3, r3, #128 ; 0x80 + 8001be6: 603b str r3, [r7, #0] + 8001be8: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET); + 8001bea: 2200 movs r2, #0 + 8001bec: 2160 movs r1, #96 ; 0x60 + 8001bee: 486e ldr r0, [pc, #440] ; (8001da8 ) + 8001bf0: f004 f94a bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET); + 8001bf4: 2201 movs r2, #1 + 8001bf6: 2120 movs r1, #32 + 8001bf8: 486c ldr r0, [pc, #432] ; (8001dac ) + 8001bfa: f004 f945 bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET); + 8001bfe: 2200 movs r2, #0 + 8001c00: 2108 movs r1, #8 + 8001c02: 486a ldr r0, [pc, #424] ; (8001dac ) + 8001c04: f004 f940 bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET); + 8001c08: 2200 movs r2, #0 + 8001c0a: 2108 movs r1, #8 + 8001c0c: 4868 ldr r0, [pc, #416] ; (8001db0 ) + 8001c0e: f004 f93b bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET); + 8001c12: 2201 movs r2, #1 + 8001c14: 2108 movs r1, #8 + 8001c16: 4867 ldr r0, [pc, #412] ; (8001db4 ) + 8001c18: f004 f936 bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET); + 8001c1c: 2201 movs r2, #1 + 8001c1e: f44f 5180 mov.w r1, #4096 ; 0x1000 + 8001c22: 4863 ldr r0, [pc, #396] ; (8001db0 ) + 8001c24: f004 f930 bl 8005e88 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin + 8001c28: 2200 movs r2, #0 + 8001c2a: f645 6140 movw r1, #24128 ; 0x5e40 + 8001c2e: 4862 ldr r0, [pc, #392] ; (8001db8 ) + 8001c30: f004 f92a bl 8005e88 + |LED2_Pin|LED18_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET); + 8001c34: 2200 movs r2, #0 + 8001c36: 2108 movs r1, #8 + 8001c38: 4860 ldr r0, [pc, #384] ; (8001dbc ) + 8001c3a: f004 f925 bl 8005e88 + + /*Configure GPIO pin : PE3 */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + 8001c3e: 2308 movs r3, #8 + 8001c40: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001c42: 2300 movs r3, #0 + 8001c44: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001c46: 2300 movs r3, #0 + 8001c48: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8001c4a: f107 032c add.w r3, r7, #44 ; 0x2c + 8001c4e: 4619 mov r1, r3 + 8001c50: 4855 ldr r0, [pc, #340] ; (8001da8 ) + 8001c52: f003 fe4d bl 80058f0 + + /*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin + ULPI_D1_Pin ULPI_D4_Pin */ + GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin + 8001c56: f643 0323 movw r3, #14371 ; 0x3823 + 8001c5a: 62fb str r3, [r7, #44] ; 0x2c + |ULPI_D1_Pin|ULPI_D4_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001c5c: 2302 movs r3, #2 + 8001c5e: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001c60: 2300 movs r3, #0 + 8001c62: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001c64: 2303 movs r3, #3 + 8001c66: 63bb str r3, [r7, #56] ; 0x38 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + 8001c68: 230a movs r3, #10 + 8001c6a: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001c6c: f107 032c add.w r3, r7, #44 ; 0x2c + 8001c70: 4619 mov r1, r3 + 8001c72: 4853 ldr r0, [pc, #332] ; (8001dc0 ) + 8001c74: f003 fe3c bl 80058f0 + + /*Configure GPIO pins : BP2_Pin BP1_Pin */ + GPIO_InitStruct.Pin = BP2_Pin|BP1_Pin; + 8001c78: f44f 4301 mov.w r3, #33024 ; 0x8100 + 8001c7c: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001c7e: 2300 movs r3, #0 + 8001c80: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001c82: 2300 movs r3, #0 + 8001c84: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001c86: f107 032c add.w r3, r7, #44 ; 0x2c + 8001c8a: 4619 mov r1, r3 + 8001c8c: 484d ldr r0, [pc, #308] ; (8001dc4 ) + 8001c8e: f003 fe2f bl 80058f0 + + /*Configure GPIO pins : LED14_Pin LED15_Pin */ + GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin; + 8001c92: 2360 movs r3, #96 ; 0x60 + 8001c94: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001c96: 2301 movs r3, #1 + 8001c98: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001c9a: 2300 movs r3, #0 + 8001c9c: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001c9e: 2300 movs r3, #0 + 8001ca0: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 8001ca2: f107 032c add.w r3, r7, #44 ; 0x2c + 8001ca6: 4619 mov r1, r3 + 8001ca8: 483f ldr r0, [pc, #252] ; (8001da8 ) + 8001caa: f003 fe21 bl 80058f0 + + /*Configure GPIO pin : OTG_FS_VBUS_Pin */ + GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin; + 8001cae: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001cb2: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001cb4: 2300 movs r3, #0 + 8001cb6: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001cb8: 2300 movs r3, #0 + 8001cba: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct); + 8001cbc: f107 032c add.w r3, r7, #44 ; 0x2c + 8001cc0: 4619 mov r1, r3 + 8001cc2: 4841 ldr r0, [pc, #260] ; (8001dc8 ) + 8001cc4: f003 fe14 bl 80058f0 + + /*Configure GPIO pin : Audio_INT_Pin */ + GPIO_InitStruct.Pin = Audio_INT_Pin; + 8001cc8: 2340 movs r3, #64 ; 0x40 + 8001cca: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + 8001ccc: 4b3f ldr r3, [pc, #252] ; (8001dcc ) + 8001cce: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001cd0: 2300 movs r3, #0 + 8001cd2: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct); + 8001cd4: f107 032c add.w r3, r7, #44 ; 0x2c + 8001cd8: 4619 mov r1, r3 + 8001cda: 4834 ldr r0, [pc, #208] ; (8001dac ) + 8001cdc: f003 fe08 bl 80058f0 + + /*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */ + GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin; + 8001ce0: 2328 movs r3, #40 ; 0x28 + 8001ce2: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001ce4: 2301 movs r3, #1 + 8001ce6: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001ce8: 2300 movs r3, #0 + 8001cea: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001cec: 2300 movs r3, #0 + 8001cee: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8001cf0: f107 032c add.w r3, r7, #44 ; 0x2c + 8001cf4: 4619 mov r1, r3 + 8001cf6: 482d ldr r0, [pc, #180] ; (8001dac ) + 8001cf8: f003 fdfa bl 80058f0 + + /*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */ + GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin; + 8001cfc: f241 0308 movw r3, #4104 ; 0x1008 + 8001d00: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001d02: 2301 movs r3, #1 + 8001d04: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d06: 2300 movs r3, #0 + 8001d08: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001d0a: 2300 movs r3, #0 + 8001d0c: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8001d0e: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d12: 4619 mov r1, r3 + 8001d14: 4826 ldr r0, [pc, #152] ; (8001db0 ) + 8001d16: f003 fdeb bl 80058f0 + + /*Configure GPIO pin : uSD_Detect_Pin */ + GPIO_InitStruct.Pin = uSD_Detect_Pin; + 8001d1a: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001d1e: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001d20: 2300 movs r3, #0 + 8001d22: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d24: 2300 movs r3, #0 + 8001d26: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct); + 8001d28: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d2c: 4619 mov r1, r3 + 8001d2e: 4828 ldr r0, [pc, #160] ; (8001dd0 ) + 8001d30: f003 fdde bl 80058f0 + + /*Configure GPIO pin : LCD_BL_CTRL_Pin */ + GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin; + 8001d34: 2308 movs r3, #8 + 8001d36: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001d38: 2301 movs r3, #1 + 8001d3a: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d3c: 2300 movs r3, #0 + 8001d3e: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001d40: 2300 movs r3, #0 + 8001d42: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct); + 8001d44: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d48: 4619 mov r1, r3 + 8001d4a: 481a ldr r0, [pc, #104] ; (8001db4 ) + 8001d4c: f003 fdd0 bl 80058f0 + + /*Configure GPIO pin : OTG_FS_OverCurrent_Pin */ + GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin; + 8001d50: 2310 movs r3, #16 + 8001d52: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001d54: 2300 movs r3, #0 + 8001d56: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d58: 2300 movs r3, #0 + 8001d5a: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct); + 8001d5c: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d60: 4619 mov r1, r3 + 8001d62: 4812 ldr r0, [pc, #72] ; (8001dac ) + 8001d64: f003 fdc4 bl 80058f0 + + /*Configure GPIO pins : TP3_Pin NC2_Pin */ + GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin; + 8001d68: f248 0304 movw r3, #32772 ; 0x8004 + 8001d6c: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001d6e: 2300 movs r3, #0 + 8001d70: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d72: 2300 movs r3, #0 + 8001d74: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8001d76: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d7a: 4619 mov r1, r3 + 8001d7c: 480e ldr r0, [pc, #56] ; (8001db8 ) + 8001d7e: f003 fdb7 bl 80058f0 + + /*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin + LED2_Pin LED18_Pin */ + GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin + 8001d82: f645 6340 movw r3, #24128 ; 0x5e40 + 8001d86: 62fb str r3, [r7, #44] ; 0x2c + |LED2_Pin|LED18_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001d88: 2301 movs r3, #1 + 8001d8a: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d8c: 2300 movs r3, #0 + 8001d8e: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001d90: 2300 movs r3, #0 + 8001d92: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8001d94: f107 032c add.w r3, r7, #44 ; 0x2c + 8001d98: 4619 mov r1, r3 + 8001d9a: 4807 ldr r0, [pc, #28] ; (8001db8 ) + 8001d9c: f003 fda8 bl 80058f0 + 8001da0: e018 b.n 8001dd4 + 8001da2: bf00 nop + 8001da4: 40023800 .word 0x40023800 + 8001da8: 40021000 .word 0x40021000 + 8001dac: 40020c00 .word 0x40020c00 + 8001db0: 40022000 .word 0x40022000 + 8001db4: 40022800 .word 0x40022800 + 8001db8: 40021c00 .word 0x40021c00 + 8001dbc: 40021800 .word 0x40021800 + 8001dc0: 40020400 .word 0x40020400 + 8001dc4: 40020000 .word 0x40020000 + 8001dc8: 40022400 .word 0x40022400 + 8001dcc: 10120000 .word 0x10120000 + 8001dd0: 40020800 .word 0x40020800 + + /*Configure GPIO pin : LCD_INT_Pin */ + GPIO_InitStruct.Pin = LCD_INT_Pin; + 8001dd4: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001dd8: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; + 8001dda: 4b2c ldr r3, [pc, #176] ; (8001e8c ) + 8001ddc: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001dde: 2300 movs r3, #0 + 8001de0: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct); + 8001de2: f107 032c add.w r3, r7, #44 ; 0x2c + 8001de6: 4619 mov r1, r3 + 8001de8: 4829 ldr r0, [pc, #164] ; (8001e90 ) + 8001dea: f003 fd81 bl 80058f0 + + /*Configure GPIO pin : ULPI_NXT_Pin */ + GPIO_InitStruct.Pin = ULPI_NXT_Pin; + 8001dee: 2310 movs r3, #16 + 8001df0: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001df2: 2302 movs r3, #2 + 8001df4: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001df6: 2300 movs r3, #0 + 8001df8: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001dfa: 2303 movs r3, #3 + 8001dfc: 63bb str r3, [r7, #56] ; 0x38 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + 8001dfe: 230a movs r3, #10 + 8001e00: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct); + 8001e02: f107 032c add.w r3, r7, #44 ; 0x2c + 8001e06: 4619 mov r1, r3 + 8001e08: 4822 ldr r0, [pc, #136] ; (8001e94 ) + 8001e0a: f003 fd71 bl 80058f0 + + /*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */ + GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin; + 8001e0e: 2384 movs r3, #132 ; 0x84 + 8001e10: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8001e12: 2300 movs r3, #0 + 8001e14: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001e16: 2300 movs r3, #0 + 8001e18: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 8001e1a: f107 032c add.w r3, r7, #44 ; 0x2c + 8001e1e: 4619 mov r1, r3 + 8001e20: 481d ldr r0, [pc, #116] ; (8001e98 ) + 8001e22: f003 fd65 bl 80058f0 + + /*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */ + GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin; + 8001e26: 2305 movs r3, #5 + 8001e28: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001e2a: 2302 movs r3, #2 + 8001e2c: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001e2e: 2300 movs r3, #0 + 8001e30: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001e32: 2303 movs r3, #3 + 8001e34: 63bb str r3, [r7, #56] ; 0x38 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + 8001e36: 230a movs r3, #10 + 8001e38: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8001e3a: f107 032c add.w r3, r7, #44 ; 0x2c + 8001e3e: 4619 mov r1, r3 + 8001e40: 4816 ldr r0, [pc, #88] ; (8001e9c ) + 8001e42: f003 fd55 bl 80058f0 + + /*Configure GPIO pin : EXT_RST_Pin */ + GPIO_InitStruct.Pin = EXT_RST_Pin; + 8001e46: 2308 movs r3, #8 + 8001e48: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001e4a: 2301 movs r3, #1 + 8001e4c: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001e4e: 2300 movs r3, #0 + 8001e50: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001e52: 2300 movs r3, #0 + 8001e54: 63bb str r3, [r7, #56] ; 0x38 + HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct); + 8001e56: f107 032c add.w r3, r7, #44 ; 0x2c + 8001e5a: 4619 mov r1, r3 + 8001e5c: 480e ldr r0, [pc, #56] ; (8001e98 ) + 8001e5e: f003 fd47 bl 80058f0 + + /*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */ + GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin; + 8001e62: 2328 movs r3, #40 ; 0x28 + 8001e64: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001e66: 2302 movs r3, #2 + 8001e68: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001e6a: 2300 movs r3, #0 + 8001e6c: 637b str r3, [r7, #52] ; 0x34 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001e6e: 2303 movs r3, #3 + 8001e70: 63bb str r3, [r7, #56] ; 0x38 + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + 8001e72: 230a movs r3, #10 + 8001e74: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001e76: f107 032c add.w r3, r7, #44 ; 0x2c + 8001e7a: 4619 mov r1, r3 + 8001e7c: 4808 ldr r0, [pc, #32] ; (8001ea0 ) + 8001e7e: f003 fd37 bl 80058f0 + +} + 8001e82: bf00 nop + 8001e84: 3740 adds r7, #64 ; 0x40 + 8001e86: 46bd mov sp, r7 + 8001e88: bd80 pop {r7, pc} + 8001e8a: bf00 nop + 8001e8c: 10120000 .word 0x10120000 + 8001e90: 40022000 .word 0x40022000 + 8001e94: 40021c00 .word 0x40021c00 + 8001e98: 40021800 .word 0x40021800 + 8001e9c: 40020800 .word 0x40020800 + 8001ea0: 40020000 .word 0x40020000 + +08001ea4 : + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void const * argument) +{ + 8001ea4: b580 push {r7, lr} + 8001ea6: b082 sub sp, #8 + 8001ea8: af00 add r7, sp, #0 + 8001eaa: 6078 str r0, [r7, #4] + /* USER CODE BEGIN 5 */ + /* Infinite loop */ + for(;;) + { + osDelay(1); + 8001eac: 2001 movs r0, #1 + 8001eae: f008 fdf3 bl 800aa98 + 8001eb2: e7fb b.n 8001eac + +08001eb4 : + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8001eb4: b580 push {r7, lr} + 8001eb6: b082 sub sp, #8 + 8001eb8: af00 add r7, sp, #0 + 8001eba: 6078 str r0, [r7, #4] + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + 8001ebc: 687b ldr r3, [r7, #4] + 8001ebe: 681b ldr r3, [r3, #0] + 8001ec0: 4a04 ldr r2, [pc, #16] ; (8001ed4 ) + 8001ec2: 4293 cmp r3, r2 + 8001ec4: d101 bne.n 8001eca + HAL_IncTick(); + 8001ec6: f002 faff bl 80044c8 + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + 8001eca: bf00 nop + 8001ecc: 3708 adds r7, #8 + 8001ece: 46bd mov sp, r7 + 8001ed0: bd80 pop {r7, pc} + 8001ed2: bf00 nop + 8001ed4: 40001000 .word 0x40001000 + +08001ed8 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8001ed8: b480 push {r7} + 8001eda: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8001edc: b672 cpsid i + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8001ede: e7fe b.n 8001ede + +08001ee0 : + * @brief Initializes I2C MSP. + * @param i2c_handler : I2C handler + * @retval None + */ +static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler) +{ + 8001ee0: b580 push {r7, lr} + 8001ee2: b08c sub sp, #48 ; 0x30 + 8001ee4: af00 add r7, sp, #0 + 8001ee6: 6078 str r0, [r7, #4] + GPIO_InitTypeDef gpio_init_structure; + + if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler)) + 8001ee8: 687b ldr r3, [r7, #4] + 8001eea: 4a51 ldr r2, [pc, #324] ; (8002030 ) + 8001eec: 4293 cmp r3, r2 + 8001eee: d14d bne.n 8001f8c + { + /* AUDIO and LCD I2C MSP init */ + + /*** Configure the GPIOs ***/ + /* Enable GPIO clock */ + DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE(); + 8001ef0: 4b50 ldr r3, [pc, #320] ; (8002034 ) + 8001ef2: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001ef4: 4a4f ldr r2, [pc, #316] ; (8002034 ) + 8001ef6: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001efa: 6313 str r3, [r2, #48] ; 0x30 + 8001efc: 4b4d ldr r3, [pc, #308] ; (8002034 ) + 8001efe: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001f00: f003 0380 and.w r3, r3, #128 ; 0x80 + 8001f04: 61bb str r3, [r7, #24] + 8001f06: 69bb ldr r3, [r7, #24] + + /* Configure I2C Tx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN; + 8001f08: 2380 movs r3, #128 ; 0x80 + 8001f0a: 61fb str r3, [r7, #28] + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + 8001f0c: 2312 movs r3, #18 + 8001f0e: 623b str r3, [r7, #32] + gpio_init_structure.Pull = GPIO_NOPULL; + 8001f10: 2300 movs r3, #0 + 8001f12: 627b str r3, [r7, #36] ; 0x24 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 8001f14: 2302 movs r3, #2 + 8001f16: 62bb str r3, [r7, #40] ; 0x28 + gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF; + 8001f18: 2304 movs r3, #4 + 8001f1a: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + 8001f1c: f107 031c add.w r3, r7, #28 + 8001f20: 4619 mov r1, r3 + 8001f22: 4845 ldr r0, [pc, #276] ; (8002038 ) + 8001f24: f003 fce4 bl 80058f0 + + /* Configure I2C Rx as alternate function */ + gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN; + 8001f28: f44f 7380 mov.w r3, #256 ; 0x100 + 8001f2c: 61fb str r3, [r7, #28] + HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + 8001f2e: f107 031c add.w r3, r7, #28 + 8001f32: 4619 mov r1, r3 + 8001f34: 4840 ldr r0, [pc, #256] ; (8002038 ) + 8001f36: f003 fcdb bl 80058f0 + + /*** Configure the I2C peripheral ***/ + /* Enable I2C clock */ + DISCOVERY_AUDIO_I2Cx_CLK_ENABLE(); + 8001f3a: 4b3e ldr r3, [pc, #248] ; (8002034 ) + 8001f3c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001f3e: 4a3d ldr r2, [pc, #244] ; (8002034 ) + 8001f40: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8001f44: 6413 str r3, [r2, #64] ; 0x40 + 8001f46: 4b3b ldr r3, [pc, #236] ; (8002034 ) + 8001f48: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001f4a: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8001f4e: 617b str r3, [r7, #20] + 8001f50: 697b ldr r3, [r7, #20] + + /* Force the I2C peripheral clock reset */ + DISCOVERY_AUDIO_I2Cx_FORCE_RESET(); + 8001f52: 4b38 ldr r3, [pc, #224] ; (8002034 ) + 8001f54: 6a1b ldr r3, [r3, #32] + 8001f56: 4a37 ldr r2, [pc, #220] ; (8002034 ) + 8001f58: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8001f5c: 6213 str r3, [r2, #32] + + /* Release the I2C peripheral clock reset */ + DISCOVERY_AUDIO_I2Cx_RELEASE_RESET(); + 8001f5e: 4b35 ldr r3, [pc, #212] ; (8002034 ) + 8001f60: 6a1b ldr r3, [r3, #32] + 8001f62: 4a34 ldr r2, [pc, #208] ; (8002034 ) + 8001f64: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8001f68: 6213 str r3, [r2, #32] + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0); + 8001f6a: 2200 movs r2, #0 + 8001f6c: 210f movs r1, #15 + 8001f6e: 2048 movs r0, #72 ; 0x48 + 8001f70: f002 ff7e bl 8004e70 + HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn); + 8001f74: 2048 movs r0, #72 ; 0x48 + 8001f76: f002 ff97 bl 8004ea8 + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0); + 8001f7a: 2200 movs r2, #0 + 8001f7c: 210f movs r1, #15 + 8001f7e: 2049 movs r0, #73 ; 0x49 + 8001f80: f002 ff76 bl 8004e70 + HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn); + 8001f84: 2049 movs r0, #73 ; 0x49 + 8001f86: f002 ff8f bl 8004ea8 + + /* Enable and set I2Cx Interrupt to a lower priority */ + HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0); + HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn); + } +} + 8001f8a: e04d b.n 8002028 + DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE(); + 8001f8c: 4b29 ldr r3, [pc, #164] ; (8002034 ) + 8001f8e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001f90: 4a28 ldr r2, [pc, #160] ; (8002034 ) + 8001f92: f043 0302 orr.w r3, r3, #2 + 8001f96: 6313 str r3, [r2, #48] ; 0x30 + 8001f98: 4b26 ldr r3, [pc, #152] ; (8002034 ) + 8001f9a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001f9c: f003 0302 and.w r3, r3, #2 + 8001fa0: 613b str r3, [r7, #16] + 8001fa2: 693b ldr r3, [r7, #16] + gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN; + 8001fa4: f44f 7380 mov.w r3, #256 ; 0x100 + 8001fa8: 61fb str r3, [r7, #28] + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + 8001faa: 2312 movs r3, #18 + 8001fac: 623b str r3, [r7, #32] + gpio_init_structure.Pull = GPIO_NOPULL; + 8001fae: 2300 movs r3, #0 + 8001fb0: 627b str r3, [r7, #36] ; 0x24 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 8001fb2: 2302 movs r3, #2 + 8001fb4: 62bb str r3, [r7, #40] ; 0x28 + gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF; + 8001fb6: 2304 movs r3, #4 + 8001fb8: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + 8001fba: f107 031c add.w r3, r7, #28 + 8001fbe: 4619 mov r1, r3 + 8001fc0: 481e ldr r0, [pc, #120] ; (800203c ) + 8001fc2: f003 fc95 bl 80058f0 + gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN; + 8001fc6: f44f 7300 mov.w r3, #512 ; 0x200 + 8001fca: 61fb str r3, [r7, #28] + HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure); + 8001fcc: f107 031c add.w r3, r7, #28 + 8001fd0: 4619 mov r1, r3 + 8001fd2: 481a ldr r0, [pc, #104] ; (800203c ) + 8001fd4: f003 fc8c bl 80058f0 + DISCOVERY_EXT_I2Cx_CLK_ENABLE(); + 8001fd8: 4b16 ldr r3, [pc, #88] ; (8002034 ) + 8001fda: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001fdc: 4a15 ldr r2, [pc, #84] ; (8002034 ) + 8001fde: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8001fe2: 6413 str r3, [r2, #64] ; 0x40 + 8001fe4: 4b13 ldr r3, [pc, #76] ; (8002034 ) + 8001fe6: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001fe8: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001fec: 60fb str r3, [r7, #12] + 8001fee: 68fb ldr r3, [r7, #12] + DISCOVERY_EXT_I2Cx_FORCE_RESET(); + 8001ff0: 4b10 ldr r3, [pc, #64] ; (8002034 ) + 8001ff2: 6a1b ldr r3, [r3, #32] + 8001ff4: 4a0f ldr r2, [pc, #60] ; (8002034 ) + 8001ff6: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8001ffa: 6213 str r3, [r2, #32] + DISCOVERY_EXT_I2Cx_RELEASE_RESET(); + 8001ffc: 4b0d ldr r3, [pc, #52] ; (8002034 ) + 8001ffe: 6a1b ldr r3, [r3, #32] + 8002000: 4a0c ldr r2, [pc, #48] ; (8002034 ) + 8002002: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 8002006: 6213 str r3, [r2, #32] + HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0); + 8002008: 2200 movs r2, #0 + 800200a: 210f movs r1, #15 + 800200c: 201f movs r0, #31 + 800200e: f002 ff2f bl 8004e70 + HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn); + 8002012: 201f movs r0, #31 + 8002014: f002 ff48 bl 8004ea8 + HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0); + 8002018: 2200 movs r2, #0 + 800201a: 210f movs r1, #15 + 800201c: 2020 movs r0, #32 + 800201e: f002 ff27 bl 8004e70 + HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn); + 8002022: 2020 movs r0, #32 + 8002024: f002 ff40 bl 8004ea8 +} + 8002028: bf00 nop + 800202a: 3730 adds r7, #48 ; 0x30 + 800202c: 46bd mov sp, r7 + 800202e: bd80 pop {r7, pc} + 8002030: 20000100 .word 0x20000100 + 8002034: 40023800 .word 0x40023800 + 8002038: 40021c00 .word 0x40021c00 + 800203c: 40020400 .word 0x40020400 + +08002040 : + * @brief Initializes I2C HAL. + * @param i2c_handler : I2C handler + * @retval None + */ +static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler) +{ + 8002040: b580 push {r7, lr} + 8002042: b082 sub sp, #8 + 8002044: af00 add r7, sp, #0 + 8002046: 6078 str r0, [r7, #4] + if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET) + 8002048: 6878 ldr r0, [r7, #4] + 800204a: f004 fa25 bl 8006498 + 800204e: 4603 mov r3, r0 + 8002050: 2b00 cmp r3, #0 + 8002052: d125 bne.n 80020a0 + { + if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler)) + 8002054: 687b ldr r3, [r7, #4] + 8002056: 4a14 ldr r2, [pc, #80] ; (80020a8 ) + 8002058: 4293 cmp r3, r2 + 800205a: d103 bne.n 8002064 + { + /* Audio and LCD I2C configuration */ + i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx; + 800205c: 687b ldr r3, [r7, #4] + 800205e: 4a13 ldr r2, [pc, #76] ; (80020ac ) + 8002060: 601a str r2, [r3, #0] + 8002062: e002 b.n 800206a + } + else + { + /* External, camera and Arduino connector I2C configuration */ + i2c_handler->Instance = DISCOVERY_EXT_I2Cx; + 8002064: 687b ldr r3, [r7, #4] + 8002066: 4a12 ldr r2, [pc, #72] ; (80020b0 ) + 8002068: 601a str r2, [r3, #0] + } + i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING; + 800206a: 687b ldr r3, [r7, #4] + 800206c: 4a11 ldr r2, [pc, #68] ; (80020b4 ) + 800206e: 605a str r2, [r3, #4] + i2c_handler->Init.OwnAddress1 = 0; + 8002070: 687b ldr r3, [r7, #4] + 8002072: 2200 movs r2, #0 + 8002074: 609a str r2, [r3, #8] + i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8002076: 687b ldr r3, [r7, #4] + 8002078: 2201 movs r2, #1 + 800207a: 60da str r2, [r3, #12] + i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 800207c: 687b ldr r3, [r7, #4] + 800207e: 2200 movs r2, #0 + 8002080: 611a str r2, [r3, #16] + i2c_handler->Init.OwnAddress2 = 0; + 8002082: 687b ldr r3, [r7, #4] + 8002084: 2200 movs r2, #0 + 8002086: 615a str r2, [r3, #20] + i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8002088: 687b ldr r3, [r7, #4] + 800208a: 2200 movs r2, #0 + 800208c: 61da str r2, [r3, #28] + i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 800208e: 687b ldr r3, [r7, #4] + 8002090: 2200 movs r2, #0 + 8002092: 621a str r2, [r3, #32] + + /* Init the I2C */ + I2Cx_MspInit(i2c_handler); + 8002094: 6878 ldr r0, [r7, #4] + 8002096: f7ff ff23 bl 8001ee0 + HAL_I2C_Init(i2c_handler); + 800209a: 6878 ldr r0, [r7, #4] + 800209c: f003 ff0e bl 8005ebc + } +} + 80020a0: bf00 nop + 80020a2: 3708 adds r7, #8 + 80020a4: 46bd mov sp, r7 + 80020a6: bd80 pop {r7, pc} + 80020a8: 20000100 .word 0x20000100 + 80020ac: 40005c00 .word 0x40005c00 + 80020b0: 40005400 .word 0x40005400 + 80020b4: 40912732 .word 0x40912732 + +080020b8 : + uint8_t Addr, + uint16_t Reg, + uint16_t MemAddress, + uint8_t *Buffer, + uint16_t Length) +{ + 80020b8: b580 push {r7, lr} + 80020ba: b08a sub sp, #40 ; 0x28 + 80020bc: af04 add r7, sp, #16 + 80020be: 60f8 str r0, [r7, #12] + 80020c0: 4608 mov r0, r1 + 80020c2: 4611 mov r1, r2 + 80020c4: 461a mov r2, r3 + 80020c6: 4603 mov r3, r0 + 80020c8: 72fb strb r3, [r7, #11] + 80020ca: 460b mov r3, r1 + 80020cc: 813b strh r3, [r7, #8] + 80020ce: 4613 mov r3, r2 + 80020d0: 80fb strh r3, [r7, #6] + HAL_StatusTypeDef status = HAL_OK; + 80020d2: 2300 movs r3, #0 + 80020d4: 75fb strb r3, [r7, #23] + + status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000); + 80020d6: 7afb ldrb r3, [r7, #11] + 80020d8: b299 uxth r1, r3 + 80020da: 88f8 ldrh r0, [r7, #6] + 80020dc: 893a ldrh r2, [r7, #8] + 80020de: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80020e2: 9302 str r3, [sp, #8] + 80020e4: 8cbb ldrh r3, [r7, #36] ; 0x24 + 80020e6: 9301 str r3, [sp, #4] + 80020e8: 6a3b ldr r3, [r7, #32] + 80020ea: 9300 str r3, [sp, #0] + 80020ec: 4603 mov r3, r0 + 80020ee: 68f8 ldr r0, [r7, #12] + 80020f0: f004 f8b8 bl 8006264 + 80020f4: 4603 mov r3, r0 + 80020f6: 75fb strb r3, [r7, #23] + + /* Check the communication status */ + if(status != HAL_OK) + 80020f8: 7dfb ldrb r3, [r7, #23] + 80020fa: 2b00 cmp r3, #0 + 80020fc: d004 beq.n 8002108 + { + /* I2C error occurred */ + I2Cx_Error(i2c_handler, Addr); + 80020fe: 7afb ldrb r3, [r7, #11] + 8002100: 4619 mov r1, r3 + 8002102: 68f8 ldr r0, [r7, #12] + 8002104: f000 f832 bl 800216c + } + return status; + 8002108: 7dfb ldrb r3, [r7, #23] +} + 800210a: 4618 mov r0, r3 + 800210c: 3718 adds r7, #24 + 800210e: 46bd mov sp, r7 + 8002110: bd80 pop {r7, pc} + +08002112 : + uint8_t Addr, + uint16_t Reg, + uint16_t MemAddress, + uint8_t *Buffer, + uint16_t Length) +{ + 8002112: b580 push {r7, lr} + 8002114: b08a sub sp, #40 ; 0x28 + 8002116: af04 add r7, sp, #16 + 8002118: 60f8 str r0, [r7, #12] + 800211a: 4608 mov r0, r1 + 800211c: 4611 mov r1, r2 + 800211e: 461a mov r2, r3 + 8002120: 4603 mov r3, r0 + 8002122: 72fb strb r3, [r7, #11] + 8002124: 460b mov r3, r1 + 8002126: 813b strh r3, [r7, #8] + 8002128: 4613 mov r3, r2 + 800212a: 80fb strh r3, [r7, #6] + HAL_StatusTypeDef status = HAL_OK; + 800212c: 2300 movs r3, #0 + 800212e: 75fb strb r3, [r7, #23] + + status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000); + 8002130: 7afb ldrb r3, [r7, #11] + 8002132: b299 uxth r1, r3 + 8002134: 88f8 ldrh r0, [r7, #6] + 8002136: 893a ldrh r2, [r7, #8] + 8002138: f44f 737a mov.w r3, #1000 ; 0x3e8 + 800213c: 9302 str r3, [sp, #8] + 800213e: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8002140: 9301 str r3, [sp, #4] + 8002142: 6a3b ldr r3, [r7, #32] + 8002144: 9300 str r3, [sp, #0] + 8002146: 4603 mov r3, r0 + 8002148: 68f8 ldr r0, [r7, #12] + 800214a: f003 ff77 bl 800603c + 800214e: 4603 mov r3, r0 + 8002150: 75fb strb r3, [r7, #23] + + /* Check the communication status */ + if(status != HAL_OK) + 8002152: 7dfb ldrb r3, [r7, #23] + 8002154: 2b00 cmp r3, #0 + 8002156: d004 beq.n 8002162 + { + /* Re-Initiaize the I2C Bus */ + I2Cx_Error(i2c_handler, Addr); + 8002158: 7afb ldrb r3, [r7, #11] + 800215a: 4619 mov r1, r3 + 800215c: 68f8 ldr r0, [r7, #12] + 800215e: f000 f805 bl 800216c + } + return status; + 8002162: 7dfb ldrb r3, [r7, #23] +} + 8002164: 4618 mov r0, r3 + 8002166: 3718 adds r7, #24 + 8002168: 46bd mov sp, r7 + 800216a: bd80 pop {r7, pc} + +0800216c : + * @param i2c_handler : I2C handler + * @param Addr: I2C Address + * @retval None + */ +static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr) +{ + 800216c: b580 push {r7, lr} + 800216e: b082 sub sp, #8 + 8002170: af00 add r7, sp, #0 + 8002172: 6078 str r0, [r7, #4] + 8002174: 460b mov r3, r1 + 8002176: 70fb strb r3, [r7, #3] + /* De-initialize the I2C communication bus */ + HAL_I2C_DeInit(i2c_handler); + 8002178: 6878 ldr r0, [r7, #4] + 800217a: f003 ff2f bl 8005fdc + + /* Re-Initialize the I2C communication bus */ + I2Cx_Init(i2c_handler); + 800217e: 6878 ldr r0, [r7, #4] + 8002180: f7ff ff5e bl 8002040 +} + 8002184: bf00 nop + 8002186: 3708 adds r7, #8 + 8002188: 46bd mov sp, r7 + 800218a: bd80 pop {r7, pc} + +0800218c : +/** + * @brief Initializes Touchscreen low level. + * @retval None + */ +void TS_IO_Init(void) +{ + 800218c: b580 push {r7, lr} + 800218e: af00 add r7, sp, #0 + I2Cx_Init(&hI2cAudioHandler); + 8002190: 4802 ldr r0, [pc, #8] ; (800219c ) + 8002192: f7ff ff55 bl 8002040 +} + 8002196: bf00 nop + 8002198: bd80 pop {r7, pc} + 800219a: bf00 nop + 800219c: 20000100 .word 0x20000100 + +080021a0 : + * @param Reg: Reg address + * @param Value: Data to be written + * @retval None + */ +void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value) +{ + 80021a0: b580 push {r7, lr} + 80021a2: b084 sub sp, #16 + 80021a4: af02 add r7, sp, #8 + 80021a6: 4603 mov r3, r0 + 80021a8: 71fb strb r3, [r7, #7] + 80021aa: 460b mov r3, r1 + 80021ac: 71bb strb r3, [r7, #6] + 80021ae: 4613 mov r3, r2 + 80021b0: 717b strb r3, [r7, #5] + I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1); + 80021b2: 79bb ldrb r3, [r7, #6] + 80021b4: b29a uxth r2, r3 + 80021b6: 79f9 ldrb r1, [r7, #7] + 80021b8: 2301 movs r3, #1 + 80021ba: 9301 str r3, [sp, #4] + 80021bc: 1d7b adds r3, r7, #5 + 80021be: 9300 str r3, [sp, #0] + 80021c0: 2301 movs r3, #1 + 80021c2: 4803 ldr r0, [pc, #12] ; (80021d0 ) + 80021c4: f7ff ffa5 bl 8002112 +} + 80021c8: bf00 nop + 80021ca: 3708 adds r7, #8 + 80021cc: 46bd mov sp, r7 + 80021ce: bd80 pop {r7, pc} + 80021d0: 20000100 .word 0x20000100 + +080021d4 : + * @param Addr: I2C address + * @param Reg: Reg address + * @retval Data to be read + */ +uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg) +{ + 80021d4: b580 push {r7, lr} + 80021d6: b086 sub sp, #24 + 80021d8: af02 add r7, sp, #8 + 80021da: 4603 mov r3, r0 + 80021dc: 460a mov r2, r1 + 80021de: 71fb strb r3, [r7, #7] + 80021e0: 4613 mov r3, r2 + 80021e2: 71bb strb r3, [r7, #6] + uint8_t read_value = 0; + 80021e4: 2300 movs r3, #0 + 80021e6: 73fb strb r3, [r7, #15] + + I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1); + 80021e8: 79bb ldrb r3, [r7, #6] + 80021ea: b29a uxth r2, r3 + 80021ec: 79f9 ldrb r1, [r7, #7] + 80021ee: 2301 movs r3, #1 + 80021f0: 9301 str r3, [sp, #4] + 80021f2: f107 030f add.w r3, r7, #15 + 80021f6: 9300 str r3, [sp, #0] + 80021f8: 2301 movs r3, #1 + 80021fa: 4804 ldr r0, [pc, #16] ; (800220c ) + 80021fc: f7ff ff5c bl 80020b8 + + return read_value; + 8002200: 7bfb ldrb r3, [r7, #15] +} + 8002202: 4618 mov r0, r3 + 8002204: 3710 adds r7, #16 + 8002206: 46bd mov sp, r7 + 8002208: bd80 pop {r7, pc} + 800220a: bf00 nop + 800220c: 20000100 .word 0x20000100 + +08002210 : + * @brief TS delay + * @param Delay: Delay in ms + * @retval None + */ +void TS_IO_Delay(uint32_t Delay) +{ + 8002210: b580 push {r7, lr} + 8002212: b082 sub sp, #8 + 8002214: af00 add r7, sp, #0 + 8002216: 6078 str r0, [r7, #4] + HAL_Delay(Delay); + 8002218: 6878 ldr r0, [r7, #4] + 800221a: f002 f975 bl 8004508 +} + 800221e: bf00 nop + 8002220: 3708 adds r7, #8 + 8002222: 46bd mov sp, r7 + 8002224: bd80 pop {r7, pc} + ... + +08002228 : +/** + * @brief Initializes the LCD. + * @retval LCD state + */ +uint8_t BSP_LCD_Init(void) +{ + 8002228: b580 push {r7, lr} + 800222a: af00 add r7, sp, #0 + /* Select the used LCD */ + + /* The RK043FN48H LCD 480x272 is selected */ + /* Timing Configuration */ + hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1); + 800222c: 4b31 ldr r3, [pc, #196] ; (80022f4 ) + 800222e: 2228 movs r2, #40 ; 0x28 + 8002230: 615a str r2, [r3, #20] + hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1); + 8002232: 4b30 ldr r3, [pc, #192] ; (80022f4 ) + 8002234: 2209 movs r2, #9 + 8002236: 619a str r2, [r3, #24] + hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + 8002238: 4b2e ldr r3, [pc, #184] ; (80022f4 ) + 800223a: 2235 movs r2, #53 ; 0x35 + 800223c: 61da str r2, [r3, #28] + hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + 800223e: 4b2d ldr r3, [pc, #180] ; (80022f4 ) + 8002240: 220b movs r2, #11 + 8002242: 621a str r2, [r3, #32] + hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1); + 8002244: 4b2b ldr r3, [pc, #172] ; (80022f4 ) + 8002246: f240 121b movw r2, #283 ; 0x11b + 800224a: 629a str r2, [r3, #40] ; 0x28 + hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1); + 800224c: 4b29 ldr r3, [pc, #164] ; (80022f4 ) + 800224e: f240 2215 movw r2, #533 ; 0x215 + 8002252: 625a str r2, [r3, #36] ; 0x24 + hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1); + 8002254: 4b27 ldr r3, [pc, #156] ; (80022f4 ) + 8002256: f240 121d movw r2, #285 ; 0x11d + 800225a: 631a str r2, [r3, #48] ; 0x30 + hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1); + 800225c: 4b25 ldr r3, [pc, #148] ; (80022f4 ) + 800225e: f240 2235 movw r2, #565 ; 0x235 + 8002262: 62da str r2, [r3, #44] ; 0x2c + + /* LCD clock configuration */ + BSP_LCD_ClockConfig(&hLtdcHandler, NULL); + 8002264: 2100 movs r1, #0 + 8002266: 4823 ldr r0, [pc, #140] ; (80022f4 ) + 8002268: f000 fdbe bl 8002de8 + + /* Initialize the LCD pixel width and pixel height */ + hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH; + 800226c: 4b21 ldr r3, [pc, #132] ; (80022f4 ) + 800226e: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 8002272: 661a str r2, [r3, #96] ; 0x60 + hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT; + 8002274: 4b1f ldr r3, [pc, #124] ; (80022f4 ) + 8002276: f44f 7288 mov.w r2, #272 ; 0x110 + 800227a: 665a str r2, [r3, #100] ; 0x64 + + /* Background value */ + hLtdcHandler.Init.Backcolor.Blue = 0; + 800227c: 4b1d ldr r3, [pc, #116] ; (80022f4 ) + 800227e: 2200 movs r2, #0 + 8002280: f883 2034 strb.w r2, [r3, #52] ; 0x34 + hLtdcHandler.Init.Backcolor.Green = 0; + 8002284: 4b1b ldr r3, [pc, #108] ; (80022f4 ) + 8002286: 2200 movs r2, #0 + 8002288: f883 2035 strb.w r2, [r3, #53] ; 0x35 + hLtdcHandler.Init.Backcolor.Red = 0; + 800228c: 4b19 ldr r3, [pc, #100] ; (80022f4 ) + 800228e: 2200 movs r2, #0 + 8002290: f883 2036 strb.w r2, [r3, #54] ; 0x36 + + /* Polarity */ + hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL; + 8002294: 4b17 ldr r3, [pc, #92] ; (80022f4 ) + 8002296: 2200 movs r2, #0 + 8002298: 605a str r2, [r3, #4] + hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL; + 800229a: 4b16 ldr r3, [pc, #88] ; (80022f4 ) + 800229c: 2200 movs r2, #0 + 800229e: 609a str r2, [r3, #8] + hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL; + 80022a0: 4b14 ldr r3, [pc, #80] ; (80022f4 ) + 80022a2: 2200 movs r2, #0 + 80022a4: 60da str r2, [r3, #12] + hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + 80022a6: 4b13 ldr r3, [pc, #76] ; (80022f4 ) + 80022a8: 2200 movs r2, #0 + 80022aa: 611a str r2, [r3, #16] + hLtdcHandler.Instance = LTDC; + 80022ac: 4b11 ldr r3, [pc, #68] ; (80022f4 ) + 80022ae: 4a12 ldr r2, [pc, #72] ; (80022f8 ) + 80022b0: 601a str r2, [r3, #0] + + if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET) + 80022b2: 4810 ldr r0, [pc, #64] ; (80022f4 ) + 80022b4: f004 fd82 bl 8006dbc + 80022b8: 4603 mov r3, r0 + 80022ba: 2b00 cmp r3, #0 + 80022bc: d103 bne.n 80022c6 + { + /* Initialize the LCD Msp: this __weak function can be rewritten by the application */ + BSP_LCD_MspInit(&hLtdcHandler, NULL); + 80022be: 2100 movs r1, #0 + 80022c0: 480c ldr r0, [pc, #48] ; (80022f4 ) + 80022c2: f000 fcb7 bl 8002c34 + } + HAL_LTDC_Init(&hLtdcHandler); + 80022c6: 480b ldr r0, [pc, #44] ; (80022f4 ) + 80022c8: f004 fba8 bl 8006a1c + + /* Assert display enable LCD_DISP pin */ + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); + 80022cc: 2201 movs r2, #1 + 80022ce: f44f 5180 mov.w r1, #4096 ; 0x1000 + 80022d2: 480a ldr r0, [pc, #40] ; (80022fc ) + 80022d4: f003 fdd8 bl 8005e88 + + /* Assert backlight LCD_BL_CTRL pin */ + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); + 80022d8: 2201 movs r2, #1 + 80022da: 2108 movs r1, #8 + 80022dc: 4808 ldr r0, [pc, #32] ; (8002300 ) + 80022de: f003 fdd3 bl 8005e88 + +#if !defined(DATA_IN_ExtSDRAM) + /* Initialize the SDRAM */ + BSP_SDRAM_Init(); + 80022e2: f000 fea1 bl 8003028 +#endif + + /* Initialize the font */ + BSP_LCD_SetFont(&LCD_DEFAULT_FONT); + 80022e6: 4807 ldr r0, [pc, #28] ; (8002304 ) + 80022e8: f000 f8d8 bl 800249c + + return LCD_OK; + 80022ec: 2300 movs r3, #0 +} + 80022ee: 4618 mov r0, r3 + 80022f0: bd80 pop {r7, pc} + 80022f2: bf00 nop + 80022f4: 200089d8 .word 0x200089d8 + 80022f8: 40016800 .word 0x40016800 + 80022fc: 40022000 .word 0x40022000 + 8002300: 40022800 .word 0x40022800 + 8002304: 20000028 .word 0x20000028 + +08002308 : +/** + * @brief Gets the LCD X size. + * @retval Used LCD X size + */ +uint32_t BSP_LCD_GetXSize(void) +{ + 8002308: b480 push {r7} + 800230a: af00 add r7, sp, #0 + return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth; + 800230c: 4b06 ldr r3, [pc, #24] ; (8002328 ) + 800230e: 681b ldr r3, [r3, #0] + 8002310: 4a06 ldr r2, [pc, #24] ; (800232c ) + 8002312: 2134 movs r1, #52 ; 0x34 + 8002314: fb01 f303 mul.w r3, r1, r3 + 8002318: 4413 add r3, r2 + 800231a: 3360 adds r3, #96 ; 0x60 + 800231c: 681b ldr r3, [r3, #0] +} + 800231e: 4618 mov r0, r3 + 8002320: 46bd mov sp, r7 + 8002322: f85d 7b04 ldr.w r7, [sp], #4 + 8002326: 4770 bx lr + 8002328: 2000018c .word 0x2000018c + 800232c: 200089d8 .word 0x200089d8 + +08002330 : +/** + * @brief Gets the LCD Y size. + * @retval Used LCD Y size + */ +uint32_t BSP_LCD_GetYSize(void) +{ + 8002330: b480 push {r7} + 8002332: af00 add r7, sp, #0 + return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight; + 8002334: 4b06 ldr r3, [pc, #24] ; (8002350 ) + 8002336: 681b ldr r3, [r3, #0] + 8002338: 4a06 ldr r2, [pc, #24] ; (8002354 ) + 800233a: 2134 movs r1, #52 ; 0x34 + 800233c: fb01 f303 mul.w r3, r1, r3 + 8002340: 4413 add r3, r2 + 8002342: 3364 adds r3, #100 ; 0x64 + 8002344: 681b ldr r3, [r3, #0] +} + 8002346: 4618 mov r0, r3 + 8002348: 46bd mov sp, r7 + 800234a: f85d 7b04 ldr.w r7, [sp], #4 + 800234e: 4770 bx lr + 8002350: 2000018c .word 0x2000018c + 8002354: 200089d8 .word 0x200089d8 + +08002358 : + * @param LayerIndex: Layer foreground or background + * @param FB_Address: Layer frame buffer + * @retval None + */ +void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address) +{ + 8002358: b580 push {r7, lr} + 800235a: b090 sub sp, #64 ; 0x40 + 800235c: af00 add r7, sp, #0 + 800235e: 4603 mov r3, r0 + 8002360: 6039 str r1, [r7, #0] + 8002362: 80fb strh r3, [r7, #6] + LCD_LayerCfgTypeDef layer_cfg; + + /* Layer Init */ + layer_cfg.WindowX0 = 0; + 8002364: 2300 movs r3, #0 + 8002366: 60fb str r3, [r7, #12] + layer_cfg.WindowX1 = BSP_LCD_GetXSize(); + 8002368: f7ff ffce bl 8002308 + 800236c: 4603 mov r3, r0 + 800236e: 613b str r3, [r7, #16] + layer_cfg.WindowY0 = 0; + 8002370: 2300 movs r3, #0 + 8002372: 617b str r3, [r7, #20] + layer_cfg.WindowY1 = BSP_LCD_GetYSize(); + 8002374: f7ff ffdc bl 8002330 + 8002378: 4603 mov r3, r0 + 800237a: 61bb str r3, [r7, #24] + layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + 800237c: 2300 movs r3, #0 + 800237e: 61fb str r3, [r7, #28] + layer_cfg.FBStartAdress = FB_Address; + 8002380: 683b ldr r3, [r7, #0] + 8002382: 633b str r3, [r7, #48] ; 0x30 + layer_cfg.Alpha = 255; + 8002384: 23ff movs r3, #255 ; 0xff + 8002386: 623b str r3, [r7, #32] + layer_cfg.Alpha0 = 0; + 8002388: 2300 movs r3, #0 + 800238a: 627b str r3, [r7, #36] ; 0x24 + layer_cfg.Backcolor.Blue = 0; + 800238c: 2300 movs r3, #0 + 800238e: f887 303c strb.w r3, [r7, #60] ; 0x3c + layer_cfg.Backcolor.Green = 0; + 8002392: 2300 movs r3, #0 + 8002394: f887 303d strb.w r3, [r7, #61] ; 0x3d + layer_cfg.Backcolor.Red = 0; + 8002398: 2300 movs r3, #0 + 800239a: f887 303e strb.w r3, [r7, #62] ; 0x3e + layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + 800239e: f44f 63c0 mov.w r3, #1536 ; 0x600 + 80023a2: 62bb str r3, [r7, #40] ; 0x28 + layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + 80023a4: 2307 movs r3, #7 + 80023a6: 62fb str r3, [r7, #44] ; 0x2c + layer_cfg.ImageWidth = BSP_LCD_GetXSize(); + 80023a8: f7ff ffae bl 8002308 + 80023ac: 4603 mov r3, r0 + 80023ae: 637b str r3, [r7, #52] ; 0x34 + layer_cfg.ImageHeight = BSP_LCD_GetYSize(); + 80023b0: f7ff ffbe bl 8002330 + 80023b4: 4603 mov r3, r0 + 80023b6: 63bb str r3, [r7, #56] ; 0x38 + + HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex); + 80023b8: 88fa ldrh r2, [r7, #6] + 80023ba: f107 030c add.w r3, r7, #12 + 80023be: 4619 mov r1, r3 + 80023c0: 4812 ldr r0, [pc, #72] ; (800240c ) + 80023c2: f004 fcbd bl 8006d40 + + DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE; + 80023c6: 88fa ldrh r2, [r7, #6] + 80023c8: 4911 ldr r1, [pc, #68] ; (8002410 ) + 80023ca: 4613 mov r3, r2 + 80023cc: 005b lsls r3, r3, #1 + 80023ce: 4413 add r3, r2 + 80023d0: 009b lsls r3, r3, #2 + 80023d2: 440b add r3, r1 + 80023d4: 3304 adds r3, #4 + 80023d6: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80023da: 601a str r2, [r3, #0] + DrawProp[LayerIndex].pFont = &Font24; + 80023dc: 88fa ldrh r2, [r7, #6] + 80023de: 490c ldr r1, [pc, #48] ; (8002410 ) + 80023e0: 4613 mov r3, r2 + 80023e2: 005b lsls r3, r3, #1 + 80023e4: 4413 add r3, r2 + 80023e6: 009b lsls r3, r3, #2 + 80023e8: 440b add r3, r1 + 80023ea: 3308 adds r3, #8 + 80023ec: 4a09 ldr r2, [pc, #36] ; (8002414 ) + 80023ee: 601a str r2, [r3, #0] + DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK; + 80023f0: 88fa ldrh r2, [r7, #6] + 80023f2: 4907 ldr r1, [pc, #28] ; (8002410 ) + 80023f4: 4613 mov r3, r2 + 80023f6: 005b lsls r3, r3, #1 + 80023f8: 4413 add r3, r2 + 80023fa: 009b lsls r3, r3, #2 + 80023fc: 440b add r3, r1 + 80023fe: f04f 427f mov.w r2, #4278190080 ; 0xff000000 + 8002402: 601a str r2, [r3, #0] +} + 8002404: bf00 nop + 8002406: 3740 adds r7, #64 ; 0x40 + 8002408: 46bd mov sp, r7 + 800240a: bd80 pop {r7, pc} + 800240c: 200089d8 .word 0x200089d8 + 8002410: 20000190 .word 0x20000190 + 8002414: 20000028 .word 0x20000028 + +08002418 : + * @brief Selects the LCD Layer. + * @param LayerIndex: Layer foreground or background + * @retval None + */ +void BSP_LCD_SelectLayer(uint32_t LayerIndex) +{ + 8002418: b480 push {r7} + 800241a: b083 sub sp, #12 + 800241c: af00 add r7, sp, #0 + 800241e: 6078 str r0, [r7, #4] + ActiveLayer = LayerIndex; + 8002420: 4a04 ldr r2, [pc, #16] ; (8002434 ) + 8002422: 687b ldr r3, [r7, #4] + 8002424: 6013 str r3, [r2, #0] +} + 8002426: bf00 nop + 8002428: 370c adds r7, #12 + 800242a: 46bd mov sp, r7 + 800242c: f85d 7b04 ldr.w r7, [sp], #4 + 8002430: 4770 bx lr + 8002432: bf00 nop + 8002434: 2000018c .word 0x2000018c + +08002438 : + * @brief Sets the LCD text color. + * @param Color: Text color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetTextColor(uint32_t Color) +{ + 8002438: b480 push {r7} + 800243a: b083 sub sp, #12 + 800243c: af00 add r7, sp, #0 + 800243e: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].TextColor = Color; + 8002440: 4b07 ldr r3, [pc, #28] ; (8002460 ) + 8002442: 681a ldr r2, [r3, #0] + 8002444: 4907 ldr r1, [pc, #28] ; (8002464 ) + 8002446: 4613 mov r3, r2 + 8002448: 005b lsls r3, r3, #1 + 800244a: 4413 add r3, r2 + 800244c: 009b lsls r3, r3, #2 + 800244e: 440b add r3, r1 + 8002450: 687a ldr r2, [r7, #4] + 8002452: 601a str r2, [r3, #0] +} + 8002454: bf00 nop + 8002456: 370c adds r7, #12 + 8002458: 46bd mov sp, r7 + 800245a: f85d 7b04 ldr.w r7, [sp], #4 + 800245e: 4770 bx lr + 8002460: 2000018c .word 0x2000018c + 8002464: 20000190 .word 0x20000190 + +08002468 : + * @brief Sets the LCD background color. + * @param Color: Layer background color code ARGB(8-8-8-8) + * @retval None + */ +void BSP_LCD_SetBackColor(uint32_t Color) +{ + 8002468: b480 push {r7} + 800246a: b083 sub sp, #12 + 800246c: af00 add r7, sp, #0 + 800246e: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].BackColor = Color; + 8002470: 4b08 ldr r3, [pc, #32] ; (8002494 ) + 8002472: 681a ldr r2, [r3, #0] + 8002474: 4908 ldr r1, [pc, #32] ; (8002498 ) + 8002476: 4613 mov r3, r2 + 8002478: 005b lsls r3, r3, #1 + 800247a: 4413 add r3, r2 + 800247c: 009b lsls r3, r3, #2 + 800247e: 440b add r3, r1 + 8002480: 3304 adds r3, #4 + 8002482: 687a ldr r2, [r7, #4] + 8002484: 601a str r2, [r3, #0] +} + 8002486: bf00 nop + 8002488: 370c adds r7, #12 + 800248a: 46bd mov sp, r7 + 800248c: f85d 7b04 ldr.w r7, [sp], #4 + 8002490: 4770 bx lr + 8002492: bf00 nop + 8002494: 2000018c .word 0x2000018c + 8002498: 20000190 .word 0x20000190 + +0800249c : + * @brief Sets the LCD text font. + * @param fonts: Layer font to be used + * @retval None + */ +void BSP_LCD_SetFont(sFONT *fonts) +{ + 800249c: b480 push {r7} + 800249e: b083 sub sp, #12 + 80024a0: af00 add r7, sp, #0 + 80024a2: 6078 str r0, [r7, #4] + DrawProp[ActiveLayer].pFont = fonts; + 80024a4: 4b08 ldr r3, [pc, #32] ; (80024c8 ) + 80024a6: 681a ldr r2, [r3, #0] + 80024a8: 4908 ldr r1, [pc, #32] ; (80024cc ) + 80024aa: 4613 mov r3, r2 + 80024ac: 005b lsls r3, r3, #1 + 80024ae: 4413 add r3, r2 + 80024b0: 009b lsls r3, r3, #2 + 80024b2: 440b add r3, r1 + 80024b4: 3308 adds r3, #8 + 80024b6: 687a ldr r2, [r7, #4] + 80024b8: 601a str r2, [r3, #0] +} + 80024ba: bf00 nop + 80024bc: 370c adds r7, #12 + 80024be: 46bd mov sp, r7 + 80024c0: f85d 7b04 ldr.w r7, [sp], #4 + 80024c4: 4770 bx lr + 80024c6: bf00 nop + 80024c8: 2000018c .word 0x2000018c + 80024cc: 20000190 .word 0x20000190 + +080024d0 : +/** + * @brief Gets the LCD text font. + * @retval Used layer font + */ +sFONT *BSP_LCD_GetFont(void) +{ + 80024d0: b480 push {r7} + 80024d2: af00 add r7, sp, #0 + return DrawProp[ActiveLayer].pFont; + 80024d4: 4b07 ldr r3, [pc, #28] ; (80024f4 ) + 80024d6: 681a ldr r2, [r3, #0] + 80024d8: 4907 ldr r1, [pc, #28] ; (80024f8 ) + 80024da: 4613 mov r3, r2 + 80024dc: 005b lsls r3, r3, #1 + 80024de: 4413 add r3, r2 + 80024e0: 009b lsls r3, r3, #2 + 80024e2: 440b add r3, r1 + 80024e4: 3308 adds r3, #8 + 80024e6: 681b ldr r3, [r3, #0] +} + 80024e8: 4618 mov r0, r3 + 80024ea: 46bd mov sp, r7 + 80024ec: f85d 7b04 ldr.w r7, [sp], #4 + 80024f0: 4770 bx lr + 80024f2: bf00 nop + 80024f4: 2000018c .word 0x2000018c + 80024f8: 20000190 .word 0x20000190 + +080024fc : + * @brief Clears the hole LCD. + * @param Color: Color of the background + * @retval None + */ +void BSP_LCD_Clear(uint32_t Color) +{ + 80024fc: b5f0 push {r4, r5, r6, r7, lr} + 80024fe: b085 sub sp, #20 + 8002500: af02 add r7, sp, #8 + 8002502: 6078 str r0, [r7, #4] + /* Clear the LCD */ + LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color); + 8002504: 4b0f ldr r3, [pc, #60] ; (8002544 ) + 8002506: 681c ldr r4, [r3, #0] + 8002508: 4b0e ldr r3, [pc, #56] ; (8002544 ) + 800250a: 681b ldr r3, [r3, #0] + 800250c: 4a0e ldr r2, [pc, #56] ; (8002548 ) + 800250e: 2134 movs r1, #52 ; 0x34 + 8002510: fb01 f303 mul.w r3, r1, r3 + 8002514: 4413 add r3, r2 + 8002516: 335c adds r3, #92 ; 0x5c + 8002518: 681b ldr r3, [r3, #0] + 800251a: 461d mov r5, r3 + 800251c: f7ff fef4 bl 8002308 + 8002520: 4606 mov r6, r0 + 8002522: f7ff ff05 bl 8002330 + 8002526: 4602 mov r2, r0 + 8002528: 687b ldr r3, [r7, #4] + 800252a: 9301 str r3, [sp, #4] + 800252c: 2300 movs r3, #0 + 800252e: 9300 str r3, [sp, #0] + 8002530: 4613 mov r3, r2 + 8002532: 4632 mov r2, r6 + 8002534: 4629 mov r1, r5 + 8002536: 4620 mov r0, r4 + 8002538: f000 fd2a bl 8002f90 +} + 800253c: bf00 nop + 800253e: 370c adds r7, #12 + 8002540: 46bd mov sp, r7 + 8002542: bdf0 pop {r4, r5, r6, r7, pc} + 8002544: 2000018c .word 0x2000018c + 8002548: 200089d8 .word 0x200089d8 + +0800254c : + * @param Ascii: Character ascii code + * This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E + * @retval None + */ +void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii) +{ + 800254c: b590 push {r4, r7, lr} + 800254e: b083 sub sp, #12 + 8002550: af00 add r7, sp, #0 + 8002552: 4603 mov r3, r0 + 8002554: 80fb strh r3, [r7, #6] + 8002556: 460b mov r3, r1 + 8002558: 80bb strh r3, [r7, #4] + 800255a: 4613 mov r3, r2 + 800255c: 70fb strb r3, [r7, #3] + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 800255e: 4b1b ldr r3, [pc, #108] ; (80025cc ) + 8002560: 681a ldr r2, [r3, #0] + 8002562: 491b ldr r1, [pc, #108] ; (80025d0 ) + 8002564: 4613 mov r3, r2 + 8002566: 005b lsls r3, r3, #1 + 8002568: 4413 add r3, r2 + 800256a: 009b lsls r3, r3, #2 + 800256c: 440b add r3, r1 + 800256e: 3308 adds r3, #8 + 8002570: 681b ldr r3, [r3, #0] + 8002572: 6819 ldr r1, [r3, #0] + 8002574: 78fb ldrb r3, [r7, #3] + 8002576: f1a3 0020 sub.w r0, r3, #32 + DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]); + 800257a: 4b14 ldr r3, [pc, #80] ; (80025cc ) + 800257c: 681a ldr r2, [r3, #0] + 800257e: 4c14 ldr r4, [pc, #80] ; (80025d0 ) + 8002580: 4613 mov r3, r2 + 8002582: 005b lsls r3, r3, #1 + 8002584: 4413 add r3, r2 + 8002586: 009b lsls r3, r3, #2 + 8002588: 4423 add r3, r4 + 800258a: 3308 adds r3, #8 + 800258c: 681b ldr r3, [r3, #0] + 800258e: 88db ldrh r3, [r3, #6] + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 8002590: fb03 f000 mul.w r0, r3, r0 + DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]); + 8002594: 4b0d ldr r3, [pc, #52] ; (80025cc ) + 8002596: 681a ldr r2, [r3, #0] + 8002598: 4c0d ldr r4, [pc, #52] ; (80025d0 ) + 800259a: 4613 mov r3, r2 + 800259c: 005b lsls r3, r3, #1 + 800259e: 4413 add r3, r2 + 80025a0: 009b lsls r3, r3, #2 + 80025a2: 4423 add r3, r4 + 80025a4: 3308 adds r3, #8 + 80025a6: 681b ldr r3, [r3, #0] + 80025a8: 889b ldrh r3, [r3, #4] + 80025aa: 3307 adds r3, #7 + 80025ac: 2b00 cmp r3, #0 + 80025ae: da00 bge.n 80025b2 + 80025b0: 3307 adds r3, #7 + 80025b2: 10db asrs r3, r3, #3 + 80025b4: fb03 f300 mul.w r3, r3, r0 + DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\ + 80025b8: 18ca adds r2, r1, r3 + 80025ba: 88b9 ldrh r1, [r7, #4] + 80025bc: 88fb ldrh r3, [r7, #6] + 80025be: 4618 mov r0, r3 + 80025c0: f000 fc2e bl 8002e20 +} + 80025c4: bf00 nop + 80025c6: 370c adds r7, #12 + 80025c8: 46bd mov sp, r7 + 80025ca: bd90 pop {r4, r7, pc} + 80025cc: 2000018c .word 0x2000018c + 80025d0: 20000190 .word 0x20000190 + +080025d4 : + * @arg RIGHT_MODE + * @arg LEFT_MODE + * @retval None + */ +void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode) +{ + 80025d4: b5b0 push {r4, r5, r7, lr} + 80025d6: b088 sub sp, #32 + 80025d8: af00 add r7, sp, #0 + 80025da: 60ba str r2, [r7, #8] + 80025dc: 461a mov r2, r3 + 80025de: 4603 mov r3, r0 + 80025e0: 81fb strh r3, [r7, #14] + 80025e2: 460b mov r3, r1 + 80025e4: 81bb strh r3, [r7, #12] + 80025e6: 4613 mov r3, r2 + 80025e8: 71fb strb r3, [r7, #7] + uint16_t ref_column = 1, i = 0; + 80025ea: 2301 movs r3, #1 + 80025ec: 83fb strh r3, [r7, #30] + 80025ee: 2300 movs r3, #0 + 80025f0: 83bb strh r3, [r7, #28] + uint32_t size = 0, xsize = 0; + 80025f2: 2300 movs r3, #0 + 80025f4: 61bb str r3, [r7, #24] + 80025f6: 2300 movs r3, #0 + 80025f8: 613b str r3, [r7, #16] + uint8_t *ptr = Text; + 80025fa: 68bb ldr r3, [r7, #8] + 80025fc: 617b str r3, [r7, #20] + + /* Get the text size */ + while (*ptr++) size ++ ; + 80025fe: e002 b.n 8002606 + 8002600: 69bb ldr r3, [r7, #24] + 8002602: 3301 adds r3, #1 + 8002604: 61bb str r3, [r7, #24] + 8002606: 697b ldr r3, [r7, #20] + 8002608: 1c5a adds r2, r3, #1 + 800260a: 617a str r2, [r7, #20] + 800260c: 781b ldrb r3, [r3, #0] + 800260e: 2b00 cmp r3, #0 + 8002610: d1f6 bne.n 8002600 + + /* Characters number per line */ + xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width); + 8002612: f7ff fe79 bl 8002308 + 8002616: 4b4f ldr r3, [pc, #316] ; (8002754 ) + 8002618: 681a ldr r2, [r3, #0] + 800261a: 494f ldr r1, [pc, #316] ; (8002758 ) + 800261c: 4613 mov r3, r2 + 800261e: 005b lsls r3, r3, #1 + 8002620: 4413 add r3, r2 + 8002622: 009b lsls r3, r3, #2 + 8002624: 440b add r3, r1 + 8002626: 3308 adds r3, #8 + 8002628: 681b ldr r3, [r3, #0] + 800262a: 889b ldrh r3, [r3, #4] + 800262c: fbb0 f3f3 udiv r3, r0, r3 + 8002630: 613b str r3, [r7, #16] + + switch (Mode) + 8002632: 79fb ldrb r3, [r7, #7] + 8002634: 2b02 cmp r3, #2 + 8002636: d01c beq.n 8002672 + 8002638: 2b03 cmp r3, #3 + 800263a: d017 beq.n 800266c + 800263c: 2b01 cmp r3, #1 + 800263e: d12e bne.n 800269e + { + case CENTER_MODE: + { + ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2; + 8002640: 693a ldr r2, [r7, #16] + 8002642: 69bb ldr r3, [r7, #24] + 8002644: 1ad1 subs r1, r2, r3 + 8002646: 4b43 ldr r3, [pc, #268] ; (8002754 ) + 8002648: 681a ldr r2, [r3, #0] + 800264a: 4843 ldr r0, [pc, #268] ; (8002758 ) + 800264c: 4613 mov r3, r2 + 800264e: 005b lsls r3, r3, #1 + 8002650: 4413 add r3, r2 + 8002652: 009b lsls r3, r3, #2 + 8002654: 4403 add r3, r0 + 8002656: 3308 adds r3, #8 + 8002658: 681b ldr r3, [r3, #0] + 800265a: 889b ldrh r3, [r3, #4] + 800265c: fb03 f301 mul.w r3, r3, r1 + 8002660: 085b lsrs r3, r3, #1 + 8002662: b29a uxth r2, r3 + 8002664: 89fb ldrh r3, [r7, #14] + 8002666: 4413 add r3, r2 + 8002668: 83fb strh r3, [r7, #30] + break; + 800266a: e01b b.n 80026a4 + } + case LEFT_MODE: + { + ref_column = Xpos; + 800266c: 89fb ldrh r3, [r7, #14] + 800266e: 83fb strh r3, [r7, #30] + break; + 8002670: e018 b.n 80026a4 + } + case RIGHT_MODE: + { + ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width); + 8002672: 693a ldr r2, [r7, #16] + 8002674: 69bb ldr r3, [r7, #24] + 8002676: 1ad3 subs r3, r2, r3 + 8002678: b299 uxth r1, r3 + 800267a: 4b36 ldr r3, [pc, #216] ; (8002754 ) + 800267c: 681a ldr r2, [r3, #0] + 800267e: 4836 ldr r0, [pc, #216] ; (8002758 ) + 8002680: 4613 mov r3, r2 + 8002682: 005b lsls r3, r3, #1 + 8002684: 4413 add r3, r2 + 8002686: 009b lsls r3, r3, #2 + 8002688: 4403 add r3, r0 + 800268a: 3308 adds r3, #8 + 800268c: 681b ldr r3, [r3, #0] + 800268e: 889b ldrh r3, [r3, #4] + 8002690: fb11 f303 smulbb r3, r1, r3 + 8002694: b29a uxth r2, r3 + 8002696: 89fb ldrh r3, [r7, #14] + 8002698: 1ad3 subs r3, r2, r3 + 800269a: 83fb strh r3, [r7, #30] + break; + 800269c: e002 b.n 80026a4 + } + default: + { + ref_column = Xpos; + 800269e: 89fb ldrh r3, [r7, #14] + 80026a0: 83fb strh r3, [r7, #30] + break; + 80026a2: bf00 nop + } + } + + /* Check that the Start column is located in the screen */ + if ((ref_column < 1) || (ref_column >= 0x8000)) + 80026a4: 8bfb ldrh r3, [r7, #30] + 80026a6: 2b00 cmp r3, #0 + 80026a8: d003 beq.n 80026b2 + 80026aa: f9b7 301e ldrsh.w r3, [r7, #30] + 80026ae: 2b00 cmp r3, #0 + 80026b0: da1d bge.n 80026ee + { + ref_column = 1; + 80026b2: 2301 movs r3, #1 + 80026b4: 83fb strh r3, [r7, #30] + } + + /* Send the string character by character on LCD */ + while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width)) + 80026b6: e01a b.n 80026ee + { + /* Display one character on LCD */ + BSP_LCD_DisplayChar(ref_column, Ypos, *Text); + 80026b8: 68bb ldr r3, [r7, #8] + 80026ba: 781a ldrb r2, [r3, #0] + 80026bc: 89b9 ldrh r1, [r7, #12] + 80026be: 8bfb ldrh r3, [r7, #30] + 80026c0: 4618 mov r0, r3 + 80026c2: f7ff ff43 bl 800254c + /* Decrement the column position by 16 */ + ref_column += DrawProp[ActiveLayer].pFont->Width; + 80026c6: 4b23 ldr r3, [pc, #140] ; (8002754 ) + 80026c8: 681a ldr r2, [r3, #0] + 80026ca: 4923 ldr r1, [pc, #140] ; (8002758 ) + 80026cc: 4613 mov r3, r2 + 80026ce: 005b lsls r3, r3, #1 + 80026d0: 4413 add r3, r2 + 80026d2: 009b lsls r3, r3, #2 + 80026d4: 440b add r3, r1 + 80026d6: 3308 adds r3, #8 + 80026d8: 681b ldr r3, [r3, #0] + 80026da: 889a ldrh r2, [r3, #4] + 80026dc: 8bfb ldrh r3, [r7, #30] + 80026de: 4413 add r3, r2 + 80026e0: 83fb strh r3, [r7, #30] + /* Point on the next character */ + Text++; + 80026e2: 68bb ldr r3, [r7, #8] + 80026e4: 3301 adds r3, #1 + 80026e6: 60bb str r3, [r7, #8] + i++; + 80026e8: 8bbb ldrh r3, [r7, #28] + 80026ea: 3301 adds r3, #1 + 80026ec: 83bb strh r3, [r7, #28] + while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width)) + 80026ee: 68bb ldr r3, [r7, #8] + 80026f0: 781b ldrb r3, [r3, #0] + 80026f2: 2b00 cmp r3, #0 + 80026f4: bf14 ite ne + 80026f6: 2301 movne r3, #1 + 80026f8: 2300 moveq r3, #0 + 80026fa: b2dc uxtb r4, r3 + 80026fc: f7ff fe04 bl 8002308 + 8002700: 4605 mov r5, r0 + 8002702: 8bb9 ldrh r1, [r7, #28] + 8002704: 4b13 ldr r3, [pc, #76] ; (8002754 ) + 8002706: 681a ldr r2, [r3, #0] + 8002708: 4813 ldr r0, [pc, #76] ; (8002758 ) + 800270a: 4613 mov r3, r2 + 800270c: 005b lsls r3, r3, #1 + 800270e: 4413 add r3, r2 + 8002710: 009b lsls r3, r3, #2 + 8002712: 4403 add r3, r0 + 8002714: 3308 adds r3, #8 + 8002716: 681b ldr r3, [r3, #0] + 8002718: 889b ldrh r3, [r3, #4] + 800271a: fb03 f301 mul.w r3, r3, r1 + 800271e: 1aeb subs r3, r5, r3 + 8002720: b299 uxth r1, r3 + 8002722: 4b0c ldr r3, [pc, #48] ; (8002754 ) + 8002724: 681a ldr r2, [r3, #0] + 8002726: 480c ldr r0, [pc, #48] ; (8002758 ) + 8002728: 4613 mov r3, r2 + 800272a: 005b lsls r3, r3, #1 + 800272c: 4413 add r3, r2 + 800272e: 009b lsls r3, r3, #2 + 8002730: 4403 add r3, r0 + 8002732: 3308 adds r3, #8 + 8002734: 681b ldr r3, [r3, #0] + 8002736: 889b ldrh r3, [r3, #4] + 8002738: 4299 cmp r1, r3 + 800273a: bf2c ite cs + 800273c: 2301 movcs r3, #1 + 800273e: 2300 movcc r3, #0 + 8002740: b2db uxtb r3, r3 + 8002742: 4023 ands r3, r4 + 8002744: b2db uxtb r3, r3 + 8002746: 2b00 cmp r3, #0 + 8002748: d1b6 bne.n 80026b8 + } +} + 800274a: bf00 nop + 800274c: 3720 adds r7, #32 + 800274e: 46bd mov sp, r7 + 8002750: bdb0 pop {r4, r5, r7, pc} + 8002752: bf00 nop + 8002754: 2000018c .word 0x2000018c + 8002758: 20000190 .word 0x20000190 + +0800275c : + * @param Line: Line where to display the character shape + * @param ptr: Pointer to string to display on LCD + * @retval None + */ +void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr) +{ + 800275c: b580 push {r7, lr} + 800275e: b082 sub sp, #8 + 8002760: af00 add r7, sp, #0 + 8002762: 4603 mov r3, r0 + 8002764: 6039 str r1, [r7, #0] + 8002766: 80fb strh r3, [r7, #6] + BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE); + 8002768: f7ff feb2 bl 80024d0 + 800276c: 4603 mov r3, r0 + 800276e: 88db ldrh r3, [r3, #6] + 8002770: 88fa ldrh r2, [r7, #6] + 8002772: fb12 f303 smulbb r3, r2, r3 + 8002776: b299 uxth r1, r3 + 8002778: 2303 movs r3, #3 + 800277a: 683a ldr r2, [r7, #0] + 800277c: 2000 movs r0, #0 + 800277e: f7ff ff29 bl 80025d4 +} + 8002782: bf00 nop + 8002784: 3708 adds r7, #8 + 8002786: 46bd mov sp, r7 + 8002788: bd80 pop {r7, pc} + ... + +0800278c : + * @param Ypos: Y position + * @param Length: Line length + * @retval None + */ +void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length) +{ + 800278c: b5b0 push {r4, r5, r7, lr} + 800278e: b086 sub sp, #24 + 8002790: af02 add r7, sp, #8 + 8002792: 4603 mov r3, r0 + 8002794: 80fb strh r3, [r7, #6] + 8002796: 460b mov r3, r1 + 8002798: 80bb strh r3, [r7, #4] + 800279a: 4613 mov r3, r2 + 800279c: 807b strh r3, [r7, #2] + uint32_t Xaddress = 0; + 800279e: 2300 movs r3, #0 + 80027a0: 60fb str r3, [r7, #12] + + /* Get the line address */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + 80027a2: 4b26 ldr r3, [pc, #152] ; (800283c ) + 80027a4: 681b ldr r3, [r3, #0] + 80027a6: 4a26 ldr r2, [pc, #152] ; (8002840 ) + 80027a8: 2134 movs r1, #52 ; 0x34 + 80027aa: fb01 f303 mul.w r3, r1, r3 + 80027ae: 4413 add r3, r2 + 80027b0: 3348 adds r3, #72 ; 0x48 + 80027b2: 681b ldr r3, [r3, #0] + 80027b4: 2b02 cmp r3, #2 + 80027b6: d114 bne.n 80027e2 + { /* RGB565 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos); + 80027b8: 4b20 ldr r3, [pc, #128] ; (800283c ) + 80027ba: 681b ldr r3, [r3, #0] + 80027bc: 4a20 ldr r2, [pc, #128] ; (8002840 ) + 80027be: 2134 movs r1, #52 ; 0x34 + 80027c0: fb01 f303 mul.w r3, r1, r3 + 80027c4: 4413 add r3, r2 + 80027c6: 335c adds r3, #92 ; 0x5c + 80027c8: 681c ldr r4, [r3, #0] + 80027ca: f7ff fd9d bl 8002308 + 80027ce: 4602 mov r2, r0 + 80027d0: 88bb ldrh r3, [r7, #4] + 80027d2: fb03 f202 mul.w r2, r3, r2 + 80027d6: 88fb ldrh r3, [r7, #6] + 80027d8: 4413 add r3, r2 + 80027da: 005b lsls r3, r3, #1 + 80027dc: 4423 add r3, r4 + 80027de: 60fb str r3, [r7, #12] + 80027e0: e013 b.n 800280a + } + else + { /* ARGB8888 format */ + Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos); + 80027e2: 4b16 ldr r3, [pc, #88] ; (800283c ) + 80027e4: 681b ldr r3, [r3, #0] + 80027e6: 4a16 ldr r2, [pc, #88] ; (8002840 ) + 80027e8: 2134 movs r1, #52 ; 0x34 + 80027ea: fb01 f303 mul.w r3, r1, r3 + 80027ee: 4413 add r3, r2 + 80027f0: 335c adds r3, #92 ; 0x5c + 80027f2: 681c ldr r4, [r3, #0] + 80027f4: f7ff fd88 bl 8002308 + 80027f8: 4602 mov r2, r0 + 80027fa: 88bb ldrh r3, [r7, #4] + 80027fc: fb03 f202 mul.w r2, r3, r2 + 8002800: 88fb ldrh r3, [r7, #6] + 8002802: 4413 add r3, r2 + 8002804: 009b lsls r3, r3, #2 + 8002806: 4423 add r3, r4 + 8002808: 60fb str r3, [r7, #12] + } + + /* Write line */ + LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor); + 800280a: 4b0c ldr r3, [pc, #48] ; (800283c ) + 800280c: 6818 ldr r0, [r3, #0] + 800280e: 68fc ldr r4, [r7, #12] + 8002810: 887d ldrh r5, [r7, #2] + 8002812: 4b0a ldr r3, [pc, #40] ; (800283c ) + 8002814: 681a ldr r2, [r3, #0] + 8002816: 490b ldr r1, [pc, #44] ; (8002844 ) + 8002818: 4613 mov r3, r2 + 800281a: 005b lsls r3, r3, #1 + 800281c: 4413 add r3, r2 + 800281e: 009b lsls r3, r3, #2 + 8002820: 440b add r3, r1 + 8002822: 681b ldr r3, [r3, #0] + 8002824: 9301 str r3, [sp, #4] + 8002826: 2300 movs r3, #0 + 8002828: 9300 str r3, [sp, #0] + 800282a: 2301 movs r3, #1 + 800282c: 462a mov r2, r5 + 800282e: 4621 mov r1, r4 + 8002830: f000 fbae bl 8002f90 +} + 8002834: bf00 nop + 8002836: 3710 adds r7, #16 + 8002838: 46bd mov sp, r7 + 800283a: bdb0 pop {r4, r5, r7, pc} + 800283c: 2000018c .word 0x2000018c + 8002840: 200089d8 .word 0x200089d8 + 8002844: 20000190 .word 0x20000190 + +08002848 : + * @param Ypos: Y position + * @param Radius: Circle radius + * @retval None + */ +void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + 8002848: b590 push {r4, r7, lr} + 800284a: b087 sub sp, #28 + 800284c: af00 add r7, sp, #0 + 800284e: 4603 mov r3, r0 + 8002850: 80fb strh r3, [r7, #6] + 8002852: 460b mov r3, r1 + 8002854: 80bb strh r3, [r7, #4] + 8002856: 4613 mov r3, r2 + 8002858: 807b strh r3, [r7, #2] + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + decision = 3 - (Radius << 1); + 800285a: 887b ldrh r3, [r7, #2] + 800285c: 005b lsls r3, r3, #1 + 800285e: f1c3 0303 rsb r3, r3, #3 + 8002862: 617b str r3, [r7, #20] + current_x = 0; + 8002864: 2300 movs r3, #0 + 8002866: 613b str r3, [r7, #16] + current_y = Radius; + 8002868: 887b ldrh r3, [r7, #2] + 800286a: 60fb str r3, [r7, #12] + + while (current_x <= current_y) + 800286c: e0cf b.n 8002a0e + { + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + 800286e: 693b ldr r3, [r7, #16] + 8002870: b29a uxth r2, r3 + 8002872: 88fb ldrh r3, [r7, #6] + 8002874: 4413 add r3, r2 + 8002876: b298 uxth r0, r3 + 8002878: 68fb ldr r3, [r7, #12] + 800287a: b29b uxth r3, r3 + 800287c: 88ba ldrh r2, [r7, #4] + 800287e: 1ad3 subs r3, r2, r3 + 8002880: b29c uxth r4, r3 + 8002882: 4b67 ldr r3, [pc, #412] ; (8002a20 ) + 8002884: 681a ldr r2, [r3, #0] + 8002886: 4967 ldr r1, [pc, #412] ; (8002a24 ) + 8002888: 4613 mov r3, r2 + 800288a: 005b lsls r3, r3, #1 + 800288c: 4413 add r3, r2 + 800288e: 009b lsls r3, r3, #2 + 8002890: 440b add r3, r1 + 8002892: 681b ldr r3, [r3, #0] + 8002894: 461a mov r2, r3 + 8002896: 4621 mov r1, r4 + 8002898: f000 f8c6 bl 8002a28 + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor); + 800289c: 693b ldr r3, [r7, #16] + 800289e: b29b uxth r3, r3 + 80028a0: 88fa ldrh r2, [r7, #6] + 80028a2: 1ad3 subs r3, r2, r3 + 80028a4: b298 uxth r0, r3 + 80028a6: 68fb ldr r3, [r7, #12] + 80028a8: b29b uxth r3, r3 + 80028aa: 88ba ldrh r2, [r7, #4] + 80028ac: 1ad3 subs r3, r2, r3 + 80028ae: b29c uxth r4, r3 + 80028b0: 4b5b ldr r3, [pc, #364] ; (8002a20 ) + 80028b2: 681a ldr r2, [r3, #0] + 80028b4: 495b ldr r1, [pc, #364] ; (8002a24 ) + 80028b6: 4613 mov r3, r2 + 80028b8: 005b lsls r3, r3, #1 + 80028ba: 4413 add r3, r2 + 80028bc: 009b lsls r3, r3, #2 + 80028be: 440b add r3, r1 + 80028c0: 681b ldr r3, [r3, #0] + 80028c2: 461a mov r2, r3 + 80028c4: 4621 mov r1, r4 + 80028c6: f000 f8af bl 8002a28 + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + 80028ca: 68fb ldr r3, [r7, #12] + 80028cc: b29a uxth r2, r3 + 80028ce: 88fb ldrh r3, [r7, #6] + 80028d0: 4413 add r3, r2 + 80028d2: b298 uxth r0, r3 + 80028d4: 693b ldr r3, [r7, #16] + 80028d6: b29b uxth r3, r3 + 80028d8: 88ba ldrh r2, [r7, #4] + 80028da: 1ad3 subs r3, r2, r3 + 80028dc: b29c uxth r4, r3 + 80028de: 4b50 ldr r3, [pc, #320] ; (8002a20 ) + 80028e0: 681a ldr r2, [r3, #0] + 80028e2: 4950 ldr r1, [pc, #320] ; (8002a24 ) + 80028e4: 4613 mov r3, r2 + 80028e6: 005b lsls r3, r3, #1 + 80028e8: 4413 add r3, r2 + 80028ea: 009b lsls r3, r3, #2 + 80028ec: 440b add r3, r1 + 80028ee: 681b ldr r3, [r3, #0] + 80028f0: 461a mov r2, r3 + 80028f2: 4621 mov r1, r4 + 80028f4: f000 f898 bl 8002a28 + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor); + 80028f8: 68fb ldr r3, [r7, #12] + 80028fa: b29b uxth r3, r3 + 80028fc: 88fa ldrh r2, [r7, #6] + 80028fe: 1ad3 subs r3, r2, r3 + 8002900: b298 uxth r0, r3 + 8002902: 693b ldr r3, [r7, #16] + 8002904: b29b uxth r3, r3 + 8002906: 88ba ldrh r2, [r7, #4] + 8002908: 1ad3 subs r3, r2, r3 + 800290a: b29c uxth r4, r3 + 800290c: 4b44 ldr r3, [pc, #272] ; (8002a20 ) + 800290e: 681a ldr r2, [r3, #0] + 8002910: 4944 ldr r1, [pc, #272] ; (8002a24 ) + 8002912: 4613 mov r3, r2 + 8002914: 005b lsls r3, r3, #1 + 8002916: 4413 add r3, r2 + 8002918: 009b lsls r3, r3, #2 + 800291a: 440b add r3, r1 + 800291c: 681b ldr r3, [r3, #0] + 800291e: 461a mov r2, r3 + 8002920: 4621 mov r1, r4 + 8002922: f000 f881 bl 8002a28 + + BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + 8002926: 693b ldr r3, [r7, #16] + 8002928: b29a uxth r2, r3 + 800292a: 88fb ldrh r3, [r7, #6] + 800292c: 4413 add r3, r2 + 800292e: b298 uxth r0, r3 + 8002930: 68fb ldr r3, [r7, #12] + 8002932: b29a uxth r2, r3 + 8002934: 88bb ldrh r3, [r7, #4] + 8002936: 4413 add r3, r2 + 8002938: b29c uxth r4, r3 + 800293a: 4b39 ldr r3, [pc, #228] ; (8002a20 ) + 800293c: 681a ldr r2, [r3, #0] + 800293e: 4939 ldr r1, [pc, #228] ; (8002a24 ) + 8002940: 4613 mov r3, r2 + 8002942: 005b lsls r3, r3, #1 + 8002944: 4413 add r3, r2 + 8002946: 009b lsls r3, r3, #2 + 8002948: 440b add r3, r1 + 800294a: 681b ldr r3, [r3, #0] + 800294c: 461a mov r2, r3 + 800294e: 4621 mov r1, r4 + 8002950: f000 f86a bl 8002a28 + + BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor); + 8002954: 693b ldr r3, [r7, #16] + 8002956: b29b uxth r3, r3 + 8002958: 88fa ldrh r2, [r7, #6] + 800295a: 1ad3 subs r3, r2, r3 + 800295c: b298 uxth r0, r3 + 800295e: 68fb ldr r3, [r7, #12] + 8002960: b29a uxth r2, r3 + 8002962: 88bb ldrh r3, [r7, #4] + 8002964: 4413 add r3, r2 + 8002966: b29c uxth r4, r3 + 8002968: 4b2d ldr r3, [pc, #180] ; (8002a20 ) + 800296a: 681a ldr r2, [r3, #0] + 800296c: 492d ldr r1, [pc, #180] ; (8002a24 ) + 800296e: 4613 mov r3, r2 + 8002970: 005b lsls r3, r3, #1 + 8002972: 4413 add r3, r2 + 8002974: 009b lsls r3, r3, #2 + 8002976: 440b add r3, r1 + 8002978: 681b ldr r3, [r3, #0] + 800297a: 461a mov r2, r3 + 800297c: 4621 mov r1, r4 + 800297e: f000 f853 bl 8002a28 + + BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + 8002982: 68fb ldr r3, [r7, #12] + 8002984: b29a uxth r2, r3 + 8002986: 88fb ldrh r3, [r7, #6] + 8002988: 4413 add r3, r2 + 800298a: b298 uxth r0, r3 + 800298c: 693b ldr r3, [r7, #16] + 800298e: b29a uxth r2, r3 + 8002990: 88bb ldrh r3, [r7, #4] + 8002992: 4413 add r3, r2 + 8002994: b29c uxth r4, r3 + 8002996: 4b22 ldr r3, [pc, #136] ; (8002a20 ) + 8002998: 681a ldr r2, [r3, #0] + 800299a: 4922 ldr r1, [pc, #136] ; (8002a24 ) + 800299c: 4613 mov r3, r2 + 800299e: 005b lsls r3, r3, #1 + 80029a0: 4413 add r3, r2 + 80029a2: 009b lsls r3, r3, #2 + 80029a4: 440b add r3, r1 + 80029a6: 681b ldr r3, [r3, #0] + 80029a8: 461a mov r2, r3 + 80029aa: 4621 mov r1, r4 + 80029ac: f000 f83c bl 8002a28 + + BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor); + 80029b0: 68fb ldr r3, [r7, #12] + 80029b2: b29b uxth r3, r3 + 80029b4: 88fa ldrh r2, [r7, #6] + 80029b6: 1ad3 subs r3, r2, r3 + 80029b8: b298 uxth r0, r3 + 80029ba: 693b ldr r3, [r7, #16] + 80029bc: b29a uxth r2, r3 + 80029be: 88bb ldrh r3, [r7, #4] + 80029c0: 4413 add r3, r2 + 80029c2: b29c uxth r4, r3 + 80029c4: 4b16 ldr r3, [pc, #88] ; (8002a20 ) + 80029c6: 681a ldr r2, [r3, #0] + 80029c8: 4916 ldr r1, [pc, #88] ; (8002a24 ) + 80029ca: 4613 mov r3, r2 + 80029cc: 005b lsls r3, r3, #1 + 80029ce: 4413 add r3, r2 + 80029d0: 009b lsls r3, r3, #2 + 80029d2: 440b add r3, r1 + 80029d4: 681b ldr r3, [r3, #0] + 80029d6: 461a mov r2, r3 + 80029d8: 4621 mov r1, r4 + 80029da: f000 f825 bl 8002a28 + + if (decision < 0) + 80029de: 697b ldr r3, [r7, #20] + 80029e0: 2b00 cmp r3, #0 + 80029e2: da06 bge.n 80029f2 + { + decision += (current_x << 2) + 6; + 80029e4: 693b ldr r3, [r7, #16] + 80029e6: 009a lsls r2, r3, #2 + 80029e8: 697b ldr r3, [r7, #20] + 80029ea: 4413 add r3, r2 + 80029ec: 3306 adds r3, #6 + 80029ee: 617b str r3, [r7, #20] + 80029f0: e00a b.n 8002a08 + } + else + { + decision += ((current_x - current_y) << 2) + 10; + 80029f2: 693a ldr r2, [r7, #16] + 80029f4: 68fb ldr r3, [r7, #12] + 80029f6: 1ad3 subs r3, r2, r3 + 80029f8: 009a lsls r2, r3, #2 + 80029fa: 697b ldr r3, [r7, #20] + 80029fc: 4413 add r3, r2 + 80029fe: 330a adds r3, #10 + 8002a00: 617b str r3, [r7, #20] + current_y--; + 8002a02: 68fb ldr r3, [r7, #12] + 8002a04: 3b01 subs r3, #1 + 8002a06: 60fb str r3, [r7, #12] + } + current_x++; + 8002a08: 693b ldr r3, [r7, #16] + 8002a0a: 3301 adds r3, #1 + 8002a0c: 613b str r3, [r7, #16] + while (current_x <= current_y) + 8002a0e: 693a ldr r2, [r7, #16] + 8002a10: 68fb ldr r3, [r7, #12] + 8002a12: 429a cmp r2, r3 + 8002a14: f67f af2b bls.w 800286e + } +} + 8002a18: bf00 nop + 8002a1a: 371c adds r7, #28 + 8002a1c: 46bd mov sp, r7 + 8002a1e: bd90 pop {r4, r7, pc} + 8002a20: 2000018c .word 0x2000018c + 8002a24: 20000190 .word 0x20000190 + +08002a28 : + * @param Ypos: Y position + * @param RGB_Code: Pixel color in ARGB mode (8-8-8-8) + * @retval None + */ +void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code) +{ + 8002a28: b5b0 push {r4, r5, r7, lr} + 8002a2a: b082 sub sp, #8 + 8002a2c: af00 add r7, sp, #0 + 8002a2e: 4603 mov r3, r0 + 8002a30: 603a str r2, [r7, #0] + 8002a32: 80fb strh r3, [r7, #6] + 8002a34: 460b mov r3, r1 + 8002a36: 80bb strh r3, [r7, #4] + /* Write data value to all SDRAM memory */ + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + 8002a38: 4b1d ldr r3, [pc, #116] ; (8002ab0 ) + 8002a3a: 681b ldr r3, [r3, #0] + 8002a3c: 4a1d ldr r2, [pc, #116] ; (8002ab4 ) + 8002a3e: 2134 movs r1, #52 ; 0x34 + 8002a40: fb01 f303 mul.w r3, r1, r3 + 8002a44: 4413 add r3, r2 + 8002a46: 3348 adds r3, #72 ; 0x48 + 8002a48: 681b ldr r3, [r3, #0] + 8002a4a: 2b02 cmp r3, #2 + 8002a4c: d116 bne.n 8002a7c + { /* RGB565 format */ + *(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code; + 8002a4e: 4b18 ldr r3, [pc, #96] ; (8002ab0 ) + 8002a50: 681b ldr r3, [r3, #0] + 8002a52: 4a18 ldr r2, [pc, #96] ; (8002ab4 ) + 8002a54: 2134 movs r1, #52 ; 0x34 + 8002a56: fb01 f303 mul.w r3, r1, r3 + 8002a5a: 4413 add r3, r2 + 8002a5c: 335c adds r3, #92 ; 0x5c + 8002a5e: 681c ldr r4, [r3, #0] + 8002a60: 88bd ldrh r5, [r7, #4] + 8002a62: f7ff fc51 bl 8002308 + 8002a66: 4603 mov r3, r0 + 8002a68: fb03 f205 mul.w r2, r3, r5 + 8002a6c: 88fb ldrh r3, [r7, #6] + 8002a6e: 4413 add r3, r2 + 8002a70: 005b lsls r3, r3, #1 + 8002a72: 4423 add r3, r4 + 8002a74: 683a ldr r2, [r7, #0] + 8002a76: b292 uxth r2, r2 + 8002a78: 801a strh r2, [r3, #0] + } + else + { /* ARGB8888 format */ + *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code; + } +} + 8002a7a: e015 b.n 8002aa8 + *(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code; + 8002a7c: 4b0c ldr r3, [pc, #48] ; (8002ab0 ) + 8002a7e: 681b ldr r3, [r3, #0] + 8002a80: 4a0c ldr r2, [pc, #48] ; (8002ab4 ) + 8002a82: 2134 movs r1, #52 ; 0x34 + 8002a84: fb01 f303 mul.w r3, r1, r3 + 8002a88: 4413 add r3, r2 + 8002a8a: 335c adds r3, #92 ; 0x5c + 8002a8c: 681c ldr r4, [r3, #0] + 8002a8e: 88bd ldrh r5, [r7, #4] + 8002a90: f7ff fc3a bl 8002308 + 8002a94: 4603 mov r3, r0 + 8002a96: fb03 f205 mul.w r2, r3, r5 + 8002a9a: 88fb ldrh r3, [r7, #6] + 8002a9c: 4413 add r3, r2 + 8002a9e: 009b lsls r3, r3, #2 + 8002aa0: 4423 add r3, r4 + 8002aa2: 461a mov r2, r3 + 8002aa4: 683b ldr r3, [r7, #0] + 8002aa6: 6013 str r3, [r2, #0] +} + 8002aa8: bf00 nop + 8002aaa: 3708 adds r7, #8 + 8002aac: 46bd mov sp, r7 + 8002aae: bdb0 pop {r4, r5, r7, pc} + 8002ab0: 2000018c .word 0x2000018c + 8002ab4: 200089d8 .word 0x200089d8 + +08002ab8 : + * @param Ypos: Y position + * @param Radius: Circle radius + * @retval None + */ +void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius) +{ + 8002ab8: b580 push {r7, lr} + 8002aba: b086 sub sp, #24 + 8002abc: af00 add r7, sp, #0 + 8002abe: 4603 mov r3, r0 + 8002ac0: 80fb strh r3, [r7, #6] + 8002ac2: 460b mov r3, r1 + 8002ac4: 80bb strh r3, [r7, #4] + 8002ac6: 4613 mov r3, r2 + 8002ac8: 807b strh r3, [r7, #2] + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + decision = 3 - (Radius << 1); + 8002aca: 887b ldrh r3, [r7, #2] + 8002acc: 005b lsls r3, r3, #1 + 8002ace: f1c3 0303 rsb r3, r3, #3 + 8002ad2: 617b str r3, [r7, #20] + + current_x = 0; + 8002ad4: 2300 movs r3, #0 + 8002ad6: 613b str r3, [r7, #16] + current_y = Radius; + 8002ad8: 887b ldrh r3, [r7, #2] + 8002ada: 60fb str r3, [r7, #12] + + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); + 8002adc: 4b44 ldr r3, [pc, #272] ; (8002bf0 ) + 8002ade: 681a ldr r2, [r3, #0] + 8002ae0: 4944 ldr r1, [pc, #272] ; (8002bf4 ) + 8002ae2: 4613 mov r3, r2 + 8002ae4: 005b lsls r3, r3, #1 + 8002ae6: 4413 add r3, r2 + 8002ae8: 009b lsls r3, r3, #2 + 8002aea: 440b add r3, r1 + 8002aec: 681b ldr r3, [r3, #0] + 8002aee: 4618 mov r0, r3 + 8002af0: f7ff fca2 bl 8002438 + + while (current_x <= current_y) + 8002af4: e061 b.n 8002bba + { + if(current_y > 0) + 8002af6: 68fb ldr r3, [r7, #12] + 8002af8: 2b00 cmp r3, #0 + 8002afa: d021 beq.n 8002b40 + { + BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y); + 8002afc: 68fb ldr r3, [r7, #12] + 8002afe: b29b uxth r3, r3 + 8002b00: 88fa ldrh r2, [r7, #6] + 8002b02: 1ad3 subs r3, r2, r3 + 8002b04: b298 uxth r0, r3 + 8002b06: 693b ldr r3, [r7, #16] + 8002b08: b29a uxth r2, r3 + 8002b0a: 88bb ldrh r3, [r7, #4] + 8002b0c: 4413 add r3, r2 + 8002b0e: b299 uxth r1, r3 + 8002b10: 68fb ldr r3, [r7, #12] + 8002b12: b29b uxth r3, r3 + 8002b14: 005b lsls r3, r3, #1 + 8002b16: b29b uxth r3, r3 + 8002b18: 461a mov r2, r3 + 8002b1a: f7ff fe37 bl 800278c + BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y); + 8002b1e: 68fb ldr r3, [r7, #12] + 8002b20: b29b uxth r3, r3 + 8002b22: 88fa ldrh r2, [r7, #6] + 8002b24: 1ad3 subs r3, r2, r3 + 8002b26: b298 uxth r0, r3 + 8002b28: 693b ldr r3, [r7, #16] + 8002b2a: b29b uxth r3, r3 + 8002b2c: 88ba ldrh r2, [r7, #4] + 8002b2e: 1ad3 subs r3, r2, r3 + 8002b30: b299 uxth r1, r3 + 8002b32: 68fb ldr r3, [r7, #12] + 8002b34: b29b uxth r3, r3 + 8002b36: 005b lsls r3, r3, #1 + 8002b38: b29b uxth r3, r3 + 8002b3a: 461a mov r2, r3 + 8002b3c: f7ff fe26 bl 800278c + } + + if(current_x > 0) + 8002b40: 693b ldr r3, [r7, #16] + 8002b42: 2b00 cmp r3, #0 + 8002b44: d021 beq.n 8002b8a + { + BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x); + 8002b46: 693b ldr r3, [r7, #16] + 8002b48: b29b uxth r3, r3 + 8002b4a: 88fa ldrh r2, [r7, #6] + 8002b4c: 1ad3 subs r3, r2, r3 + 8002b4e: b298 uxth r0, r3 + 8002b50: 68fb ldr r3, [r7, #12] + 8002b52: b29b uxth r3, r3 + 8002b54: 88ba ldrh r2, [r7, #4] + 8002b56: 1ad3 subs r3, r2, r3 + 8002b58: b299 uxth r1, r3 + 8002b5a: 693b ldr r3, [r7, #16] + 8002b5c: b29b uxth r3, r3 + 8002b5e: 005b lsls r3, r3, #1 + 8002b60: b29b uxth r3, r3 + 8002b62: 461a mov r2, r3 + 8002b64: f7ff fe12 bl 800278c + BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x); + 8002b68: 693b ldr r3, [r7, #16] + 8002b6a: b29b uxth r3, r3 + 8002b6c: 88fa ldrh r2, [r7, #6] + 8002b6e: 1ad3 subs r3, r2, r3 + 8002b70: b298 uxth r0, r3 + 8002b72: 68fb ldr r3, [r7, #12] + 8002b74: b29a uxth r2, r3 + 8002b76: 88bb ldrh r3, [r7, #4] + 8002b78: 4413 add r3, r2 + 8002b7a: b299 uxth r1, r3 + 8002b7c: 693b ldr r3, [r7, #16] + 8002b7e: b29b uxth r3, r3 + 8002b80: 005b lsls r3, r3, #1 + 8002b82: b29b uxth r3, r3 + 8002b84: 461a mov r2, r3 + 8002b86: f7ff fe01 bl 800278c + } + if (decision < 0) + 8002b8a: 697b ldr r3, [r7, #20] + 8002b8c: 2b00 cmp r3, #0 + 8002b8e: da06 bge.n 8002b9e + { + decision += (current_x << 2) + 6; + 8002b90: 693b ldr r3, [r7, #16] + 8002b92: 009a lsls r2, r3, #2 + 8002b94: 697b ldr r3, [r7, #20] + 8002b96: 4413 add r3, r2 + 8002b98: 3306 adds r3, #6 + 8002b9a: 617b str r3, [r7, #20] + 8002b9c: e00a b.n 8002bb4 + } + else + { + decision += ((current_x - current_y) << 2) + 10; + 8002b9e: 693a ldr r2, [r7, #16] + 8002ba0: 68fb ldr r3, [r7, #12] + 8002ba2: 1ad3 subs r3, r2, r3 + 8002ba4: 009a lsls r2, r3, #2 + 8002ba6: 697b ldr r3, [r7, #20] + 8002ba8: 4413 add r3, r2 + 8002baa: 330a adds r3, #10 + 8002bac: 617b str r3, [r7, #20] + current_y--; + 8002bae: 68fb ldr r3, [r7, #12] + 8002bb0: 3b01 subs r3, #1 + 8002bb2: 60fb str r3, [r7, #12] + } + current_x++; + 8002bb4: 693b ldr r3, [r7, #16] + 8002bb6: 3301 adds r3, #1 + 8002bb8: 613b str r3, [r7, #16] + while (current_x <= current_y) + 8002bba: 693a ldr r2, [r7, #16] + 8002bbc: 68fb ldr r3, [r7, #12] + 8002bbe: 429a cmp r2, r3 + 8002bc0: d999 bls.n 8002af6 + } + + BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor); + 8002bc2: 4b0b ldr r3, [pc, #44] ; (8002bf0 ) + 8002bc4: 681a ldr r2, [r3, #0] + 8002bc6: 490b ldr r1, [pc, #44] ; (8002bf4 ) + 8002bc8: 4613 mov r3, r2 + 8002bca: 005b lsls r3, r3, #1 + 8002bcc: 4413 add r3, r2 + 8002bce: 009b lsls r3, r3, #2 + 8002bd0: 440b add r3, r1 + 8002bd2: 681b ldr r3, [r3, #0] + 8002bd4: 4618 mov r0, r3 + 8002bd6: f7ff fc2f bl 8002438 + BSP_LCD_DrawCircle(Xpos, Ypos, Radius); + 8002bda: 887a ldrh r2, [r7, #2] + 8002bdc: 88b9 ldrh r1, [r7, #4] + 8002bde: 88fb ldrh r3, [r7, #6] + 8002be0: 4618 mov r0, r3 + 8002be2: f7ff fe31 bl 8002848 +} + 8002be6: bf00 nop + 8002be8: 3718 adds r7, #24 + 8002bea: 46bd mov sp, r7 + 8002bec: bd80 pop {r7, pc} + 8002bee: bf00 nop + 8002bf0: 2000018c .word 0x2000018c + 8002bf4: 20000190 .word 0x20000190 + +08002bf8 : +/** + * @brief Enables the display. + * @retval None + */ +void BSP_LCD_DisplayOn(void) +{ + 8002bf8: b580 push {r7, lr} + 8002bfa: af00 add r7, sp, #0 + /* Display On */ + __HAL_LTDC_ENABLE(&hLtdcHandler); + 8002bfc: 4b0a ldr r3, [pc, #40] ; (8002c28 ) + 8002bfe: 681b ldr r3, [r3, #0] + 8002c00: 699a ldr r2, [r3, #24] + 8002c02: 4b09 ldr r3, [pc, #36] ; (8002c28 ) + 8002c04: 681b ldr r3, [r3, #0] + 8002c06: f042 0201 orr.w r2, r2, #1 + 8002c0a: 619a str r2, [r3, #24] + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */ + 8002c0c: 2201 movs r2, #1 + 8002c0e: f44f 5180 mov.w r1, #4096 ; 0x1000 + 8002c12: 4806 ldr r0, [pc, #24] ; (8002c2c ) + 8002c14: f003 f938 bl 8005e88 + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */ + 8002c18: 2201 movs r2, #1 + 8002c1a: 2108 movs r1, #8 + 8002c1c: 4804 ldr r0, [pc, #16] ; (8002c30 ) + 8002c1e: f003 f933 bl 8005e88 +} + 8002c22: bf00 nop + 8002c24: bd80 pop {r7, pc} + 8002c26: bf00 nop + 8002c28: 200089d8 .word 0x200089d8 + 8002c2c: 40022000 .word 0x40022000 + 8002c30: 40022800 .word 0x40022800 + +08002c34 : + * @param hltdc: LTDC handle + * @param Params + * @retval None + */ +__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params) +{ + 8002c34: b580 push {r7, lr} + 8002c36: b090 sub sp, #64 ; 0x40 + 8002c38: af00 add r7, sp, #0 + 8002c3a: 6078 str r0, [r7, #4] + 8002c3c: 6039 str r1, [r7, #0] + GPIO_InitTypeDef gpio_init_structure; + + /* Enable the LTDC and DMA2D clocks */ + __HAL_RCC_LTDC_CLK_ENABLE(); + 8002c3e: 4b64 ldr r3, [pc, #400] ; (8002dd0 ) + 8002c40: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002c42: 4a63 ldr r2, [pc, #396] ; (8002dd0 ) + 8002c44: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 8002c48: 6453 str r3, [r2, #68] ; 0x44 + 8002c4a: 4b61 ldr r3, [pc, #388] ; (8002dd0 ) + 8002c4c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002c4e: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8002c52: 62bb str r3, [r7, #40] ; 0x28 + 8002c54: 6abb ldr r3, [r7, #40] ; 0x28 + __HAL_RCC_DMA2D_CLK_ENABLE(); + 8002c56: 4b5e ldr r3, [pc, #376] ; (8002dd0 ) + 8002c58: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c5a: 4a5d ldr r2, [pc, #372] ; (8002dd0 ) + 8002c5c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8002c60: 6313 str r3, [r2, #48] ; 0x30 + 8002c62: 4b5b ldr r3, [pc, #364] ; (8002dd0 ) + 8002c64: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c66: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8002c6a: 627b str r3, [r7, #36] ; 0x24 + 8002c6c: 6a7b ldr r3, [r7, #36] ; 0x24 + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8002c6e: 4b58 ldr r3, [pc, #352] ; (8002dd0 ) + 8002c70: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c72: 4a57 ldr r2, [pc, #348] ; (8002dd0 ) + 8002c74: f043 0310 orr.w r3, r3, #16 + 8002c78: 6313 str r3, [r2, #48] ; 0x30 + 8002c7a: 4b55 ldr r3, [pc, #340] ; (8002dd0 ) + 8002c7c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c7e: f003 0310 and.w r3, r3, #16 + 8002c82: 623b str r3, [r7, #32] + 8002c84: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8002c86: 4b52 ldr r3, [pc, #328] ; (8002dd0 ) + 8002c88: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c8a: 4a51 ldr r2, [pc, #324] ; (8002dd0 ) + 8002c8c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002c90: 6313 str r3, [r2, #48] ; 0x30 + 8002c92: 4b4f ldr r3, [pc, #316] ; (8002dd0 ) + 8002c94: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002c96: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002c9a: 61fb str r3, [r7, #28] + 8002c9c: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8002c9e: 4b4c ldr r3, [pc, #304] ; (8002dd0 ) + 8002ca0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002ca2: 4a4b ldr r2, [pc, #300] ; (8002dd0 ) + 8002ca4: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002ca8: 6313 str r3, [r2, #48] ; 0x30 + 8002caa: 4b49 ldr r3, [pc, #292] ; (8002dd0 ) + 8002cac: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cae: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002cb2: 61bb str r3, [r7, #24] + 8002cb4: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8002cb6: 4b46 ldr r3, [pc, #280] ; (8002dd0 ) + 8002cb8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cba: 4a45 ldr r2, [pc, #276] ; (8002dd0 ) + 8002cbc: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002cc0: 6313 str r3, [r2, #48] ; 0x30 + 8002cc2: 4b43 ldr r3, [pc, #268] ; (8002dd0 ) + 8002cc4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cc6: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002cca: 617b str r3, [r7, #20] + 8002ccc: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 8002cce: 4b40 ldr r3, [pc, #256] ; (8002dd0 ) + 8002cd0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cd2: 4a3f ldr r2, [pc, #252] ; (8002dd0 ) + 8002cd4: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002cd8: 6313 str r3, [r2, #48] ; 0x30 + 8002cda: 4b3d ldr r3, [pc, #244] ; (8002dd0 ) + 8002cdc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cde: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002ce2: 613b str r3, [r7, #16] + 8002ce4: 693b ldr r3, [r7, #16] + LCD_DISP_GPIO_CLK_ENABLE(); + 8002ce6: 4b3a ldr r3, [pc, #232] ; (8002dd0 ) + 8002ce8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cea: 4a39 ldr r2, [pc, #228] ; (8002dd0 ) + 8002cec: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002cf0: 6313 str r3, [r2, #48] ; 0x30 + 8002cf2: 4b37 ldr r3, [pc, #220] ; (8002dd0 ) + 8002cf4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002cf6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002cfa: 60fb str r3, [r7, #12] + 8002cfc: 68fb ldr r3, [r7, #12] + LCD_BL_CTRL_GPIO_CLK_ENABLE(); + 8002cfe: 4b34 ldr r3, [pc, #208] ; (8002dd0 ) + 8002d00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002d02: 4a33 ldr r2, [pc, #204] ; (8002dd0 ) + 8002d04: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002d08: 6313 str r3, [r2, #48] ; 0x30 + 8002d0a: 4b31 ldr r3, [pc, #196] ; (8002dd0 ) + 8002d0c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002d0e: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002d12: 60bb str r3, [r7, #8] + 8002d14: 68bb ldr r3, [r7, #8] + + /*** LTDC Pins configuration ***/ + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_4; + 8002d16: 2310 movs r3, #16 + 8002d18: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8002d1a: 2302 movs r3, #2 + 8002d1c: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Pull = GPIO_NOPULL; + 8002d1e: 2300 movs r3, #0 + 8002d20: 637b str r3, [r7, #52] ; 0x34 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 8002d22: 2302 movs r3, #2 + 8002d24: 63bb str r3, [r7, #56] ; 0x38 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8002d26: 230e movs r3, #14 + 8002d28: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + 8002d2a: f107 032c add.w r3, r7, #44 ; 0x2c + 8002d2e: 4619 mov r1, r3 + 8002d30: 4828 ldr r0, [pc, #160] ; (8002dd4 ) + 8002d32: f002 fddd bl 80058f0 + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_12; + 8002d36: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8002d3a: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8002d3c: 2302 movs r3, #2 + 8002d3e: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF9_LTDC; + 8002d40: 2309 movs r3, #9 + 8002d42: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + 8002d44: f107 032c add.w r3, r7, #44 ; 0x2c + 8002d48: 4619 mov r1, r3 + 8002d4a: 4823 ldr r0, [pc, #140] ; (8002dd8 ) + 8002d4c: f002 fdd0 bl 80058f0 + + /* GPIOI LTDC alternate configuration */ + gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \ + 8002d50: f44f 4366 mov.w r3, #58880 ; 0xe600 + 8002d54: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8002d56: 2302 movs r3, #2 + 8002d58: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8002d5a: 230e movs r3, #14 + 8002d5c: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + 8002d5e: f107 032c add.w r3, r7, #44 ; 0x2c + 8002d62: 4619 mov r1, r3 + 8002d64: 481d ldr r0, [pc, #116] ; (8002ddc ) + 8002d66: f002 fdc3 bl 80058f0 + + /* GPIOJ configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \ + 8002d6a: f64e 73ff movw r3, #61439 ; 0xefff + 8002d6e: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8002d70: 2302 movs r3, #2 + 8002d72: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8002d74: 230e movs r3, #14 + 8002d76: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOJ, &gpio_init_structure); + 8002d78: f107 032c add.w r3, r7, #44 ; 0x2c + 8002d7c: 4619 mov r1, r3 + 8002d7e: 4818 ldr r0, [pc, #96] ; (8002de0 ) + 8002d80: f002 fdb6 bl 80058f0 + + /* GPIOK configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \ + 8002d84: 23f7 movs r3, #247 ; 0xf7 + 8002d86: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 8002d88: 2302 movs r3, #2 + 8002d8a: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + 8002d8c: 230e movs r3, #14 + 8002d8e: 63fb str r3, [r7, #60] ; 0x3c + HAL_GPIO_Init(GPIOK, &gpio_init_structure); + 8002d90: f107 032c add.w r3, r7, #44 ; 0x2c + 8002d94: 4619 mov r1, r3 + 8002d96: 4813 ldr r0, [pc, #76] ; (8002de4 ) + 8002d98: f002 fdaa bl 80058f0 + + /* LCD_DISP GPIO configuration */ + gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */ + 8002d9c: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8002da0: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8002da2: 2301 movs r3, #1 + 8002da4: 633b str r3, [r7, #48] ; 0x30 + HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure); + 8002da6: f107 032c add.w r3, r7, #44 ; 0x2c + 8002daa: 4619 mov r1, r3 + 8002dac: 480b ldr r0, [pc, #44] ; (8002ddc ) + 8002dae: f002 fd9f bl 80058f0 + + /* LCD_BL_CTRL GPIO configuration */ + gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */ + 8002db2: 2308 movs r3, #8 + 8002db4: 62fb str r3, [r7, #44] ; 0x2c + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8002db6: 2301 movs r3, #1 + 8002db8: 633b str r3, [r7, #48] ; 0x30 + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure); + 8002dba: f107 032c add.w r3, r7, #44 ; 0x2c + 8002dbe: 4619 mov r1, r3 + 8002dc0: 4808 ldr r0, [pc, #32] ; (8002de4 ) + 8002dc2: f002 fd95 bl 80058f0 +} + 8002dc6: bf00 nop + 8002dc8: 3740 adds r7, #64 ; 0x40 + 8002dca: 46bd mov sp, r7 + 8002dcc: bd80 pop {r7, pc} + 8002dce: bf00 nop + 8002dd0: 40023800 .word 0x40023800 + 8002dd4: 40021000 .word 0x40021000 + 8002dd8: 40021800 .word 0x40021800 + 8002ddc: 40022000 .word 0x40022000 + 8002de0: 40022400 .word 0x40022400 + 8002de4: 40022800 .word 0x40022800 + +08002de8 : + * @note This API is called by BSP_LCD_Init() + * Being __weak it can be overwritten by the application + * @retval None + */ +__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params) +{ + 8002de8: b580 push {r7, lr} + 8002dea: b082 sub sp, #8 + 8002dec: af00 add r7, sp, #0 + 8002dee: 6078 str r0, [r7, #4] + 8002df0: 6039 str r1, [r7, #0] + /* RK043FN48H LCD clock configuration */ + /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */ + /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */ + /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */ + periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + 8002df2: 4b0a ldr r3, [pc, #40] ; (8002e1c ) + 8002df4: 2208 movs r2, #8 + 8002df6: 601a str r2, [r3, #0] + periph_clk_init_struct.PLLSAI.PLLSAIN = 192; + 8002df8: 4b08 ldr r3, [pc, #32] ; (8002e1c ) + 8002dfa: 22c0 movs r2, #192 ; 0xc0 + 8002dfc: 615a str r2, [r3, #20] + periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER; + 8002dfe: 4b07 ldr r3, [pc, #28] ; (8002e1c ) + 8002e00: 2205 movs r2, #5 + 8002e02: 61da str r2, [r3, #28] + periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4; + 8002e04: 4b05 ldr r3, [pc, #20] ; (8002e1c ) + 8002e06: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8002e0a: 62da str r2, [r3, #44] ; 0x2c + HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct); + 8002e0c: 4803 ldr r0, [pc, #12] ; (8002e1c ) + 8002e0e: f004 fe85 bl 8007b1c +} + 8002e12: bf00 nop + 8002e14: 3708 adds r7, #8 + 8002e16: 46bd mov sp, r7 + 8002e18: bd80 pop {r7, pc} + 8002e1a: bf00 nop + 8002e1c: 200001a8 .word 0x200001a8 + +08002e20 : + * @param Ypos: Start column address + * @param c: Pointer to the character data + * @retval None + */ +static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c) +{ + 8002e20: b580 push {r7, lr} + 8002e22: b088 sub sp, #32 + 8002e24: af00 add r7, sp, #0 + 8002e26: 4603 mov r3, r0 + 8002e28: 603a str r2, [r7, #0] + 8002e2a: 80fb strh r3, [r7, #6] + 8002e2c: 460b mov r3, r1 + 8002e2e: 80bb strh r3, [r7, #4] + uint32_t i = 0, j = 0; + 8002e30: 2300 movs r3, #0 + 8002e32: 61fb str r3, [r7, #28] + 8002e34: 2300 movs r3, #0 + 8002e36: 61bb str r3, [r7, #24] + uint16_t height, width; + uint8_t offset; + uint8_t *pchar; + uint32_t line; + + height = DrawProp[ActiveLayer].pFont->Height; + 8002e38: 4b53 ldr r3, [pc, #332] ; (8002f88 ) + 8002e3a: 681a ldr r2, [r3, #0] + 8002e3c: 4953 ldr r1, [pc, #332] ; (8002f8c ) + 8002e3e: 4613 mov r3, r2 + 8002e40: 005b lsls r3, r3, #1 + 8002e42: 4413 add r3, r2 + 8002e44: 009b lsls r3, r3, #2 + 8002e46: 440b add r3, r1 + 8002e48: 3308 adds r3, #8 + 8002e4a: 681b ldr r3, [r3, #0] + 8002e4c: 88db ldrh r3, [r3, #6] + 8002e4e: 827b strh r3, [r7, #18] + width = DrawProp[ActiveLayer].pFont->Width; + 8002e50: 4b4d ldr r3, [pc, #308] ; (8002f88 ) + 8002e52: 681a ldr r2, [r3, #0] + 8002e54: 494d ldr r1, [pc, #308] ; (8002f8c ) + 8002e56: 4613 mov r3, r2 + 8002e58: 005b lsls r3, r3, #1 + 8002e5a: 4413 add r3, r2 + 8002e5c: 009b lsls r3, r3, #2 + 8002e5e: 440b add r3, r1 + 8002e60: 3308 adds r3, #8 + 8002e62: 681b ldr r3, [r3, #0] + 8002e64: 889b ldrh r3, [r3, #4] + 8002e66: 823b strh r3, [r7, #16] + + offset = 8 *((width + 7)/8) - width ; + 8002e68: 8a3b ldrh r3, [r7, #16] + 8002e6a: 3307 adds r3, #7 + 8002e6c: 2b00 cmp r3, #0 + 8002e6e: da00 bge.n 8002e72 + 8002e70: 3307 adds r3, #7 + 8002e72: 10db asrs r3, r3, #3 + 8002e74: b2db uxtb r3, r3 + 8002e76: 00db lsls r3, r3, #3 + 8002e78: b2da uxtb r2, r3 + 8002e7a: 8a3b ldrh r3, [r7, #16] + 8002e7c: b2db uxtb r3, r3 + 8002e7e: 1ad3 subs r3, r2, r3 + 8002e80: 73fb strb r3, [r7, #15] + + for(i = 0; i < height; i++) + 8002e82: 2300 movs r3, #0 + 8002e84: 61fb str r3, [r7, #28] + 8002e86: e076 b.n 8002f76 + { + pchar = ((uint8_t *)c + (width + 7)/8 * i); + 8002e88: 8a3b ldrh r3, [r7, #16] + 8002e8a: 3307 adds r3, #7 + 8002e8c: 2b00 cmp r3, #0 + 8002e8e: da00 bge.n 8002e92 + 8002e90: 3307 adds r3, #7 + 8002e92: 10db asrs r3, r3, #3 + 8002e94: 461a mov r2, r3 + 8002e96: 69fb ldr r3, [r7, #28] + 8002e98: fb03 f302 mul.w r3, r3, r2 + 8002e9c: 683a ldr r2, [r7, #0] + 8002e9e: 4413 add r3, r2 + 8002ea0: 60bb str r3, [r7, #8] + + switch(((width + 7)/8)) + 8002ea2: 8a3b ldrh r3, [r7, #16] + 8002ea4: 3307 adds r3, #7 + 8002ea6: 2b00 cmp r3, #0 + 8002ea8: da00 bge.n 8002eac + 8002eaa: 3307 adds r3, #7 + 8002eac: 10db asrs r3, r3, #3 + 8002eae: 2b01 cmp r3, #1 + 8002eb0: d002 beq.n 8002eb8 + 8002eb2: 2b02 cmp r3, #2 + 8002eb4: d004 beq.n 8002ec0 + 8002eb6: e00c b.n 8002ed2 + { + + case 1: + line = pchar[0]; + 8002eb8: 68bb ldr r3, [r7, #8] + 8002eba: 781b ldrb r3, [r3, #0] + 8002ebc: 617b str r3, [r7, #20] + break; + 8002ebe: e016 b.n 8002eee + + case 2: + line = (pchar[0]<< 8) | pchar[1]; + 8002ec0: 68bb ldr r3, [r7, #8] + 8002ec2: 781b ldrb r3, [r3, #0] + 8002ec4: 021b lsls r3, r3, #8 + 8002ec6: 68ba ldr r2, [r7, #8] + 8002ec8: 3201 adds r2, #1 + 8002eca: 7812 ldrb r2, [r2, #0] + 8002ecc: 4313 orrs r3, r2 + 8002ece: 617b str r3, [r7, #20] + break; + 8002ed0: e00d b.n 8002eee + + case 3: + default: + line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2]; + 8002ed2: 68bb ldr r3, [r7, #8] + 8002ed4: 781b ldrb r3, [r3, #0] + 8002ed6: 041a lsls r2, r3, #16 + 8002ed8: 68bb ldr r3, [r7, #8] + 8002eda: 3301 adds r3, #1 + 8002edc: 781b ldrb r3, [r3, #0] + 8002ede: 021b lsls r3, r3, #8 + 8002ee0: 4313 orrs r3, r2 + 8002ee2: 68ba ldr r2, [r7, #8] + 8002ee4: 3202 adds r2, #2 + 8002ee6: 7812 ldrb r2, [r2, #0] + 8002ee8: 4313 orrs r3, r2 + 8002eea: 617b str r3, [r7, #20] + break; + 8002eec: bf00 nop + } + + for (j = 0; j < width; j++) + 8002eee: 2300 movs r3, #0 + 8002ef0: 61bb str r3, [r7, #24] + 8002ef2: e036 b.n 8002f62 + { + if(line & (1 << (width- j + offset- 1))) + 8002ef4: 8a3a ldrh r2, [r7, #16] + 8002ef6: 69bb ldr r3, [r7, #24] + 8002ef8: 1ad2 subs r2, r2, r3 + 8002efa: 7bfb ldrb r3, [r7, #15] + 8002efc: 4413 add r3, r2 + 8002efe: 3b01 subs r3, #1 + 8002f00: 2201 movs r2, #1 + 8002f02: fa02 f303 lsl.w r3, r2, r3 + 8002f06: 461a mov r2, r3 + 8002f08: 697b ldr r3, [r7, #20] + 8002f0a: 4013 ands r3, r2 + 8002f0c: 2b00 cmp r3, #0 + 8002f0e: d012 beq.n 8002f36 + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor); + 8002f10: 69bb ldr r3, [r7, #24] + 8002f12: b29a uxth r2, r3 + 8002f14: 88fb ldrh r3, [r7, #6] + 8002f16: 4413 add r3, r2 + 8002f18: b298 uxth r0, r3 + 8002f1a: 4b1b ldr r3, [pc, #108] ; (8002f88 ) + 8002f1c: 681a ldr r2, [r3, #0] + 8002f1e: 491b ldr r1, [pc, #108] ; (8002f8c ) + 8002f20: 4613 mov r3, r2 + 8002f22: 005b lsls r3, r3, #1 + 8002f24: 4413 add r3, r2 + 8002f26: 009b lsls r3, r3, #2 + 8002f28: 440b add r3, r1 + 8002f2a: 681a ldr r2, [r3, #0] + 8002f2c: 88bb ldrh r3, [r7, #4] + 8002f2e: 4619 mov r1, r3 + 8002f30: f7ff fd7a bl 8002a28 + 8002f34: e012 b.n 8002f5c + } + else + { + BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor); + 8002f36: 69bb ldr r3, [r7, #24] + 8002f38: b29a uxth r2, r3 + 8002f3a: 88fb ldrh r3, [r7, #6] + 8002f3c: 4413 add r3, r2 + 8002f3e: b298 uxth r0, r3 + 8002f40: 4b11 ldr r3, [pc, #68] ; (8002f88 ) + 8002f42: 681a ldr r2, [r3, #0] + 8002f44: 4911 ldr r1, [pc, #68] ; (8002f8c ) + 8002f46: 4613 mov r3, r2 + 8002f48: 005b lsls r3, r3, #1 + 8002f4a: 4413 add r3, r2 + 8002f4c: 009b lsls r3, r3, #2 + 8002f4e: 440b add r3, r1 + 8002f50: 3304 adds r3, #4 + 8002f52: 681a ldr r2, [r3, #0] + 8002f54: 88bb ldrh r3, [r7, #4] + 8002f56: 4619 mov r1, r3 + 8002f58: f7ff fd66 bl 8002a28 + for (j = 0; j < width; j++) + 8002f5c: 69bb ldr r3, [r7, #24] + 8002f5e: 3301 adds r3, #1 + 8002f60: 61bb str r3, [r7, #24] + 8002f62: 8a3b ldrh r3, [r7, #16] + 8002f64: 69ba ldr r2, [r7, #24] + 8002f66: 429a cmp r2, r3 + 8002f68: d3c4 bcc.n 8002ef4 + } + } + Ypos++; + 8002f6a: 88bb ldrh r3, [r7, #4] + 8002f6c: 3301 adds r3, #1 + 8002f6e: 80bb strh r3, [r7, #4] + for(i = 0; i < height; i++) + 8002f70: 69fb ldr r3, [r7, #28] + 8002f72: 3301 adds r3, #1 + 8002f74: 61fb str r3, [r7, #28] + 8002f76: 8a7b ldrh r3, [r7, #18] + 8002f78: 69fa ldr r2, [r7, #28] + 8002f7a: 429a cmp r2, r3 + 8002f7c: d384 bcc.n 8002e88 + } +} + 8002f7e: bf00 nop + 8002f80: 3720 adds r7, #32 + 8002f82: 46bd mov sp, r7 + 8002f84: bd80 pop {r7, pc} + 8002f86: bf00 nop + 8002f88: 2000018c .word 0x2000018c + 8002f8c: 20000190 .word 0x20000190 + +08002f90 : + * @param OffLine: Offset + * @param ColorIndex: Color index + * @retval None + */ +static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex) +{ + 8002f90: b580 push {r7, lr} + 8002f92: b086 sub sp, #24 + 8002f94: af02 add r7, sp, #8 + 8002f96: 60f8 str r0, [r7, #12] + 8002f98: 60b9 str r1, [r7, #8] + 8002f9a: 607a str r2, [r7, #4] + 8002f9c: 603b str r3, [r7, #0] + /* Register to memory mode with ARGB8888 as color Mode */ + hDma2dHandler.Init.Mode = DMA2D_R2M; + 8002f9e: 4b1e ldr r3, [pc, #120] ; (8003018 ) + 8002fa0: f44f 3240 mov.w r2, #196608 ; 0x30000 + 8002fa4: 605a str r2, [r3, #4] + if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565) + 8002fa6: 4b1d ldr r3, [pc, #116] ; (800301c ) + 8002fa8: 681b ldr r3, [r3, #0] + 8002faa: 4a1d ldr r2, [pc, #116] ; (8003020 ) + 8002fac: 2134 movs r1, #52 ; 0x34 + 8002fae: fb01 f303 mul.w r3, r1, r3 + 8002fb2: 4413 add r3, r2 + 8002fb4: 3348 adds r3, #72 ; 0x48 + 8002fb6: 681b ldr r3, [r3, #0] + 8002fb8: 2b02 cmp r3, #2 + 8002fba: d103 bne.n 8002fc4 + { /* RGB565 format */ + hDma2dHandler.Init.ColorMode = DMA2D_RGB565; + 8002fbc: 4b16 ldr r3, [pc, #88] ; (8003018 ) + 8002fbe: 2202 movs r2, #2 + 8002fc0: 609a str r2, [r3, #8] + 8002fc2: e002 b.n 8002fca + } + else + { /* ARGB8888 format */ + hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888; + 8002fc4: 4b14 ldr r3, [pc, #80] ; (8003018 ) + 8002fc6: 2200 movs r2, #0 + 8002fc8: 609a str r2, [r3, #8] + } + hDma2dHandler.Init.OutputOffset = OffLine; + 8002fca: 4a13 ldr r2, [pc, #76] ; (8003018 ) + 8002fcc: 69bb ldr r3, [r7, #24] + 8002fce: 60d3 str r3, [r2, #12] + + hDma2dHandler.Instance = DMA2D; + 8002fd0: 4b11 ldr r3, [pc, #68] ; (8003018 ) + 8002fd2: 4a14 ldr r2, [pc, #80] ; (8003024 ) + 8002fd4: 601a str r2, [r3, #0] + + /* DMA2D Initialization */ + if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK) + 8002fd6: 4810 ldr r0, [pc, #64] ; (8003018 ) + 8002fd8: f002 f9fe bl 80053d8 + 8002fdc: 4603 mov r3, r0 + 8002fde: 2b00 cmp r3, #0 + 8002fe0: d115 bne.n 800300e + { + if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK) + 8002fe2: 68f9 ldr r1, [r7, #12] + 8002fe4: 480c ldr r0, [pc, #48] ; (8003018 ) + 8002fe6: f002 fb55 bl 8005694 + 8002fea: 4603 mov r3, r0 + 8002fec: 2b00 cmp r3, #0 + 8002fee: d10e bne.n 800300e + { + if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK) + 8002ff0: 68ba ldr r2, [r7, #8] + 8002ff2: 683b ldr r3, [r7, #0] + 8002ff4: 9300 str r3, [sp, #0] + 8002ff6: 687b ldr r3, [r7, #4] + 8002ff8: 69f9 ldr r1, [r7, #28] + 8002ffa: 4807 ldr r0, [pc, #28] ; (8003018 ) + 8002ffc: f002 fa36 bl 800546c + 8003000: 4603 mov r3, r0 + 8003002: 2b00 cmp r3, #0 + 8003004: d103 bne.n 800300e + { + /* Polling For DMA transfer */ + HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10); + 8003006: 210a movs r1, #10 + 8003008: 4803 ldr r0, [pc, #12] ; (8003018 ) + 800300a: f002 fa5a bl 80054c2 + } + } + } +} + 800300e: bf00 nop + 8003010: 3710 adds r7, #16 + 8003012: 46bd mov sp, r7 + 8003014: bd80 pop {r7, pc} + 8003016: bf00 nop + 8003018: 2000014c .word 0x2000014c + 800301c: 2000018c .word 0x2000018c + 8003020: 200089d8 .word 0x200089d8 + 8003024: 4002b000 .word 0x4002b000 + +08003028 : +/** + * @brief Initializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Init(void) +{ + 8003028: b580 push {r7, lr} + 800302a: af00 add r7, sp, #0 + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device configuration */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + 800302c: 4b29 ldr r3, [pc, #164] ; (80030d4 ) + 800302e: 4a2a ldr r2, [pc, #168] ; (80030d8 ) + 8003030: 601a str r2, [r3, #0] + + /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ + Timing.LoadToActiveDelay = 2; + 8003032: 4b2a ldr r3, [pc, #168] ; (80030dc ) + 8003034: 2202 movs r2, #2 + 8003036: 601a str r2, [r3, #0] + Timing.ExitSelfRefreshDelay = 7; + 8003038: 4b28 ldr r3, [pc, #160] ; (80030dc ) + 800303a: 2207 movs r2, #7 + 800303c: 605a str r2, [r3, #4] + Timing.SelfRefreshTime = 4; + 800303e: 4b27 ldr r3, [pc, #156] ; (80030dc ) + 8003040: 2204 movs r2, #4 + 8003042: 609a str r2, [r3, #8] + Timing.RowCycleDelay = 7; + 8003044: 4b25 ldr r3, [pc, #148] ; (80030dc ) + 8003046: 2207 movs r2, #7 + 8003048: 60da str r2, [r3, #12] + Timing.WriteRecoveryTime = 2; + 800304a: 4b24 ldr r3, [pc, #144] ; (80030dc ) + 800304c: 2202 movs r2, #2 + 800304e: 611a str r2, [r3, #16] + Timing.RPDelay = 2; + 8003050: 4b22 ldr r3, [pc, #136] ; (80030dc ) + 8003052: 2202 movs r2, #2 + 8003054: 615a str r2, [r3, #20] + Timing.RCDDelay = 2; + 8003056: 4b21 ldr r3, [pc, #132] ; (80030dc ) + 8003058: 2202 movs r2, #2 + 800305a: 619a str r2, [r3, #24] + + sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; + 800305c: 4b1d ldr r3, [pc, #116] ; (80030d4 ) + 800305e: 2200 movs r2, #0 + 8003060: 605a str r2, [r3, #4] + sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + 8003062: 4b1c ldr r3, [pc, #112] ; (80030d4 ) + 8003064: 2200 movs r2, #0 + 8003066: 609a str r2, [r3, #8] + sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + 8003068: 4b1a ldr r3, [pc, #104] ; (80030d4 ) + 800306a: 2204 movs r2, #4 + 800306c: 60da str r2, [r3, #12] + sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + 800306e: 4b19 ldr r3, [pc, #100] ; (80030d4 ) + 8003070: 2210 movs r2, #16 + 8003072: 611a str r2, [r3, #16] + sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + 8003074: 4b17 ldr r3, [pc, #92] ; (80030d4 ) + 8003076: 2240 movs r2, #64 ; 0x40 + 8003078: 615a str r2, [r3, #20] + sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + 800307a: 4b16 ldr r3, [pc, #88] ; (80030d4 ) + 800307c: f44f 7280 mov.w r2, #256 ; 0x100 + 8003080: 619a str r2, [r3, #24] + sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + 8003082: 4b14 ldr r3, [pc, #80] ; (80030d4 ) + 8003084: 2200 movs r2, #0 + 8003086: 61da str r2, [r3, #28] + sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + 8003088: 4b12 ldr r3, [pc, #72] ; (80030d4 ) + 800308a: f44f 6200 mov.w r2, #2048 ; 0x800 + 800308e: 621a str r2, [r3, #32] + sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + 8003090: 4b10 ldr r3, [pc, #64] ; (80030d4 ) + 8003092: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8003096: 625a str r2, [r3, #36] ; 0x24 + sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + 8003098: 4b0e ldr r3, [pc, #56] ; (80030d4 ) + 800309a: 2200 movs r2, #0 + 800309c: 629a str r2, [r3, #40] ; 0x28 + + /* SDRAM controller initialization */ + + BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + 800309e: 2100 movs r1, #0 + 80030a0: 480c ldr r0, [pc, #48] ; (80030d4 ) + 80030a2: f000 f87f bl 80031a4 + + if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + 80030a6: 490d ldr r1, [pc, #52] ; (80030dc ) + 80030a8: 480a ldr r0, [pc, #40] ; (80030d4 ) + 80030aa: f005 fce7 bl 8008a7c + 80030ae: 4603 mov r3, r0 + 80030b0: 2b00 cmp r3, #0 + 80030b2: d003 beq.n 80030bc + { + sdramstatus = SDRAM_ERROR; + 80030b4: 4b0a ldr r3, [pc, #40] ; (80030e0 ) + 80030b6: 2201 movs r2, #1 + 80030b8: 701a strb r2, [r3, #0] + 80030ba: e002 b.n 80030c2 + } + else + { + sdramstatus = SDRAM_OK; + 80030bc: 4b08 ldr r3, [pc, #32] ; (80030e0 ) + 80030be: 2200 movs r2, #0 + 80030c0: 701a strb r2, [r3, #0] + } + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + 80030c2: f240 6003 movw r0, #1539 ; 0x603 + 80030c6: f000 f80d bl 80030e4 + + return sdramstatus; + 80030ca: 4b05 ldr r3, [pc, #20] ; (80030e0 ) + 80030cc: 781b ldrb r3, [r3, #0] +} + 80030ce: 4618 mov r0, r3 + 80030d0: bd80 pop {r7, pc} + 80030d2: bf00 nop + 80030d4: 20008a80 .word 0x20008a80 + 80030d8: a0000140 .word 0xa0000140 + 80030dc: 2000022c .word 0x2000022c + 80030e0: 20000038 .word 0x20000038 + +080030e4 : + * @brief Programs the SDRAM device. + * @param RefreshCount: SDRAM refresh counter value + * @retval None + */ +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +{ + 80030e4: b580 push {r7, lr} + 80030e6: b084 sub sp, #16 + 80030e8: af00 add r7, sp, #0 + 80030ea: 6078 str r0, [r7, #4] + __IO uint32_t tmpmrd = 0; + 80030ec: 2300 movs r3, #0 + 80030ee: 60fb str r3, [r7, #12] + + /* Step 1: Configure a clock configuration enable command */ + Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + 80030f0: 4b2a ldr r3, [pc, #168] ; (800319c ) + 80030f2: 2201 movs r2, #1 + 80030f4: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 80030f6: 4b29 ldr r3, [pc, #164] ; (800319c ) + 80030f8: 2210 movs r2, #16 + 80030fa: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 80030fc: 4b27 ldr r3, [pc, #156] ; (800319c ) + 80030fe: 2201 movs r2, #1 + 8003100: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 8003102: 4b26 ldr r3, [pc, #152] ; (800319c ) + 8003104: 2200 movs r2, #0 + 8003106: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 8003108: f64f 72ff movw r2, #65535 ; 0xffff + 800310c: 4923 ldr r1, [pc, #140] ; (800319c ) + 800310e: 4824 ldr r0, [pc, #144] ; (80031a0 ) + 8003110: f005 fce8 bl 8008ae4 + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + 8003114: 2001 movs r0, #1 + 8003116: f001 f9f7 bl 8004508 + + /* Step 3: Configure a PALL (precharge all) command */ + Command.CommandMode = FMC_SDRAM_CMD_PALL; + 800311a: 4b20 ldr r3, [pc, #128] ; (800319c ) + 800311c: 2202 movs r2, #2 + 800311e: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 8003120: 4b1e ldr r3, [pc, #120] ; (800319c ) + 8003122: 2210 movs r2, #16 + 8003124: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 8003126: 4b1d ldr r3, [pc, #116] ; (800319c ) + 8003128: 2201 movs r2, #1 + 800312a: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 800312c: 4b1b ldr r3, [pc, #108] ; (800319c ) + 800312e: 2200 movs r2, #0 + 8003130: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 8003132: f64f 72ff movw r2, #65535 ; 0xffff + 8003136: 4919 ldr r1, [pc, #100] ; (800319c ) + 8003138: 4819 ldr r0, [pc, #100] ; (80031a0 ) + 800313a: f005 fcd3 bl 8008ae4 + + /* Step 4: Configure an Auto Refresh command */ + Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + 800313e: 4b17 ldr r3, [pc, #92] ; (800319c ) + 8003140: 2203 movs r2, #3 + 8003142: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 8003144: 4b15 ldr r3, [pc, #84] ; (800319c ) + 8003146: 2210 movs r2, #16 + 8003148: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 8; + 800314a: 4b14 ldr r3, [pc, #80] ; (800319c ) + 800314c: 2208 movs r2, #8 + 800314e: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = 0; + 8003150: 4b12 ldr r3, [pc, #72] ; (800319c ) + 8003152: 2200 movs r2, #0 + 8003154: 60da str r2, [r3, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 8003156: f64f 72ff movw r2, #65535 ; 0xffff + 800315a: 4910 ldr r1, [pc, #64] ; (800319c ) + 800315c: 4810 ldr r0, [pc, #64] ; (80031a0 ) + 800315e: f005 fcc1 bl 8008ae4 + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + 8003162: f44f 7308 mov.w r3, #544 ; 0x220 + 8003166: 60fb str r3, [r7, #12] + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + 8003168: 4b0c ldr r3, [pc, #48] ; (800319c ) + 800316a: 2204 movs r2, #4 + 800316c: 601a str r2, [r3, #0] + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + 800316e: 4b0b ldr r3, [pc, #44] ; (800319c ) + 8003170: 2210 movs r2, #16 + 8003172: 605a str r2, [r3, #4] + Command.AutoRefreshNumber = 1; + 8003174: 4b09 ldr r3, [pc, #36] ; (800319c ) + 8003176: 2201 movs r2, #1 + 8003178: 609a str r2, [r3, #8] + Command.ModeRegisterDefinition = tmpmrd; + 800317a: 68fb ldr r3, [r7, #12] + 800317c: 4a07 ldr r2, [pc, #28] ; (800319c ) + 800317e: 60d3 str r3, [r2, #12] + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + 8003180: f64f 72ff movw r2, #65535 ; 0xffff + 8003184: 4905 ldr r1, [pc, #20] ; (800319c ) + 8003186: 4806 ldr r0, [pc, #24] ; (80031a0 ) + 8003188: f005 fcac bl 8008ae4 + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); + 800318c: 6879 ldr r1, [r7, #4] + 800318e: 4804 ldr r0, [pc, #16] ; (80031a0 ) + 8003190: f005 fcd3 bl 8008b3a +} + 8003194: bf00 nop + 8003196: 3710 adds r7, #16 + 8003198: 46bd mov sp, r7 + 800319a: bd80 pop {r7, pc} + 800319c: 20000248 .word 0x20000248 + 80031a0: 20008a80 .word 0x20008a80 + +080031a4 : + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + 80031a4: b580 push {r7, lr} + 80031a6: b090 sub sp, #64 ; 0x40 + 80031a8: af00 add r7, sp, #0 + 80031aa: 6078 str r0, [r7, #4] + 80031ac: 6039 str r1, [r7, #0] + static DMA_HandleTypeDef dma_handle; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + 80031ae: 4b70 ldr r3, [pc, #448] ; (8003370 ) + 80031b0: 6b9b ldr r3, [r3, #56] ; 0x38 + 80031b2: 4a6f ldr r2, [pc, #444] ; (8003370 ) + 80031b4: f043 0301 orr.w r3, r3, #1 + 80031b8: 6393 str r3, [r2, #56] ; 0x38 + 80031ba: 4b6d ldr r3, [pc, #436] ; (8003370 ) + 80031bc: 6b9b ldr r3, [r3, #56] ; 0x38 + 80031be: f003 0301 and.w r3, r3, #1 + 80031c2: 62bb str r3, [r7, #40] ; 0x28 + 80031c4: 6abb ldr r3, [r7, #40] ; 0x28 + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + 80031c6: 4b6a ldr r3, [pc, #424] ; (8003370 ) + 80031c8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031ca: 4a69 ldr r2, [pc, #420] ; (8003370 ) + 80031cc: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 80031d0: 6313 str r3, [r2, #48] ; 0x30 + 80031d2: 4b67 ldr r3, [pc, #412] ; (8003370 ) + 80031d4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031d6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80031da: 627b str r3, [r7, #36] ; 0x24 + 80031dc: 6a7b ldr r3, [r7, #36] ; 0x24 + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 80031de: 4b64 ldr r3, [pc, #400] ; (8003370 ) + 80031e0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031e2: 4a63 ldr r2, [pc, #396] ; (8003370 ) + 80031e4: f043 0304 orr.w r3, r3, #4 + 80031e8: 6313 str r3, [r2, #48] ; 0x30 + 80031ea: 4b61 ldr r3, [pc, #388] ; (8003370 ) + 80031ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031ee: f003 0304 and.w r3, r3, #4 + 80031f2: 623b str r3, [r7, #32] + 80031f4: 6a3b ldr r3, [r7, #32] + __HAL_RCC_GPIOD_CLK_ENABLE(); + 80031f6: 4b5e ldr r3, [pc, #376] ; (8003370 ) + 80031f8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80031fa: 4a5d ldr r2, [pc, #372] ; (8003370 ) + 80031fc: f043 0308 orr.w r3, r3, #8 + 8003200: 6313 str r3, [r2, #48] ; 0x30 + 8003202: 4b5b ldr r3, [pc, #364] ; (8003370 ) + 8003204: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003206: f003 0308 and.w r3, r3, #8 + 800320a: 61fb str r3, [r7, #28] + 800320c: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOE_CLK_ENABLE(); + 800320e: 4b58 ldr r3, [pc, #352] ; (8003370 ) + 8003210: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003212: 4a57 ldr r2, [pc, #348] ; (8003370 ) + 8003214: f043 0310 orr.w r3, r3, #16 + 8003218: 6313 str r3, [r2, #48] ; 0x30 + 800321a: 4b55 ldr r3, [pc, #340] ; (8003370 ) + 800321c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800321e: f003 0310 and.w r3, r3, #16 + 8003222: 61bb str r3, [r7, #24] + 8003224: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8003226: 4b52 ldr r3, [pc, #328] ; (8003370 ) + 8003228: 6b1b ldr r3, [r3, #48] ; 0x30 + 800322a: 4a51 ldr r2, [pc, #324] ; (8003370 ) + 800322c: f043 0320 orr.w r3, r3, #32 + 8003230: 6313 str r3, [r2, #48] ; 0x30 + 8003232: 4b4f ldr r3, [pc, #316] ; (8003370 ) + 8003234: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003236: f003 0320 and.w r3, r3, #32 + 800323a: 617b str r3, [r7, #20] + 800323c: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 800323e: 4b4c ldr r3, [pc, #304] ; (8003370 ) + 8003240: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003242: 4a4b ldr r2, [pc, #300] ; (8003370 ) + 8003244: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8003248: 6313 str r3, [r2, #48] ; 0x30 + 800324a: 4b49 ldr r3, [pc, #292] ; (8003370 ) + 800324c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800324e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003252: 613b str r3, [r7, #16] + 8003254: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8003256: 4b46 ldr r3, [pc, #280] ; (8003370 ) + 8003258: 6b1b ldr r3, [r3, #48] ; 0x30 + 800325a: 4a45 ldr r2, [pc, #276] ; (8003370 ) + 800325c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8003260: 6313 str r3, [r2, #48] ; 0x30 + 8003262: 4b43 ldr r3, [pc, #268] ; (8003370 ) + 8003264: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003266: f003 0380 and.w r3, r3, #128 ; 0x80 + 800326a: 60fb str r3, [r7, #12] + 800326c: 68fb ldr r3, [r7, #12] + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + 800326e: 2302 movs r3, #2 + 8003270: 633b str r3, [r7, #48] ; 0x30 + gpio_init_structure.Pull = GPIO_PULLUP; + 8003272: 2301 movs r3, #1 + 8003274: 637b str r3, [r7, #52] ; 0x34 + gpio_init_structure.Speed = GPIO_SPEED_FAST; + 8003276: 2302 movs r3, #2 + 8003278: 63bb str r3, [r7, #56] ; 0x38 + gpio_init_structure.Alternate = GPIO_AF12_FMC; + 800327a: 230c movs r3, #12 + 800327c: 63fb str r3, [r7, #60] ; 0x3c + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + 800327e: 2308 movs r3, #8 + 8003280: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + 8003282: f107 032c add.w r3, r7, #44 ; 0x2c + 8003286: 4619 mov r1, r3 + 8003288: 483a ldr r0, [pc, #232] ; (8003374 ) + 800328a: f002 fb31 bl 80058f0 + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | + 800328e: f24c 7303 movw r3, #50947 ; 0xc703 + 8003292: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + 8003294: f107 032c add.w r3, r7, #44 ; 0x2c + 8003298: 4619 mov r1, r3 + 800329a: 4837 ldr r0, [pc, #220] ; (8003378 ) + 800329c: f002 fb28 bl 80058f0 + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + 80032a0: f64f 7383 movw r3, #65411 ; 0xff83 + 80032a4: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + 80032a6: f107 032c add.w r3, r7, #44 ; 0x2c + 80032aa: 4619 mov r1, r3 + 80032ac: 4833 ldr r0, [pc, #204] ; (800337c ) + 80032ae: f002 fb1f bl 80058f0 + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + 80032b2: f64f 033f movw r3, #63551 ; 0xf83f + 80032b6: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + 80032b8: f107 032c add.w r3, r7, #44 ; 0x2c + 80032bc: 4619 mov r1, r3 + 80032be: 4830 ldr r0, [pc, #192] ; (8003380 ) + 80032c0: f002 fb16 bl 80058f0 + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + 80032c4: f248 1333 movw r3, #33075 ; 0x8133 + 80032c8: 62fb str r3, [r7, #44] ; 0x2c + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + 80032ca: f107 032c add.w r3, r7, #44 ; 0x2c + 80032ce: 4619 mov r1, r3 + 80032d0: 482c ldr r0, [pc, #176] ; (8003384 ) + 80032d2: f002 fb0d bl 80058f0 + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + 80032d6: 2328 movs r3, #40 ; 0x28 + 80032d8: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + 80032da: f107 032c add.w r3, r7, #44 ; 0x2c + 80032de: 4619 mov r1, r3 + 80032e0: 4829 ldr r0, [pc, #164] ; (8003388 ) + 80032e2: f002 fb05 bl 80058f0 + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + 80032e6: 4b29 ldr r3, [pc, #164] ; (800338c ) + 80032e8: 2200 movs r2, #0 + 80032ea: 605a str r2, [r3, #4] + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + 80032ec: 4b27 ldr r3, [pc, #156] ; (800338c ) + 80032ee: 2280 movs r2, #128 ; 0x80 + 80032f0: 609a str r2, [r3, #8] + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + 80032f2: 4b26 ldr r3, [pc, #152] ; (800338c ) + 80032f4: f44f 7200 mov.w r2, #512 ; 0x200 + 80032f8: 60da str r2, [r3, #12] + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + 80032fa: 4b24 ldr r3, [pc, #144] ; (800338c ) + 80032fc: f44f 6280 mov.w r2, #1024 ; 0x400 + 8003300: 611a str r2, [r3, #16] + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + 8003302: 4b22 ldr r3, [pc, #136] ; (800338c ) + 8003304: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8003308: 615a str r2, [r3, #20] + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + 800330a: 4b20 ldr r3, [pc, #128] ; (800338c ) + 800330c: f44f 4280 mov.w r2, #16384 ; 0x4000 + 8003310: 619a str r2, [r3, #24] + dma_handle.Init.Mode = DMA_NORMAL; + 8003312: 4b1e ldr r3, [pc, #120] ; (800338c ) + 8003314: 2200 movs r2, #0 + 8003316: 61da str r2, [r3, #28] + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + 8003318: 4b1c ldr r3, [pc, #112] ; (800338c ) + 800331a: f44f 3200 mov.w r2, #131072 ; 0x20000 + 800331e: 621a str r2, [r3, #32] + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + 8003320: 4b1a ldr r3, [pc, #104] ; (800338c ) + 8003322: 2200 movs r2, #0 + 8003324: 625a str r2, [r3, #36] ; 0x24 + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + 8003326: 4b19 ldr r3, [pc, #100] ; (800338c ) + 8003328: 2203 movs r2, #3 + 800332a: 629a str r2, [r3, #40] ; 0x28 + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + 800332c: 4b17 ldr r3, [pc, #92] ; (800338c ) + 800332e: 2200 movs r2, #0 + 8003330: 62da str r2, [r3, #44] ; 0x2c + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + 8003332: 4b16 ldr r3, [pc, #88] ; (800338c ) + 8003334: 2200 movs r2, #0 + 8003336: 631a str r2, [r3, #48] ; 0x30 + + dma_handle.Instance = SDRAM_DMAx_STREAM; + 8003338: 4b14 ldr r3, [pc, #80] ; (800338c ) + 800333a: 4a15 ldr r2, [pc, #84] ; (8003390 ) + 800333c: 601a str r2, [r3, #0] + + /* Associate the DMA handle */ + __HAL_LINKDMA(hsdram, hdma, dma_handle); + 800333e: 687b ldr r3, [r7, #4] + 8003340: 4a12 ldr r2, [pc, #72] ; (800338c ) + 8003342: 631a str r2, [r3, #48] ; 0x30 + 8003344: 4a11 ldr r2, [pc, #68] ; (800338c ) + 8003346: 687b ldr r3, [r7, #4] + 8003348: 6393 str r3, [r2, #56] ; 0x38 + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + 800334a: 4810 ldr r0, [pc, #64] ; (800338c ) + 800334c: f001 ff36 bl 80051bc + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + 8003350: 480e ldr r0, [pc, #56] ; (800338c ) + 8003352: f001 fe85 bl 8005060 + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0); + 8003356: 2200 movs r2, #0 + 8003358: 210f movs r1, #15 + 800335a: 2038 movs r0, #56 ; 0x38 + 800335c: f001 fd88 bl 8004e70 + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); + 8003360: 2038 movs r0, #56 ; 0x38 + 8003362: f001 fda1 bl 8004ea8 +} + 8003366: bf00 nop + 8003368: 3740 adds r7, #64 ; 0x40 + 800336a: 46bd mov sp, r7 + 800336c: bd80 pop {r7, pc} + 800336e: bf00 nop + 8003370: 40023800 .word 0x40023800 + 8003374: 40020800 .word 0x40020800 + 8003378: 40020c00 .word 0x40020c00 + 800337c: 40021000 .word 0x40021000 + 8003380: 40021400 .word 0x40021400 + 8003384: 40021800 .word 0x40021800 + 8003388: 40021c00 .word 0x40021c00 + 800338c: 20000258 .word 0x20000258 + 8003390: 40026410 .word 0x40026410 + +08003394 : + * @param ts_SizeX: Maximum X size of the TS area on LCD + * @param ts_SizeY: Maximum Y size of the TS area on LCD + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY) +{ + 8003394: b580 push {r7, lr} + 8003396: b084 sub sp, #16 + 8003398: af00 add r7, sp, #0 + 800339a: 4603 mov r3, r0 + 800339c: 460a mov r2, r1 + 800339e: 80fb strh r3, [r7, #6] + 80033a0: 4613 mov r3, r2 + 80033a2: 80bb strh r3, [r7, #4] + uint8_t status = TS_OK; + 80033a4: 2300 movs r3, #0 + 80033a6: 73fb strb r3, [r7, #15] + tsXBoundary = ts_SizeX; + 80033a8: 4a14 ldr r2, [pc, #80] ; (80033fc ) + 80033aa: 88fb ldrh r3, [r7, #6] + 80033ac: 8013 strh r3, [r2, #0] + tsYBoundary = ts_SizeY; + 80033ae: 4a14 ldr r2, [pc, #80] ; (8003400 ) + 80033b0: 88bb ldrh r3, [r7, #4] + 80033b2: 8013 strh r3, [r2, #0] + + /* Read ID and verify if the touch screen driver is ready */ + ft5336_ts_drv.Init(TS_I2C_ADDRESS); + 80033b4: 4b13 ldr r3, [pc, #76] ; (8003404 ) + 80033b6: 681b ldr r3, [r3, #0] + 80033b8: 2070 movs r0, #112 ; 0x70 + 80033ba: 4798 blx r3 + if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE) + 80033bc: 4b11 ldr r3, [pc, #68] ; (8003404 ) + 80033be: 685b ldr r3, [r3, #4] + 80033c0: 2070 movs r0, #112 ; 0x70 + 80033c2: 4798 blx r3 + 80033c4: 4603 mov r3, r0 + 80033c6: 2b51 cmp r3, #81 ; 0x51 + 80033c8: d111 bne.n 80033ee + { + /* Initialize the TS driver structure */ + tsDriver = &ft5336_ts_drv; + 80033ca: 4b0f ldr r3, [pc, #60] ; (8003408 ) + 80033cc: 4a0d ldr r2, [pc, #52] ; (8003404 ) + 80033ce: 601a str r2, [r3, #0] + I2cAddress = TS_I2C_ADDRESS; + 80033d0: 4b0e ldr r3, [pc, #56] ; (800340c ) + 80033d2: 2270 movs r2, #112 ; 0x70 + 80033d4: 701a strb r2, [r3, #0] + tsOrientation = TS_SWAP_XY; + 80033d6: 4b0e ldr r3, [pc, #56] ; (8003410 ) + 80033d8: 2208 movs r2, #8 + 80033da: 701a strb r2, [r3, #0] + + /* Initialize the TS driver */ + tsDriver->Start(I2cAddress); + 80033dc: 4b0a ldr r3, [pc, #40] ; (8003408 ) + 80033de: 681b ldr r3, [r3, #0] + 80033e0: 68db ldr r3, [r3, #12] + 80033e2: 4a0a ldr r2, [pc, #40] ; (800340c ) + 80033e4: 7812 ldrb r2, [r2, #0] + 80033e6: b292 uxth r2, r2 + 80033e8: 4610 mov r0, r2 + 80033ea: 4798 blx r3 + 80033ec: e001 b.n 80033f2 + } + else + { + status = TS_DEVICE_NOT_FOUND; + 80033ee: 2303 movs r3, #3 + 80033f0: 73fb strb r3, [r7, #15] + } + + return status; + 80033f2: 7bfb ldrb r3, [r7, #15] +} + 80033f4: 4618 mov r0, r3 + 80033f6: 3710 adds r7, #16 + 80033f8: 46bd mov sp, r7 + 80033fa: bd80 pop {r7, pc} + 80033fc: 200002bc .word 0x200002bc + 8003400: 200002be .word 0x200002be + 8003404: 20000000 .word 0x20000000 + 8003408: 200002b8 .word 0x200002b8 + 800340c: 200002c1 .word 0x200002c1 + 8003410: 200002c0 .word 0x200002c0 + +08003414 : + * @brief Returns status and positions of the touch screen. + * @param TS_State: Pointer to touch screen current state structure + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State) +{ + 8003414: b590 push {r4, r7, lr} + 8003416: b097 sub sp, #92 ; 0x5c + 8003418: af02 add r7, sp, #8 + 800341a: 6078 str r0, [r7, #4] + static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0}; + static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0}; + uint8_t ts_status = TS_OK; + 800341c: 2300 movs r3, #0 + 800341e: f887 304f strb.w r3, [r7, #79] ; 0x4f + uint16_t brute_y[TS_MAX_NB_TOUCH]; + uint16_t x_diff; + uint16_t y_diff; + uint32_t index; +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + uint32_t weight = 0; + 8003422: 2300 movs r3, #0 + 8003424: 613b str r3, [r7, #16] + uint32_t area = 0; + 8003426: 2300 movs r3, #0 + 8003428: 60fb str r3, [r7, #12] + uint32_t event = 0; + 800342a: 2300 movs r3, #0 + 800342c: 60bb str r3, [r7, #8] +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + + /* Check and update the number of touches active detected */ + TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress); + 800342e: 4b97 ldr r3, [pc, #604] ; (800368c ) + 8003430: 681b ldr r3, [r3, #0] + 8003432: 691b ldr r3, [r3, #16] + 8003434: 4a96 ldr r2, [pc, #600] ; (8003690 ) + 8003436: 7812 ldrb r2, [r2, #0] + 8003438: b292 uxth r2, r2 + 800343a: 4610 mov r0, r2 + 800343c: 4798 blx r3 + 800343e: 4603 mov r3, r0 + 8003440: 461a mov r2, r3 + 8003442: 687b ldr r3, [r7, #4] + 8003444: 701a strb r2, [r3, #0] + + if(TS_State->touchDetected) + 8003446: 687b ldr r3, [r7, #4] + 8003448: 781b ldrb r3, [r3, #0] + 800344a: 2b00 cmp r3, #0 + 800344c: f000 81a8 beq.w 80037a0 + { + for(index=0; index < TS_State->touchDetected; index++) + 8003450: 2300 movs r3, #0 + 8003452: 64bb str r3, [r7, #72] ; 0x48 + 8003454: e197 b.n 8003786 + { + /* Get each touch coordinates */ + tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index])); + 8003456: 4b8d ldr r3, [pc, #564] ; (800368c ) + 8003458: 681b ldr r3, [r3, #0] + 800345a: 695b ldr r3, [r3, #20] + 800345c: 4a8c ldr r2, [pc, #560] ; (8003690 ) + 800345e: 7812 ldrb r2, [r2, #0] + 8003460: b290 uxth r0, r2 + 8003462: f107 0120 add.w r1, r7, #32 + 8003466: 6cba ldr r2, [r7, #72] ; 0x48 + 8003468: 0052 lsls r2, r2, #1 + 800346a: 188c adds r4, r1, r2 + 800346c: f107 0114 add.w r1, r7, #20 + 8003470: 6cba ldr r2, [r7, #72] ; 0x48 + 8003472: 0052 lsls r2, r2, #1 + 8003474: 440a add r2, r1 + 8003476: 4621 mov r1, r4 + 8003478: 4798 blx r3 + + if(tsOrientation == TS_SWAP_NONE) + 800347a: 4b86 ldr r3, [pc, #536] ; (8003694 ) + 800347c: 781b ldrb r3, [r3, #0] + 800347e: 2b01 cmp r3, #1 + 8003480: d11b bne.n 80034ba + { + x[index] = brute_x[index]; + 8003482: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003484: 005b lsls r3, r3, #1 + 8003486: f107 0250 add.w r2, r7, #80 ; 0x50 + 800348a: 4413 add r3, r2 + 800348c: f833 2c30 ldrh.w r2, [r3, #-48] + 8003490: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003492: 005b lsls r3, r3, #1 + 8003494: f107 0150 add.w r1, r7, #80 ; 0x50 + 8003498: 440b add r3, r1 + 800349a: f823 2c18 strh.w r2, [r3, #-24] + y[index] = brute_y[index]; + 800349e: 6cbb ldr r3, [r7, #72] ; 0x48 + 80034a0: 005b lsls r3, r3, #1 + 80034a2: f107 0250 add.w r2, r7, #80 ; 0x50 + 80034a6: 4413 add r3, r2 + 80034a8: f833 2c3c ldrh.w r2, [r3, #-60] + 80034ac: 6cbb ldr r3, [r7, #72] ; 0x48 + 80034ae: 005b lsls r3, r3, #1 + 80034b0: f107 0150 add.w r1, r7, #80 ; 0x50 + 80034b4: 440b add r3, r1 + 80034b6: f823 2c24 strh.w r2, [r3, #-36] + } + + if(tsOrientation & TS_SWAP_X) + 80034ba: 4b76 ldr r3, [pc, #472] ; (8003694 ) + 80034bc: 781b ldrb r3, [r3, #0] + 80034be: f003 0302 and.w r3, r3, #2 + 80034c2: 2b00 cmp r3, #0 + 80034c4: d010 beq.n 80034e8 + { + x[index] = 4096 - brute_x[index]; + 80034c6: 6cbb ldr r3, [r7, #72] ; 0x48 + 80034c8: 005b lsls r3, r3, #1 + 80034ca: f107 0250 add.w r2, r7, #80 ; 0x50 + 80034ce: 4413 add r3, r2 + 80034d0: f833 3c30 ldrh.w r3, [r3, #-48] + 80034d4: f5c3 5380 rsb r3, r3, #4096 ; 0x1000 + 80034d8: b29a uxth r2, r3 + 80034da: 6cbb ldr r3, [r7, #72] ; 0x48 + 80034dc: 005b lsls r3, r3, #1 + 80034de: f107 0150 add.w r1, r7, #80 ; 0x50 + 80034e2: 440b add r3, r1 + 80034e4: f823 2c18 strh.w r2, [r3, #-24] + } + + if(tsOrientation & TS_SWAP_Y) + 80034e8: 4b6a ldr r3, [pc, #424] ; (8003694 ) + 80034ea: 781b ldrb r3, [r3, #0] + 80034ec: f003 0304 and.w r3, r3, #4 + 80034f0: 2b00 cmp r3, #0 + 80034f2: d010 beq.n 8003516 + { + y[index] = 4096 - brute_y[index]; + 80034f4: 6cbb ldr r3, [r7, #72] ; 0x48 + 80034f6: 005b lsls r3, r3, #1 + 80034f8: f107 0250 add.w r2, r7, #80 ; 0x50 + 80034fc: 4413 add r3, r2 + 80034fe: f833 3c3c ldrh.w r3, [r3, #-60] + 8003502: f5c3 5380 rsb r3, r3, #4096 ; 0x1000 + 8003506: b29a uxth r2, r3 + 8003508: 6cbb ldr r3, [r7, #72] ; 0x48 + 800350a: 005b lsls r3, r3, #1 + 800350c: f107 0150 add.w r1, r7, #80 ; 0x50 + 8003510: 440b add r3, r1 + 8003512: f823 2c24 strh.w r2, [r3, #-36] + } + + if(tsOrientation & TS_SWAP_XY) + 8003516: 4b5f ldr r3, [pc, #380] ; (8003694 ) + 8003518: 781b ldrb r3, [r3, #0] + 800351a: f003 0308 and.w r3, r3, #8 + 800351e: 2b00 cmp r3, #0 + 8003520: d01b beq.n 800355a + { + y[index] = brute_x[index]; + 8003522: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003524: 005b lsls r3, r3, #1 + 8003526: f107 0250 add.w r2, r7, #80 ; 0x50 + 800352a: 4413 add r3, r2 + 800352c: f833 2c30 ldrh.w r2, [r3, #-48] + 8003530: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003532: 005b lsls r3, r3, #1 + 8003534: f107 0150 add.w r1, r7, #80 ; 0x50 + 8003538: 440b add r3, r1 + 800353a: f823 2c24 strh.w r2, [r3, #-36] + x[index] = brute_y[index]; + 800353e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003540: 005b lsls r3, r3, #1 + 8003542: f107 0250 add.w r2, r7, #80 ; 0x50 + 8003546: 4413 add r3, r2 + 8003548: f833 2c3c ldrh.w r2, [r3, #-60] + 800354c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800354e: 005b lsls r3, r3, #1 + 8003550: f107 0150 add.w r1, r7, #80 ; 0x50 + 8003554: 440b add r3, r1 + 8003556: f823 2c18 strh.w r2, [r3, #-24] + } + + x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]); + 800355a: 6cbb ldr r3, [r7, #72] ; 0x48 + 800355c: 005b lsls r3, r3, #1 + 800355e: f107 0250 add.w r2, r7, #80 ; 0x50 + 8003562: 4413 add r3, r2 + 8003564: f833 3c18 ldrh.w r3, [r3, #-24] + 8003568: 4619 mov r1, r3 + 800356a: 4a4b ldr r2, [pc, #300] ; (8003698 ) + 800356c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800356e: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003572: 4299 cmp r1, r3 + 8003574: d90e bls.n 8003594 + 8003576: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003578: 005b lsls r3, r3, #1 + 800357a: f107 0250 add.w r2, r7, #80 ; 0x50 + 800357e: 4413 add r3, r2 + 8003580: f833 2c18 ldrh.w r2, [r3, #-24] + 8003584: 4944 ldr r1, [pc, #272] ; (8003698 ) + 8003586: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003588: f851 3023 ldr.w r3, [r1, r3, lsl #2] + 800358c: b29b uxth r3, r3 + 800358e: 1ad3 subs r3, r2, r3 + 8003590: b29b uxth r3, r3 + 8003592: e00d b.n 80035b0 + 8003594: 4a40 ldr r2, [pc, #256] ; (8003698 ) + 8003596: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003598: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800359c: b29a uxth r2, r3 + 800359e: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035a0: 005b lsls r3, r3, #1 + 80035a2: f107 0150 add.w r1, r7, #80 ; 0x50 + 80035a6: 440b add r3, r1 + 80035a8: f833 3c18 ldrh.w r3, [r3, #-24] + 80035ac: 1ad3 subs r3, r2, r3 + 80035ae: b29b uxth r3, r3 + 80035b0: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]); + 80035b4: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035b6: 005b lsls r3, r3, #1 + 80035b8: f107 0250 add.w r2, r7, #80 ; 0x50 + 80035bc: 4413 add r3, r2 + 80035be: f833 3c24 ldrh.w r3, [r3, #-36] + 80035c2: 4619 mov r1, r3 + 80035c4: 4a35 ldr r2, [pc, #212] ; (800369c ) + 80035c6: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035c8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80035cc: 4299 cmp r1, r3 + 80035ce: d90e bls.n 80035ee + 80035d0: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035d2: 005b lsls r3, r3, #1 + 80035d4: f107 0250 add.w r2, r7, #80 ; 0x50 + 80035d8: 4413 add r3, r2 + 80035da: f833 2c24 ldrh.w r2, [r3, #-36] + 80035de: 492f ldr r1, [pc, #188] ; (800369c ) + 80035e0: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035e2: f851 3023 ldr.w r3, [r1, r3, lsl #2] + 80035e6: b29b uxth r3, r3 + 80035e8: 1ad3 subs r3, r2, r3 + 80035ea: b29b uxth r3, r3 + 80035ec: e00d b.n 800360a + 80035ee: 4a2b ldr r2, [pc, #172] ; (800369c ) + 80035f0: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035f2: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80035f6: b29a uxth r2, r3 + 80035f8: 6cbb ldr r3, [r7, #72] ; 0x48 + 80035fa: 005b lsls r3, r3, #1 + 80035fc: f107 0150 add.w r1, r7, #80 ; 0x50 + 8003600: 440b add r3, r1 + 8003602: f833 3c24 ldrh.w r3, [r3, #-36] + 8003606: 1ad3 subs r3, r2, r3 + 8003608: b29b uxth r3, r3 + 800360a: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + + if ((x_diff + y_diff) > 5) + 800360e: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 + 8003612: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 8003616: 4413 add r3, r2 + 8003618: 2b05 cmp r3, #5 + 800361a: dd17 ble.n 800364c + { + _x[index] = x[index]; + 800361c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800361e: 005b lsls r3, r3, #1 + 8003620: f107 0250 add.w r2, r7, #80 ; 0x50 + 8003624: 4413 add r3, r2 + 8003626: f833 3c18 ldrh.w r3, [r3, #-24] + 800362a: 4619 mov r1, r3 + 800362c: 4a1a ldr r2, [pc, #104] ; (8003698 ) + 800362e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003630: f842 1023 str.w r1, [r2, r3, lsl #2] + _y[index] = y[index]; + 8003634: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003636: 005b lsls r3, r3, #1 + 8003638: f107 0250 add.w r2, r7, #80 ; 0x50 + 800363c: 4413 add r3, r2 + 800363e: f833 3c24 ldrh.w r3, [r3, #-36] + 8003642: 4619 mov r1, r3 + 8003644: 4a15 ldr r2, [pc, #84] ; (800369c ) + 8003646: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003648: f842 1023 str.w r1, [r2, r3, lsl #2] + } + + if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS) + 800364c: 4b10 ldr r3, [pc, #64] ; (8003690 ) + 800364e: 781b ldrb r3, [r3, #0] + 8003650: 2b70 cmp r3, #112 ; 0x70 + 8003652: d125 bne.n 80036a0 + { + TS_State->touchX[index] = x[index]; + 8003654: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003656: 005b lsls r3, r3, #1 + 8003658: f107 0250 add.w r2, r7, #80 ; 0x50 + 800365c: 4413 add r3, r2 + 800365e: f833 1c18 ldrh.w r1, [r3, #-24] + 8003662: 687a ldr r2, [r7, #4] + 8003664: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003666: 005b lsls r3, r3, #1 + 8003668: 4413 add r3, r2 + 800366a: 460a mov r2, r1 + 800366c: 805a strh r2, [r3, #2] + TS_State->touchY[index] = y[index]; + 800366e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003670: 005b lsls r3, r3, #1 + 8003672: f107 0250 add.w r2, r7, #80 ; 0x50 + 8003676: 4413 add r3, r2 + 8003678: f833 1c24 ldrh.w r1, [r3, #-36] + 800367c: 687a ldr r2, [r7, #4] + 800367e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003680: 3304 adds r3, #4 + 8003682: 005b lsls r3, r3, #1 + 8003684: 4413 add r3, r2 + 8003686: 460a mov r2, r1 + 8003688: 809a strh r2, [r3, #4] + 800368a: e02c b.n 80036e6 + 800368c: 200002b8 .word 0x200002b8 + 8003690: 200002c1 .word 0x200002c1 + 8003694: 200002c0 .word 0x200002c0 + 8003698: 200002c4 .word 0x200002c4 + 800369c: 200002d8 .word 0x200002d8 + } + else + { + /* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */ + TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12; + 80036a0: 4b42 ldr r3, [pc, #264] ; (80037ac ) + 80036a2: 881b ldrh r3, [r3, #0] + 80036a4: 4619 mov r1, r3 + 80036a6: 4a42 ldr r2, [pc, #264] ; (80037b0 ) + 80036a8: 6cbb ldr r3, [r7, #72] ; 0x48 + 80036aa: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80036ae: fb03 f301 mul.w r3, r3, r1 + 80036b2: 0b1b lsrs r3, r3, #12 + 80036b4: b299 uxth r1, r3 + 80036b6: 687a ldr r2, [r7, #4] + 80036b8: 6cbb ldr r3, [r7, #72] ; 0x48 + 80036ba: 005b lsls r3, r3, #1 + 80036bc: 4413 add r3, r2 + 80036be: 460a mov r2, r1 + 80036c0: 805a strh r2, [r3, #2] + TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12; + 80036c2: 4b3c ldr r3, [pc, #240] ; (80037b4 ) + 80036c4: 881b ldrh r3, [r3, #0] + 80036c6: 4619 mov r1, r3 + 80036c8: 4a3b ldr r2, [pc, #236] ; (80037b8 ) + 80036ca: 6cbb ldr r3, [r7, #72] ; 0x48 + 80036cc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80036d0: fb03 f301 mul.w r3, r3, r1 + 80036d4: 0b1b lsrs r3, r3, #12 + 80036d6: b299 uxth r1, r3 + 80036d8: 687a ldr r2, [r7, #4] + 80036da: 6cbb ldr r3, [r7, #72] ; 0x48 + 80036dc: 3304 adds r3, #4 + 80036de: 005b lsls r3, r3, #1 + 80036e0: 4413 add r3, r2 + 80036e2: 460a mov r2, r1 + 80036e4: 809a strh r2, [r3, #4] + } + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + + /* Get touch info related to the current touch */ + ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event); + 80036e6: 4b35 ldr r3, [pc, #212] ; (80037bc ) + 80036e8: 781b ldrb r3, [r3, #0] + 80036ea: b298 uxth r0, r3 + 80036ec: f107 010c add.w r1, r7, #12 + 80036f0: f107 0210 add.w r2, r7, #16 + 80036f4: f107 0308 add.w r3, r7, #8 + 80036f8: 9300 str r3, [sp, #0] + 80036fa: 460b mov r3, r1 + 80036fc: 6cb9 ldr r1, [r7, #72] ; 0x48 + 80036fe: f7fd f933 bl 8000968 + + /* Update TS_State structure */ + TS_State->touchWeight[index] = weight; + 8003702: 693b ldr r3, [r7, #16] + 8003704: b2d9 uxtb r1, r3 + 8003706: 687a ldr r2, [r7, #4] + 8003708: 6cbb ldr r3, [r7, #72] ; 0x48 + 800370a: 4413 add r3, r2 + 800370c: 3316 adds r3, #22 + 800370e: 460a mov r2, r1 + 8003710: 701a strb r2, [r3, #0] + TS_State->touchArea[index] = area; + 8003712: 68fb ldr r3, [r7, #12] + 8003714: b2d9 uxtb r1, r3 + 8003716: 687a ldr r2, [r7, #4] + 8003718: 6cbb ldr r3, [r7, #72] ; 0x48 + 800371a: 4413 add r3, r2 + 800371c: 3320 adds r3, #32 + 800371e: 460a mov r2, r1 + 8003720: 701a strb r2, [r3, #0] + + /* Remap touch event */ + switch(event) + 8003722: 68bb ldr r3, [r7, #8] + 8003724: 2b03 cmp r3, #3 + 8003726: d827 bhi.n 8003778 + 8003728: a201 add r2, pc, #4 ; (adr r2, 8003730 ) + 800372a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800372e: bf00 nop + 8003730: 08003741 .word 0x08003741 + 8003734: 0800374f .word 0x0800374f + 8003738: 0800375d .word 0x0800375d + 800373c: 0800376b .word 0x0800376b + { + case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN : + TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN; + 8003740: 687a ldr r2, [r7, #4] + 8003742: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003744: 4413 add r3, r2 + 8003746: 331b adds r3, #27 + 8003748: 2201 movs r2, #1 + 800374a: 701a strb r2, [r3, #0] + break; + 800374c: e018 b.n 8003780 + case FT5336_TOUCH_EVT_FLAG_LIFT_UP : + TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP; + 800374e: 687a ldr r2, [r7, #4] + 8003750: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003752: 4413 add r3, r2 + 8003754: 331b adds r3, #27 + 8003756: 2202 movs r2, #2 + 8003758: 701a strb r2, [r3, #0] + break; + 800375a: e011 b.n 8003780 + case FT5336_TOUCH_EVT_FLAG_CONTACT : + TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT; + 800375c: 687a ldr r2, [r7, #4] + 800375e: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003760: 4413 add r3, r2 + 8003762: 331b adds r3, #27 + 8003764: 2203 movs r2, #3 + 8003766: 701a strb r2, [r3, #0] + break; + 8003768: e00a b.n 8003780 + case FT5336_TOUCH_EVT_FLAG_NO_EVENT : + TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT; + 800376a: 687a ldr r2, [r7, #4] + 800376c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800376e: 4413 add r3, r2 + 8003770: 331b adds r3, #27 + 8003772: 2200 movs r2, #0 + 8003774: 701a strb r2, [r3, #0] + break; + 8003776: e003 b.n 8003780 + default : + ts_status = TS_ERROR; + 8003778: 2301 movs r3, #1 + 800377a: f887 304f strb.w r3, [r7, #79] ; 0x4f + break; + 800377e: bf00 nop + for(index=0; index < TS_State->touchDetected; index++) + 8003780: 6cbb ldr r3, [r7, #72] ; 0x48 + 8003782: 3301 adds r3, #1 + 8003784: 64bb str r3, [r7, #72] ; 0x48 + 8003786: 687b ldr r3, [r7, #4] + 8003788: 781b ldrb r3, [r3, #0] + 800378a: 461a mov r2, r3 + 800378c: 6cbb ldr r3, [r7, #72] ; 0x48 + 800378e: 4293 cmp r3, r2 + 8003790: f4ff ae61 bcc.w 8003456 + + } /* of for(index=0; index < TS_State->touchDetected; index++) */ + +#if (TS_MULTI_TOUCH_SUPPORTED == 1) + /* Get gesture Id */ + ts_status = BSP_TS_Get_GestureId(TS_State); + 8003794: 6878 ldr r0, [r7, #4] + 8003796: f000 f813 bl 80037c0 + 800379a: 4603 mov r3, r0 + 800379c: f887 304f strb.w r3, [r7, #79] ; 0x4f +#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */ + + } /* end of if(TS_State->touchDetected != 0) */ + + return (ts_status); + 80037a0: f897 304f ldrb.w r3, [r7, #79] ; 0x4f +} + 80037a4: 4618 mov r0, r3 + 80037a6: 3754 adds r7, #84 ; 0x54 + 80037a8: 46bd mov sp, r7 + 80037aa: bd90 pop {r4, r7, pc} + 80037ac: 200002bc .word 0x200002bc + 80037b0: 200002c4 .word 0x200002c4 + 80037b4: 200002be .word 0x200002be + 80037b8: 200002d8 .word 0x200002d8 + 80037bc: 200002c1 .word 0x200002c1 + +080037c0 : + * @brief Update gesture Id following a touch detected. + * @param TS_State: Pointer to touch screen current state structure + * @retval TS_OK if all initializations are OK. Other value if error. + */ +uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State) +{ + 80037c0: b580 push {r7, lr} + 80037c2: b084 sub sp, #16 + 80037c4: af00 add r7, sp, #0 + 80037c6: 6078 str r0, [r7, #4] + uint32_t gestureId = 0; + 80037c8: 2300 movs r3, #0 + 80037ca: 60bb str r3, [r7, #8] + uint8_t ts_status = TS_OK; + 80037cc: 2300 movs r3, #0 + 80037ce: 73fb strb r3, [r7, #15] + + /* Get gesture Id */ + ft5336_TS_GetGestureID(I2cAddress, &gestureId); + 80037d0: 4b1f ldr r3, [pc, #124] ; (8003850 ) + 80037d2: 781b ldrb r3, [r3, #0] + 80037d4: b29b uxth r3, r3 + 80037d6: f107 0208 add.w r2, r7, #8 + 80037da: 4611 mov r1, r2 + 80037dc: 4618 mov r0, r3 + 80037de: f7fd f8aa bl 8000936 + + /* Remap gesture Id to a TS_GestureIdTypeDef value */ + switch(gestureId) + 80037e2: 68bb ldr r3, [r7, #8] + 80037e4: 2b18 cmp r3, #24 + 80037e6: d01b beq.n 8003820 + 80037e8: 2b18 cmp r3, #24 + 80037ea: d806 bhi.n 80037fa + 80037ec: 2b10 cmp r3, #16 + 80037ee: d00f beq.n 8003810 + 80037f0: 2b14 cmp r3, #20 + 80037f2: d011 beq.n 8003818 + 80037f4: 2b00 cmp r3, #0 + 80037f6: d007 beq.n 8003808 + 80037f8: e022 b.n 8003840 + 80037fa: 2b40 cmp r3, #64 ; 0x40 + 80037fc: d018 beq.n 8003830 + 80037fe: 2b49 cmp r3, #73 ; 0x49 + 8003800: d01a beq.n 8003838 + 8003802: 2b1c cmp r3, #28 + 8003804: d010 beq.n 8003828 + 8003806: e01b b.n 8003840 + { + case FT5336_GEST_ID_NO_GESTURE : + TS_State->gestureId = GEST_ID_NO_GESTURE; + 8003808: 687b ldr r3, [r7, #4] + 800380a: 2200 movs r2, #0 + 800380c: 629a str r2, [r3, #40] ; 0x28 + break; + 800380e: e01a b.n 8003846 + case FT5336_GEST_ID_MOVE_UP : + TS_State->gestureId = GEST_ID_MOVE_UP; + 8003810: 687b ldr r3, [r7, #4] + 8003812: 2201 movs r2, #1 + 8003814: 629a str r2, [r3, #40] ; 0x28 + break; + 8003816: e016 b.n 8003846 + case FT5336_GEST_ID_MOVE_RIGHT : + TS_State->gestureId = GEST_ID_MOVE_RIGHT; + 8003818: 687b ldr r3, [r7, #4] + 800381a: 2202 movs r2, #2 + 800381c: 629a str r2, [r3, #40] ; 0x28 + break; + 800381e: e012 b.n 8003846 + case FT5336_GEST_ID_MOVE_DOWN : + TS_State->gestureId = GEST_ID_MOVE_DOWN; + 8003820: 687b ldr r3, [r7, #4] + 8003822: 2203 movs r2, #3 + 8003824: 629a str r2, [r3, #40] ; 0x28 + break; + 8003826: e00e b.n 8003846 + case FT5336_GEST_ID_MOVE_LEFT : + TS_State->gestureId = GEST_ID_MOVE_LEFT; + 8003828: 687b ldr r3, [r7, #4] + 800382a: 2204 movs r2, #4 + 800382c: 629a str r2, [r3, #40] ; 0x28 + break; + 800382e: e00a b.n 8003846 + case FT5336_GEST_ID_ZOOM_IN : + TS_State->gestureId = GEST_ID_ZOOM_IN; + 8003830: 687b ldr r3, [r7, #4] + 8003832: 2205 movs r2, #5 + 8003834: 629a str r2, [r3, #40] ; 0x28 + break; + 8003836: e006 b.n 8003846 + case FT5336_GEST_ID_ZOOM_OUT : + TS_State->gestureId = GEST_ID_ZOOM_OUT; + 8003838: 687b ldr r3, [r7, #4] + 800383a: 2206 movs r2, #6 + 800383c: 629a str r2, [r3, #40] ; 0x28 + break; + 800383e: e002 b.n 8003846 + default : + ts_status = TS_ERROR; + 8003840: 2301 movs r3, #1 + 8003842: 73fb strb r3, [r7, #15] + break; + 8003844: bf00 nop + } /* of switch(gestureId) */ + + return(ts_status); + 8003846: 7bfb ldrb r3, [r7, #15] +} + 8003848: 4618 mov r0, r3 + 800384a: 3710 adds r7, #16 + 800384c: 46bd mov sp, r7 + 800384e: bd80 pop {r7, pc} + 8003850: 200002c1 .word 0x200002c1 + +08003854 : +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8003854: b580 push {r7, lr} + 8003856: b082 sub sp, #8 + 8003858: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + 800385a: 4b11 ldr r3, [pc, #68] ; (80038a0 ) + 800385c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800385e: 4a10 ldr r2, [pc, #64] ; (80038a0 ) + 8003860: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8003864: 6413 str r3, [r2, #64] ; 0x40 + 8003866: 4b0e ldr r3, [pc, #56] ; (80038a0 ) + 8003868: 6c1b ldr r3, [r3, #64] ; 0x40 + 800386a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800386e: 607b str r3, [r7, #4] + 8003870: 687b ldr r3, [r7, #4] + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8003872: 4b0b ldr r3, [pc, #44] ; (80038a0 ) + 8003874: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003876: 4a0a ldr r2, [pc, #40] ; (80038a0 ) + 8003878: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 800387c: 6453 str r3, [r2, #68] ; 0x44 + 800387e: 4b08 ldr r3, [pc, #32] ; (80038a0 ) + 8003880: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003882: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8003886: 603b str r3, [r7, #0] + 8003888: 683b ldr r3, [r7, #0] + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + 800388a: 2200 movs r2, #0 + 800388c: 210f movs r1, #15 + 800388e: f06f 0001 mvn.w r0, #1 + 8003892: f001 faed bl 8004e70 + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8003896: bf00 nop + 8003898: 3708 adds r7, #8 + 800389a: 46bd mov sp, r7 + 800389c: bd80 pop {r7, pc} + 800389e: bf00 nop + 80038a0: 40023800 .word 0x40023800 + +080038a4 : +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + 80038a4: b580 push {r7, lr} + 80038a6: b08c sub sp, #48 ; 0x30 + 80038a8: af00 add r7, sp, #0 + 80038aa: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80038ac: f107 031c add.w r3, r7, #28 + 80038b0: 2200 movs r2, #0 + 80038b2: 601a str r2, [r3, #0] + 80038b4: 605a str r2, [r3, #4] + 80038b6: 609a str r2, [r3, #8] + 80038b8: 60da str r2, [r3, #12] + 80038ba: 611a str r2, [r3, #16] + if(hadc->Instance==ADC1) + 80038bc: 687b ldr r3, [r7, #4] + 80038be: 681b ldr r3, [r3, #0] + 80038c0: 4a2a ldr r2, [pc, #168] ; (800396c ) + 80038c2: 4293 cmp r3, r2 + 80038c4: d124 bne.n 8003910 + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + 80038c6: 4b2a ldr r3, [pc, #168] ; (8003970 ) + 80038c8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80038ca: 4a29 ldr r2, [pc, #164] ; (8003970 ) + 80038cc: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80038d0: 6453 str r3, [r2, #68] ; 0x44 + 80038d2: 4b27 ldr r3, [pc, #156] ; (8003970 ) + 80038d4: 6c5b ldr r3, [r3, #68] ; 0x44 + 80038d6: f403 7380 and.w r3, r3, #256 ; 0x100 + 80038da: 61bb str r3, [r7, #24] + 80038dc: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80038de: 4b24 ldr r3, [pc, #144] ; (8003970 ) + 80038e0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80038e2: 4a23 ldr r2, [pc, #140] ; (8003970 ) + 80038e4: f043 0301 orr.w r3, r3, #1 + 80038e8: 6313 str r3, [r2, #48] ; 0x30 + 80038ea: 4b21 ldr r3, [pc, #132] ; (8003970 ) + 80038ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80038ee: f003 0301 and.w r3, r3, #1 + 80038f2: 617b str r3, [r7, #20] + 80038f4: 697b ldr r3, [r7, #20] + /**ADC1 GPIO Configuration + PA0/WKUP ------> ADC1_IN0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0; + 80038f6: 2301 movs r3, #1 + 80038f8: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80038fa: 2303 movs r3, #3 + 80038fc: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80038fe: 2300 movs r3, #0 + 8003900: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8003902: f107 031c add.w r3, r7, #28 + 8003906: 4619 mov r1, r3 + 8003908: 481a ldr r0, [pc, #104] ; (8003974 ) + 800390a: f001 fff1 bl 80058f0 + /* USER CODE BEGIN ADC3_MspInit 1 */ + + /* USER CODE END ADC3_MspInit 1 */ + } + +} + 800390e: e029 b.n 8003964 + else if(hadc->Instance==ADC3) + 8003910: 687b ldr r3, [r7, #4] + 8003912: 681b ldr r3, [r3, #0] + 8003914: 4a18 ldr r2, [pc, #96] ; (8003978 ) + 8003916: 4293 cmp r3, r2 + 8003918: d124 bne.n 8003964 + __HAL_RCC_ADC3_CLK_ENABLE(); + 800391a: 4b15 ldr r3, [pc, #84] ; (8003970 ) + 800391c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800391e: 4a14 ldr r2, [pc, #80] ; (8003970 ) + 8003920: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8003924: 6453 str r3, [r2, #68] ; 0x44 + 8003926: 4b12 ldr r3, [pc, #72] ; (8003970 ) + 8003928: 6c5b ldr r3, [r3, #68] ; 0x44 + 800392a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800392e: 613b str r3, [r7, #16] + 8003930: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8003932: 4b0f ldr r3, [pc, #60] ; (8003970 ) + 8003934: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003936: 4a0e ldr r2, [pc, #56] ; (8003970 ) + 8003938: f043 0320 orr.w r3, r3, #32 + 800393c: 6313 str r3, [r2, #48] ; 0x30 + 800393e: 4b0c ldr r3, [pc, #48] ; (8003970 ) + 8003940: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003942: f003 0320 and.w r3, r3, #32 + 8003946: 60fb str r3, [r7, #12] + 8003948: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8; + 800394a: f44f 63e0 mov.w r3, #1792 ; 0x700 + 800394e: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8003950: 2303 movs r3, #3 + 8003952: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003954: 2300 movs r3, #0 + 8003956: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 8003958: f107 031c add.w r3, r7, #28 + 800395c: 4619 mov r1, r3 + 800395e: 4807 ldr r0, [pc, #28] ; (800397c ) + 8003960: f001 ffc6 bl 80058f0 +} + 8003964: bf00 nop + 8003966: 3730 adds r7, #48 ; 0x30 + 8003968: 46bd mov sp, r7 + 800396a: bd80 pop {r7, pc} + 800396c: 40012000 .word 0x40012000 + 8003970: 40023800 .word 0x40023800 + 8003974: 40020000 .word 0x40020000 + 8003978: 40012200 .word 0x40012200 + 800397c: 40021400 .word 0x40021400 + +08003980 : +* This function configures the hardware resources used in this example +* @param hdac: DAC handle pointer +* @retval None +*/ +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + 8003980: b580 push {r7, lr} + 8003982: b08a sub sp, #40 ; 0x28 + 8003984: af00 add r7, sp, #0 + 8003986: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8003988: f107 0314 add.w r3, r7, #20 + 800398c: 2200 movs r2, #0 + 800398e: 601a str r2, [r3, #0] + 8003990: 605a str r2, [r3, #4] + 8003992: 609a str r2, [r3, #8] + 8003994: 60da str r2, [r3, #12] + 8003996: 611a str r2, [r3, #16] + if(hdac->Instance==DAC) + 8003998: 687b ldr r3, [r7, #4] + 800399a: 681b ldr r3, [r3, #0] + 800399c: 4a19 ldr r2, [pc, #100] ; (8003a04 ) + 800399e: 4293 cmp r3, r2 + 80039a0: d12b bne.n 80039fa + { + /* USER CODE BEGIN DAC_MspInit 0 */ + + /* USER CODE END DAC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DAC_CLK_ENABLE(); + 80039a2: 4b19 ldr r3, [pc, #100] ; (8003a08 ) + 80039a4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80039a6: 4a18 ldr r2, [pc, #96] ; (8003a08 ) + 80039a8: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 80039ac: 6413 str r3, [r2, #64] ; 0x40 + 80039ae: 4b16 ldr r3, [pc, #88] ; (8003a08 ) + 80039b0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80039b2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 80039b6: 613b str r3, [r7, #16] + 80039b8: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80039ba: 4b13 ldr r3, [pc, #76] ; (8003a08 ) + 80039bc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80039be: 4a12 ldr r2, [pc, #72] ; (8003a08 ) + 80039c0: f043 0301 orr.w r3, r3, #1 + 80039c4: 6313 str r3, [r2, #48] ; 0x30 + 80039c6: 4b10 ldr r3, [pc, #64] ; (8003a08 ) + 80039c8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80039ca: f003 0301 and.w r3, r3, #1 + 80039ce: 60fb str r3, [r7, #12] + 80039d0: 68fb ldr r3, [r7, #12] + /**DAC GPIO Configuration + PA4 ------> DAC_OUT1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + 80039d2: 2310 movs r3, #16 + 80039d4: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80039d6: 2303 movs r3, #3 + 80039d8: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80039da: 2300 movs r3, #0 + 80039dc: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80039de: f107 0314 add.w r3, r7, #20 + 80039e2: 4619 mov r1, r3 + 80039e4: 4809 ldr r0, [pc, #36] ; (8003a0c ) + 80039e6: f001 ff83 bl 80058f0 + + /* DAC interrupt Init */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); + 80039ea: 2200 movs r2, #0 + 80039ec: 2100 movs r1, #0 + 80039ee: 2036 movs r0, #54 ; 0x36 + 80039f0: f001 fa3e bl 8004e70 + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 80039f4: 2036 movs r0, #54 ; 0x36 + 80039f6: f001 fa57 bl 8004ea8 + /* USER CODE BEGIN DAC_MspInit 1 */ + + /* USER CODE END DAC_MspInit 1 */ + } + +} + 80039fa: bf00 nop + 80039fc: 3728 adds r7, #40 ; 0x28 + 80039fe: 46bd mov sp, r7 + 8003a00: bd80 pop {r7, pc} + 8003a02: bf00 nop + 8003a04: 40007400 .word 0x40007400 + 8003a08: 40023800 .word 0x40023800 + 8003a0c: 40020000 .word 0x40020000 + +08003a10 : +* This function configures the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + 8003a10: b480 push {r7} + 8003a12: b085 sub sp, #20 + 8003a14: af00 add r7, sp, #0 + 8003a16: 6078 str r0, [r7, #4] + if(hdma2d->Instance==DMA2D) + 8003a18: 687b ldr r3, [r7, #4] + 8003a1a: 681b ldr r3, [r3, #0] + 8003a1c: 4a0a ldr r2, [pc, #40] ; (8003a48 ) + 8003a1e: 4293 cmp r3, r2 + 8003a20: d10b bne.n 8003a3a + { + /* USER CODE BEGIN DMA2D_MspInit 0 */ + + /* USER CODE END DMA2D_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DMA2D_CLK_ENABLE(); + 8003a22: 4b0a ldr r3, [pc, #40] ; (8003a4c ) + 8003a24: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003a26: 4a09 ldr r2, [pc, #36] ; (8003a4c ) + 8003a28: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8003a2c: 6313 str r3, [r2, #48] ; 0x30 + 8003a2e: 4b07 ldr r3, [pc, #28] ; (8003a4c ) + 8003a30: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003a32: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8003a36: 60fb str r3, [r7, #12] + 8003a38: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN DMA2D_MspInit 1 */ + + /* USER CODE END DMA2D_MspInit 1 */ + } + +} + 8003a3a: bf00 nop + 8003a3c: 3714 adds r7, #20 + 8003a3e: 46bd mov sp, r7 + 8003a40: f85d 7b04 ldr.w r7, [sp], #4 + 8003a44: 4770 bx lr + 8003a46: bf00 nop + 8003a48: 4002b000 .word 0x4002b000 + 8003a4c: 40023800 .word 0x40023800 + +08003a50 : +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8003a50: b580 push {r7, lr} + 8003a52: b08c sub sp, #48 ; 0x30 + 8003a54: af00 add r7, sp, #0 + 8003a56: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8003a58: f107 031c add.w r3, r7, #28 + 8003a5c: 2200 movs r2, #0 + 8003a5e: 601a str r2, [r3, #0] + 8003a60: 605a str r2, [r3, #4] + 8003a62: 609a str r2, [r3, #8] + 8003a64: 60da str r2, [r3, #12] + 8003a66: 611a str r2, [r3, #16] + if(hi2c->Instance==I2C1) + 8003a68: 687b ldr r3, [r7, #4] + 8003a6a: 681b ldr r3, [r3, #0] + 8003a6c: 4a2f ldr r2, [pc, #188] ; (8003b2c ) + 8003a6e: 4293 cmp r3, r2 + 8003a70: d129 bne.n 8003ac6 + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8003a72: 4b2f ldr r3, [pc, #188] ; (8003b30 ) + 8003a74: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003a76: 4a2e ldr r2, [pc, #184] ; (8003b30 ) + 8003a78: f043 0302 orr.w r3, r3, #2 + 8003a7c: 6313 str r3, [r2, #48] ; 0x30 + 8003a7e: 4b2c ldr r3, [pc, #176] ; (8003b30 ) + 8003a80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003a82: f003 0302 and.w r3, r3, #2 + 8003a86: 61bb str r3, [r7, #24] + 8003a88: 69bb ldr r3, [r7, #24] + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin; + 8003a8a: f44f 7340 mov.w r3, #768 ; 0x300 + 8003a8e: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8003a90: 2312 movs r3, #18 + 8003a92: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8003a94: 2301 movs r3, #1 + 8003a96: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003a98: 2300 movs r3, #0 + 8003a9a: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8003a9c: 2304 movs r3, #4 + 8003a9e: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8003aa0: f107 031c add.w r3, r7, #28 + 8003aa4: 4619 mov r1, r3 + 8003aa6: 4823 ldr r0, [pc, #140] ; (8003b34 ) + 8003aa8: f001 ff22 bl 80058f0 + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8003aac: 4b20 ldr r3, [pc, #128] ; (8003b30 ) + 8003aae: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003ab0: 4a1f ldr r2, [pc, #124] ; (8003b30 ) + 8003ab2: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8003ab6: 6413 str r3, [r2, #64] ; 0x40 + 8003ab8: 4b1d ldr r3, [pc, #116] ; (8003b30 ) + 8003aba: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003abc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8003ac0: 617b str r3, [r7, #20] + 8003ac2: 697b ldr r3, [r7, #20] + /* USER CODE BEGIN I2C3_MspInit 1 */ + + /* USER CODE END I2C3_MspInit 1 */ + } + +} + 8003ac4: e02d b.n 8003b22 + else if(hi2c->Instance==I2C3) + 8003ac6: 687b ldr r3, [r7, #4] + 8003ac8: 681b ldr r3, [r3, #0] + 8003aca: 4a1b ldr r2, [pc, #108] ; (8003b38 ) + 8003acc: 4293 cmp r3, r2 + 8003ace: d128 bne.n 8003b22 + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8003ad0: 4b17 ldr r3, [pc, #92] ; (8003b30 ) + 8003ad2: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003ad4: 4a16 ldr r2, [pc, #88] ; (8003b30 ) + 8003ad6: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8003ada: 6313 str r3, [r2, #48] ; 0x30 + 8003adc: 4b14 ldr r3, [pc, #80] ; (8003b30 ) + 8003ade: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003ae0: f003 0380 and.w r3, r3, #128 ; 0x80 + 8003ae4: 613b str r3, [r7, #16] + 8003ae6: 693b ldr r3, [r7, #16] + GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin; + 8003ae8: f44f 73c0 mov.w r3, #384 ; 0x180 + 8003aec: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8003aee: 2312 movs r3, #18 + 8003af0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 8003af2: 2301 movs r3, #1 + 8003af4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003af6: 2303 movs r3, #3 + 8003af8: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; + 8003afa: 2304 movs r3, #4 + 8003afc: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8003afe: f107 031c add.w r3, r7, #28 + 8003b02: 4619 mov r1, r3 + 8003b04: 480d ldr r0, [pc, #52] ; (8003b3c ) + 8003b06: f001 fef3 bl 80058f0 + __HAL_RCC_I2C3_CLK_ENABLE(); + 8003b0a: 4b09 ldr r3, [pc, #36] ; (8003b30 ) + 8003b0c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003b0e: 4a08 ldr r2, [pc, #32] ; (8003b30 ) + 8003b10: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8003b14: 6413 str r3, [r2, #64] ; 0x40 + 8003b16: 4b06 ldr r3, [pc, #24] ; (8003b30 ) + 8003b18: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003b1a: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8003b1e: 60fb str r3, [r7, #12] + 8003b20: 68fb ldr r3, [r7, #12] +} + 8003b22: bf00 nop + 8003b24: 3730 adds r7, #48 ; 0x30 + 8003b26: 46bd mov sp, r7 + 8003b28: bd80 pop {r7, pc} + 8003b2a: bf00 nop + 8003b2c: 40005400 .word 0x40005400 + 8003b30: 40023800 .word 0x40023800 + 8003b34: 40020400 .word 0x40020400 + 8003b38: 40005c00 .word 0x40005c00 + 8003b3c: 40021c00 .word 0x40021c00 + +08003b40 : +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + 8003b40: b580 push {r7, lr} + 8003b42: b082 sub sp, #8 + 8003b44: af00 add r7, sp, #0 + 8003b46: 6078 str r0, [r7, #4] + if(hi2c->Instance==I2C1) + 8003b48: 687b ldr r3, [r7, #4] + 8003b4a: 681b ldr r3, [r3, #0] + 8003b4c: 4a15 ldr r2, [pc, #84] ; (8003ba4 ) + 8003b4e: 4293 cmp r3, r2 + 8003b50: d110 bne.n 8003b74 + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + 8003b52: 4b15 ldr r3, [pc, #84] ; (8003ba8 ) + 8003b54: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003b56: 4a14 ldr r2, [pc, #80] ; (8003ba8 ) + 8003b58: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 8003b5c: 6413 str r3, [r2, #64] ; 0x40 + + /**I2C1 GPIO Configuration + PB8 ------> I2C1_SCL + PB9 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(ARDUINO_SCL_D15_GPIO_Port, ARDUINO_SCL_D15_Pin); + 8003b5e: f44f 7180 mov.w r1, #256 ; 0x100 + 8003b62: 4812 ldr r0, [pc, #72] ; (8003bac ) + 8003b64: f002 f86e bl 8005c44 + + HAL_GPIO_DeInit(ARDUINO_SDA_D14_GPIO_Port, ARDUINO_SDA_D14_Pin); + 8003b68: f44f 7100 mov.w r1, #512 ; 0x200 + 8003b6c: 480f ldr r0, [pc, #60] ; (8003bac ) + 8003b6e: f002 f869 bl 8005c44 + /* USER CODE BEGIN I2C3_MspDeInit 1 */ + + /* USER CODE END I2C3_MspDeInit 1 */ + } + +} + 8003b72: e013 b.n 8003b9c + else if(hi2c->Instance==I2C3) + 8003b74: 687b ldr r3, [r7, #4] + 8003b76: 681b ldr r3, [r3, #0] + 8003b78: 4a0d ldr r2, [pc, #52] ; (8003bb0 ) + 8003b7a: 4293 cmp r3, r2 + 8003b7c: d10e bne.n 8003b9c + __HAL_RCC_I2C3_CLK_DISABLE(); + 8003b7e: 4b0a ldr r3, [pc, #40] ; (8003ba8 ) + 8003b80: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003b82: 4a09 ldr r2, [pc, #36] ; (8003ba8 ) + 8003b84: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8003b88: 6413 str r3, [r2, #64] ; 0x40 + HAL_GPIO_DeInit(LCD_SCL_GPIO_Port, LCD_SCL_Pin); + 8003b8a: 2180 movs r1, #128 ; 0x80 + 8003b8c: 4809 ldr r0, [pc, #36] ; (8003bb4 ) + 8003b8e: f002 f859 bl 8005c44 + HAL_GPIO_DeInit(LCD_SDA_GPIO_Port, LCD_SDA_Pin); + 8003b92: f44f 7180 mov.w r1, #256 ; 0x100 + 8003b96: 4807 ldr r0, [pc, #28] ; (8003bb4 ) + 8003b98: f002 f854 bl 8005c44 +} + 8003b9c: bf00 nop + 8003b9e: 3708 adds r7, #8 + 8003ba0: 46bd mov sp, r7 + 8003ba2: bd80 pop {r7, pc} + 8003ba4: 40005400 .word 0x40005400 + 8003ba8: 40023800 .word 0x40023800 + 8003bac: 40020400 .word 0x40020400 + 8003bb0: 40005c00 .word 0x40005c00 + 8003bb4: 40021c00 .word 0x40021c00 + +08003bb8 : +* This function configures the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + 8003bb8: b580 push {r7, lr} + 8003bba: b08e sub sp, #56 ; 0x38 + 8003bbc: af00 add r7, sp, #0 + 8003bbe: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8003bc0: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003bc4: 2200 movs r2, #0 + 8003bc6: 601a str r2, [r3, #0] + 8003bc8: 605a str r2, [r3, #4] + 8003bca: 609a str r2, [r3, #8] + 8003bcc: 60da str r2, [r3, #12] + 8003bce: 611a str r2, [r3, #16] + if(hltdc->Instance==LTDC) + 8003bd0: 687b ldr r3, [r7, #4] + 8003bd2: 681b ldr r3, [r3, #0] + 8003bd4: 4a55 ldr r2, [pc, #340] ; (8003d2c ) + 8003bd6: 4293 cmp r3, r2 + 8003bd8: f040 80a3 bne.w 8003d22 + { + /* USER CODE BEGIN LTDC_MspInit 0 */ + + /* USER CODE END LTDC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + 8003bdc: 4b54 ldr r3, [pc, #336] ; (8003d30 ) + 8003bde: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003be0: 4a53 ldr r2, [pc, #332] ; (8003d30 ) + 8003be2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 8003be6: 6453 str r3, [r2, #68] ; 0x44 + 8003be8: 4b51 ldr r3, [pc, #324] ; (8003d30 ) + 8003bea: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003bec: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8003bf0: 623b str r3, [r7, #32] + 8003bf2: 6a3b ldr r3, [r7, #32] + + __HAL_RCC_GPIOE_CLK_ENABLE(); + 8003bf4: 4b4e ldr r3, [pc, #312] ; (8003d30 ) + 8003bf6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003bf8: 4a4d ldr r2, [pc, #308] ; (8003d30 ) + 8003bfa: f043 0310 orr.w r3, r3, #16 + 8003bfe: 6313 str r3, [r2, #48] ; 0x30 + 8003c00: 4b4b ldr r3, [pc, #300] ; (8003d30 ) + 8003c02: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c04: f003 0310 and.w r3, r3, #16 + 8003c08: 61fb str r3, [r7, #28] + 8003c0a: 69fb ldr r3, [r7, #28] + __HAL_RCC_GPIOJ_CLK_ENABLE(); + 8003c0c: 4b48 ldr r3, [pc, #288] ; (8003d30 ) + 8003c0e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c10: 4a47 ldr r2, [pc, #284] ; (8003d30 ) + 8003c12: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8003c16: 6313 str r3, [r2, #48] ; 0x30 + 8003c18: 4b45 ldr r3, [pc, #276] ; (8003d30 ) + 8003c1a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c1c: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003c20: 61bb str r3, [r7, #24] + 8003c22: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOK_CLK_ENABLE(); + 8003c24: 4b42 ldr r3, [pc, #264] ; (8003d30 ) + 8003c26: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c28: 4a41 ldr r2, [pc, #260] ; (8003d30 ) + 8003c2a: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8003c2e: 6313 str r3, [r2, #48] ; 0x30 + 8003c30: 4b3f ldr r3, [pc, #252] ; (8003d30 ) + 8003c32: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c34: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8003c38: 617b str r3, [r7, #20] + 8003c3a: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOG_CLK_ENABLE(); + 8003c3c: 4b3c ldr r3, [pc, #240] ; (8003d30 ) + 8003c3e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c40: 4a3b ldr r2, [pc, #236] ; (8003d30 ) + 8003c42: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8003c46: 6313 str r3, [r2, #48] ; 0x30 + 8003c48: 4b39 ldr r3, [pc, #228] ; (8003d30 ) + 8003c4a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c4c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003c50: 613b str r3, [r7, #16] + 8003c52: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8003c54: 4b36 ldr r3, [pc, #216] ; (8003d30 ) + 8003c56: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c58: 4a35 ldr r2, [pc, #212] ; (8003d30 ) + 8003c5a: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003c5e: 6313 str r3, [r2, #48] ; 0x30 + 8003c60: 4b33 ldr r3, [pc, #204] ; (8003d30 ) + 8003c62: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003c64: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003c68: 60fb str r3, [r7, #12] + 8003c6a: 68fb ldr r3, [r7, #12] + PJ3 ------> LTDC_R4 + PJ2 ------> LTDC_R3 + PJ0 ------> LTDC_R1 + PJ1 ------> LTDC_R2 + */ + GPIO_InitStruct.Pin = LCD_B0_Pin; + 8003c6c: 2310 movs r3, #16 + 8003c6e: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003c70: 2302 movs r3, #2 + 8003c72: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003c74: 2300 movs r3, #0 + 8003c76: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003c78: 2300 movs r3, #0 + 8003c7a: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8003c7c: 230e movs r3, #14 + 8003c7e: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct); + 8003c80: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003c84: 4619 mov r1, r3 + 8003c86: 482b ldr r0, [pc, #172] ; (8003d34 ) + 8003c88: f001 fe32 bl 80058f0 + + GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin + 8003c8c: f64e 73ff movw r3, #61439 ; 0xefff + 8003c90: 627b str r3, [r7, #36] ; 0x24 + |LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin + |LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin + |LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003c92: 2302 movs r3, #2 + 8003c94: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003c96: 2300 movs r3, #0 + 8003c98: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003c9a: 2300 movs r3, #0 + 8003c9c: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8003c9e: 230e movs r3, #14 + 8003ca0: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct); + 8003ca2: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003ca6: 4619 mov r1, r3 + 8003ca8: 4823 ldr r0, [pc, #140] ; (8003d38 ) + 8003caa: f001 fe21 bl 80058f0 + + GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin + 8003cae: 23f7 movs r3, #247 ; 0xf7 + 8003cb0: 627b str r3, [r7, #36] ; 0x24 + |LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003cb2: 2302 movs r3, #2 + 8003cb4: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003cb6: 2300 movs r3, #0 + 8003cb8: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003cba: 2300 movs r3, #0 + 8003cbc: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8003cbe: 230e movs r3, #14 + 8003cc0: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOK, &GPIO_InitStruct); + 8003cc2: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003cc6: 4619 mov r1, r3 + 8003cc8: 481c ldr r0, [pc, #112] ; (8003d3c ) + 8003cca: f001 fe11 bl 80058f0 + + GPIO_InitStruct.Pin = LCD_B4_Pin; + 8003cce: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8003cd2: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003cd4: 2302 movs r3, #2 + 8003cd6: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003cd8: 2300 movs r3, #0 + 8003cda: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003cdc: 2300 movs r3, #0 + 8003cde: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + 8003ce0: 2309 movs r3, #9 + 8003ce2: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct); + 8003ce4: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003ce8: 4619 mov r1, r3 + 8003cea: 4815 ldr r0, [pc, #84] ; (8003d40 ) + 8003cec: f001 fe00 bl 80058f0 + + GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin; + 8003cf0: f44f 4346 mov.w r3, #50688 ; 0xc600 + 8003cf4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003cf6: 2302 movs r3, #2 + 8003cf8: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003cfa: 2300 movs r3, #0 + 8003cfc: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003cfe: 2300 movs r3, #0 + 8003d00: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + 8003d02: 230e movs r3, #14 + 8003d04: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8003d06: f107 0324 add.w r3, r7, #36 ; 0x24 + 8003d0a: 4619 mov r1, r3 + 8003d0c: 480d ldr r0, [pc, #52] ; (8003d44 ) + 8003d0e: f001 fdef bl 80058f0 + + /* LTDC interrupt Init */ + HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0); + 8003d12: 2200 movs r2, #0 + 8003d14: 2105 movs r1, #5 + 8003d16: 2058 movs r0, #88 ; 0x58 + 8003d18: f001 f8aa bl 8004e70 + HAL_NVIC_EnableIRQ(LTDC_IRQn); + 8003d1c: 2058 movs r0, #88 ; 0x58 + 8003d1e: f001 f8c3 bl 8004ea8 + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } + +} + 8003d22: bf00 nop + 8003d24: 3738 adds r7, #56 ; 0x38 + 8003d26: 46bd mov sp, r7 + 8003d28: bd80 pop {r7, pc} + 8003d2a: bf00 nop + 8003d2c: 40016800 .word 0x40016800 + 8003d30: 40023800 .word 0x40023800 + 8003d34: 40021000 .word 0x40021000 + 8003d38: 40022400 .word 0x40022400 + 8003d3c: 40022800 .word 0x40022800 + 8003d40: 40021800 .word 0x40021800 + 8003d44: 40022000 .word 0x40022000 + +08003d48 : +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + 8003d48: b480 push {r7} + 8003d4a: b083 sub sp, #12 + 8003d4c: af00 add r7, sp, #0 + 8003d4e: 6078 str r0, [r7, #4] + if(hrtc->Instance==RTC) + 8003d50: 687b ldr r3, [r7, #4] + 8003d52: 681b ldr r3, [r3, #0] + 8003d54: 4a07 ldr r2, [pc, #28] ; (8003d74 ) + 8003d56: 4293 cmp r3, r2 + 8003d58: d105 bne.n 8003d66 + { + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8003d5a: 4b07 ldr r3, [pc, #28] ; (8003d78 ) + 8003d5c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003d5e: 4a06 ldr r2, [pc, #24] ; (8003d78 ) + 8003d60: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8003d64: 6713 str r3, [r2, #112] ; 0x70 + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + 8003d66: bf00 nop + 8003d68: 370c adds r7, #12 + 8003d6a: 46bd mov sp, r7 + 8003d6c: f85d 7b04 ldr.w r7, [sp], #4 + 8003d70: 4770 bx lr + 8003d72: bf00 nop + 8003d74: 40002800 .word 0x40002800 + 8003d78: 40023800 .word 0x40023800 + +08003d7c : +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 8003d7c: b580 push {r7, lr} + 8003d7e: b08a sub sp, #40 ; 0x28 + 8003d80: af00 add r7, sp, #0 + 8003d82: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8003d84: f107 0314 add.w r3, r7, #20 + 8003d88: 2200 movs r2, #0 + 8003d8a: 601a str r2, [r3, #0] + 8003d8c: 605a str r2, [r3, #4] + 8003d8e: 609a str r2, [r3, #8] + 8003d90: 60da str r2, [r3, #12] + 8003d92: 611a str r2, [r3, #16] + if(hspi->Instance==SPI2) + 8003d94: 687b ldr r3, [r7, #4] + 8003d96: 681b ldr r3, [r3, #0] + 8003d98: 4a2d ldr r2, [pc, #180] ; (8003e50 ) + 8003d9a: 4293 cmp r3, r2 + 8003d9c: d154 bne.n 8003e48 + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + 8003d9e: 4b2d ldr r3, [pc, #180] ; (8003e54 ) + 8003da0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003da2: 4a2c ldr r2, [pc, #176] ; (8003e54 ) + 8003da4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8003da8: 6413 str r3, [r2, #64] ; 0x40 + 8003daa: 4b2a ldr r3, [pc, #168] ; (8003e54 ) + 8003dac: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003dae: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8003db2: 613b str r3, [r7, #16] + 8003db4: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8003db6: 4b27 ldr r3, [pc, #156] ; (8003e54 ) + 8003db8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003dba: 4a26 ldr r2, [pc, #152] ; (8003e54 ) + 8003dbc: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003dc0: 6313 str r3, [r2, #48] ; 0x30 + 8003dc2: 4b24 ldr r3, [pc, #144] ; (8003e54 ) + 8003dc4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003dc6: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003dca: 60fb str r3, [r7, #12] + 8003dcc: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8003dce: 4b21 ldr r3, [pc, #132] ; (8003e54 ) + 8003dd0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003dd2: 4a20 ldr r2, [pc, #128] ; (8003e54 ) + 8003dd4: f043 0302 orr.w r3, r3, #2 + 8003dd8: 6313 str r3, [r2, #48] ; 0x30 + 8003dda: 4b1e ldr r3, [pc, #120] ; (8003e54 ) + 8003ddc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003dde: f003 0302 and.w r3, r3, #2 + 8003de2: 60bb str r3, [r7, #8] + 8003de4: 68bb ldr r3, [r7, #8] + PI1 ------> SPI2_SCK + PI0 ------> SPI2_NSS + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin; + 8003de6: 2302 movs r3, #2 + 8003de8: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003dea: 2302 movs r3, #2 + 8003dec: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003dee: 2300 movs r3, #0 + 8003df0: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003df2: 2300 movs r3, #0 + 8003df4: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 8003df6: 2305 movs r3, #5 + 8003df8: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct); + 8003dfa: f107 0314 add.w r3, r7, #20 + 8003dfe: 4619 mov r1, r3 + 8003e00: 4815 ldr r0, [pc, #84] ; (8003e58 ) + 8003e02: f001 fd75 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_0; + 8003e06: 2301 movs r3, #1 + 8003e08: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003e0a: 2302 movs r3, #2 + 8003e0c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003e0e: 2300 movs r3, #0 + 8003e10: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003e12: 2303 movs r3, #3 + 8003e14: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 8003e16: 2305 movs r3, #5 + 8003e18: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8003e1a: f107 0314 add.w r3, r7, #20 + 8003e1e: 4619 mov r1, r3 + 8003e20: 480d ldr r0, [pc, #52] ; (8003e58 ) + 8003e22: f001 fd65 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + 8003e26: f44f 4340 mov.w r3, #49152 ; 0xc000 + 8003e2a: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003e2c: 2302 movs r3, #2 + 8003e2e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003e30: 2300 movs r3, #0 + 8003e32: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8003e34: 2303 movs r3, #3 + 8003e36: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + 8003e38: 2305 movs r3, #5 + 8003e3a: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8003e3c: f107 0314 add.w r3, r7, #20 + 8003e40: 4619 mov r1, r3 + 8003e42: 4806 ldr r0, [pc, #24] ; (8003e5c ) + 8003e44: f001 fd54 bl 80058f0 + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + 8003e48: bf00 nop + 8003e4a: 3728 adds r7, #40 ; 0x28 + 8003e4c: 46bd mov sp, r7 + 8003e4e: bd80 pop {r7, pc} + 8003e50: 40003800 .word 0x40003800 + 8003e54: 40023800 .word 0x40023800 + 8003e58: 40022000 .word 0x40022000 + 8003e5c: 40020400 .word 0x40020400 + +08003e60 : +* This function configures the hardware resources used in this example +* @param htim_base: TIM_Base handle pointer +* @retval None +*/ +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + 8003e60: b480 push {r7} + 8003e62: b089 sub sp, #36 ; 0x24 + 8003e64: af00 add r7, sp, #0 + 8003e66: 6078 str r0, [r7, #4] + if(htim_base->Instance==TIM1) + 8003e68: 687b ldr r3, [r7, #4] + 8003e6a: 681b ldr r3, [r3, #0] + 8003e6c: 4a2e ldr r2, [pc, #184] ; (8003f28 ) + 8003e6e: 4293 cmp r3, r2 + 8003e70: d10c bne.n 8003e8c + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + 8003e72: 4b2e ldr r3, [pc, #184] ; (8003f2c ) + 8003e74: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003e76: 4a2d ldr r2, [pc, #180] ; (8003f2c ) + 8003e78: f043 0301 orr.w r3, r3, #1 + 8003e7c: 6453 str r3, [r2, #68] ; 0x44 + 8003e7e: 4b2b ldr r3, [pc, #172] ; (8003f2c ) + 8003e80: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003e82: f003 0301 and.w r3, r3, #1 + 8003e86: 61fb str r3, [r7, #28] + 8003e88: 69fb ldr r3, [r7, #28] + /* USER CODE BEGIN TIM8_MspInit 1 */ + + /* USER CODE END TIM8_MspInit 1 */ + } + +} + 8003e8a: e046 b.n 8003f1a + else if(htim_base->Instance==TIM2) + 8003e8c: 687b ldr r3, [r7, #4] + 8003e8e: 681b ldr r3, [r3, #0] + 8003e90: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8003e94: d10c bne.n 8003eb0 + __HAL_RCC_TIM2_CLK_ENABLE(); + 8003e96: 4b25 ldr r3, [pc, #148] ; (8003f2c ) + 8003e98: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003e9a: 4a24 ldr r2, [pc, #144] ; (8003f2c ) + 8003e9c: f043 0301 orr.w r3, r3, #1 + 8003ea0: 6413 str r3, [r2, #64] ; 0x40 + 8003ea2: 4b22 ldr r3, [pc, #136] ; (8003f2c ) + 8003ea4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003ea6: f003 0301 and.w r3, r3, #1 + 8003eaa: 61bb str r3, [r7, #24] + 8003eac: 69bb ldr r3, [r7, #24] +} + 8003eae: e034 b.n 8003f1a + else if(htim_base->Instance==TIM3) + 8003eb0: 687b ldr r3, [r7, #4] + 8003eb2: 681b ldr r3, [r3, #0] + 8003eb4: 4a1e ldr r2, [pc, #120] ; (8003f30 ) + 8003eb6: 4293 cmp r3, r2 + 8003eb8: d10c bne.n 8003ed4 + __HAL_RCC_TIM3_CLK_ENABLE(); + 8003eba: 4b1c ldr r3, [pc, #112] ; (8003f2c ) + 8003ebc: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003ebe: 4a1b ldr r2, [pc, #108] ; (8003f2c ) + 8003ec0: f043 0302 orr.w r3, r3, #2 + 8003ec4: 6413 str r3, [r2, #64] ; 0x40 + 8003ec6: 4b19 ldr r3, [pc, #100] ; (8003f2c ) + 8003ec8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003eca: f003 0302 and.w r3, r3, #2 + 8003ece: 617b str r3, [r7, #20] + 8003ed0: 697b ldr r3, [r7, #20] +} + 8003ed2: e022 b.n 8003f1a + else if(htim_base->Instance==TIM5) + 8003ed4: 687b ldr r3, [r7, #4] + 8003ed6: 681b ldr r3, [r3, #0] + 8003ed8: 4a16 ldr r2, [pc, #88] ; (8003f34 ) + 8003eda: 4293 cmp r3, r2 + 8003edc: d10c bne.n 8003ef8 + __HAL_RCC_TIM5_CLK_ENABLE(); + 8003ede: 4b13 ldr r3, [pc, #76] ; (8003f2c ) + 8003ee0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003ee2: 4a12 ldr r2, [pc, #72] ; (8003f2c ) + 8003ee4: f043 0308 orr.w r3, r3, #8 + 8003ee8: 6413 str r3, [r2, #64] ; 0x40 + 8003eea: 4b10 ldr r3, [pc, #64] ; (8003f2c ) + 8003eec: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003eee: f003 0308 and.w r3, r3, #8 + 8003ef2: 613b str r3, [r7, #16] + 8003ef4: 693b ldr r3, [r7, #16] +} + 8003ef6: e010 b.n 8003f1a + else if(htim_base->Instance==TIM8) + 8003ef8: 687b ldr r3, [r7, #4] + 8003efa: 681b ldr r3, [r3, #0] + 8003efc: 4a0e ldr r2, [pc, #56] ; (8003f38 ) + 8003efe: 4293 cmp r3, r2 + 8003f00: d10b bne.n 8003f1a + __HAL_RCC_TIM8_CLK_ENABLE(); + 8003f02: 4b0a ldr r3, [pc, #40] ; (8003f2c ) + 8003f04: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003f06: 4a09 ldr r2, [pc, #36] ; (8003f2c ) + 8003f08: f043 0302 orr.w r3, r3, #2 + 8003f0c: 6453 str r3, [r2, #68] ; 0x44 + 8003f0e: 4b07 ldr r3, [pc, #28] ; (8003f2c ) + 8003f10: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003f12: f003 0302 and.w r3, r3, #2 + 8003f16: 60fb str r3, [r7, #12] + 8003f18: 68fb ldr r3, [r7, #12] +} + 8003f1a: bf00 nop + 8003f1c: 3724 adds r7, #36 ; 0x24 + 8003f1e: 46bd mov sp, r7 + 8003f20: f85d 7b04 ldr.w r7, [sp], #4 + 8003f24: 4770 bx lr + 8003f26: bf00 nop + 8003f28: 40010000 .word 0x40010000 + 8003f2c: 40023800 .word 0x40023800 + 8003f30: 40000400 .word 0x40000400 + 8003f34: 40000c00 .word 0x40000c00 + 8003f38: 40010400 .word 0x40010400 + +08003f3c : + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + 8003f3c: b580 push {r7, lr} + 8003f3e: b08a sub sp, #40 ; 0x28 + 8003f40: af00 add r7, sp, #0 + 8003f42: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8003f44: f107 0314 add.w r3, r7, #20 + 8003f48: 2200 movs r2, #0 + 8003f4a: 601a str r2, [r3, #0] + 8003f4c: 605a str r2, [r3, #4] + 8003f4e: 609a str r2, [r3, #8] + 8003f50: 60da str r2, [r3, #12] + 8003f52: 611a str r2, [r3, #16] + if(htim->Instance==TIM3) + 8003f54: 687b ldr r3, [r7, #4] + 8003f56: 681b ldr r3, [r3, #0] + 8003f58: 4a22 ldr r2, [pc, #136] ; (8003fe4 ) + 8003f5a: 4293 cmp r3, r2 + 8003f5c: d11c bne.n 8003f98 + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8003f5e: 4b22 ldr r3, [pc, #136] ; (8003fe8 ) + 8003f60: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003f62: 4a21 ldr r2, [pc, #132] ; (8003fe8 ) + 8003f64: f043 0302 orr.w r3, r3, #2 + 8003f68: 6313 str r3, [r2, #48] ; 0x30 + 8003f6a: 4b1f ldr r3, [pc, #124] ; (8003fe8 ) + 8003f6c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003f6e: f003 0302 and.w r3, r3, #2 + 8003f72: 613b str r3, [r7, #16] + 8003f74: 693b ldr r3, [r7, #16] + /**TIM3 GPIO Configuration + PB4 ------> TIM3_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4; + 8003f76: 2310 movs r3, #16 + 8003f78: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003f7a: 2302 movs r3, #2 + 8003f7c: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003f7e: 2300 movs r3, #0 + 8003f80: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003f82: 2300 movs r3, #0 + 8003f84: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 8003f86: 2302 movs r3, #2 + 8003f88: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8003f8a: f107 0314 add.w r3, r7, #20 + 8003f8e: 4619 mov r1, r3 + 8003f90: 4816 ldr r0, [pc, #88] ; (8003fec ) + 8003f92: f001 fcad bl 80058f0 + /* USER CODE BEGIN TIM8_MspPostInit 1 */ + + /* USER CODE END TIM8_MspPostInit 1 */ + } + +} + 8003f96: e020 b.n 8003fda + else if(htim->Instance==TIM8) + 8003f98: 687b ldr r3, [r7, #4] + 8003f9a: 681b ldr r3, [r3, #0] + 8003f9c: 4a14 ldr r2, [pc, #80] ; (8003ff0 ) + 8003f9e: 4293 cmp r3, r2 + 8003fa0: d11b bne.n 8003fda + __HAL_RCC_GPIOI_CLK_ENABLE(); + 8003fa2: 4b11 ldr r3, [pc, #68] ; (8003fe8 ) + 8003fa4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003fa6: 4a10 ldr r2, [pc, #64] ; (8003fe8 ) + 8003fa8: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003fac: 6313 str r3, [r2, #48] ; 0x30 + 8003fae: 4b0e ldr r3, [pc, #56] ; (8003fe8 ) + 8003fb0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003fb2: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003fb6: 60fb str r3, [r7, #12] + 8003fb8: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_2; + 8003fba: 2304 movs r3, #4 + 8003fbc: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8003fbe: 2302 movs r3, #2 + 8003fc0: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8003fc2: 2300 movs r3, #0 + 8003fc4: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8003fc6: 2300 movs r3, #0 + 8003fc8: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF3_TIM8; + 8003fca: 2303 movs r3, #3 + 8003fcc: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + 8003fce: f107 0314 add.w r3, r7, #20 + 8003fd2: 4619 mov r1, r3 + 8003fd4: 4807 ldr r0, [pc, #28] ; (8003ff4 ) + 8003fd6: f001 fc8b bl 80058f0 +} + 8003fda: bf00 nop + 8003fdc: 3728 adds r7, #40 ; 0x28 + 8003fde: 46bd mov sp, r7 + 8003fe0: bd80 pop {r7, pc} + 8003fe2: bf00 nop + 8003fe4: 40000400 .word 0x40000400 + 8003fe8: 40023800 .word 0x40023800 + 8003fec: 40020400 .word 0x40020400 + 8003ff0: 40010400 .word 0x40010400 + 8003ff4: 40022000 .word 0x40022000 + +08003ff8 : +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + 8003ff8: b580 push {r7, lr} + 8003ffa: b08e sub sp, #56 ; 0x38 + 8003ffc: af00 add r7, sp, #0 + 8003ffe: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8004000: f107 0324 add.w r3, r7, #36 ; 0x24 + 8004004: 2200 movs r2, #0 + 8004006: 601a str r2, [r3, #0] + 8004008: 605a str r2, [r3, #4] + 800400a: 609a str r2, [r3, #8] + 800400c: 60da str r2, [r3, #12] + 800400e: 611a str r2, [r3, #16] + if(huart->Instance==UART7) + 8004010: 687b ldr r3, [r7, #4] + 8004012: 681b ldr r3, [r3, #0] + 8004014: 4a53 ldr r2, [pc, #332] ; (8004164 ) + 8004016: 4293 cmp r3, r2 + 8004018: d128 bne.n 800406c + { + /* USER CODE BEGIN UART7_MspInit 0 */ + + /* USER CODE END UART7_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_UART7_CLK_ENABLE(); + 800401a: 4b53 ldr r3, [pc, #332] ; (8004168 ) + 800401c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800401e: 4a52 ldr r2, [pc, #328] ; (8004168 ) + 8004020: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 + 8004024: 6413 str r3, [r2, #64] ; 0x40 + 8004026: 4b50 ldr r3, [pc, #320] ; (8004168 ) + 8004028: 6c1b ldr r3, [r3, #64] ; 0x40 + 800402a: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 + 800402e: 623b str r3, [r7, #32] + 8004030: 6a3b ldr r3, [r7, #32] + + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8004032: 4b4d ldr r3, [pc, #308] ; (8004168 ) + 8004034: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004036: 4a4c ldr r2, [pc, #304] ; (8004168 ) + 8004038: f043 0320 orr.w r3, r3, #32 + 800403c: 6313 str r3, [r2, #48] ; 0x30 + 800403e: 4b4a ldr r3, [pc, #296] ; (8004168 ) + 8004040: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004042: f003 0320 and.w r3, r3, #32 + 8004046: 61fb str r3, [r7, #28] + 8004048: 69fb ldr r3, [r7, #28] + /**UART7 GPIO Configuration + PF7 ------> UART7_TX + PF6 ------> UART7_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; + 800404a: 23c0 movs r3, #192 ; 0xc0 + 800404c: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800404e: 2302 movs r3, #2 + 8004050: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004052: 2300 movs r3, #0 + 8004054: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8004056: 2303 movs r3, #3 + 8004058: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF8_UART7; + 800405a: 2308 movs r3, #8 + 800405c: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 800405e: f107 0324 add.w r3, r7, #36 ; 0x24 + 8004062: 4619 mov r1, r3 + 8004064: 4841 ldr r0, [pc, #260] ; (800416c ) + 8004066: f001 fc43 bl 80058f0 + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } + +} + 800406a: e077 b.n 800415c + else if(huart->Instance==USART1) + 800406c: 687b ldr r3, [r7, #4] + 800406e: 681b ldr r3, [r3, #0] + 8004070: 4a3f ldr r2, [pc, #252] ; (8004170 ) + 8004072: 4293 cmp r3, r2 + 8004074: d145 bne.n 8004102 + __HAL_RCC_USART1_CLK_ENABLE(); + 8004076: 4b3c ldr r3, [pc, #240] ; (8004168 ) + 8004078: 6c5b ldr r3, [r3, #68] ; 0x44 + 800407a: 4a3b ldr r2, [pc, #236] ; (8004168 ) + 800407c: f043 0310 orr.w r3, r3, #16 + 8004080: 6453 str r3, [r2, #68] ; 0x44 + 8004082: 4b39 ldr r3, [pc, #228] ; (8004168 ) + 8004084: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004086: f003 0310 and.w r3, r3, #16 + 800408a: 61bb str r3, [r7, #24] + 800408c: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800408e: 4b36 ldr r3, [pc, #216] ; (8004168 ) + 8004090: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004092: 4a35 ldr r2, [pc, #212] ; (8004168 ) + 8004094: f043 0302 orr.w r3, r3, #2 + 8004098: 6313 str r3, [r2, #48] ; 0x30 + 800409a: 4b33 ldr r3, [pc, #204] ; (8004168 ) + 800409c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800409e: f003 0302 and.w r3, r3, #2 + 80040a2: 617b str r3, [r7, #20] + 80040a4: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80040a6: 4b30 ldr r3, [pc, #192] ; (8004168 ) + 80040a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80040aa: 4a2f ldr r2, [pc, #188] ; (8004168 ) + 80040ac: f043 0301 orr.w r3, r3, #1 + 80040b0: 6313 str r3, [r2, #48] ; 0x30 + 80040b2: 4b2d ldr r3, [pc, #180] ; (8004168 ) + 80040b4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80040b6: f003 0301 and.w r3, r3, #1 + 80040ba: 613b str r3, [r7, #16] + 80040bc: 693b ldr r3, [r7, #16] + GPIO_InitStruct.Pin = VCP_RX_Pin; + 80040be: 2380 movs r3, #128 ; 0x80 + 80040c0: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80040c2: 2302 movs r3, #2 + 80040c4: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80040c6: 2300 movs r3, #0 + 80040c8: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80040ca: 2300 movs r3, #0 + 80040cc: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 80040ce: 2307 movs r3, #7 + 80040d0: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct); + 80040d2: f107 0324 add.w r3, r7, #36 ; 0x24 + 80040d6: 4619 mov r1, r3 + 80040d8: 4826 ldr r0, [pc, #152] ; (8004174 ) + 80040da: f001 fc09 bl 80058f0 + GPIO_InitStruct.Pin = VCP_TX_Pin; + 80040de: f44f 7300 mov.w r3, #512 ; 0x200 + 80040e2: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80040e4: 2302 movs r3, #2 + 80040e6: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80040e8: 2300 movs r3, #0 + 80040ea: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80040ec: 2300 movs r3, #0 + 80040ee: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 80040f0: 2307 movs r3, #7 + 80040f2: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct); + 80040f4: f107 0324 add.w r3, r7, #36 ; 0x24 + 80040f8: 4619 mov r1, r3 + 80040fa: 481f ldr r0, [pc, #124] ; (8004178 ) + 80040fc: f001 fbf8 bl 80058f0 +} + 8004100: e02c b.n 800415c + else if(huart->Instance==USART6) + 8004102: 687b ldr r3, [r7, #4] + 8004104: 681b ldr r3, [r3, #0] + 8004106: 4a1d ldr r2, [pc, #116] ; (800417c ) + 8004108: 4293 cmp r3, r2 + 800410a: d127 bne.n 800415c + __HAL_RCC_USART6_CLK_ENABLE(); + 800410c: 4b16 ldr r3, [pc, #88] ; (8004168 ) + 800410e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004110: 4a15 ldr r2, [pc, #84] ; (8004168 ) + 8004112: f043 0320 orr.w r3, r3, #32 + 8004116: 6453 str r3, [r2, #68] ; 0x44 + 8004118: 4b13 ldr r3, [pc, #76] ; (8004168 ) + 800411a: 6c5b ldr r3, [r3, #68] ; 0x44 + 800411c: f003 0320 and.w r3, r3, #32 + 8004120: 60fb str r3, [r7, #12] + 8004122: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8004124: 4b10 ldr r3, [pc, #64] ; (8004168 ) + 8004126: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004128: 4a0f ldr r2, [pc, #60] ; (8004168 ) + 800412a: f043 0304 orr.w r3, r3, #4 + 800412e: 6313 str r3, [r2, #48] ; 0x30 + 8004130: 4b0d ldr r3, [pc, #52] ; (8004168 ) + 8004132: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004134: f003 0304 and.w r3, r3, #4 + 8004138: 60bb str r3, [r7, #8] + 800413a: 68bb ldr r3, [r7, #8] + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; + 800413c: 23c0 movs r3, #192 ; 0xc0 + 800413e: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004140: 2302 movs r3, #2 + 8004142: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004144: 2300 movs r3, #0 + 8004146: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8004148: 2303 movs r3, #3 + 800414a: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + 800414c: 2308 movs r3, #8 + 800414e: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8004150: f107 0324 add.w r3, r7, #36 ; 0x24 + 8004154: 4619 mov r1, r3 + 8004156: 480a ldr r0, [pc, #40] ; (8004180 ) + 8004158: f001 fbca bl 80058f0 +} + 800415c: bf00 nop + 800415e: 3738 adds r7, #56 ; 0x38 + 8004160: 46bd mov sp, r7 + 8004162: bd80 pop {r7, pc} + 8004164: 40007800 .word 0x40007800 + 8004168: 40023800 .word 0x40023800 + 800416c: 40021400 .word 0x40021400 + 8004170: 40011000 .word 0x40011000 + 8004174: 40020400 .word 0x40020400 + 8004178: 40020000 .word 0x40020000 + 800417c: 40011400 .word 0x40011400 + 8004180: 40020800 .word 0x40020800 + +08004184 : + +} + +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + 8004184: b580 push {r7, lr} + 8004186: b086 sub sp, #24 + 8004188: af00 add r7, sp, #0 + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + 800418a: 1d3b adds r3, r7, #4 + 800418c: 2200 movs r2, #0 + 800418e: 601a str r2, [r3, #0] + 8004190: 605a str r2, [r3, #4] + 8004192: 609a str r2, [r3, #8] + 8004194: 60da str r2, [r3, #12] + 8004196: 611a str r2, [r3, #16] + if (FMC_Initialized) { + 8004198: 4b3a ldr r3, [pc, #232] ; (8004284 ) + 800419a: 681b ldr r3, [r3, #0] + 800419c: 2b00 cmp r3, #0 + 800419e: d16d bne.n 800427c + return; + } + FMC_Initialized = 1; + 80041a0: 4b38 ldr r3, [pc, #224] ; (8004284 ) + 80041a2: 2201 movs r2, #1 + 80041a4: 601a str r2, [r3, #0] + + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + 80041a6: 4b38 ldr r3, [pc, #224] ; (8004288 ) + 80041a8: 6b9b ldr r3, [r3, #56] ; 0x38 + 80041aa: 4a37 ldr r2, [pc, #220] ; (8004288 ) + 80041ac: f043 0301 orr.w r3, r3, #1 + 80041b0: 6393 str r3, [r2, #56] ; 0x38 + 80041b2: 4b35 ldr r3, [pc, #212] ; (8004288 ) + 80041b4: 6b9b ldr r3, [r3, #56] ; 0x38 + 80041b6: f003 0301 and.w r3, r3, #1 + 80041ba: 603b str r3, [r7, #0] + 80041bc: 683b ldr r3, [r7, #0] + PE10 ------> FMC_D7 + PE12 ------> FMC_D9 + PE15 ------> FMC_D12 + PE13 ------> FMC_D10 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9 + 80041be: f64f 7383 movw r3, #65411 ; 0xff83 + 80041c2: 607b str r3, [r7, #4] + |GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10 + |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80041c4: 2302 movs r3, #2 + 80041c6: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80041c8: 2300 movs r3, #0 + 80041ca: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80041cc: 2303 movs r3, #3 + 80041ce: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 80041d0: 230c movs r3, #12 + 80041d2: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 80041d4: 1d3b adds r3, r7, #4 + 80041d6: 4619 mov r1, r3 + 80041d8: 482c ldr r0, [pc, #176] ; (800428c ) + 80041da: f001 fb89 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0 + 80041de: f248 1333 movw r3, #33075 ; 0x8133 + 80041e2: 607b str r3, [r7, #4] + |GPIO_PIN_5|GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80041e4: 2302 movs r3, #2 + 80041e6: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80041e8: 2300 movs r3, #0 + 80041ea: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80041ec: 2303 movs r3, #3 + 80041ee: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 80041f0: 230c movs r3, #12 + 80041f2: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + 80041f4: 1d3b adds r3, r7, #4 + 80041f6: 4619 mov r1, r3 + 80041f8: 4825 ldr r0, [pc, #148] ; (8004290 ) + 80041fa: f001 fb79 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 + 80041fe: f24c 7303 movw r3, #50947 ; 0xc703 + 8004202: 607b str r3, [r7, #4] + |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004204: 2302 movs r3, #2 + 8004206: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004208: 2300 movs r3, #0 + 800420a: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800420c: 2303 movs r3, #3 + 800420e: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8004210: 230c movs r3, #12 + 8004212: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 8004214: 1d3b adds r3, r7, #4 + 8004216: 4619 mov r1, r3 + 8004218: 481e ldr r0, [pc, #120] ; (8004294 ) + 800421a: f001 fb69 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + 800421e: f64f 033f movw r3, #63551 ; 0xf83f + 8004222: 607b str r3, [r7, #4] + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004224: 2302 movs r3, #2 + 8004226: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004228: 2300 movs r3, #0 + 800422a: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800422c: 2303 movs r3, #3 + 800422e: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 8004230: 230c movs r3, #12 + 8004232: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 8004234: 1d3b adds r3, r7, #4 + 8004236: 4619 mov r1, r3 + 8004238: 4817 ldr r0, [pc, #92] ; (8004298 ) + 800423a: f001 fb59 bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3; + 800423e: 2328 movs r3, #40 ; 0x28 + 8004240: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004242: 2302 movs r3, #2 + 8004244: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004246: 2300 movs r3, #0 + 8004248: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 800424a: 2303 movs r3, #3 + 800424c: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 800424e: 230c movs r3, #12 + 8004250: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8004252: 1d3b adds r3, r7, #4 + 8004254: 4619 mov r1, r3 + 8004256: 4811 ldr r0, [pc, #68] ; (800429c ) + 8004258: f001 fb4a bl 80058f0 + + GPIO_InitStruct.Pin = GPIO_PIN_3; + 800425c: 2308 movs r3, #8 + 800425e: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8004260: 2302 movs r3, #2 + 8004262: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8004264: 2300 movs r3, #0 + 8004266: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8004268: 2303 movs r3, #3 + 800426a: 613b str r3, [r7, #16] + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + 800426c: 230c movs r3, #12 + 800426e: 617b str r3, [r7, #20] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 8004270: 1d3b adds r3, r7, #4 + 8004272: 4619 mov r1, r3 + 8004274: 480a ldr r0, [pc, #40] ; (80042a0 ) + 8004276: f001 fb3b bl 80058f0 + 800427a: e000 b.n 800427e + return; + 800427c: bf00 nop + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + 800427e: 3718 adds r7, #24 + 8004280: 46bd mov sp, r7 + 8004282: bd80 pop {r7, pc} + 8004284: 200002ec .word 0x200002ec + 8004288: 40023800 .word 0x40023800 + 800428c: 40021000 .word 0x40021000 + 8004290: 40021800 .word 0x40021800 + 8004294: 40020c00 .word 0x40020c00 + 8004298: 40021400 .word 0x40021400 + 800429c: 40021c00 .word 0x40021c00 + 80042a0: 40020800 .word 0x40020800 + +080042a4 : + +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ + 80042a4: b580 push {r7, lr} + 80042a6: b082 sub sp, #8 + 80042a8: af00 add r7, sp, #0 + 80042aa: 6078 str r0, [r7, #4] + /* USER CODE BEGIN SDRAM_MspInit 0 */ + + /* USER CODE END SDRAM_MspInit 0 */ + HAL_FMC_MspInit(); + 80042ac: f7ff ff6a bl 8004184 + /* USER CODE BEGIN SDRAM_MspInit 1 */ + + /* USER CODE END SDRAM_MspInit 1 */ +} + 80042b0: bf00 nop + 80042b2: 3708 adds r7, #8 + 80042b4: 46bd mov sp, r7 + 80042b6: bd80 pop {r7, pc} + +080042b8 : + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80042b8: b580 push {r7, lr} + 80042ba: b08c sub sp, #48 ; 0x30 + 80042bc: af00 add r7, sp, #0 + 80042be: 6078 str r0, [r7, #4] + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock = 0; + 80042c0: 2300 movs r3, #0 + 80042c2: 62fb str r3, [r7, #44] ; 0x2c + uint32_t uwPrescalerValue = 0; + 80042c4: 2300 movs r3, #0 + 80042c6: 62bb str r3, [r7, #40] ; 0x28 + uint32_t pFLatency; + /*Configure the TIM6 IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0); + 80042c8: 2200 movs r2, #0 + 80042ca: 6879 ldr r1, [r7, #4] + 80042cc: 2036 movs r0, #54 ; 0x36 + 80042ce: f000 fdcf bl 8004e70 + + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + 80042d2: 2036 movs r0, #54 ; 0x36 + 80042d4: f000 fde8 bl 8004ea8 + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + 80042d8: 4b1f ldr r3, [pc, #124] ; (8004358 ) + 80042da: 6c1b ldr r3, [r3, #64] ; 0x40 + 80042dc: 4a1e ldr r2, [pc, #120] ; (8004358 ) + 80042de: f043 0310 orr.w r3, r3, #16 + 80042e2: 6413 str r3, [r2, #64] ; 0x40 + 80042e4: 4b1c ldr r3, [pc, #112] ; (8004358 ) + 80042e6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80042e8: f003 0310 and.w r3, r3, #16 + 80042ec: 60fb str r3, [r7, #12] + 80042ee: 68fb ldr r3, [r7, #12] + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + 80042f0: f107 0210 add.w r2, r7, #16 + 80042f4: f107 0314 add.w r3, r7, #20 + 80042f8: 4611 mov r1, r2 + 80042fa: 4618 mov r0, r3 + 80042fc: f003 fbdc bl 8007ab8 + + /* Compute TIM6 clock */ + uwTimclock = 2*HAL_RCC_GetPCLK1Freq(); + 8004300: f003 fbb2 bl 8007a68 + 8004304: 4603 mov r3, r0 + 8004306: 005b lsls r3, r3, #1 + 8004308: 62fb str r3, [r7, #44] ; 0x2c + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + 800430a: 6afb ldr r3, [r7, #44] ; 0x2c + 800430c: 4a13 ldr r2, [pc, #76] ; (800435c ) + 800430e: fba2 2303 umull r2, r3, r2, r3 + 8004312: 0c9b lsrs r3, r3, #18 + 8004314: 3b01 subs r3, #1 + 8004316: 62bb str r3, [r7, #40] ; 0x28 + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + 8004318: 4b11 ldr r3, [pc, #68] ; (8004360 ) + 800431a: 4a12 ldr r2, [pc, #72] ; (8004364 ) + 800431c: 601a str r2, [r3, #0] + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + 800431e: 4b10 ldr r3, [pc, #64] ; (8004360 ) + 8004320: f240 32e7 movw r2, #999 ; 0x3e7 + 8004324: 60da str r2, [r3, #12] + htim6.Init.Prescaler = uwPrescalerValue; + 8004326: 4a0e ldr r2, [pc, #56] ; (8004360 ) + 8004328: 6abb ldr r3, [r7, #40] ; 0x28 + 800432a: 6053 str r3, [r2, #4] + htim6.Init.ClockDivision = 0; + 800432c: 4b0c ldr r3, [pc, #48] ; (8004360 ) + 800432e: 2200 movs r2, #0 + 8004330: 611a str r2, [r3, #16] + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + 8004332: 4b0b ldr r3, [pc, #44] ; (8004360 ) + 8004334: 2200 movs r2, #0 + 8004336: 609a str r2, [r3, #8] + if(HAL_TIM_Base_Init(&htim6) == HAL_OK) + 8004338: 4809 ldr r0, [pc, #36] ; (8004360 ) + 800433a: f004 fcb0 bl 8008c9e + 800433e: 4603 mov r3, r0 + 8004340: 2b00 cmp r3, #0 + 8004342: d104 bne.n 800434e + { + /* Start the TIM time Base generation in interrupt mode */ + return HAL_TIM_Base_Start_IT(&htim6); + 8004344: 4806 ldr r0, [pc, #24] ; (8004360 ) + 8004346: f004 fcd5 bl 8008cf4 + 800434a: 4603 mov r3, r0 + 800434c: e000 b.n 8004350 + } + + /* Return function status */ + return HAL_ERROR; + 800434e: 2301 movs r3, #1 +} + 8004350: 4618 mov r0, r3 + 8004352: 3730 adds r7, #48 ; 0x30 + 8004354: 46bd mov sp, r7 + 8004356: bd80 pop {r7, pc} + 8004358: 40023800 .word 0x40023800 + 800435c: 431bde83 .word 0x431bde83 + 8004360: 20008ab4 .word 0x20008ab4 + 8004364: 40001000 .word 0x40001000 + +08004368 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8004368: b480 push {r7} + 800436a: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 800436c: e7fe b.n 800436c + +0800436e : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800436e: b480 push {r7} + 8004370: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8004372: e7fe b.n 8004372 + +08004374 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8004374: b480 push {r7} + 8004376: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8004378: e7fe b.n 8004378 + +0800437a : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800437a: b480 push {r7} + 800437c: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800437e: e7fe b.n 800437e + +08004380 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8004380: b480 push {r7} + 8004382: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8004384: e7fe b.n 8004384 + +08004386 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8004386: b480 push {r7} + 8004388: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 800438a: bf00 nop + 800438c: 46bd mov sp, r7 + 800438e: f85d 7b04 ldr.w r7, [sp], #4 + 8004392: 4770 bx lr + +08004394 : + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + 8004394: b580 push {r7, lr} + 8004396: af00 add r7, sp, #0 + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_DAC_IRQHandler(&hdac); + 8004398: 4803 ldr r0, [pc, #12] ; (80043a8 ) + 800439a: f000 fdb5 bl 8004f08 + HAL_TIM_IRQHandler(&htim6); + 800439e: 4803 ldr r0, [pc, #12] ; (80043ac ) + 80043a0: f004 fd07 bl 8008db2 + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + 80043a4: bf00 nop + 80043a6: bd80 pop {r7, pc} + 80043a8: 20008830 .word 0x20008830 + 80043ac: 20008ab4 .word 0x20008ab4 + +080043b0 : + +/** + * @brief This function handles LTDC global interrupt. + */ +void LTDC_IRQHandler(void) +{ + 80043b0: b580 push {r7, lr} + 80043b2: af00 add r7, sp, #0 + /* USER CODE BEGIN LTDC_IRQn 0 */ + + /* USER CODE END LTDC_IRQn 0 */ + HAL_LTDC_IRQHandler(&hltdc); + 80043b4: 4802 ldr r0, [pc, #8] ; (80043c0 ) + 80043b6: f002 fc01 bl 8006bbc + /* USER CODE BEGIN LTDC_IRQn 1 */ + + /* USER CODE END LTDC_IRQn 1 */ +} + 80043ba: bf00 nop + 80043bc: bd80 pop {r7, pc} + 80043be: bf00 nop + 80043c0: 20008678 .word 0x20008678 + +080043c4 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 80043c4: b580 push {r7, lr} + 80043c6: b086 sub sp, #24 + 80043c8: af00 add r7, sp, #0 + 80043ca: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 80043cc: 4a14 ldr r2, [pc, #80] ; (8004420 <_sbrk+0x5c>) + 80043ce: 4b15 ldr r3, [pc, #84] ; (8004424 <_sbrk+0x60>) + 80043d0: 1ad3 subs r3, r2, r3 + 80043d2: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 80043d4: 697b ldr r3, [r7, #20] + 80043d6: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 80043d8: 4b13 ldr r3, [pc, #76] ; (8004428 <_sbrk+0x64>) + 80043da: 681b ldr r3, [r3, #0] + 80043dc: 2b00 cmp r3, #0 + 80043de: d102 bne.n 80043e6 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 80043e0: 4b11 ldr r3, [pc, #68] ; (8004428 <_sbrk+0x64>) + 80043e2: 4a12 ldr r2, [pc, #72] ; (800442c <_sbrk+0x68>) + 80043e4: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 80043e6: 4b10 ldr r3, [pc, #64] ; (8004428 <_sbrk+0x64>) + 80043e8: 681a ldr r2, [r3, #0] + 80043ea: 687b ldr r3, [r7, #4] + 80043ec: 4413 add r3, r2 + 80043ee: 693a ldr r2, [r7, #16] + 80043f0: 429a cmp r2, r3 + 80043f2: d207 bcs.n 8004404 <_sbrk+0x40> + { + errno = ENOMEM; + 80043f4: f007 fbae bl 800bb54 <__errno> + 80043f8: 4602 mov r2, r0 + 80043fa: 230c movs r3, #12 + 80043fc: 6013 str r3, [r2, #0] + return (void *)-1; + 80043fe: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 8004402: e009 b.n 8004418 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8004404: 4b08 ldr r3, [pc, #32] ; (8004428 <_sbrk+0x64>) + 8004406: 681b ldr r3, [r3, #0] + 8004408: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 800440a: 4b07 ldr r3, [pc, #28] ; (8004428 <_sbrk+0x64>) + 800440c: 681a ldr r2, [r3, #0] + 800440e: 687b ldr r3, [r7, #4] + 8004410: 4413 add r3, r2 + 8004412: 4a05 ldr r2, [pc, #20] ; (8004428 <_sbrk+0x64>) + 8004414: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8004416: 68fb ldr r3, [r7, #12] +} + 8004418: 4618 mov r0, r3 + 800441a: 3718 adds r7, #24 + 800441c: 46bd mov sp, r7 + 800441e: bd80 pop {r7, pc} + 8004420: 20050000 .word 0x20050000 + 8004424: 00000400 .word 0x00000400 + 8004428: 200002f0 .word 0x200002f0 + 800442c: 20008b00 .word 0x20008b00 + +08004430 : + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8004430: b480 push {r7} + 8004432: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8004434: 4b08 ldr r3, [pc, #32] ; (8004458 ) + 8004436: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800443a: 4a07 ldr r2, [pc, #28] ; (8004458 ) + 800443c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8004440: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8004444: 4b04 ldr r3, [pc, #16] ; (8004458 ) + 8004446: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 800444a: 609a str r2, [r3, #8] +#endif +} + 800444c: bf00 nop + 800444e: 46bd mov sp, r7 + 8004450: f85d 7b04 ldr.w r7, [sp], #4 + 8004454: 4770 bx lr + 8004456: bf00 nop + 8004458: e000ed00 .word 0xe000ed00 + +0800445c : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 800445c: f8df d034 ldr.w sp, [pc, #52] ; 8004494 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8004460: 2100 movs r1, #0 + b LoopCopyDataInit + 8004462: e003 b.n 800446c + +08004464 : + +CopyDataInit: + ldr r3, =_sidata + 8004464: 4b0c ldr r3, [pc, #48] ; (8004498 ) + ldr r3, [r3, r1] + 8004466: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 8004468: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 800446a: 3104 adds r1, #4 + +0800446c : + +LoopCopyDataInit: + ldr r0, =_sdata + 800446c: 480b ldr r0, [pc, #44] ; (800449c ) + ldr r3, =_edata + 800446e: 4b0c ldr r3, [pc, #48] ; (80044a0 ) + adds r2, r0, r1 + 8004470: 1842 adds r2, r0, r1 + cmp r2, r3 + 8004472: 429a cmp r2, r3 + bcc CopyDataInit + 8004474: d3f6 bcc.n 8004464 + ldr r2, =_sbss + 8004476: 4a0b ldr r2, [pc, #44] ; (80044a4 ) + b LoopFillZerobss + 8004478: e002 b.n 8004480 + +0800447a : +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 800447a: 2300 movs r3, #0 + str r3, [r2], #4 + 800447c: f842 3b04 str.w r3, [r2], #4 + +08004480 : + +LoopFillZerobss: + ldr r3, = _ebss + 8004480: 4b09 ldr r3, [pc, #36] ; (80044a8 ) + cmp r2, r3 + 8004482: 429a cmp r2, r3 + bcc FillZerobss + 8004484: d3f9 bcc.n 800447a + +/* Call the clock system initialization function.*/ + bl SystemInit + 8004486: f7ff ffd3 bl 8004430 +/* Call static constructors */ + bl __libc_init_array + 800448a: f007 fb69 bl 800bb60 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800448e: f7fc fb43 bl 8000b18
+ bx lr + 8004492: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8004494: 20050000 .word 0x20050000 + ldr r3, =_sidata + 8004498: 0800e3d4 .word 0x0800e3d4 + ldr r0, =_sdata + 800449c: 20000000 .word 0x20000000 + ldr r3, =_edata + 80044a0: 200000b0 .word 0x200000b0 + ldr r2, =_sbss + 80044a4: 200000b0 .word 0x200000b0 + ldr r3, = _ebss + 80044a8: 20008afc .word 0x20008afc + +080044ac : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80044ac: e7fe b.n 80044ac + +080044ae : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80044ae: b580 push {r7, lr} + 80044b0: af00 add r7, sp, #0 +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80044b2: 2003 movs r0, #3 + 80044b4: f000 fcd1 bl 8004e5a + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 80044b8: 2000 movs r0, #0 + 80044ba: f7ff fefd bl 80042b8 + + /* Init the low level hardware */ + HAL_MspInit(); + 80044be: f7ff f9c9 bl 8003854 + + /* Return function status */ + return HAL_OK; + 80044c2: 2300 movs r3, #0 +} + 80044c4: 4618 mov r0, r3 + 80044c6: bd80 pop {r7, pc} + +080044c8 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 80044c8: b480 push {r7} + 80044ca: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 80044cc: 4b06 ldr r3, [pc, #24] ; (80044e8 ) + 80044ce: 781b ldrb r3, [r3, #0] + 80044d0: 461a mov r2, r3 + 80044d2: 4b06 ldr r3, [pc, #24] ; (80044ec ) + 80044d4: 681b ldr r3, [r3, #0] + 80044d6: 4413 add r3, r2 + 80044d8: 4a04 ldr r2, [pc, #16] ; (80044ec ) + 80044da: 6013 str r3, [r2, #0] +} + 80044dc: bf00 nop + 80044de: 46bd mov sp, r7 + 80044e0: f85d 7b04 ldr.w r7, [sp], #4 + 80044e4: 4770 bx lr + 80044e6: bf00 nop + 80044e8: 20000044 .word 0x20000044 + 80044ec: 20008af4 .word 0x20008af4 + +080044f0 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 80044f0: b480 push {r7} + 80044f2: af00 add r7, sp, #0 + return uwTick; + 80044f4: 4b03 ldr r3, [pc, #12] ; (8004504 ) + 80044f6: 681b ldr r3, [r3, #0] +} + 80044f8: 4618 mov r0, r3 + 80044fa: 46bd mov sp, r7 + 80044fc: f85d 7b04 ldr.w r7, [sp], #4 + 8004500: 4770 bx lr + 8004502: bf00 nop + 8004504: 20008af4 .word 0x20008af4 + +08004508 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 8004508: b580 push {r7, lr} + 800450a: b084 sub sp, #16 + 800450c: af00 add r7, sp, #0 + 800450e: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8004510: f7ff ffee bl 80044f0 + 8004514: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 8004516: 687b ldr r3, [r7, #4] + 8004518: 60fb str r3, [r7, #12] + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800451a: 68fb ldr r3, [r7, #12] + 800451c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8004520: d005 beq.n 800452e + { + wait += (uint32_t)(uwTickFreq); + 8004522: 4b09 ldr r3, [pc, #36] ; (8004548 ) + 8004524: 781b ldrb r3, [r3, #0] + 8004526: 461a mov r2, r3 + 8004528: 68fb ldr r3, [r7, #12] + 800452a: 4413 add r3, r2 + 800452c: 60fb str r3, [r7, #12] + } + + while ((HAL_GetTick() - tickstart) < wait) + 800452e: bf00 nop + 8004530: f7ff ffde bl 80044f0 + 8004534: 4602 mov r2, r0 + 8004536: 68bb ldr r3, [r7, #8] + 8004538: 1ad3 subs r3, r2, r3 + 800453a: 68fa ldr r2, [r7, #12] + 800453c: 429a cmp r2, r3 + 800453e: d8f7 bhi.n 8004530 + { + } +} + 8004540: bf00 nop + 8004542: 3710 adds r7, #16 + 8004544: 46bd mov sp, r7 + 8004546: bd80 pop {r7, pc} + 8004548: 20000044 .word 0x20000044 + +0800454c : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + 800454c: b580 push {r7, lr} + 800454e: b084 sub sp, #16 + 8004550: af00 add r7, sp, #0 + 8004552: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 8004554: 2300 movs r3, #0 + 8004556: 73fb strb r3, [r7, #15] + + /* Check ADC handle */ + if(hadc == NULL) + 8004558: 687b ldr r3, [r7, #4] + 800455a: 2b00 cmp r3, #0 + 800455c: d101 bne.n 8004562 + { + return HAL_ERROR; + 800455e: 2301 movs r3, #1 + 8004560: e031 b.n 80045c6 + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + if(hadc->State == HAL_ADC_STATE_RESET) + 8004562: 687b ldr r3, [r7, #4] + 8004564: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004566: 2b00 cmp r3, #0 + 8004568: d109 bne.n 800457e + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 800456a: 6878 ldr r0, [r7, #4] + 800456c: f7ff f99a bl 80038a4 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 8004570: 687b ldr r3, [r7, #4] + 8004572: 2200 movs r2, #0 + 8004574: 645a str r2, [r3, #68] ; 0x44 + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + 8004576: 687b ldr r3, [r7, #4] + 8004578: 2200 movs r2, #0 + 800457a: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 800457e: 687b ldr r3, [r7, #4] + 8004580: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004582: f003 0310 and.w r3, r3, #16 + 8004586: 2b00 cmp r3, #0 + 8004588: d116 bne.n 80045b8 + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 800458a: 687b ldr r3, [r7, #4] + 800458c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800458e: 4b10 ldr r3, [pc, #64] ; (80045d0 ) + 8004590: 4013 ands r3, r2 + 8004592: f043 0202 orr.w r2, r3, #2 + 8004596: 687b ldr r3, [r7, #4] + 8004598: 641a str r2, [r3, #64] ; 0x40 + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + ADC_Init(hadc); + 800459a: 6878 ldr r0, [r7, #4] + 800459c: f000 fab6 bl 8004b0c + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 80045a0: 687b ldr r3, [r7, #4] + 80045a2: 2200 movs r2, #0 + 80045a4: 645a str r2, [r3, #68] ; 0x44 + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 80045a6: 687b ldr r3, [r7, #4] + 80045a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80045aa: f023 0303 bic.w r3, r3, #3 + 80045ae: f043 0201 orr.w r2, r3, #1 + 80045b2: 687b ldr r3, [r7, #4] + 80045b4: 641a str r2, [r3, #64] ; 0x40 + 80045b6: e001 b.n 80045bc + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + 80045b8: 2301 movs r3, #1 + 80045ba: 73fb strb r3, [r7, #15] + } + + /* Release Lock */ + __HAL_UNLOCK(hadc); + 80045bc: 687b ldr r3, [r7, #4] + 80045be: 2200 movs r2, #0 + 80045c0: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Return function status */ + return tmp_hal_status; + 80045c4: 7bfb ldrb r3, [r7, #15] +} + 80045c6: 4618 mov r0, r3 + 80045c8: 3710 adds r7, #16 + 80045ca: 46bd mov sp, r7 + 80045cc: bd80 pop {r7, pc} + 80045ce: bf00 nop + 80045d0: ffffeefd .word 0xffffeefd + +080045d4 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + 80045d4: b480 push {r7} + 80045d6: b085 sub sp, #20 + 80045d8: af00 add r7, sp, #0 + 80045da: 6078 str r0, [r7, #4] + __IO uint32_t counter = 0; + 80045dc: 2300 movs r3, #0 + 80045de: 60fb str r3, [r7, #12] + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + 80045e0: 687b ldr r3, [r7, #4] + 80045e2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80045e6: 2b01 cmp r3, #1 + 80045e8: d101 bne.n 80045ee + 80045ea: 2302 movs r3, #2 + 80045ec: e0a0 b.n 8004730 + 80045ee: 687b ldr r3, [r7, #4] + 80045f0: 2201 movs r2, #1 + 80045f2: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + 80045f6: 687b ldr r3, [r7, #4] + 80045f8: 681b ldr r3, [r3, #0] + 80045fa: 689b ldr r3, [r3, #8] + 80045fc: f003 0301 and.w r3, r3, #1 + 8004600: 2b01 cmp r3, #1 + 8004602: d018 beq.n 8004636 + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + 8004604: 687b ldr r3, [r7, #4] + 8004606: 681b ldr r3, [r3, #0] + 8004608: 689a ldr r2, [r3, #8] + 800460a: 687b ldr r3, [r7, #4] + 800460c: 681b ldr r3, [r3, #0] + 800460e: f042 0201 orr.w r2, r2, #1 + 8004612: 609a str r2, [r3, #8] + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + 8004614: 4b49 ldr r3, [pc, #292] ; (800473c ) + 8004616: 681b ldr r3, [r3, #0] + 8004618: 4a49 ldr r2, [pc, #292] ; (8004740 ) + 800461a: fba2 2303 umull r2, r3, r2, r3 + 800461e: 0c9a lsrs r2, r3, #18 + 8004620: 4613 mov r3, r2 + 8004622: 005b lsls r3, r3, #1 + 8004624: 4413 add r3, r2 + 8004626: 60fb str r3, [r7, #12] + while(counter != 0) + 8004628: e002 b.n 8004630 + { + counter--; + 800462a: 68fb ldr r3, [r7, #12] + 800462c: 3b01 subs r3, #1 + 800462e: 60fb str r3, [r7, #12] + while(counter != 0) + 8004630: 68fb ldr r3, [r7, #12] + 8004632: 2b00 cmp r3, #0 + 8004634: d1f9 bne.n 800462a + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 8004636: 687b ldr r3, [r7, #4] + 8004638: 681b ldr r3, [r3, #0] + 800463a: 689b ldr r3, [r3, #8] + 800463c: f003 0301 and.w r3, r3, #1 + 8004640: 2b01 cmp r3, #1 + 8004642: d174 bne.n 800472e + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + 8004644: 687b ldr r3, [r7, #4] + 8004646: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004648: 4b3e ldr r3, [pc, #248] ; (8004744 ) + 800464a: 4013 ands r3, r2 + 800464c: f443 7280 orr.w r2, r3, #256 ; 0x100 + 8004650: 687b ldr r3, [r7, #4] + 8004652: 641a str r2, [r3, #64] ; 0x40 + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 8004654: 687b ldr r3, [r7, #4] + 8004656: 681b ldr r3, [r3, #0] + 8004658: 685b ldr r3, [r3, #4] + 800465a: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800465e: 2b00 cmp r3, #0 + 8004660: d007 beq.n 8004672 + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + 8004662: 687b ldr r3, [r7, #4] + 8004664: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004666: f423 5340 bic.w r3, r3, #12288 ; 0x3000 + 800466a: f443 5280 orr.w r2, r3, #4096 ; 0x1000 + 800466e: 687b ldr r3, [r7, #4] + 8004670: 641a str r2, [r3, #64] ; 0x40 + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 8004672: 687b ldr r3, [r7, #4] + 8004674: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004676: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 800467a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800467e: d106 bne.n 800468e + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + 8004680: 687b ldr r3, [r7, #4] + 8004682: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004684: f023 0206 bic.w r2, r3, #6 + 8004688: 687b ldr r3, [r7, #4] + 800468a: 645a str r2, [r3, #68] ; 0x44 + 800468c: e002 b.n 8004694 + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + 800468e: 687b ldr r3, [r7, #4] + 8004690: 2200 movs r2, #0 + 8004692: 645a str r2, [r3, #68] ; 0x44 + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + 8004694: 687b ldr r3, [r7, #4] + 8004696: 2200 movs r2, #0 + 8004698: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + 800469c: 687b ldr r3, [r7, #4] + 800469e: 681b ldr r3, [r3, #0] + 80046a0: f06f 0222 mvn.w r2, #34 ; 0x22 + 80046a4: 601a str r2, [r3, #0] + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + 80046a6: 4b28 ldr r3, [pc, #160] ; (8004748 ) + 80046a8: 685b ldr r3, [r3, #4] + 80046aa: f003 031f and.w r3, r3, #31 + 80046ae: 2b00 cmp r3, #0 + 80046b0: d10f bne.n 80046d2 + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + 80046b2: 687b ldr r3, [r7, #4] + 80046b4: 681b ldr r3, [r3, #0] + 80046b6: 689b ldr r3, [r3, #8] + 80046b8: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 80046bc: 2b00 cmp r3, #0 + 80046be: d136 bne.n 800472e + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 80046c0: 687b ldr r3, [r7, #4] + 80046c2: 681b ldr r3, [r3, #0] + 80046c4: 689a ldr r2, [r3, #8] + 80046c6: 687b ldr r3, [r7, #4] + 80046c8: 681b ldr r3, [r3, #0] + 80046ca: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000 + 80046ce: 609a str r2, [r3, #8] + 80046d0: e02d b.n 800472e + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + 80046d2: 687b ldr r3, [r7, #4] + 80046d4: 681b ldr r3, [r3, #0] + 80046d6: 4a1d ldr r2, [pc, #116] ; (800474c ) + 80046d8: 4293 cmp r3, r2 + 80046da: d10e bne.n 80046fa + 80046dc: 687b ldr r3, [r7, #4] + 80046de: 681b ldr r3, [r3, #0] + 80046e0: 689b ldr r3, [r3, #8] + 80046e2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 80046e6: 2b00 cmp r3, #0 + 80046e8: d107 bne.n 80046fa + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 80046ea: 687b ldr r3, [r7, #4] + 80046ec: 681b ldr r3, [r3, #0] + 80046ee: 689a ldr r2, [r3, #8] + 80046f0: 687b ldr r3, [r7, #4] + 80046f2: 681b ldr r3, [r3, #0] + 80046f4: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000 + 80046f8: 609a str r2, [r3, #8] + } + + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + 80046fa: 4b13 ldr r3, [pc, #76] ; (8004748 ) + 80046fc: 685b ldr r3, [r3, #4] + 80046fe: f003 0310 and.w r3, r3, #16 + 8004702: 2b00 cmp r3, #0 + 8004704: d113 bne.n 800472e + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + 8004706: 687b ldr r3, [r7, #4] + 8004708: 681b ldr r3, [r3, #0] + 800470a: 4a11 ldr r2, [pc, #68] ; (8004750 ) + 800470c: 4293 cmp r3, r2 + 800470e: d10e bne.n 800472e + 8004710: 687b ldr r3, [r7, #4] + 8004712: 681b ldr r3, [r3, #0] + 8004714: 689b ldr r3, [r3, #8] + 8004716: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 800471a: 2b00 cmp r3, #0 + 800471c: d107 bne.n 800472e + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 800471e: 687b ldr r3, [r7, #4] + 8004720: 681b ldr r3, [r3, #0] + 8004722: 689a ldr r2, [r3, #8] + 8004724: 687b ldr r3, [r7, #4] + 8004726: 681b ldr r3, [r3, #0] + 8004728: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000 + 800472c: 609a str r2, [r3, #8] + } + } + } + + /* Return function status */ + return HAL_OK; + 800472e: 2300 movs r3, #0 +} + 8004730: 4618 mov r0, r3 + 8004732: 3714 adds r7, #20 + 8004734: 46bd mov sp, r7 + 8004736: f85d 7b04 ldr.w r7, [sp], #4 + 800473a: 4770 bx lr + 800473c: 2000003c .word 0x2000003c + 8004740: 431bde83 .word 0x431bde83 + 8004744: fffff8fe .word 0xfffff8fe + 8004748: 40012300 .word 0x40012300 + 800474c: 40012000 .word 0x40012000 + 8004750: 40012200 .word 0x40012200 + +08004754 : + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + 8004754: b580 push {r7, lr} + 8004756: b084 sub sp, #16 + 8004758: af00 add r7, sp, #0 + 800475a: 6078 str r0, [r7, #4] + 800475c: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 800475e: 2300 movs r3, #0 + 8004760: 60fb str r3, [r7, #12] + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + 8004762: 687b ldr r3, [r7, #4] + 8004764: 681b ldr r3, [r3, #0] + 8004766: 689b ldr r3, [r3, #8] + 8004768: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800476c: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004770: d113 bne.n 800479a + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 8004772: 687b ldr r3, [r7, #4] + 8004774: 681b ldr r3, [r3, #0] + 8004776: 689b ldr r3, [r3, #8] + 8004778: f403 7380 and.w r3, r3, #256 ; 0x100 + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + 800477c: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004780: d10b bne.n 800479a + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 8004782: 687b ldr r3, [r7, #4] + 8004784: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004786: f043 0220 orr.w r2, r3, #32 + 800478a: 687b ldr r3, [r7, #4] + 800478c: 641a str r2, [r3, #64] ; 0x40 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 800478e: 687b ldr r3, [r7, #4] + 8004790: 2200 movs r2, #0 + 8004792: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_ERROR; + 8004796: 2301 movs r3, #1 + 8004798: e05c b.n 8004854 + } + + /* Get tick */ + tickstart = HAL_GetTick(); + 800479a: f7ff fea9 bl 80044f0 + 800479e: 60f8 str r0, [r7, #12] + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + 80047a0: e01a b.n 80047d8 + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + 80047a2: 683b ldr r3, [r7, #0] + 80047a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80047a8: d016 beq.n 80047d8 + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + 80047aa: 683b ldr r3, [r7, #0] + 80047ac: 2b00 cmp r3, #0 + 80047ae: d007 beq.n 80047c0 + 80047b0: f7ff fe9e bl 80044f0 + 80047b4: 4602 mov r2, r0 + 80047b6: 68fb ldr r3, [r7, #12] + 80047b8: 1ad3 subs r3, r2, r3 + 80047ba: 683a ldr r2, [r7, #0] + 80047bc: 429a cmp r2, r3 + 80047be: d20b bcs.n 80047d8 + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + 80047c0: 687b ldr r3, [r7, #4] + 80047c2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80047c4: f043 0204 orr.w r2, r3, #4 + 80047c8: 687b ldr r3, [r7, #4] + 80047ca: 641a str r2, [r3, #64] ; 0x40 + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 80047cc: 687b ldr r3, [r7, #4] + 80047ce: 2200 movs r2, #0 + 80047d0: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_TIMEOUT; + 80047d4: 2303 movs r3, #3 + 80047d6: e03d b.n 8004854 + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + 80047d8: 687b ldr r3, [r7, #4] + 80047da: 681b ldr r3, [r3, #0] + 80047dc: 681b ldr r3, [r3, #0] + 80047de: f003 0302 and.w r3, r3, #2 + 80047e2: 2b02 cmp r3, #2 + 80047e4: d1dd bne.n 80047a2 + } + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + 80047e6: 687b ldr r3, [r7, #4] + 80047e8: 681b ldr r3, [r3, #0] + 80047ea: f06f 0212 mvn.w r2, #18 + 80047ee: 601a str r2, [r3, #0] + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 80047f0: 687b ldr r3, [r7, #4] + 80047f2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80047f4: f443 7200 orr.w r2, r3, #512 ; 0x200 + 80047f8: 687b ldr r3, [r7, #4] + 80047fa: 641a str r2, [r3, #64] ; 0x40 + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 80047fc: 687b ldr r3, [r7, #4] + 80047fe: 681b ldr r3, [r3, #0] + 8004800: 689b ldr r3, [r3, #8] + 8004802: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 8004806: 2b00 cmp r3, #0 + 8004808: d123 bne.n 8004852 + (hadc->Init.ContinuousConvMode == DISABLE) && + 800480a: 687b ldr r3, [r7, #4] + 800480c: 699b ldr r3, [r3, #24] + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 800480e: 2b00 cmp r3, #0 + 8004810: d11f bne.n 8004852 + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 8004812: 687b ldr r3, [r7, #4] + 8004814: 681b ldr r3, [r3, #0] + 8004816: 6adb ldr r3, [r3, #44] ; 0x2c + 8004818: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 + (hadc->Init.ContinuousConvMode == DISABLE) && + 800481c: 2b00 cmp r3, #0 + 800481e: d006 beq.n 800482e + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 8004820: 687b ldr r3, [r7, #4] + 8004822: 681b ldr r3, [r3, #0] + 8004824: 689b ldr r3, [r3, #8] + 8004826: f403 6380 and.w r3, r3, #1024 ; 0x400 + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 800482a: 2b00 cmp r3, #0 + 800482c: d111 bne.n 8004852 + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + 800482e: 687b ldr r3, [r7, #4] + 8004830: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004832: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8004836: 687b ldr r3, [r7, #4] + 8004838: 641a str r2, [r3, #64] ; 0x40 + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 800483a: 687b ldr r3, [r7, #4] + 800483c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800483e: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8004842: 2b00 cmp r3, #0 + 8004844: d105 bne.n 8004852 + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 8004846: 687b ldr r3, [r7, #4] + 8004848: 6c1b ldr r3, [r3, #64] ; 0x40 + 800484a: f043 0201 orr.w r2, r3, #1 + 800484e: 687b ldr r3, [r7, #4] + 8004850: 641a str r2, [r3, #64] ; 0x40 + } + } + + /* Return ADC state */ + return HAL_OK; + 8004852: 2300 movs r3, #0 +} + 8004854: 4618 mov r0, r3 + 8004856: 3710 adds r7, #16 + 8004858: 46bd mov sp, r7 + 800485a: bd80 pop {r7, pc} + +0800485c : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + 800485c: b480 push {r7} + 800485e: b083 sub sp, #12 + 8004860: af00 add r7, sp, #0 + 8004862: 6078 str r0, [r7, #4] + /* Return the selected ADC converted value */ + return hadc->Instance->DR; + 8004864: 687b ldr r3, [r7, #4] + 8004866: 681b ldr r3, [r3, #0] + 8004868: 6cdb ldr r3, [r3, #76] ; 0x4c +} + 800486a: 4618 mov r0, r3 + 800486c: 370c adds r7, #12 + 800486e: 46bd mov sp, r7 + 8004870: f85d 7b04 ldr.w r7, [sp], #4 + 8004874: 4770 bx lr + ... + +08004878 : + * the configuration information for the specified ADC. + * @param sConfig ADC configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + 8004878: b480 push {r7} + 800487a: b085 sub sp, #20 + 800487c: af00 add r7, sp, #0 + 800487e: 6078 str r0, [r7, #4] + 8004880: 6039 str r1, [r7, #0] + __IO uint32_t counter = 0; + 8004882: 2300 movs r3, #0 + 8004884: 60fb str r3, [r7, #12] + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + 8004886: 687b ldr r3, [r7, #4] + 8004888: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800488c: 2b01 cmp r3, #1 + 800488e: d101 bne.n 8004894 + 8004890: 2302 movs r3, #2 + 8004892: e12a b.n 8004aea + 8004894: 687b ldr r3, [r7, #4] + 8004896: 2201 movs r2, #1 + 8004898: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) + 800489c: 683b ldr r3, [r7, #0] + 800489e: 681b ldr r3, [r3, #0] + 80048a0: 2b09 cmp r3, #9 + 80048a2: d93a bls.n 800491a + 80048a4: 683b ldr r3, [r7, #0] + 80048a6: 681b ldr r3, [r3, #0] + 80048a8: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 80048ac: d035 beq.n 800491a + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + 80048ae: 687b ldr r3, [r7, #4] + 80048b0: 681b ldr r3, [r3, #0] + 80048b2: 68d9 ldr r1, [r3, #12] + 80048b4: 683b ldr r3, [r7, #0] + 80048b6: 681b ldr r3, [r3, #0] + 80048b8: b29b uxth r3, r3 + 80048ba: 461a mov r2, r3 + 80048bc: 4613 mov r3, r2 + 80048be: 005b lsls r3, r3, #1 + 80048c0: 4413 add r3, r2 + 80048c2: 3b1e subs r3, #30 + 80048c4: 2207 movs r2, #7 + 80048c6: fa02 f303 lsl.w r3, r2, r3 + 80048ca: 43da mvns r2, r3 + 80048cc: 687b ldr r3, [r7, #4] + 80048ce: 681b ldr r3, [r3, #0] + 80048d0: 400a ands r2, r1 + 80048d2: 60da str r2, [r3, #12] + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 80048d4: 683b ldr r3, [r7, #0] + 80048d6: 681b ldr r3, [r3, #0] + 80048d8: 4a87 ldr r2, [pc, #540] ; (8004af8 ) + 80048da: 4293 cmp r3, r2 + 80048dc: d10a bne.n 80048f4 + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); + 80048de: 687b ldr r3, [r7, #4] + 80048e0: 681b ldr r3, [r3, #0] + 80048e2: 68d9 ldr r1, [r3, #12] + 80048e4: 683b ldr r3, [r7, #0] + 80048e6: 689b ldr r3, [r3, #8] + 80048e8: 061a lsls r2, r3, #24 + 80048ea: 687b ldr r3, [r7, #4] + 80048ec: 681b ldr r3, [r3, #0] + 80048ee: 430a orrs r2, r1 + 80048f0: 60da str r2, [r3, #12] + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 80048f2: e035 b.n 8004960 + } + else + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + 80048f4: 687b ldr r3, [r7, #4] + 80048f6: 681b ldr r3, [r3, #0] + 80048f8: 68d9 ldr r1, [r3, #12] + 80048fa: 683b ldr r3, [r7, #0] + 80048fc: 689a ldr r2, [r3, #8] + 80048fe: 683b ldr r3, [r7, #0] + 8004900: 681b ldr r3, [r3, #0] + 8004902: b29b uxth r3, r3 + 8004904: 4618 mov r0, r3 + 8004906: 4603 mov r3, r0 + 8004908: 005b lsls r3, r3, #1 + 800490a: 4403 add r3, r0 + 800490c: 3b1e subs r3, #30 + 800490e: 409a lsls r2, r3 + 8004910: 687b ldr r3, [r7, #4] + 8004912: 681b ldr r3, [r3, #0] + 8004914: 430a orrs r2, r1 + 8004916: 60da str r2, [r3, #12] + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 8004918: e022 b.n 8004960 + } + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); + 800491a: 687b ldr r3, [r7, #4] + 800491c: 681b ldr r3, [r3, #0] + 800491e: 6919 ldr r1, [r3, #16] + 8004920: 683b ldr r3, [r7, #0] + 8004922: 681b ldr r3, [r3, #0] + 8004924: b29b uxth r3, r3 + 8004926: 461a mov r2, r3 + 8004928: 4613 mov r3, r2 + 800492a: 005b lsls r3, r3, #1 + 800492c: 4413 add r3, r2 + 800492e: 2207 movs r2, #7 + 8004930: fa02 f303 lsl.w r3, r2, r3 + 8004934: 43da mvns r2, r3 + 8004936: 687b ldr r3, [r7, #4] + 8004938: 681b ldr r3, [r3, #0] + 800493a: 400a ands r2, r1 + 800493c: 611a str r2, [r3, #16] + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); + 800493e: 687b ldr r3, [r7, #4] + 8004940: 681b ldr r3, [r3, #0] + 8004942: 6919 ldr r1, [r3, #16] + 8004944: 683b ldr r3, [r7, #0] + 8004946: 689a ldr r2, [r3, #8] + 8004948: 683b ldr r3, [r7, #0] + 800494a: 681b ldr r3, [r3, #0] + 800494c: b29b uxth r3, r3 + 800494e: 4618 mov r0, r3 + 8004950: 4603 mov r3, r0 + 8004952: 005b lsls r3, r3, #1 + 8004954: 4403 add r3, r0 + 8004956: 409a lsls r2, r3 + 8004958: 687b ldr r3, [r7, #4] + 800495a: 681b ldr r3, [r3, #0] + 800495c: 430a orrs r2, r1 + 800495e: 611a str r2, [r3, #16] + } + + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7) + 8004960: 683b ldr r3, [r7, #0] + 8004962: 685b ldr r3, [r3, #4] + 8004964: 2b06 cmp r3, #6 + 8004966: d824 bhi.n 80049b2 + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); + 8004968: 687b ldr r3, [r7, #4] + 800496a: 681b ldr r3, [r3, #0] + 800496c: 6b59 ldr r1, [r3, #52] ; 0x34 + 800496e: 683b ldr r3, [r7, #0] + 8004970: 685a ldr r2, [r3, #4] + 8004972: 4613 mov r3, r2 + 8004974: 009b lsls r3, r3, #2 + 8004976: 4413 add r3, r2 + 8004978: 3b05 subs r3, #5 + 800497a: 221f movs r2, #31 + 800497c: fa02 f303 lsl.w r3, r2, r3 + 8004980: 43da mvns r2, r3 + 8004982: 687b ldr r3, [r7, #4] + 8004984: 681b ldr r3, [r3, #0] + 8004986: 400a ands r2, r1 + 8004988: 635a str r2, [r3, #52] ; 0x34 + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); + 800498a: 687b ldr r3, [r7, #4] + 800498c: 681b ldr r3, [r3, #0] + 800498e: 6b59 ldr r1, [r3, #52] ; 0x34 + 8004990: 683b ldr r3, [r7, #0] + 8004992: 681b ldr r3, [r3, #0] + 8004994: b29b uxth r3, r3 + 8004996: 4618 mov r0, r3 + 8004998: 683b ldr r3, [r7, #0] + 800499a: 685a ldr r2, [r3, #4] + 800499c: 4613 mov r3, r2 + 800499e: 009b lsls r3, r3, #2 + 80049a0: 4413 add r3, r2 + 80049a2: 3b05 subs r3, #5 + 80049a4: fa00 f203 lsl.w r2, r0, r3 + 80049a8: 687b ldr r3, [r7, #4] + 80049aa: 681b ldr r3, [r3, #0] + 80049ac: 430a orrs r2, r1 + 80049ae: 635a str r2, [r3, #52] ; 0x34 + 80049b0: e04c b.n 8004a4c + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13) + 80049b2: 683b ldr r3, [r7, #0] + 80049b4: 685b ldr r3, [r3, #4] + 80049b6: 2b0c cmp r3, #12 + 80049b8: d824 bhi.n 8004a04 + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); + 80049ba: 687b ldr r3, [r7, #4] + 80049bc: 681b ldr r3, [r3, #0] + 80049be: 6b19 ldr r1, [r3, #48] ; 0x30 + 80049c0: 683b ldr r3, [r7, #0] + 80049c2: 685a ldr r2, [r3, #4] + 80049c4: 4613 mov r3, r2 + 80049c6: 009b lsls r3, r3, #2 + 80049c8: 4413 add r3, r2 + 80049ca: 3b23 subs r3, #35 ; 0x23 + 80049cc: 221f movs r2, #31 + 80049ce: fa02 f303 lsl.w r3, r2, r3 + 80049d2: 43da mvns r2, r3 + 80049d4: 687b ldr r3, [r7, #4] + 80049d6: 681b ldr r3, [r3, #0] + 80049d8: 400a ands r2, r1 + 80049da: 631a str r2, [r3, #48] ; 0x30 + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); + 80049dc: 687b ldr r3, [r7, #4] + 80049de: 681b ldr r3, [r3, #0] + 80049e0: 6b19 ldr r1, [r3, #48] ; 0x30 + 80049e2: 683b ldr r3, [r7, #0] + 80049e4: 681b ldr r3, [r3, #0] + 80049e6: b29b uxth r3, r3 + 80049e8: 4618 mov r0, r3 + 80049ea: 683b ldr r3, [r7, #0] + 80049ec: 685a ldr r2, [r3, #4] + 80049ee: 4613 mov r3, r2 + 80049f0: 009b lsls r3, r3, #2 + 80049f2: 4413 add r3, r2 + 80049f4: 3b23 subs r3, #35 ; 0x23 + 80049f6: fa00 f203 lsl.w r2, r0, r3 + 80049fa: 687b ldr r3, [r7, #4] + 80049fc: 681b ldr r3, [r3, #0] + 80049fe: 430a orrs r2, r1 + 8004a00: 631a str r2, [r3, #48] ; 0x30 + 8004a02: e023 b.n 8004a4c + } + /* For Rank 13 to 16 */ + else + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); + 8004a04: 687b ldr r3, [r7, #4] + 8004a06: 681b ldr r3, [r3, #0] + 8004a08: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8004a0a: 683b ldr r3, [r7, #0] + 8004a0c: 685a ldr r2, [r3, #4] + 8004a0e: 4613 mov r3, r2 + 8004a10: 009b lsls r3, r3, #2 + 8004a12: 4413 add r3, r2 + 8004a14: 3b41 subs r3, #65 ; 0x41 + 8004a16: 221f movs r2, #31 + 8004a18: fa02 f303 lsl.w r3, r2, r3 + 8004a1c: 43da mvns r2, r3 + 8004a1e: 687b ldr r3, [r7, #4] + 8004a20: 681b ldr r3, [r3, #0] + 8004a22: 400a ands r2, r1 + 8004a24: 62da str r2, [r3, #44] ; 0x2c + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); + 8004a26: 687b ldr r3, [r7, #4] + 8004a28: 681b ldr r3, [r3, #0] + 8004a2a: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8004a2c: 683b ldr r3, [r7, #0] + 8004a2e: 681b ldr r3, [r3, #0] + 8004a30: b29b uxth r3, r3 + 8004a32: 4618 mov r0, r3 + 8004a34: 683b ldr r3, [r7, #0] + 8004a36: 685a ldr r2, [r3, #4] + 8004a38: 4613 mov r3, r2 + 8004a3a: 009b lsls r3, r3, #2 + 8004a3c: 4413 add r3, r2 + 8004a3e: 3b41 subs r3, #65 ; 0x41 + 8004a40: fa00 f203 lsl.w r2, r0, r3 + 8004a44: 687b ldr r3, [r7, #4] + 8004a46: 681b ldr r3, [r3, #0] + 8004a48: 430a orrs r2, r1 + 8004a4a: 62da str r2, [r3, #44] ; 0x2c + } + + /* if no internal channel selected */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 681b ldr r3, [r3, #0] + 8004a50: 4a2a ldr r2, [pc, #168] ; (8004afc ) + 8004a52: 4293 cmp r3, r2 + 8004a54: d10a bne.n 8004a6c + 8004a56: 683b ldr r3, [r7, #0] + 8004a58: 681b ldr r3, [r3, #0] + 8004a5a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8004a5e: d105 bne.n 8004a6c + { + /* Disable the VBAT & TSVREFE channel*/ + ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); + 8004a60: 4b27 ldr r3, [pc, #156] ; (8004b00 ) + 8004a62: 685b ldr r3, [r3, #4] + 8004a64: 4a26 ldr r2, [pc, #152] ; (8004b00 ) + 8004a66: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000 + 8004a6a: 6053 str r3, [r2, #4] + } + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) + 8004a6c: 687b ldr r3, [r7, #4] + 8004a6e: 681b ldr r3, [r3, #0] + 8004a70: 4a22 ldr r2, [pc, #136] ; (8004afc ) + 8004a72: 4293 cmp r3, r2 + 8004a74: d109 bne.n 8004a8a + 8004a76: 683b ldr r3, [r7, #0] + 8004a78: 681b ldr r3, [r3, #0] + 8004a7a: 2b12 cmp r3, #18 + 8004a7c: d105 bne.n 8004a8a + { + /* Enable the VBAT channel*/ + ADC->CCR |= ADC_CCR_VBATE; + 8004a7e: 4b20 ldr r3, [pc, #128] ; (8004b00 ) + 8004a80: 685b ldr r3, [r3, #4] + 8004a82: 4a1f ldr r2, [pc, #124] ; (8004b00 ) + 8004a84: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 8004a88: 6053 str r3, [r2, #4] + } + + /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) + 8004a8a: 687b ldr r3, [r7, #4] + 8004a8c: 681b ldr r3, [r3, #0] + 8004a8e: 4a1b ldr r2, [pc, #108] ; (8004afc ) + 8004a90: 4293 cmp r3, r2 + 8004a92: d125 bne.n 8004ae0 + 8004a94: 683b ldr r3, [r7, #0] + 8004a96: 681b ldr r3, [r3, #0] + 8004a98: 4a17 ldr r2, [pc, #92] ; (8004af8 ) + 8004a9a: 4293 cmp r3, r2 + 8004a9c: d003 beq.n 8004aa6 + 8004a9e: 683b ldr r3, [r7, #0] + 8004aa0: 681b ldr r3, [r3, #0] + 8004aa2: 2b11 cmp r3, #17 + 8004aa4: d11c bne.n 8004ae0 + { + /* Enable the TSVREFE channel*/ + ADC->CCR |= ADC_CCR_TSVREFE; + 8004aa6: 4b16 ldr r3, [pc, #88] ; (8004b00 ) + 8004aa8: 685b ldr r3, [r3, #4] + 8004aaa: 4a15 ldr r2, [pc, #84] ; (8004b00 ) + 8004aac: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 8004ab0: 6053 str r3, [r2, #4] + + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 8004ab2: 683b ldr r3, [r7, #0] + 8004ab4: 681b ldr r3, [r3, #0] + 8004ab6: 4a10 ldr r2, [pc, #64] ; (8004af8 ) + 8004ab8: 4293 cmp r3, r2 + 8004aba: d111 bne.n 8004ae0 + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + 8004abc: 4b11 ldr r3, [pc, #68] ; (8004b04 ) + 8004abe: 681b ldr r3, [r3, #0] + 8004ac0: 4a11 ldr r2, [pc, #68] ; (8004b08 ) + 8004ac2: fba2 2303 umull r2, r3, r2, r3 + 8004ac6: 0c9a lsrs r2, r3, #18 + 8004ac8: 4613 mov r3, r2 + 8004aca: 009b lsls r3, r3, #2 + 8004acc: 4413 add r3, r2 + 8004ace: 005b lsls r3, r3, #1 + 8004ad0: 60fb str r3, [r7, #12] + while(counter != 0) + 8004ad2: e002 b.n 8004ada + { + counter--; + 8004ad4: 68fb ldr r3, [r7, #12] + 8004ad6: 3b01 subs r3, #1 + 8004ad8: 60fb str r3, [r7, #12] + while(counter != 0) + 8004ada: 68fb ldr r3, [r7, #12] + 8004adc: 2b00 cmp r3, #0 + 8004ade: d1f9 bne.n 8004ad4 + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8004ae0: 687b ldr r3, [r7, #4] + 8004ae2: 2200 movs r2, #0 + 8004ae4: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Return function status */ + return HAL_OK; + 8004ae8: 2300 movs r3, #0 +} + 8004aea: 4618 mov r0, r3 + 8004aec: 3714 adds r7, #20 + 8004aee: 46bd mov sp, r7 + 8004af0: f85d 7b04 ldr.w r7, [sp], #4 + 8004af4: 4770 bx lr + 8004af6: bf00 nop + 8004af8: 10000012 .word 0x10000012 + 8004afc: 40012000 .word 0x40012000 + 8004b00: 40012300 .word 0x40012300 + 8004b04: 2000003c .word 0x2000003c + 8004b08: 431bde83 .word 0x431bde83 + +08004b0c : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +static void ADC_Init(ADC_HandleTypeDef* hadc) +{ + 8004b0c: b480 push {r7} + 8004b0e: b083 sub sp, #12 + 8004b10: af00 add r7, sp, #0 + 8004b12: 6078 str r0, [r7, #4] + /* Set ADC parameters */ + /* Set the ADC clock prescaler */ + ADC->CCR &= ~(ADC_CCR_ADCPRE); + 8004b14: 4b78 ldr r3, [pc, #480] ; (8004cf8 ) + 8004b16: 685b ldr r3, [r3, #4] + 8004b18: 4a77 ldr r2, [pc, #476] ; (8004cf8 ) + 8004b1a: f423 3340 bic.w r3, r3, #196608 ; 0x30000 + 8004b1e: 6053 str r3, [r2, #4] + ADC->CCR |= hadc->Init.ClockPrescaler; + 8004b20: 4b75 ldr r3, [pc, #468] ; (8004cf8 ) + 8004b22: 685a ldr r2, [r3, #4] + 8004b24: 687b ldr r3, [r7, #4] + 8004b26: 685b ldr r3, [r3, #4] + 8004b28: 4973 ldr r1, [pc, #460] ; (8004cf8 ) + 8004b2a: 4313 orrs r3, r2 + 8004b2c: 604b str r3, [r1, #4] + + /* Set ADC scan mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + 8004b2e: 687b ldr r3, [r7, #4] + 8004b30: 681b ldr r3, [r3, #0] + 8004b32: 685a ldr r2, [r3, #4] + 8004b34: 687b ldr r3, [r7, #4] + 8004b36: 681b ldr r3, [r3, #0] + 8004b38: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8004b3c: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + 8004b3e: 687b ldr r3, [r7, #4] + 8004b40: 681b ldr r3, [r3, #0] + 8004b42: 6859 ldr r1, [r3, #4] + 8004b44: 687b ldr r3, [r7, #4] + 8004b46: 691b ldr r3, [r3, #16] + 8004b48: 021a lsls r2, r3, #8 + 8004b4a: 687b ldr r3, [r7, #4] + 8004b4c: 681b ldr r3, [r3, #0] + 8004b4e: 430a orrs r2, r1 + 8004b50: 605a str r2, [r3, #4] + + /* Set ADC resolution */ + hadc->Instance->CR1 &= ~(ADC_CR1_RES); + 8004b52: 687b ldr r3, [r7, #4] + 8004b54: 681b ldr r3, [r3, #0] + 8004b56: 685a ldr r2, [r3, #4] + 8004b58: 687b ldr r3, [r7, #4] + 8004b5a: 681b ldr r3, [r3, #0] + 8004b5c: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000 + 8004b60: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= hadc->Init.Resolution; + 8004b62: 687b ldr r3, [r7, #4] + 8004b64: 681b ldr r3, [r3, #0] + 8004b66: 6859 ldr r1, [r3, #4] + 8004b68: 687b ldr r3, [r7, #4] + 8004b6a: 689a ldr r2, [r3, #8] + 8004b6c: 687b ldr r3, [r7, #4] + 8004b6e: 681b ldr r3, [r3, #0] + 8004b70: 430a orrs r2, r1 + 8004b72: 605a str r2, [r3, #4] + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + 8004b74: 687b ldr r3, [r7, #4] + 8004b76: 681b ldr r3, [r3, #0] + 8004b78: 689a ldr r2, [r3, #8] + 8004b7a: 687b ldr r3, [r7, #4] + 8004b7c: 681b ldr r3, [r3, #0] + 8004b7e: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8004b82: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.DataAlign; + 8004b84: 687b ldr r3, [r7, #4] + 8004b86: 681b ldr r3, [r3, #0] + 8004b88: 6899 ldr r1, [r3, #8] + 8004b8a: 687b ldr r3, [r7, #4] + 8004b8c: 68da ldr r2, [r3, #12] + 8004b8e: 687b ldr r3, [r7, #4] + 8004b90: 681b ldr r3, [r3, #0] + 8004b92: 430a orrs r2, r1 + 8004b94: 609a str r2, [r3, #8] + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 8004b96: 687b ldr r3, [r7, #4] + 8004b98: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004b9a: 4a58 ldr r2, [pc, #352] ; (8004cfc ) + 8004b9c: 4293 cmp r3, r2 + 8004b9e: d022 beq.n 8004be6 + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + 8004ba0: 687b ldr r3, [r7, #4] + 8004ba2: 681b ldr r3, [r3, #0] + 8004ba4: 689a ldr r2, [r3, #8] + 8004ba6: 687b ldr r3, [r7, #4] + 8004ba8: 681b ldr r3, [r3, #0] + 8004baa: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 8004bae: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + 8004bb0: 687b ldr r3, [r7, #4] + 8004bb2: 681b ldr r3, [r3, #0] + 8004bb4: 6899 ldr r1, [r3, #8] + 8004bb6: 687b ldr r3, [r7, #4] + 8004bb8: 6a9a ldr r2, [r3, #40] ; 0x28 + 8004bba: 687b ldr r3, [r7, #4] + 8004bbc: 681b ldr r3, [r3, #0] + 8004bbe: 430a orrs r2, r1 + 8004bc0: 609a str r2, [r3, #8] + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 8004bc2: 687b ldr r3, [r7, #4] + 8004bc4: 681b ldr r3, [r3, #0] + 8004bc6: 689a ldr r2, [r3, #8] + 8004bc8: 687b ldr r3, [r7, #4] + 8004bca: 681b ldr r3, [r3, #0] + 8004bcc: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 + 8004bd0: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + 8004bd2: 687b ldr r3, [r7, #4] + 8004bd4: 681b ldr r3, [r3, #0] + 8004bd6: 6899 ldr r1, [r3, #8] + 8004bd8: 687b ldr r3, [r7, #4] + 8004bda: 6ada ldr r2, [r3, #44] ; 0x2c + 8004bdc: 687b ldr r3, [r7, #4] + 8004bde: 681b ldr r3, [r3, #0] + 8004be0: 430a orrs r2, r1 + 8004be2: 609a str r2, [r3, #8] + 8004be4: e00f b.n 8004c06 + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + 8004be6: 687b ldr r3, [r7, #4] + 8004be8: 681b ldr r3, [r3, #0] + 8004bea: 689a ldr r2, [r3, #8] + 8004bec: 687b ldr r3, [r7, #4] + 8004bee: 681b ldr r3, [r3, #0] + 8004bf0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 8004bf4: 609a str r2, [r3, #8] + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 8004bf6: 687b ldr r3, [r7, #4] + 8004bf8: 681b ldr r3, [r3, #0] + 8004bfa: 689a ldr r2, [r3, #8] + 8004bfc: 687b ldr r3, [r7, #4] + 8004bfe: 681b ldr r3, [r3, #0] + 8004c00: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 + 8004c04: 609a str r2, [r3, #8] + } + + /* Enable or disable ADC continuous conversion mode */ + hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + 8004c06: 687b ldr r3, [r7, #4] + 8004c08: 681b ldr r3, [r3, #0] + 8004c0a: 689a ldr r2, [r3, #8] + 8004c0c: 687b ldr r3, [r7, #4] + 8004c0e: 681b ldr r3, [r3, #0] + 8004c10: f022 0202 bic.w r2, r2, #2 + 8004c14: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + 8004c16: 687b ldr r3, [r7, #4] + 8004c18: 681b ldr r3, [r3, #0] + 8004c1a: 6899 ldr r1, [r3, #8] + 8004c1c: 687b ldr r3, [r7, #4] + 8004c1e: 699b ldr r3, [r3, #24] + 8004c20: 005a lsls r2, r3, #1 + 8004c22: 687b ldr r3, [r7, #4] + 8004c24: 681b ldr r3, [r3, #0] + 8004c26: 430a orrs r2, r1 + 8004c28: 609a str r2, [r3, #8] + + if(hadc->Init.DiscontinuousConvMode != DISABLE) + 8004c2a: 687b ldr r3, [r7, #4] + 8004c2c: f893 3020 ldrb.w r3, [r3, #32] + 8004c30: 2b00 cmp r3, #0 + 8004c32: d01b beq.n 8004c6c + { + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + 8004c34: 687b ldr r3, [r7, #4] + 8004c36: 681b ldr r3, [r3, #0] + 8004c38: 685a ldr r2, [r3, #4] + 8004c3a: 687b ldr r3, [r7, #4] + 8004c3c: 681b ldr r3, [r3, #0] + 8004c3e: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8004c42: 605a str r2, [r3, #4] + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + 8004c44: 687b ldr r3, [r7, #4] + 8004c46: 681b ldr r3, [r3, #0] + 8004c48: 685a ldr r2, [r3, #4] + 8004c4a: 687b ldr r3, [r7, #4] + 8004c4c: 681b ldr r3, [r3, #0] + 8004c4e: f422 4260 bic.w r2, r2, #57344 ; 0xe000 + 8004c52: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + 8004c54: 687b ldr r3, [r7, #4] + 8004c56: 681b ldr r3, [r3, #0] + 8004c58: 6859 ldr r1, [r3, #4] + 8004c5a: 687b ldr r3, [r7, #4] + 8004c5c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004c5e: 3b01 subs r3, #1 + 8004c60: 035a lsls r2, r3, #13 + 8004c62: 687b ldr r3, [r7, #4] + 8004c64: 681b ldr r3, [r3, #0] + 8004c66: 430a orrs r2, r1 + 8004c68: 605a str r2, [r3, #4] + 8004c6a: e007 b.n 8004c7c + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); + 8004c6c: 687b ldr r3, [r7, #4] + 8004c6e: 681b ldr r3, [r3, #0] + 8004c70: 685a ldr r2, [r3, #4] + 8004c72: 687b ldr r3, [r7, #4] + 8004c74: 681b ldr r3, [r3, #0] + 8004c76: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8004c7a: 605a str r2, [r3, #4] + } + + /* Set ADC number of conversion */ + hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + 8004c7c: 687b ldr r3, [r7, #4] + 8004c7e: 681b ldr r3, [r3, #0] + 8004c80: 6ada ldr r2, [r3, #44] ; 0x2c + 8004c82: 687b ldr r3, [r7, #4] + 8004c84: 681b ldr r3, [r3, #0] + 8004c86: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000 + 8004c8a: 62da str r2, [r3, #44] ; 0x2c + hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + 8004c8c: 687b ldr r3, [r7, #4] + 8004c8e: 681b ldr r3, [r3, #0] + 8004c90: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8004c92: 687b ldr r3, [r7, #4] + 8004c94: 69db ldr r3, [r3, #28] + 8004c96: 3b01 subs r3, #1 + 8004c98: 051a lsls r2, r3, #20 + 8004c9a: 687b ldr r3, [r7, #4] + 8004c9c: 681b ldr r3, [r3, #0] + 8004c9e: 430a orrs r2, r1 + 8004ca0: 62da str r2, [r3, #44] ; 0x2c + + /* Enable or disable ADC DMA continuous request */ + hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + 8004ca2: 687b ldr r3, [r7, #4] + 8004ca4: 681b ldr r3, [r3, #0] + 8004ca6: 689a ldr r2, [r3, #8] + 8004ca8: 687b ldr r3, [r7, #4] + 8004caa: 681b ldr r3, [r3, #0] + 8004cac: f422 7200 bic.w r2, r2, #512 ; 0x200 + 8004cb0: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + 8004cb2: 687b ldr r3, [r7, #4] + 8004cb4: 681b ldr r3, [r3, #0] + 8004cb6: 6899 ldr r1, [r3, #8] + 8004cb8: 687b ldr r3, [r7, #4] + 8004cba: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8004cbe: 025a lsls r2, r3, #9 + 8004cc0: 687b ldr r3, [r7, #4] + 8004cc2: 681b ldr r3, [r3, #0] + 8004cc4: 430a orrs r2, r1 + 8004cc6: 609a str r2, [r3, #8] + + /* Enable or disable ADC end of conversion selection */ + hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + 8004cc8: 687b ldr r3, [r7, #4] + 8004cca: 681b ldr r3, [r3, #0] + 8004ccc: 689a ldr r2, [r3, #8] + 8004cce: 687b ldr r3, [r7, #4] + 8004cd0: 681b ldr r3, [r3, #0] + 8004cd2: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8004cd6: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); + 8004cd8: 687b ldr r3, [r7, #4] + 8004cda: 681b ldr r3, [r3, #0] + 8004cdc: 6899 ldr r1, [r3, #8] + 8004cde: 687b ldr r3, [r7, #4] + 8004ce0: 695b ldr r3, [r3, #20] + 8004ce2: 029a lsls r2, r3, #10 + 8004ce4: 687b ldr r3, [r7, #4] + 8004ce6: 681b ldr r3, [r3, #0] + 8004ce8: 430a orrs r2, r1 + 8004cea: 609a str r2, [r3, #8] +} + 8004cec: bf00 nop + 8004cee: 370c adds r7, #12 + 8004cf0: 46bd mov sp, r7 + 8004cf2: f85d 7b04 ldr.w r7, [sp], #4 + 8004cf6: 4770 bx lr + 8004cf8: 40012300 .word 0x40012300 + 8004cfc: 0f000001 .word 0x0f000001 + +08004d00 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8004d00: b480 push {r7} + 8004d02: b085 sub sp, #20 + 8004d04: af00 add r7, sp, #0 + 8004d06: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8004d08: 687b ldr r3, [r7, #4] + 8004d0a: f003 0307 and.w r3, r3, #7 + 8004d0e: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8004d10: 4b0b ldr r3, [pc, #44] ; (8004d40 <__NVIC_SetPriorityGrouping+0x40>) + 8004d12: 68db ldr r3, [r3, #12] + 8004d14: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8004d16: 68ba ldr r2, [r7, #8] + 8004d18: f64f 03ff movw r3, #63743 ; 0xf8ff + 8004d1c: 4013 ands r3, r2 + 8004d1e: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8004d20: 68fb ldr r3, [r7, #12] + 8004d22: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8004d24: 68bb ldr r3, [r7, #8] + 8004d26: 431a orrs r2, r3 + reg_value = (reg_value | + 8004d28: 4b06 ldr r3, [pc, #24] ; (8004d44 <__NVIC_SetPriorityGrouping+0x44>) + 8004d2a: 4313 orrs r3, r2 + 8004d2c: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8004d2e: 4a04 ldr r2, [pc, #16] ; (8004d40 <__NVIC_SetPriorityGrouping+0x40>) + 8004d30: 68bb ldr r3, [r7, #8] + 8004d32: 60d3 str r3, [r2, #12] +} + 8004d34: bf00 nop + 8004d36: 3714 adds r7, #20 + 8004d38: 46bd mov sp, r7 + 8004d3a: f85d 7b04 ldr.w r7, [sp], #4 + 8004d3e: 4770 bx lr + 8004d40: e000ed00 .word 0xe000ed00 + 8004d44: 05fa0000 .word 0x05fa0000 + +08004d48 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8004d48: b480 push {r7} + 8004d4a: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8004d4c: 4b04 ldr r3, [pc, #16] ; (8004d60 <__NVIC_GetPriorityGrouping+0x18>) + 8004d4e: 68db ldr r3, [r3, #12] + 8004d50: 0a1b lsrs r3, r3, #8 + 8004d52: f003 0307 and.w r3, r3, #7 +} + 8004d56: 4618 mov r0, r3 + 8004d58: 46bd mov sp, r7 + 8004d5a: f85d 7b04 ldr.w r7, [sp], #4 + 8004d5e: 4770 bx lr + 8004d60: e000ed00 .word 0xe000ed00 + +08004d64 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8004d64: b480 push {r7} + 8004d66: b083 sub sp, #12 + 8004d68: af00 add r7, sp, #0 + 8004d6a: 4603 mov r3, r0 + 8004d6c: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8004d6e: f997 3007 ldrsb.w r3, [r7, #7] + 8004d72: 2b00 cmp r3, #0 + 8004d74: db0b blt.n 8004d8e <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8004d76: 79fb ldrb r3, [r7, #7] + 8004d78: f003 021f and.w r2, r3, #31 + 8004d7c: 4907 ldr r1, [pc, #28] ; (8004d9c <__NVIC_EnableIRQ+0x38>) + 8004d7e: f997 3007 ldrsb.w r3, [r7, #7] + 8004d82: 095b lsrs r3, r3, #5 + 8004d84: 2001 movs r0, #1 + 8004d86: fa00 f202 lsl.w r2, r0, r2 + 8004d8a: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8004d8e: bf00 nop + 8004d90: 370c adds r7, #12 + 8004d92: 46bd mov sp, r7 + 8004d94: f85d 7b04 ldr.w r7, [sp], #4 + 8004d98: 4770 bx lr + 8004d9a: bf00 nop + 8004d9c: e000e100 .word 0xe000e100 + +08004da0 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8004da0: b480 push {r7} + 8004da2: b083 sub sp, #12 + 8004da4: af00 add r7, sp, #0 + 8004da6: 4603 mov r3, r0 + 8004da8: 6039 str r1, [r7, #0] + 8004daa: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8004dac: f997 3007 ldrsb.w r3, [r7, #7] + 8004db0: 2b00 cmp r3, #0 + 8004db2: db0a blt.n 8004dca <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8004db4: 683b ldr r3, [r7, #0] + 8004db6: b2da uxtb r2, r3 + 8004db8: 490c ldr r1, [pc, #48] ; (8004dec <__NVIC_SetPriority+0x4c>) + 8004dba: f997 3007 ldrsb.w r3, [r7, #7] + 8004dbe: 0112 lsls r2, r2, #4 + 8004dc0: b2d2 uxtb r2, r2 + 8004dc2: 440b add r3, r1 + 8004dc4: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8004dc8: e00a b.n 8004de0 <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8004dca: 683b ldr r3, [r7, #0] + 8004dcc: b2da uxtb r2, r3 + 8004dce: 4908 ldr r1, [pc, #32] ; (8004df0 <__NVIC_SetPriority+0x50>) + 8004dd0: 79fb ldrb r3, [r7, #7] + 8004dd2: f003 030f and.w r3, r3, #15 + 8004dd6: 3b04 subs r3, #4 + 8004dd8: 0112 lsls r2, r2, #4 + 8004dda: b2d2 uxtb r2, r2 + 8004ddc: 440b add r3, r1 + 8004dde: 761a strb r2, [r3, #24] +} + 8004de0: bf00 nop + 8004de2: 370c adds r7, #12 + 8004de4: 46bd mov sp, r7 + 8004de6: f85d 7b04 ldr.w r7, [sp], #4 + 8004dea: 4770 bx lr + 8004dec: e000e100 .word 0xe000e100 + 8004df0: e000ed00 .word 0xe000ed00 + +08004df4 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8004df4: b480 push {r7} + 8004df6: b089 sub sp, #36 ; 0x24 + 8004df8: af00 add r7, sp, #0 + 8004dfa: 60f8 str r0, [r7, #12] + 8004dfc: 60b9 str r1, [r7, #8] + 8004dfe: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8004e00: 68fb ldr r3, [r7, #12] + 8004e02: f003 0307 and.w r3, r3, #7 + 8004e06: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8004e08: 69fb ldr r3, [r7, #28] + 8004e0a: f1c3 0307 rsb r3, r3, #7 + 8004e0e: 2b04 cmp r3, #4 + 8004e10: bf28 it cs + 8004e12: 2304 movcs r3, #4 + 8004e14: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8004e16: 69fb ldr r3, [r7, #28] + 8004e18: 3304 adds r3, #4 + 8004e1a: 2b06 cmp r3, #6 + 8004e1c: d902 bls.n 8004e24 + 8004e1e: 69fb ldr r3, [r7, #28] + 8004e20: 3b03 subs r3, #3 + 8004e22: e000 b.n 8004e26 + 8004e24: 2300 movs r3, #0 + 8004e26: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8004e28: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 8004e2c: 69bb ldr r3, [r7, #24] + 8004e2e: fa02 f303 lsl.w r3, r2, r3 + 8004e32: 43da mvns r2, r3 + 8004e34: 68bb ldr r3, [r7, #8] + 8004e36: 401a ands r2, r3 + 8004e38: 697b ldr r3, [r7, #20] + 8004e3a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8004e3c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8004e40: 697b ldr r3, [r7, #20] + 8004e42: fa01 f303 lsl.w r3, r1, r3 + 8004e46: 43d9 mvns r1, r3 + 8004e48: 687b ldr r3, [r7, #4] + 8004e4a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8004e4c: 4313 orrs r3, r2 + ); +} + 8004e4e: 4618 mov r0, r3 + 8004e50: 3724 adds r7, #36 ; 0x24 + 8004e52: 46bd mov sp, r7 + 8004e54: f85d 7b04 ldr.w r7, [sp], #4 + 8004e58: 4770 bx lr + +08004e5a : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8004e5a: b580 push {r7, lr} + 8004e5c: b082 sub sp, #8 + 8004e5e: af00 add r7, sp, #0 + 8004e60: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 8004e62: 6878 ldr r0, [r7, #4] + 8004e64: f7ff ff4c bl 8004d00 <__NVIC_SetPriorityGrouping> +} + 8004e68: bf00 nop + 8004e6a: 3708 adds r7, #8 + 8004e6c: 46bd mov sp, r7 + 8004e6e: bd80 pop {r7, pc} + +08004e70 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8004e70: b580 push {r7, lr} + 8004e72: b086 sub sp, #24 + 8004e74: af00 add r7, sp, #0 + 8004e76: 4603 mov r3, r0 + 8004e78: 60b9 str r1, [r7, #8] + 8004e7a: 607a str r2, [r7, #4] + 8004e7c: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00; + 8004e7e: 2300 movs r3, #0 + 8004e80: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8004e82: f7ff ff61 bl 8004d48 <__NVIC_GetPriorityGrouping> + 8004e86: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8004e88: 687a ldr r2, [r7, #4] + 8004e8a: 68b9 ldr r1, [r7, #8] + 8004e8c: 6978 ldr r0, [r7, #20] + 8004e8e: f7ff ffb1 bl 8004df4 + 8004e92: 4602 mov r2, r0 + 8004e94: f997 300f ldrsb.w r3, [r7, #15] + 8004e98: 4611 mov r1, r2 + 8004e9a: 4618 mov r0, r3 + 8004e9c: f7ff ff80 bl 8004da0 <__NVIC_SetPriority> +} + 8004ea0: bf00 nop + 8004ea2: 3718 adds r7, #24 + 8004ea4: 46bd mov sp, r7 + 8004ea6: bd80 pop {r7, pc} + +08004ea8 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8004ea8: b580 push {r7, lr} + 8004eaa: b082 sub sp, #8 + 8004eac: af00 add r7, sp, #0 + 8004eae: 4603 mov r3, r0 + 8004eb0: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8004eb2: f997 3007 ldrsb.w r3, [r7, #7] + 8004eb6: 4618 mov r0, r3 + 8004eb8: f7ff ff54 bl 8004d64 <__NVIC_EnableIRQ> +} + 8004ebc: bf00 nop + 8004ebe: 3708 adds r7, #8 + 8004ec0: 46bd mov sp, r7 + 8004ec2: bd80 pop {r7, pc} + +08004ec4 : + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) +{ + 8004ec4: b580 push {r7, lr} + 8004ec6: b082 sub sp, #8 + 8004ec8: af00 add r7, sp, #0 + 8004eca: 6078 str r0, [r7, #4] + /* Check DAC handle */ + if(hdac == NULL) + 8004ecc: 687b ldr r3, [r7, #4] + 8004ece: 2b00 cmp r3, #0 + 8004ed0: d101 bne.n 8004ed6 + { + return HAL_ERROR; + 8004ed2: 2301 movs r3, #1 + 8004ed4: e014 b.n 8004f00 + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if(hdac->State == HAL_DAC_STATE_RESET) + 8004ed6: 687b ldr r3, [r7, #4] + 8004ed8: 791b ldrb r3, [r3, #4] + 8004eda: b2db uxtb r3, r3 + 8004edc: 2b00 cmp r3, #0 + 8004ede: d105 bne.n 8004eec + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; + 8004ee0: 687b ldr r3, [r7, #4] + 8004ee2: 2200 movs r2, #0 + 8004ee4: 715a strb r2, [r3, #5] +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); + 8004ee6: 6878 ldr r0, [r7, #4] + 8004ee8: f7fe fd4a bl 8003980 +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + 8004eec: 687b ldr r3, [r7, #4] + 8004eee: 2202 movs r2, #2 + 8004ef0: 711a strb r2, [r3, #4] + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + 8004ef2: 687b ldr r3, [r7, #4] + 8004ef4: 2200 movs r2, #0 + 8004ef6: 611a str r2, [r3, #16] + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + 8004ef8: 687b ldr r3, [r7, #4] + 8004efa: 2201 movs r2, #1 + 8004efc: 711a strb r2, [r3, #4] + + /* Return function status */ + return HAL_OK; + 8004efe: 2300 movs r3, #0 +} + 8004f00: 4618 mov r0, r3 + 8004f02: 3708 adds r7, #8 + 8004f04: 46bd mov sp, r7 + 8004f06: bd80 pop {r7, pc} + +08004f08 : + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + 8004f08: b580 push {r7, lr} + 8004f0a: b082 sub sp, #8 + 8004f0c: af00 add r7, sp, #0 + 8004f0e: 6078 str r0, [r7, #4] + /* Check underrun channel 1 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + 8004f10: 687b ldr r3, [r7, #4] + 8004f12: 681b ldr r3, [r3, #0] + 8004f14: 6b5b ldr r3, [r3, #52] ; 0x34 + 8004f16: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8004f1a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8004f1e: d118 bne.n 8004f52 + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + 8004f20: 687b ldr r3, [r7, #4] + 8004f22: 2204 movs r2, #4 + 8004f24: 711a strb r2, [r3, #4] + + /* Set DAC error code to channel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + 8004f26: 687b ldr r3, [r7, #4] + 8004f28: 691b ldr r3, [r3, #16] + 8004f2a: f043 0201 orr.w r2, r3, #1 + 8004f2e: 687b ldr r3, [r7, #4] + 8004f30: 611a str r2, [r3, #16] + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + 8004f32: 687b ldr r3, [r7, #4] + 8004f34: 681b ldr r3, [r3, #0] + 8004f36: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8004f3a: 635a str r2, [r3, #52] ; 0x34 + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + 8004f3c: 687b ldr r3, [r7, #4] + 8004f3e: 681b ldr r3, [r3, #0] + 8004f40: 681a ldr r2, [r3, #0] + 8004f42: 687b ldr r3, [r7, #4] + 8004f44: 681b ldr r3, [r3, #0] + 8004f46: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8004f4a: 601a str r2, [r3, #0] + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + 8004f4c: 6878 ldr r0, [r7, #4] + 8004f4e: f000 f825 bl 8004f9c +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + /* Check underrun channel 2 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + 8004f52: 687b ldr r3, [r7, #4] + 8004f54: 681b ldr r3, [r3, #0] + 8004f56: 6b5b ldr r3, [r3, #52] ; 0x34 + 8004f58: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8004f5c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8004f60: d118 bne.n 8004f94 + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + 8004f62: 687b ldr r3, [r7, #4] + 8004f64: 2204 movs r2, #4 + 8004f66: 711a strb r2, [r3, #4] + + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + 8004f68: 687b ldr r3, [r7, #4] + 8004f6a: 691b ldr r3, [r3, #16] + 8004f6c: f043 0202 orr.w r2, r3, #2 + 8004f70: 687b ldr r3, [r7, #4] + 8004f72: 611a str r2, [r3, #16] + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + 8004f74: 687b ldr r3, [r7, #4] + 8004f76: 681b ldr r3, [r3, #0] + 8004f78: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8004f7c: 635a str r2, [r3, #52] ; 0x34 + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + 8004f7e: 687b ldr r3, [r7, #4] + 8004f80: 681b ldr r3, [r3, #0] + 8004f82: 681a ldr r2, [r3, #0] + 8004f84: 687b ldr r3, [r7, #4] + 8004f86: 681b ldr r3, [r3, #0] + 8004f88: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000 + 8004f8c: 601a str r2, [r3, #0] + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + 8004f8e: 6878 ldr r0, [r7, #4] + 8004f90: f000 f85b bl 800504a +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } +} + 8004f94: bf00 nop + 8004f96: 3708 adds r7, #8 + 8004f98: 46bd mov sp, r7 + 8004f9a: bd80 pop {r7, pc} + +08004f9c : + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + 8004f9c: b480 push {r7} + 8004f9e: b083 sub sp, #12 + 8004fa0: af00 add r7, sp, #0 + 8004fa2: 6078 str r0, [r7, #4] + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + 8004fa4: bf00 nop + 8004fa6: 370c adds r7, #12 + 8004fa8: 46bd mov sp, r7 + 8004faa: f85d 7b04 ldr.w r7, [sp], #4 + 8004fae: 4770 bx lr + +08004fb0 : + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + 8004fb0: b480 push {r7} + 8004fb2: b087 sub sp, #28 + 8004fb4: af00 add r7, sp, #0 + 8004fb6: 60f8 str r0, [r7, #12] + 8004fb8: 60b9 str r1, [r7, #8] + 8004fba: 607a str r2, [r7, #4] + uint32_t tmpreg1 = 0, tmpreg2 = 0; + 8004fbc: 2300 movs r3, #0 + 8004fbe: 617b str r3, [r7, #20] + 8004fc0: 2300 movs r3, #0 + 8004fc2: 613b str r3, [r7, #16] + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + 8004fc4: 68fb ldr r3, [r7, #12] + 8004fc6: 795b ldrb r3, [r3, #5] + 8004fc8: 2b01 cmp r3, #1 + 8004fca: d101 bne.n 8004fd0 + 8004fcc: 2302 movs r3, #2 + 8004fce: e036 b.n 800503e + 8004fd0: 68fb ldr r3, [r7, #12] + 8004fd2: 2201 movs r2, #1 + 8004fd4: 715a strb r2, [r3, #5] + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + 8004fd6: 68fb ldr r3, [r7, #12] + 8004fd8: 2202 movs r2, #2 + 8004fda: 711a strb r2, [r3, #4] + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + 8004fdc: 68fb ldr r3, [r7, #12] + 8004fde: 681b ldr r3, [r3, #0] + 8004fe0: 681b ldr r3, [r3, #0] + 8004fe2: 617b str r3, [r7, #20] + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + 8004fe4: f640 72fe movw r2, #4094 ; 0xffe + 8004fe8: 687b ldr r3, [r7, #4] + 8004fea: fa02 f303 lsl.w r3, r2, r3 + 8004fee: 43db mvns r3, r3 + 8004ff0: 697a ldr r2, [r7, #20] + 8004ff2: 4013 ands r3, r2 + 8004ff4: 617b str r3, [r7, #20] + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + 8004ff6: 68bb ldr r3, [r7, #8] + 8004ff8: 681a ldr r2, [r3, #0] + 8004ffa: 68bb ldr r3, [r7, #8] + 8004ffc: 685b ldr r3, [r3, #4] + 8004ffe: 4313 orrs r3, r2 + 8005000: 613b str r3, [r7, #16] + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << Channel; + 8005002: 693a ldr r2, [r7, #16] + 8005004: 687b ldr r3, [r7, #4] + 8005006: fa02 f303 lsl.w r3, r2, r3 + 800500a: 697a ldr r2, [r7, #20] + 800500c: 4313 orrs r3, r2 + 800500e: 617b str r3, [r7, #20] + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + 8005010: 68fb ldr r3, [r7, #12] + 8005012: 681b ldr r3, [r3, #0] + 8005014: 697a ldr r2, [r7, #20] + 8005016: 601a str r2, [r3, #0] + /* Disable wave generation */ + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); + 8005018: 68fb ldr r3, [r7, #12] + 800501a: 681b ldr r3, [r3, #0] + 800501c: 6819 ldr r1, [r3, #0] + 800501e: 22c0 movs r2, #192 ; 0xc0 + 8005020: 687b ldr r3, [r7, #4] + 8005022: fa02 f303 lsl.w r3, r2, r3 + 8005026: 43da mvns r2, r3 + 8005028: 68fb ldr r3, [r7, #12] + 800502a: 681b ldr r3, [r3, #0] + 800502c: 400a ands r2, r1 + 800502e: 601a str r2, [r3, #0] + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + 8005030: 68fb ldr r3, [r7, #12] + 8005032: 2201 movs r2, #1 + 8005034: 711a strb r2, [r3, #4] + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + 8005036: 68fb ldr r3, [r7, #12] + 8005038: 2200 movs r2, #0 + 800503a: 715a strb r2, [r3, #5] + + /* Return function status */ + return HAL_OK; + 800503c: 2300 movs r3, #0 +} + 800503e: 4618 mov r0, r3 + 8005040: 371c adds r7, #28 + 8005042: 46bd mov sp, r7 + 8005044: f85d 7b04 ldr.w r7, [sp], #4 + 8005048: 4770 bx lr + +0800504a : + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + 800504a: b480 push {r7} + 800504c: b083 sub sp, #12 + 800504e: af00 add r7, sp, #0 + 8005050: 6078 str r0, [r7, #4] + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + 8005052: bf00 nop + 8005054: 370c adds r7, #12 + 8005056: 46bd mov sp, r7 + 8005058: f85d 7b04 ldr.w r7, [sp], #4 + 800505c: 4770 bx lr + ... + +08005060 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8005060: b580 push {r7, lr} + 8005062: b086 sub sp, #24 + 8005064: af00 add r7, sp, #0 + 8005066: 6078 str r0, [r7, #4] + uint32_t tmp = 0U; + 8005068: 2300 movs r3, #0 + 800506a: 617b str r3, [r7, #20] + uint32_t tickstart = HAL_GetTick(); + 800506c: f7ff fa40 bl 80044f0 + 8005070: 6138 str r0, [r7, #16] + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + 8005072: 687b ldr r3, [r7, #4] + 8005074: 2b00 cmp r3, #0 + 8005076: d101 bne.n 800507c + { + return HAL_ERROR; + 8005078: 2301 movs r3, #1 + 800507a: e099 b.n 80051b0 + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + 800507c: 687b ldr r3, [r7, #4] + 800507e: 2200 movs r2, #0 + 8005080: f883 2034 strb.w r2, [r3, #52] ; 0x34 + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8005084: 687b ldr r3, [r7, #4] + 8005086: 2202 movs r2, #2 + 8005088: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 800508c: 687b ldr r3, [r7, #4] + 800508e: 681b ldr r3, [r3, #0] + 8005090: 681a ldr r2, [r3, #0] + 8005092: 687b ldr r3, [r7, #4] + 8005094: 681b ldr r3, [r3, #0] + 8005096: f022 0201 bic.w r2, r2, #1 + 800509a: 601a str r2, [r3, #0] + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 800509c: e00f b.n 80050be + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 800509e: f7ff fa27 bl 80044f0 + 80050a2: 4602 mov r2, r0 + 80050a4: 693b ldr r3, [r7, #16] + 80050a6: 1ad3 subs r3, r2, r3 + 80050a8: 2b05 cmp r3, #5 + 80050aa: d908 bls.n 80050be + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 80050ac: 687b ldr r3, [r7, #4] + 80050ae: 2220 movs r2, #32 + 80050b0: 655a str r2, [r3, #84] ; 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + 80050b2: 687b ldr r3, [r7, #4] + 80050b4: 2203 movs r2, #3 + 80050b6: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_TIMEOUT; + 80050ba: 2303 movs r3, #3 + 80050bc: e078 b.n 80051b0 + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 80050be: 687b ldr r3, [r7, #4] + 80050c0: 681b ldr r3, [r3, #0] + 80050c2: 681b ldr r3, [r3, #0] + 80050c4: f003 0301 and.w r3, r3, #1 + 80050c8: 2b00 cmp r3, #0 + 80050ca: d1e8 bne.n 800509e + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + 80050cc: 687b ldr r3, [r7, #4] + 80050ce: 681b ldr r3, [r3, #0] + 80050d0: 681b ldr r3, [r3, #0] + 80050d2: 617b str r3, [r7, #20] + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + 80050d4: 697a ldr r2, [r7, #20] + 80050d6: 4b38 ldr r3, [pc, #224] ; (80051b8 ) + 80050d8: 4013 ands r3, r2 + 80050da: 617b str r3, [r7, #20] + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 80050dc: 687b ldr r3, [r7, #4] + 80050de: 685a ldr r2, [r3, #4] + 80050e0: 687b ldr r3, [r7, #4] + 80050e2: 689b ldr r3, [r3, #8] + 80050e4: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 80050e6: 687b ldr r3, [r7, #4] + 80050e8: 68db ldr r3, [r3, #12] + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 80050ea: 431a orrs r2, r3 + hdma->Init.PeriphInc | hdma->Init.MemInc | + 80050ec: 687b ldr r3, [r7, #4] + 80050ee: 691b ldr r3, [r3, #16] + 80050f0: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 80050f2: 687b ldr r3, [r7, #4] + 80050f4: 695b ldr r3, [r3, #20] + hdma->Init.PeriphInc | hdma->Init.MemInc | + 80050f6: 431a orrs r2, r3 + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 80050f8: 687b ldr r3, [r7, #4] + 80050fa: 699b ldr r3, [r3, #24] + 80050fc: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 80050fe: 687b ldr r3, [r7, #4] + 8005100: 69db ldr r3, [r3, #28] + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 8005102: 431a orrs r2, r3 + hdma->Init.Mode | hdma->Init.Priority; + 8005104: 687b ldr r3, [r7, #4] + 8005106: 6a1b ldr r3, [r3, #32] + 8005108: 4313 orrs r3, r2 + tmp |= hdma->Init.Channel | hdma->Init.Direction | + 800510a: 697a ldr r2, [r7, #20] + 800510c: 4313 orrs r3, r2 + 800510e: 617b str r3, [r7, #20] + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 8005110: 687b ldr r3, [r7, #4] + 8005112: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005114: 2b04 cmp r3, #4 + 8005116: d107 bne.n 8005128 + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + 8005118: 687b ldr r3, [r7, #4] + 800511a: 6ada ldr r2, [r3, #44] ; 0x2c + 800511c: 687b ldr r3, [r7, #4] + 800511e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005120: 4313 orrs r3, r2 + 8005122: 697a ldr r2, [r7, #20] + 8005124: 4313 orrs r3, r2 + 8005126: 617b str r3, [r7, #20] + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + 8005128: 687b ldr r3, [r7, #4] + 800512a: 681b ldr r3, [r3, #0] + 800512c: 697a ldr r2, [r7, #20] + 800512e: 601a str r2, [r3, #0] + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + 8005130: 687b ldr r3, [r7, #4] + 8005132: 681b ldr r3, [r3, #0] + 8005134: 695b ldr r3, [r3, #20] + 8005136: 617b str r3, [r7, #20] + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + 8005138: 697b ldr r3, [r7, #20] + 800513a: f023 0307 bic.w r3, r3, #7 + 800513e: 617b str r3, [r7, #20] + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + 8005140: 687b ldr r3, [r7, #4] + 8005142: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005144: 697a ldr r2, [r7, #20] + 8005146: 4313 orrs r3, r2 + 8005148: 617b str r3, [r7, #20] + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 800514a: 687b ldr r3, [r7, #4] + 800514c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800514e: 2b04 cmp r3, #4 + 8005150: d117 bne.n 8005182 + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + 8005152: 687b ldr r3, [r7, #4] + 8005154: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005156: 697a ldr r2, [r7, #20] + 8005158: 4313 orrs r3, r2 + 800515a: 617b str r3, [r7, #20] + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + 800515c: 687b ldr r3, [r7, #4] + 800515e: 6adb ldr r3, [r3, #44] ; 0x2c + 8005160: 2b00 cmp r3, #0 + 8005162: d00e beq.n 8005182 + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + 8005164: 6878 ldr r0, [r7, #4] + 8005166: f000 f8bd bl 80052e4 + 800516a: 4603 mov r3, r0 + 800516c: 2b00 cmp r3, #0 + 800516e: d008 beq.n 8005182 + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 8005170: 687b ldr r3, [r7, #4] + 8005172: 2240 movs r2, #64 ; 0x40 + 8005174: 655a str r2, [r3, #84] ; 0x54 + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8005176: 687b ldr r3, [r7, #4] + 8005178: 2201 movs r2, #1 + 800517a: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_ERROR; + 800517e: 2301 movs r3, #1 + 8005180: e016 b.n 80051b0 + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + 8005182: 687b ldr r3, [r7, #4] + 8005184: 681b ldr r3, [r3, #0] + 8005186: 697a ldr r2, [r7, #20] + 8005188: 615a str r2, [r3, #20] + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 800518a: 6878 ldr r0, [r7, #4] + 800518c: f000 f874 bl 8005278 + 8005190: 4603 mov r3, r0 + 8005192: 60fb str r3, [r7, #12] + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 8005194: 687b ldr r3, [r7, #4] + 8005196: 6ddb ldr r3, [r3, #92] ; 0x5c + 8005198: 223f movs r2, #63 ; 0x3f + 800519a: 409a lsls r2, r3 + 800519c: 68fb ldr r3, [r7, #12] + 800519e: 609a str r2, [r3, #8] + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 80051a0: 687b ldr r3, [r7, #4] + 80051a2: 2200 movs r2, #0 + 80051a4: 655a str r2, [r3, #84] ; 0x54 + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80051a6: 687b ldr r3, [r7, #4] + 80051a8: 2201 movs r2, #1 + 80051aa: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + return HAL_OK; + 80051ae: 2300 movs r3, #0 +} + 80051b0: 4618 mov r0, r3 + 80051b2: 3718 adds r7, #24 + 80051b4: 46bd mov sp, r7 + 80051b6: bd80 pop {r7, pc} + 80051b8: f010803f .word 0xf010803f + +080051bc : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + 80051bc: b580 push {r7, lr} + 80051be: b084 sub sp, #16 + 80051c0: af00 add r7, sp, #0 + 80051c2: 6078 str r0, [r7, #4] + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + 80051c4: 687b ldr r3, [r7, #4] + 80051c6: 2b00 cmp r3, #0 + 80051c8: d101 bne.n 80051ce + { + return HAL_ERROR; + 80051ca: 2301 movs r3, #1 + 80051cc: e050 b.n 8005270 + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + 80051ce: 687b ldr r3, [r7, #4] + 80051d0: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 80051d4: b2db uxtb r3, r3 + 80051d6: 2b02 cmp r3, #2 + 80051d8: d101 bne.n 80051de + { + /* Return error status */ + return HAL_BUSY; + 80051da: 2302 movs r3, #2 + 80051dc: e048 b.n 8005270 + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + 80051de: 687b ldr r3, [r7, #4] + 80051e0: 681b ldr r3, [r3, #0] + 80051e2: 681a ldr r2, [r3, #0] + 80051e4: 687b ldr r3, [r7, #4] + 80051e6: 681b ldr r3, [r3, #0] + 80051e8: f022 0201 bic.w r2, r2, #1 + 80051ec: 601a str r2, [r3, #0] + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + 80051ee: 687b ldr r3, [r7, #4] + 80051f0: 681b ldr r3, [r3, #0] + 80051f2: 2200 movs r2, #0 + 80051f4: 601a str r2, [r3, #0] + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + 80051f6: 687b ldr r3, [r7, #4] + 80051f8: 681b ldr r3, [r3, #0] + 80051fa: 2200 movs r2, #0 + 80051fc: 605a str r2, [r3, #4] + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + 80051fe: 687b ldr r3, [r7, #4] + 8005200: 681b ldr r3, [r3, #0] + 8005202: 2200 movs r2, #0 + 8005204: 609a str r2, [r3, #8] + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + 8005206: 687b ldr r3, [r7, #4] + 8005208: 681b ldr r3, [r3, #0] + 800520a: 2200 movs r2, #0 + 800520c: 60da str r2, [r3, #12] + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + 800520e: 687b ldr r3, [r7, #4] + 8005210: 681b ldr r3, [r3, #0] + 8005212: 2200 movs r2, #0 + 8005214: 611a str r2, [r3, #16] + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021U; + 8005216: 687b ldr r3, [r7, #4] + 8005218: 681b ldr r3, [r3, #0] + 800521a: 2221 movs r2, #33 ; 0x21 + 800521c: 615a str r2, [r3, #20] + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 800521e: 6878 ldr r0, [r7, #4] + 8005220: f000 f82a bl 8005278 + 8005224: 4603 mov r3, r0 + 8005226: 60fb str r3, [r7, #12] + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + 8005228: 687b ldr r3, [r7, #4] + 800522a: 6ddb ldr r3, [r3, #92] ; 0x5c + 800522c: 223f movs r2, #63 ; 0x3f + 800522e: 409a lsls r2, r3 + 8005230: 68fb ldr r3, [r7, #12] + 8005232: 609a str r2, [r3, #8] + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + 8005234: 687b ldr r3, [r7, #4] + 8005236: 2200 movs r2, #0 + 8005238: 63da str r2, [r3, #60] ; 0x3c + hdma->XferHalfCpltCallback = NULL; + 800523a: 687b ldr r3, [r7, #4] + 800523c: 2200 movs r2, #0 + 800523e: 641a str r2, [r3, #64] ; 0x40 + hdma->XferM1CpltCallback = NULL; + 8005240: 687b ldr r3, [r7, #4] + 8005242: 2200 movs r2, #0 + 8005244: 645a str r2, [r3, #68] ; 0x44 + hdma->XferM1HalfCpltCallback = NULL; + 8005246: 687b ldr r3, [r7, #4] + 8005248: 2200 movs r2, #0 + 800524a: 649a str r2, [r3, #72] ; 0x48 + hdma->XferErrorCallback = NULL; + 800524c: 687b ldr r3, [r7, #4] + 800524e: 2200 movs r2, #0 + 8005250: 64da str r2, [r3, #76] ; 0x4c + hdma->XferAbortCallback = NULL; + 8005252: 687b ldr r3, [r7, #4] + 8005254: 2200 movs r2, #0 + 8005256: 651a str r2, [r3, #80] ; 0x50 + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8005258: 687b ldr r3, [r7, #4] + 800525a: 2200 movs r2, #0 + 800525c: 655a str r2, [r3, #84] ; 0x54 + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + 800525e: 687b ldr r3, [r7, #4] + 8005260: 2200 movs r2, #0 + 8005262: f883 2035 strb.w r2, [r3, #53] ; 0x35 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 8005266: 687b ldr r3, [r7, #4] + 8005268: 2200 movs r2, #0 + 800526a: f883 2034 strb.w r2, [r3, #52] ; 0x34 + + return HAL_OK; + 800526e: 2300 movs r3, #0 +} + 8005270: 4618 mov r0, r3 + 8005272: 3710 adds r7, #16 + 8005274: 46bd mov sp, r7 + 8005276: bd80 pop {r7, pc} + +08005278 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + 8005278: b480 push {r7} + 800527a: b085 sub sp, #20 + 800527c: af00 add r7, sp, #0 + 800527e: 6078 str r0, [r7, #4] + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + 8005280: 687b ldr r3, [r7, #4] + 8005282: 681b ldr r3, [r3, #0] + 8005284: b2db uxtb r3, r3 + 8005286: 3b10 subs r3, #16 + 8005288: 4a13 ldr r2, [pc, #76] ; (80052d8 ) + 800528a: fba2 2303 umull r2, r3, r2, r3 + 800528e: 091b lsrs r3, r3, #4 + 8005290: 60fb str r3, [r7, #12] + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + 8005292: 4a12 ldr r2, [pc, #72] ; (80052dc ) + 8005294: 68fb ldr r3, [r7, #12] + 8005296: 4413 add r3, r2 + 8005298: 781b ldrb r3, [r3, #0] + 800529a: 461a mov r2, r3 + 800529c: 687b ldr r3, [r7, #4] + 800529e: 65da str r2, [r3, #92] ; 0x5c + + if (stream_number > 3U) + 80052a0: 68fb ldr r3, [r7, #12] + 80052a2: 2b03 cmp r3, #3 + 80052a4: d908 bls.n 80052b8 + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + 80052a6: 687b ldr r3, [r7, #4] + 80052a8: 681b ldr r3, [r3, #0] + 80052aa: 461a mov r2, r3 + 80052ac: 4b0c ldr r3, [pc, #48] ; (80052e0 ) + 80052ae: 4013 ands r3, r2 + 80052b0: 1d1a adds r2, r3, #4 + 80052b2: 687b ldr r3, [r7, #4] + 80052b4: 659a str r2, [r3, #88] ; 0x58 + 80052b6: e006 b.n 80052c6 + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + 80052b8: 687b ldr r3, [r7, #4] + 80052ba: 681b ldr r3, [r3, #0] + 80052bc: 461a mov r2, r3 + 80052be: 4b08 ldr r3, [pc, #32] ; (80052e0 ) + 80052c0: 4013 ands r3, r2 + 80052c2: 687a ldr r2, [r7, #4] + 80052c4: 6593 str r3, [r2, #88] ; 0x58 + } + + return hdma->StreamBaseAddress; + 80052c6: 687b ldr r3, [r7, #4] + 80052c8: 6d9b ldr r3, [r3, #88] ; 0x58 +} + 80052ca: 4618 mov r0, r3 + 80052cc: 3714 adds r7, #20 + 80052ce: 46bd mov sp, r7 + 80052d0: f85d 7b04 ldr.w r7, [sp], #4 + 80052d4: 4770 bx lr + 80052d6: bf00 nop + 80052d8: aaaaaaab .word 0xaaaaaaab + 80052dc: 0800e388 .word 0x0800e388 + 80052e0: fffffc00 .word 0xfffffc00 + +080052e4 : + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + 80052e4: b480 push {r7} + 80052e6: b085 sub sp, #20 + 80052e8: af00 add r7, sp, #0 + 80052ea: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80052ec: 2300 movs r3, #0 + 80052ee: 73fb strb r3, [r7, #15] + uint32_t tmp = hdma->Init.FIFOThreshold; + 80052f0: 687b ldr r3, [r7, #4] + 80052f2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80052f4: 60bb str r3, [r7, #8] + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + 80052f6: 687b ldr r3, [r7, #4] + 80052f8: 699b ldr r3, [r3, #24] + 80052fa: 2b00 cmp r3, #0 + 80052fc: d11f bne.n 800533e + { + switch (tmp) + 80052fe: 68bb ldr r3, [r7, #8] + 8005300: 2b03 cmp r3, #3 + 8005302: d855 bhi.n 80053b0 + 8005304: a201 add r2, pc, #4 ; (adr r2, 800530c ) + 8005306: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800530a: bf00 nop + 800530c: 0800531d .word 0x0800531d + 8005310: 0800532f .word 0x0800532f + 8005314: 0800531d .word 0x0800531d + 8005318: 080053b1 .word 0x080053b1 + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 800531c: 687b ldr r3, [r7, #4] + 800531e: 6adb ldr r3, [r3, #44] ; 0x2c + 8005320: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8005324: 2b00 cmp r3, #0 + 8005326: d045 beq.n 80053b4 + { + status = HAL_ERROR; + 8005328: 2301 movs r3, #1 + 800532a: 73fb strb r3, [r7, #15] + } + break; + 800532c: e042 b.n 80053b4 + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 800532e: 687b ldr r3, [r7, #4] + 8005330: 6adb ldr r3, [r3, #44] ; 0x2c + 8005332: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 + 8005336: d13f bne.n 80053b8 + { + status = HAL_ERROR; + 8005338: 2301 movs r3, #1 + 800533a: 73fb strb r3, [r7, #15] + } + break; + 800533c: e03c b.n 80053b8 + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 800533e: 687b ldr r3, [r7, #4] + 8005340: 699b ldr r3, [r3, #24] + 8005342: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8005346: d121 bne.n 800538c + { + switch (tmp) + 8005348: 68bb ldr r3, [r7, #8] + 800534a: 2b03 cmp r3, #3 + 800534c: d836 bhi.n 80053bc + 800534e: a201 add r2, pc, #4 ; (adr r2, 8005354 ) + 8005350: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005354: 08005365 .word 0x08005365 + 8005358: 0800536b .word 0x0800536b + 800535c: 08005365 .word 0x08005365 + 8005360: 0800537d .word 0x0800537d + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + 8005364: 2301 movs r3, #1 + 8005366: 73fb strb r3, [r7, #15] + break; + 8005368: e02f b.n 80053ca + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 800536a: 687b ldr r3, [r7, #4] + 800536c: 6adb ldr r3, [r3, #44] ; 0x2c + 800536e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8005372: 2b00 cmp r3, #0 + 8005374: d024 beq.n 80053c0 + { + status = HAL_ERROR; + 8005376: 2301 movs r3, #1 + 8005378: 73fb strb r3, [r7, #15] + } + break; + 800537a: e021 b.n 80053c0 + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 800537c: 687b ldr r3, [r7, #4] + 800537e: 6adb ldr r3, [r3, #44] ; 0x2c + 8005380: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000 + 8005384: d11e bne.n 80053c4 + { + status = HAL_ERROR; + 8005386: 2301 movs r3, #1 + 8005388: 73fb strb r3, [r7, #15] + } + break; + 800538a: e01b b.n 80053c4 + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + 800538c: 68bb ldr r3, [r7, #8] + 800538e: 2b02 cmp r3, #2 + 8005390: d902 bls.n 8005398 + 8005392: 2b03 cmp r3, #3 + 8005394: d003 beq.n 800539e + { + status = HAL_ERROR; + } + break; + default: + break; + 8005396: e018 b.n 80053ca + status = HAL_ERROR; + 8005398: 2301 movs r3, #1 + 800539a: 73fb strb r3, [r7, #15] + break; + 800539c: e015 b.n 80053ca + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 800539e: 687b ldr r3, [r7, #4] + 80053a0: 6adb ldr r3, [r3, #44] ; 0x2c + 80053a2: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 80053a6: 2b00 cmp r3, #0 + 80053a8: d00e beq.n 80053c8 + status = HAL_ERROR; + 80053aa: 2301 movs r3, #1 + 80053ac: 73fb strb r3, [r7, #15] + break; + 80053ae: e00b b.n 80053c8 + break; + 80053b0: bf00 nop + 80053b2: e00a b.n 80053ca + break; + 80053b4: bf00 nop + 80053b6: e008 b.n 80053ca + break; + 80053b8: bf00 nop + 80053ba: e006 b.n 80053ca + break; + 80053bc: bf00 nop + 80053be: e004 b.n 80053ca + break; + 80053c0: bf00 nop + 80053c2: e002 b.n 80053ca + break; + 80053c4: bf00 nop + 80053c6: e000 b.n 80053ca + break; + 80053c8: bf00 nop + } + } + + return status; + 80053ca: 7bfb ldrb r3, [r7, #15] +} + 80053cc: 4618 mov r0, r3 + 80053ce: 3714 adds r7, #20 + 80053d0: 46bd mov sp, r7 + 80053d2: f85d 7b04 ldr.w r7, [sp], #4 + 80053d6: 4770 bx lr + +080053d8 : + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) +{ + 80053d8: b580 push {r7, lr} + 80053da: b082 sub sp, #8 + 80053dc: af00 add r7, sp, #0 + 80053de: 6078 str r0, [r7, #4] + /* Check the DMA2D peripheral state */ + if(hdma2d == NULL) + 80053e0: 687b ldr r3, [r7, #4] + 80053e2: 2b00 cmp r3, #0 + 80053e4: d101 bne.n 80053ea + { + return HAL_ERROR; + 80053e6: 2301 movs r3, #1 + 80053e8: e039 b.n 800545e + + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else + if(hdma2d->State == HAL_DMA2D_STATE_RESET) + 80053ea: 687b ldr r3, [r7, #4] + 80053ec: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 80053f0: b2db uxtb r3, r3 + 80053f2: 2b00 cmp r3, #0 + 80053f4: d106 bne.n 8005404 + { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; + 80053f6: 687b ldr r3, [r7, #4] + 80053f8: 2200 movs r2, #0 + 80053fa: f883 2038 strb.w r2, [r3, #56] ; 0x38 + /* Init the low level hardware */ + HAL_DMA2D_MspInit(hdma2d); + 80053fe: 6878 ldr r0, [r7, #4] + 8005400: f7fe fb06 bl 8003a10 + } +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 8005404: 687b ldr r3, [r7, #4] + 8005406: 2202 movs r2, #2 + 8005408: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); + 800540c: 687b ldr r3, [r7, #4] + 800540e: 681b ldr r3, [r3, #0] + 8005410: 681b ldr r3, [r3, #0] + 8005412: f423 3140 bic.w r1, r3, #196608 ; 0x30000 + 8005416: 687b ldr r3, [r7, #4] + 8005418: 685a ldr r2, [r3, #4] + 800541a: 687b ldr r3, [r7, #4] + 800541c: 681b ldr r3, [r3, #0] + 800541e: 430a orrs r2, r1 + 8005420: 601a str r2, [r3, #0] + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); + 8005422: 687b ldr r3, [r7, #4] + 8005424: 681b ldr r3, [r3, #0] + 8005426: 6b5b ldr r3, [r3, #52] ; 0x34 + 8005428: f023 0107 bic.w r1, r3, #7 + 800542c: 687b ldr r3, [r7, #4] + 800542e: 689a ldr r2, [r3, #8] + 8005430: 687b ldr r3, [r7, #4] + 8005432: 681b ldr r3, [r3, #0] + 8005434: 430a orrs r2, r1 + 8005436: 635a str r2, [r3, #52] ; 0x34 + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + 8005438: 687b ldr r3, [r7, #4] + 800543a: 681b ldr r3, [r3, #0] + 800543c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800543e: 4b0a ldr r3, [pc, #40] ; (8005468 ) + 8005440: 4013 ands r3, r2 + 8005442: 687a ldr r2, [r7, #4] + 8005444: 68d1 ldr r1, [r2, #12] + 8005446: 687a ldr r2, [r7, #4] + 8005448: 6812 ldr r2, [r2, #0] + 800544a: 430b orrs r3, r1 + 800544c: 6413 str r3, [r2, #64] ; 0x40 + MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + 800544e: 687b ldr r3, [r7, #4] + 8005450: 2200 movs r2, #0 + 8005452: 63da str r2, [r3, #60] ; 0x3c + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + 8005454: 687b ldr r3, [r7, #4] + 8005456: 2201 movs r2, #1 + 8005458: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + return HAL_OK; + 800545c: 2300 movs r3, #0 +} + 800545e: 4618 mov r0, r3 + 8005460: 3708 adds r7, #8 + 8005462: 46bd mov sp, r7 + 8005464: bd80 pop {r7, pc} + 8005466: bf00 nop + 8005468: ffffc000 .word 0xffffc000 + +0800546c : + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + 800546c: b580 push {r7, lr} + 800546e: b086 sub sp, #24 + 8005470: af02 add r7, sp, #8 + 8005472: 60f8 str r0, [r7, #12] + 8005474: 60b9 str r1, [r7, #8] + 8005476: 607a str r2, [r7, #4] + 8005478: 603b str r3, [r7, #0] + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + 800547a: 68fb ldr r3, [r7, #12] + 800547c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 8005480: 2b01 cmp r3, #1 + 8005482: d101 bne.n 8005488 + 8005484: 2302 movs r3, #2 + 8005486: e018 b.n 80054ba + 8005488: 68fb ldr r3, [r7, #12] + 800548a: 2201 movs r2, #1 + 800548c: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 8005490: 68fb ldr r3, [r7, #12] + 8005492: 2202 movs r2, #2 + 8005494: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + 8005498: 69bb ldr r3, [r7, #24] + 800549a: 9300 str r3, [sp, #0] + 800549c: 683b ldr r3, [r7, #0] + 800549e: 687a ldr r2, [r7, #4] + 80054a0: 68b9 ldr r1, [r7, #8] + 80054a2: 68f8 ldr r0, [r7, #12] + 80054a4: f000 f988 bl 80057b8 + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + 80054a8: 68fb ldr r3, [r7, #12] + 80054aa: 681b ldr r3, [r3, #0] + 80054ac: 681a ldr r2, [r3, #0] + 80054ae: 68fb ldr r3, [r7, #12] + 80054b0: 681b ldr r3, [r3, #0] + 80054b2: f042 0201 orr.w r2, r2, #1 + 80054b6: 601a str r2, [r3, #0] + + return HAL_OK; + 80054b8: 2300 movs r3, #0 +} + 80054ba: 4618 mov r0, r3 + 80054bc: 3710 adds r7, #16 + 80054be: 46bd mov sp, r7 + 80054c0: bd80 pop {r7, pc} + +080054c2 : + * the configuration information for the DMA2D. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + 80054c2: b580 push {r7, lr} + 80054c4: b086 sub sp, #24 + 80054c6: af00 add r7, sp, #0 + 80054c8: 6078 str r0, [r7, #4] + 80054ca: 6039 str r1, [r7, #0] + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; + 80054cc: 2300 movs r3, #0 + 80054ce: 60fb str r3, [r7, #12] + + /* Polling for DMA2D transfer */ + if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + 80054d0: 687b ldr r3, [r7, #4] + 80054d2: 681b ldr r3, [r3, #0] + 80054d4: 681b ldr r3, [r3, #0] + 80054d6: f003 0301 and.w r3, r3, #1 + 80054da: 2b00 cmp r3, #0 + 80054dc: d056 beq.n 800558c + { + /* Get tick */ + tickstart = HAL_GetTick(); + 80054de: f7ff f807 bl 80044f0 + 80054e2: 6178 str r0, [r7, #20] + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + 80054e4: e04b b.n 800557e + { + isrflags = READ_REG(hdma2d->Instance->ISR); + 80054e6: 687b ldr r3, [r7, #4] + 80054e8: 681b ldr r3, [r3, #0] + 80054ea: 685b ldr r3, [r3, #4] + 80054ec: 60fb str r3, [r7, #12] + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + 80054ee: 68fb ldr r3, [r7, #12] + 80054f0: f003 0321 and.w r3, r3, #33 ; 0x21 + 80054f4: 2b00 cmp r3, #0 + 80054f6: d023 beq.n 8005540 + { + if ((isrflags & DMA2D_FLAG_CE) != 0U) + 80054f8: 68fb ldr r3, [r7, #12] + 80054fa: f003 0320 and.w r3, r3, #32 + 80054fe: 2b00 cmp r3, #0 + 8005500: d005 beq.n 800550e + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + 8005502: 687b ldr r3, [r7, #4] + 8005504: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005506: f043 0202 orr.w r2, r3, #2 + 800550a: 687b ldr r3, [r7, #4] + 800550c: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + 800550e: 68fb ldr r3, [r7, #12] + 8005510: f003 0301 and.w r3, r3, #1 + 8005514: 2b00 cmp r3, #0 + 8005516: d005 beq.n 8005524 + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + 8005518: 687b ldr r3, [r7, #4] + 800551a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800551c: f043 0201 orr.w r2, r3, #1 + 8005520: 687b ldr r3, [r7, #4] + 8005522: 63da str r2, [r3, #60] ; 0x3c + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + 8005524: 687b ldr r3, [r7, #4] + 8005526: 681b ldr r3, [r3, #0] + 8005528: 2221 movs r2, #33 ; 0x21 + 800552a: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + 800552c: 687b ldr r3, [r7, #4] + 800552e: 2204 movs r2, #4 + 8005530: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005534: 687b ldr r3, [r7, #4] + 8005536: 2200 movs r2, #0 + 8005538: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_ERROR; + 800553c: 2301 movs r3, #1 + 800553e: e0a5 b.n 800568c + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + 8005540: 683b ldr r3, [r7, #0] + 8005542: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8005546: d01a beq.n 800557e + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + 8005548: f7fe ffd2 bl 80044f0 + 800554c: 4602 mov r2, r0 + 800554e: 697b ldr r3, [r7, #20] + 8005550: 1ad3 subs r3, r2, r3 + 8005552: 683a ldr r2, [r7, #0] + 8005554: 429a cmp r2, r3 + 8005556: d302 bcc.n 800555e + 8005558: 683b ldr r3, [r7, #0] + 800555a: 2b00 cmp r3, #0 + 800555c: d10f bne.n 800557e + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + 800555e: 687b ldr r3, [r7, #4] + 8005560: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005562: f043 0220 orr.w r2, r3, #32 + 8005566: 687b ldr r3, [r7, #4] + 8005568: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + 800556a: 687b ldr r3, [r7, #4] + 800556c: 2203 movs r2, #3 + 800556e: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005572: 687b ldr r3, [r7, #4] + 8005574: 2200 movs r2, #0 + 8005576: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 800557a: 2303 movs r3, #3 + 800557c: e086 b.n 800568c + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + 800557e: 687b ldr r3, [r7, #4] + 8005580: 681b ldr r3, [r3, #0] + 8005582: 685b ldr r3, [r3, #4] + 8005584: f003 0302 and.w r3, r3, #2 + 8005588: 2b00 cmp r3, #0 + 800558a: d0ac beq.n 80054e6 + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + 800558c: 687b ldr r3, [r7, #4] + 800558e: 681b ldr r3, [r3, #0] + 8005590: 69db ldr r3, [r3, #28] + 8005592: f003 0320 and.w r3, r3, #32 + 8005596: 613b str r3, [r7, #16] + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + 8005598: 687b ldr r3, [r7, #4] + 800559a: 681b ldr r3, [r3, #0] + 800559c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800559e: f003 0320 and.w r3, r3, #32 + 80055a2: 693a ldr r2, [r7, #16] + 80055a4: 4313 orrs r3, r2 + 80055a6: 613b str r3, [r7, #16] + if (layer_start != 0U) + 80055a8: 693b ldr r3, [r7, #16] + 80055aa: 2b00 cmp r3, #0 + 80055ac: d061 beq.n 8005672 + { + /* Get tick */ + tickstart = HAL_GetTick(); + 80055ae: f7fe ff9f bl 80044f0 + 80055b2: 6178 str r0, [r7, #20] + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + 80055b4: e056 b.n 8005664 + { + isrflags = READ_REG(hdma2d->Instance->ISR); + 80055b6: 687b ldr r3, [r7, #4] + 80055b8: 681b ldr r3, [r3, #0] + 80055ba: 685b ldr r3, [r3, #4] + 80055bc: 60fb str r3, [r7, #12] + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + 80055be: 68fb ldr r3, [r7, #12] + 80055c0: f003 0329 and.w r3, r3, #41 ; 0x29 + 80055c4: 2b00 cmp r3, #0 + 80055c6: d02e beq.n 8005626 + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + 80055c8: 68fb ldr r3, [r7, #12] + 80055ca: f003 0308 and.w r3, r3, #8 + 80055ce: 2b00 cmp r3, #0 + 80055d0: d005 beq.n 80055de + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + 80055d2: 687b ldr r3, [r7, #4] + 80055d4: 6bdb ldr r3, [r3, #60] ; 0x3c + 80055d6: f043 0204 orr.w r2, r3, #4 + 80055da: 687b ldr r3, [r7, #4] + 80055dc: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_CE) != 0U) + 80055de: 68fb ldr r3, [r7, #12] + 80055e0: f003 0320 and.w r3, r3, #32 + 80055e4: 2b00 cmp r3, #0 + 80055e6: d005 beq.n 80055f4 + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + 80055e8: 687b ldr r3, [r7, #4] + 80055ea: 6bdb ldr r3, [r3, #60] ; 0x3c + 80055ec: f043 0202 orr.w r2, r3, #2 + 80055f0: 687b ldr r3, [r7, #4] + 80055f2: 63da str r2, [r3, #60] ; 0x3c + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + 80055f4: 68fb ldr r3, [r7, #12] + 80055f6: f003 0301 and.w r3, r3, #1 + 80055fa: 2b00 cmp r3, #0 + 80055fc: d005 beq.n 800560a + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + 80055fe: 687b ldr r3, [r7, #4] + 8005600: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005602: f043 0201 orr.w r2, r3, #1 + 8005606: 687b ldr r3, [r7, #4] + 8005608: 63da str r2, [r3, #60] ; 0x3c + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + 800560a: 687b ldr r3, [r7, #4] + 800560c: 681b ldr r3, [r3, #0] + 800560e: 2229 movs r2, #41 ; 0x29 + 8005610: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_ERROR; + 8005612: 687b ldr r3, [r7, #4] + 8005614: 2204 movs r2, #4 + 8005616: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 800561a: 687b ldr r3, [r7, #4] + 800561c: 2200 movs r2, #0 + 800561e: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_ERROR; + 8005622: 2301 movs r3, #1 + 8005624: e032 b.n 800568c + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + 8005626: 683b ldr r3, [r7, #0] + 8005628: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800562c: d01a beq.n 8005664 + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + 800562e: f7fe ff5f bl 80044f0 + 8005632: 4602 mov r2, r0 + 8005634: 697b ldr r3, [r7, #20] + 8005636: 1ad3 subs r3, r2, r3 + 8005638: 683a ldr r2, [r7, #0] + 800563a: 429a cmp r2, r3 + 800563c: d302 bcc.n 8005644 + 800563e: 683b ldr r3, [r7, #0] + 8005640: 2b00 cmp r3, #0 + 8005642: d10f bne.n 8005664 + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + 8005644: 687b ldr r3, [r7, #4] + 8005646: 6bdb ldr r3, [r3, #60] ; 0x3c + 8005648: f043 0220 orr.w r2, r3, #32 + 800564c: 687b ldr r3, [r7, #4] + 800564e: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + 8005650: 687b ldr r3, [r7, #4] + 8005652: 2203 movs r2, #3 + 8005654: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005658: 687b ldr r3, [r7, #4] + 800565a: 2200 movs r2, #0 + 800565c: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 8005660: 2303 movs r3, #3 + 8005662: e013 b.n 800568c + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + 8005664: 687b ldr r3, [r7, #4] + 8005666: 681b ldr r3, [r3, #0] + 8005668: 685b ldr r3, [r3, #4] + 800566a: f003 0310 and.w r3, r3, #16 + 800566e: 2b00 cmp r3, #0 + 8005670: d0a1 beq.n 80055b6 + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + 8005672: 687b ldr r3, [r7, #4] + 8005674: 681b ldr r3, [r3, #0] + 8005676: 2212 movs r2, #18 + 8005678: 609a str r2, [r3, #8] + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + 800567a: 687b ldr r3, [r7, #4] + 800567c: 2201 movs r2, #1 + 800567e: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 8005682: 687b ldr r3, [r7, #4] + 8005684: 2200 movs r2, #0 + 8005686: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_OK; + 800568a: 2300 movs r3, #0 +} + 800568c: 4618 mov r0, r3 + 800568e: 3718 adds r7, #24 + 8005690: 46bd mov sp, r7 + 8005692: bd80 pop {r7, pc} + +08005694 : + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + 8005694: b480 push {r7} + 8005696: b087 sub sp, #28 + 8005698: af00 add r7, sp, #0 + 800569a: 6078 str r0, [r7, #4] + 800569c: 6039 str r1, [r7, #0] + uint32_t regMask, regValue; + + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); + if(hdma2d->Init.Mode != DMA2D_R2M) + 800569e: 687b ldr r3, [r7, #4] + 80056a0: 685b ldr r3, [r3, #4] + 80056a2: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* Process locked */ + __HAL_LOCK(hdma2d); + 80056a6: 687b ldr r3, [r7, #4] + 80056a8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 80056ac: 2b01 cmp r3, #1 + 80056ae: d101 bne.n 80056b4 + 80056b0: 2302 movs r3, #2 + 80056b2: e079 b.n 80057a8 + 80056b4: 687b ldr r3, [r7, #4] + 80056b6: 2201 movs r2, #1 + 80056b8: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + 80056bc: 687b ldr r3, [r7, #4] + 80056be: 2202 movs r2, #2 + 80056c0: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + 80056c4: 683b ldr r3, [r7, #0] + 80056c6: 011b lsls r3, r3, #4 + 80056c8: 3318 adds r3, #24 + 80056ca: 687a ldr r2, [r7, #4] + 80056cc: 4413 add r3, r2 + 80056ce: 613b str r3, [r7, #16] +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); +#else + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); + 80056d0: 693b ldr r3, [r7, #16] + 80056d2: 685a ldr r2, [r3, #4] + 80056d4: 693b ldr r3, [r7, #16] + 80056d6: 689b ldr r3, [r3, #8] + 80056d8: 041b lsls r3, r3, #16 + 80056da: 4313 orrs r3, r2 + 80056dc: 617b str r3, [r7, #20] + regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; + 80056de: 4b35 ldr r3, [pc, #212] ; (80057b4 ) + 80056e0: 60fb str r3, [r7, #12] +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 80056e2: 693b ldr r3, [r7, #16] + 80056e4: 685b ldr r3, [r3, #4] + 80056e6: 2b0a cmp r3, #10 + 80056e8: d003 beq.n 80056f2 + 80056ea: 693b ldr r3, [r7, #16] + 80056ec: 685b ldr r3, [r3, #4] + 80056ee: 2b09 cmp r3, #9 + 80056f0: d107 bne.n 8005702 + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + 80056f2: 693b ldr r3, [r7, #16] + 80056f4: 68db ldr r3, [r3, #12] + 80056f6: f003 437f and.w r3, r3, #4278190080 ; 0xff000000 + 80056fa: 697a ldr r2, [r7, #20] + 80056fc: 4313 orrs r3, r2 + 80056fe: 617b str r3, [r7, #20] + 8005700: e005 b.n 800570e + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + 8005702: 693b ldr r3, [r7, #16] + 8005704: 68db ldr r3, [r3, #12] + 8005706: 061b lsls r3, r3, #24 + 8005708: 697a ldr r2, [r7, #20] + 800570a: 4313 orrs r3, r2 + 800570c: 617b str r3, [r7, #20] + } + + /* Configure the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + 800570e: 683b ldr r3, [r7, #0] + 8005710: 2b00 cmp r3, #0 + 8005712: d120 bne.n 8005756 + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + 8005714: 687b ldr r3, [r7, #4] + 8005716: 681b ldr r3, [r3, #0] + 8005718: 6a5a ldr r2, [r3, #36] ; 0x24 + 800571a: 68fb ldr r3, [r7, #12] + 800571c: 43db mvns r3, r3 + 800571e: ea02 0103 and.w r1, r2, r3 + 8005722: 687b ldr r3, [r7, #4] + 8005724: 681b ldr r3, [r3, #0] + 8005726: 697a ldr r2, [r7, #20] + 8005728: 430a orrs r2, r1 + 800572a: 625a str r2, [r3, #36] ; 0x24 + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + 800572c: 687b ldr r3, [r7, #4] + 800572e: 681b ldr r3, [r3, #0] + 8005730: 693a ldr r2, [r7, #16] + 8005732: 6812 ldr r2, [r2, #0] + 8005734: 619a str r2, [r3, #24] + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 8005736: 693b ldr r3, [r7, #16] + 8005738: 685b ldr r3, [r3, #4] + 800573a: 2b0a cmp r3, #10 + 800573c: d003 beq.n 8005746 + 800573e: 693b ldr r3, [r7, #16] + 8005740: 685b ldr r3, [r3, #4] + 8005742: 2b09 cmp r3, #9 + 8005744: d127 bne.n 8005796 + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + 8005746: 693b ldr r3, [r7, #16] + 8005748: 68da ldr r2, [r3, #12] + 800574a: 687b ldr r3, [r7, #4] + 800574c: 681b ldr r3, [r3, #0] + 800574e: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + 8005752: 629a str r2, [r3, #40] ; 0x28 + 8005754: e01f b.n 8005796 + else + { + + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + 8005756: 687b ldr r3, [r7, #4] + 8005758: 681b ldr r3, [r3, #0] + 800575a: 69da ldr r2, [r3, #28] + 800575c: 68fb ldr r3, [r7, #12] + 800575e: 43db mvns r3, r3 + 8005760: ea02 0103 and.w r1, r2, r3 + 8005764: 687b ldr r3, [r7, #4] + 8005766: 681b ldr r3, [r3, #0] + 8005768: 697a ldr r2, [r7, #20] + 800576a: 430a orrs r2, r1 + 800576c: 61da str r2, [r3, #28] + + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + 800576e: 687b ldr r3, [r7, #4] + 8005770: 681b ldr r3, [r3, #0] + 8005772: 693a ldr r2, [r7, #16] + 8005774: 6812 ldr r2, [r2, #0] + 8005776: 611a str r2, [r3, #16] + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + 8005778: 693b ldr r3, [r7, #16] + 800577a: 685b ldr r3, [r3, #4] + 800577c: 2b0a cmp r3, #10 + 800577e: d003 beq.n 8005788 + 8005780: 693b ldr r3, [r7, #16] + 8005782: 685b ldr r3, [r3, #4] + 8005784: 2b09 cmp r3, #9 + 8005786: d106 bne.n 8005796 + { + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + 8005788: 693b ldr r3, [r7, #16] + 800578a: 68da ldr r2, [r3, #12] + 800578c: 687b ldr r3, [r7, #4] + 800578e: 681b ldr r3, [r3, #0] + 8005790: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + 8005794: 621a str r2, [r3, #32] + } + } + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + 8005796: 687b ldr r3, [r7, #4] + 8005798: 2201 movs r2, #1 + 800579a: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + 800579e: 687b ldr r3, [r7, #4] + 80057a0: 2200 movs r2, #0 + 80057a2: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_OK; + 80057a6: 2300 movs r3, #0 +} + 80057a8: 4618 mov r0, r3 + 80057aa: 371c adds r7, #28 + 80057ac: 46bd mov sp, r7 + 80057ae: f85d 7b04 ldr.w r7, [sp], #4 + 80057b2: 4770 bx lr + 80057b4: ff03000f .word 0xff03000f + +080057b8 : + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. + * @retval HAL status + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + 80057b8: b480 push {r7} + 80057ba: b08b sub sp, #44 ; 0x2c + 80057bc: af00 add r7, sp, #0 + 80057be: 60f8 str r0, [r7, #12] + 80057c0: 60b9 str r1, [r7, #8] + 80057c2: 607a str r2, [r7, #4] + 80057c4: 603b str r3, [r7, #0] + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + + /* Configure DMA2D data size */ + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + 80057c6: 68fb ldr r3, [r7, #12] + 80057c8: 681b ldr r3, [r3, #0] + 80057ca: 6c5b ldr r3, [r3, #68] ; 0x44 + 80057cc: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000 + 80057d0: 683b ldr r3, [r7, #0] + 80057d2: 041a lsls r2, r3, #16 + 80057d4: 6b3b ldr r3, [r7, #48] ; 0x30 + 80057d6: 431a orrs r2, r3 + 80057d8: 68fb ldr r3, [r7, #12] + 80057da: 681b ldr r3, [r3, #0] + 80057dc: 430a orrs r2, r1 + 80057de: 645a str r2, [r3, #68] ; 0x44 + + /* Configure DMA2D destination address */ + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); + 80057e0: 68fb ldr r3, [r7, #12] + 80057e2: 681b ldr r3, [r3, #0] + 80057e4: 687a ldr r2, [r7, #4] + 80057e6: 63da str r2, [r3, #60] ; 0x3c + + /* Register to memory DMA2D mode selected */ + if (hdma2d->Init.Mode == DMA2D_R2M) + 80057e8: 68fb ldr r3, [r7, #12] + 80057ea: 685b ldr r3, [r3, #4] + 80057ec: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 + 80057f0: d174 bne.n 80058dc + { + tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; + 80057f2: 68bb ldr r3, [r7, #8] + 80057f4: f003 437f and.w r3, r3, #4278190080 ; 0xff000000 + 80057f8: 623b str r3, [r7, #32] + tmp2 = pdata & DMA2D_OCOLR_RED_1; + 80057fa: 68bb ldr r3, [r7, #8] + 80057fc: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8005800: 61fb str r3, [r7, #28] + tmp3 = pdata & DMA2D_OCOLR_GREEN_1; + 8005802: 68bb ldr r3, [r7, #8] + 8005804: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8005808: 61bb str r3, [r7, #24] + tmp4 = pdata & DMA2D_OCOLR_BLUE_1; + 800580a: 68bb ldr r3, [r7, #8] + 800580c: b2db uxtb r3, r3 + 800580e: 617b str r3, [r7, #20] + + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) + 8005810: 68fb ldr r3, [r7, #12] + 8005812: 689b ldr r3, [r3, #8] + 8005814: 2b00 cmp r3, #0 + 8005816: d108 bne.n 800582a + { + tmp = (tmp3 | tmp2 | tmp1| tmp4); + 8005818: 69ba ldr r2, [r7, #24] + 800581a: 69fb ldr r3, [r7, #28] + 800581c: 431a orrs r2, r3 + 800581e: 6a3b ldr r3, [r7, #32] + 8005820: 4313 orrs r3, r2 + 8005822: 697a ldr r2, [r7, #20] + 8005824: 4313 orrs r3, r2 + 8005826: 627b str r3, [r7, #36] ; 0x24 + 8005828: e053 b.n 80058d2 + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) + 800582a: 68fb ldr r3, [r7, #12] + 800582c: 689b ldr r3, [r3, #8] + 800582e: 2b01 cmp r3, #1 + 8005830: d106 bne.n 8005840 + { + tmp = (tmp3 | tmp2 | tmp4); + 8005832: 69ba ldr r2, [r7, #24] + 8005834: 69fb ldr r3, [r7, #28] + 8005836: 4313 orrs r3, r2 + 8005838: 697a ldr r2, [r7, #20] + 800583a: 4313 orrs r3, r2 + 800583c: 627b str r3, [r7, #36] ; 0x24 + 800583e: e048 b.n 80058d2 + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) + 8005840: 68fb ldr r3, [r7, #12] + 8005842: 689b ldr r3, [r3, #8] + 8005844: 2b02 cmp r3, #2 + 8005846: d111 bne.n 800586c + { + tmp2 = (tmp2 >> 19U); + 8005848: 69fb ldr r3, [r7, #28] + 800584a: 0cdb lsrs r3, r3, #19 + 800584c: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 10U); + 800584e: 69bb ldr r3, [r7, #24] + 8005850: 0a9b lsrs r3, r3, #10 + 8005852: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 3U ); + 8005854: 697b ldr r3, [r7, #20] + 8005856: 08db lsrs r3, r3, #3 + 8005858: 617b str r3, [r7, #20] + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); + 800585a: 69bb ldr r3, [r7, #24] + 800585c: 015a lsls r2, r3, #5 + 800585e: 69fb ldr r3, [r7, #28] + 8005860: 02db lsls r3, r3, #11 + 8005862: 4313 orrs r3, r2 + 8005864: 697a ldr r2, [r7, #20] + 8005866: 4313 orrs r3, r2 + 8005868: 627b str r3, [r7, #36] ; 0x24 + 800586a: e032 b.n 80058d2 + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) + 800586c: 68fb ldr r3, [r7, #12] + 800586e: 689b ldr r3, [r3, #8] + 8005870: 2b03 cmp r3, #3 + 8005872: d117 bne.n 80058a4 + { + tmp1 = (tmp1 >> 31U); + 8005874: 6a3b ldr r3, [r7, #32] + 8005876: 0fdb lsrs r3, r3, #31 + 8005878: 623b str r3, [r7, #32] + tmp2 = (tmp2 >> 19U); + 800587a: 69fb ldr r3, [r7, #28] + 800587c: 0cdb lsrs r3, r3, #19 + 800587e: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 11U); + 8005880: 69bb ldr r3, [r7, #24] + 8005882: 0adb lsrs r3, r3, #11 + 8005884: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 3U ); + 8005886: 697b ldr r3, [r7, #20] + 8005888: 08db lsrs r3, r3, #3 + 800588a: 617b str r3, [r7, #20] + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + 800588c: 69bb ldr r3, [r7, #24] + 800588e: 015a lsls r2, r3, #5 + 8005890: 69fb ldr r3, [r7, #28] + 8005892: 029b lsls r3, r3, #10 + 8005894: 431a orrs r2, r3 + 8005896: 6a3b ldr r3, [r7, #32] + 8005898: 03db lsls r3, r3, #15 + 800589a: 4313 orrs r3, r2 + 800589c: 697a ldr r2, [r7, #20] + 800589e: 4313 orrs r3, r2 + 80058a0: 627b str r3, [r7, #36] ; 0x24 + 80058a2: e016 b.n 80058d2 + } + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ + { + tmp1 = (tmp1 >> 28U); + 80058a4: 6a3b ldr r3, [r7, #32] + 80058a6: 0f1b lsrs r3, r3, #28 + 80058a8: 623b str r3, [r7, #32] + tmp2 = (tmp2 >> 20U); + 80058aa: 69fb ldr r3, [r7, #28] + 80058ac: 0d1b lsrs r3, r3, #20 + 80058ae: 61fb str r3, [r7, #28] + tmp3 = (tmp3 >> 12U); + 80058b0: 69bb ldr r3, [r7, #24] + 80058b2: 0b1b lsrs r3, r3, #12 + 80058b4: 61bb str r3, [r7, #24] + tmp4 = (tmp4 >> 4U ); + 80058b6: 697b ldr r3, [r7, #20] + 80058b8: 091b lsrs r3, r3, #4 + 80058ba: 617b str r3, [r7, #20] + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + 80058bc: 69bb ldr r3, [r7, #24] + 80058be: 011a lsls r2, r3, #4 + 80058c0: 69fb ldr r3, [r7, #28] + 80058c2: 021b lsls r3, r3, #8 + 80058c4: 431a orrs r2, r3 + 80058c6: 6a3b ldr r3, [r7, #32] + 80058c8: 031b lsls r3, r3, #12 + 80058ca: 4313 orrs r3, r2 + 80058cc: 697a ldr r2, [r7, #20] + 80058ce: 4313 orrs r3, r2 + 80058d0: 627b str r3, [r7, #36] ; 0x24 + } + /* Write to DMA2D OCOLR register */ + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + 80058d2: 68fb ldr r3, [r7, #12] + 80058d4: 681b ldr r3, [r3, #0] + 80058d6: 6a7a ldr r2, [r7, #36] ; 0x24 + 80058d8: 639a str r2, [r3, #56] ; 0x38 + else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ + { + /* Configure DMA2D source address */ + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + } +} + 80058da: e003 b.n 80058e4 + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + 80058dc: 68fb ldr r3, [r7, #12] + 80058de: 681b ldr r3, [r3, #0] + 80058e0: 68ba ldr r2, [r7, #8] + 80058e2: 60da str r2, [r3, #12] +} + 80058e4: bf00 nop + 80058e6: 372c adds r7, #44 ; 0x2c + 80058e8: 46bd mov sp, r7 + 80058ea: f85d 7b04 ldr.w r7, [sp], #4 + 80058ee: 4770 bx lr + +080058f0 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80058f0: b480 push {r7} + 80058f2: b089 sub sp, #36 ; 0x24 + 80058f4: af00 add r7, sp, #0 + 80058f6: 6078 str r0, [r7, #4] + 80058f8: 6039 str r1, [r7, #0] + uint32_t position = 0x00; + 80058fa: 2300 movs r3, #0 + 80058fc: 61fb str r3, [r7, #28] + uint32_t ioposition = 0x00; + 80058fe: 2300 movs r3, #0 + 8005900: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00; + 8005902: 2300 movs r3, #0 + 8005904: 613b str r3, [r7, #16] + uint32_t temp = 0x00; + 8005906: 2300 movs r3, #0 + 8005908: 61bb str r3, [r7, #24] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 800590a: 2300 movs r3, #0 + 800590c: 61fb str r3, [r7, #28] + 800590e: e175 b.n 8005bfc + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 8005910: 2201 movs r2, #1 + 8005912: 69fb ldr r3, [r7, #28] + 8005914: fa02 f303 lsl.w r3, r2, r3 + 8005918: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 800591a: 683b ldr r3, [r7, #0] + 800591c: 681b ldr r3, [r3, #0] + 800591e: 697a ldr r2, [r7, #20] + 8005920: 4013 ands r3, r2 + 8005922: 613b str r3, [r7, #16] + + if(iocurrent == ioposition) + 8005924: 693a ldr r2, [r7, #16] + 8005926: 697b ldr r3, [r7, #20] + 8005928: 429a cmp r2, r3 + 800592a: f040 8164 bne.w 8005bf6 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 800592e: 683b ldr r3, [r7, #0] + 8005930: 685b ldr r3, [r3, #4] + 8005932: 2b01 cmp r3, #1 + 8005934: d00b beq.n 800594e + 8005936: 683b ldr r3, [r7, #0] + 8005938: 685b ldr r3, [r3, #4] + 800593a: 2b02 cmp r3, #2 + 800593c: d007 beq.n 800594e + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 800593e: 683b ldr r3, [r7, #0] + 8005940: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 8005942: 2b11 cmp r3, #17 + 8005944: d003 beq.n 800594e + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 8005946: 683b ldr r3, [r7, #0] + 8005948: 685b ldr r3, [r3, #4] + 800594a: 2b12 cmp r3, #18 + 800594c: d130 bne.n 80059b0 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 800594e: 687b ldr r3, [r7, #4] + 8005950: 689b ldr r3, [r3, #8] + 8005952: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8005954: 69fb ldr r3, [r7, #28] + 8005956: 005b lsls r3, r3, #1 + 8005958: 2203 movs r2, #3 + 800595a: fa02 f303 lsl.w r3, r2, r3 + 800595e: 43db mvns r3, r3 + 8005960: 69ba ldr r2, [r7, #24] + 8005962: 4013 ands r3, r2 + 8005964: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2)); + 8005966: 683b ldr r3, [r7, #0] + 8005968: 68da ldr r2, [r3, #12] + 800596a: 69fb ldr r3, [r7, #28] + 800596c: 005b lsls r3, r3, #1 + 800596e: fa02 f303 lsl.w r3, r2, r3 + 8005972: 69ba ldr r2, [r7, #24] + 8005974: 4313 orrs r3, r2 + 8005976: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8005978: 687b ldr r3, [r7, #4] + 800597a: 69ba ldr r2, [r7, #24] + 800597c: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 800597e: 687b ldr r3, [r7, #4] + 8005980: 685b ldr r3, [r3, #4] + 8005982: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8005984: 2201 movs r2, #1 + 8005986: 69fb ldr r3, [r7, #28] + 8005988: fa02 f303 lsl.w r3, r2, r3 + 800598c: 43db mvns r3, r3 + 800598e: 69ba ldr r2, [r7, #24] + 8005990: 4013 ands r3, r2 + 8005992: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + 8005994: 683b ldr r3, [r7, #0] + 8005996: 685b ldr r3, [r3, #4] + 8005998: 091b lsrs r3, r3, #4 + 800599a: f003 0201 and.w r2, r3, #1 + 800599e: 69fb ldr r3, [r7, #28] + 80059a0: fa02 f303 lsl.w r3, r2, r3 + 80059a4: 69ba ldr r2, [r7, #24] + 80059a6: 4313 orrs r3, r2 + 80059a8: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 80059aa: 687b ldr r3, [r7, #4] + 80059ac: 69ba ldr r2, [r7, #24] + 80059ae: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 80059b0: 687b ldr r3, [r7, #4] + 80059b2: 68db ldr r3, [r3, #12] + 80059b4: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 80059b6: 69fb ldr r3, [r7, #28] + 80059b8: 005b lsls r3, r3, #1 + 80059ba: 2203 movs r2, #3 + 80059bc: fa02 f303 lsl.w r3, r2, r3 + 80059c0: 43db mvns r3, r3 + 80059c2: 69ba ldr r2, [r7, #24] + 80059c4: 4013 ands r3, r2 + 80059c6: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2)); + 80059c8: 683b ldr r3, [r7, #0] + 80059ca: 689a ldr r2, [r3, #8] + 80059cc: 69fb ldr r3, [r7, #28] + 80059ce: 005b lsls r3, r3, #1 + 80059d0: fa02 f303 lsl.w r3, r2, r3 + 80059d4: 69ba ldr r2, [r7, #24] + 80059d6: 4313 orrs r3, r2 + 80059d8: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 80059da: 687b ldr r3, [r7, #4] + 80059dc: 69ba ldr r2, [r7, #24] + 80059de: 60da str r2, [r3, #12] + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80059e0: 683b ldr r3, [r7, #0] + 80059e2: 685b ldr r3, [r3, #4] + 80059e4: 2b02 cmp r3, #2 + 80059e6: d003 beq.n 80059f0 + 80059e8: 683b ldr r3, [r7, #0] + 80059ea: 685b ldr r3, [r3, #4] + 80059ec: 2b12 cmp r3, #18 + 80059ee: d123 bne.n 8005a38 + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + 80059f0: 69fb ldr r3, [r7, #28] + 80059f2: 08da lsrs r2, r3, #3 + 80059f4: 687b ldr r3, [r7, #4] + 80059f6: 3208 adds r2, #8 + 80059f8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80059fc: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 80059fe: 69fb ldr r3, [r7, #28] + 8005a00: f003 0307 and.w r3, r3, #7 + 8005a04: 009b lsls r3, r3, #2 + 8005a06: 220f movs r2, #15 + 8005a08: fa02 f303 lsl.w r3, r2, r3 + 8005a0c: 43db mvns r3, r3 + 8005a0e: 69ba ldr r2, [r7, #24] + 8005a10: 4013 ands r3, r2 + 8005a12: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 8005a14: 683b ldr r3, [r7, #0] + 8005a16: 691a ldr r2, [r3, #16] + 8005a18: 69fb ldr r3, [r7, #28] + 8005a1a: f003 0307 and.w r3, r3, #7 + 8005a1e: 009b lsls r3, r3, #2 + 8005a20: fa02 f303 lsl.w r3, r2, r3 + 8005a24: 69ba ldr r2, [r7, #24] + 8005a26: 4313 orrs r3, r2 + 8005a28: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3] = temp; + 8005a2a: 69fb ldr r3, [r7, #28] + 8005a2c: 08da lsrs r2, r3, #3 + 8005a2e: 687b ldr r3, [r7, #4] + 8005a30: 3208 adds r2, #8 + 8005a32: 69b9 ldr r1, [r7, #24] + 8005a34: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8005a38: 687b ldr r3, [r7, #4] + 8005a3a: 681b ldr r3, [r3, #0] + 8005a3c: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 8005a3e: 69fb ldr r3, [r7, #28] + 8005a40: 005b lsls r3, r3, #1 + 8005a42: 2203 movs r2, #3 + 8005a44: fa02 f303 lsl.w r3, r2, r3 + 8005a48: 43db mvns r3, r3 + 8005a4a: 69ba ldr r2, [r7, #24] + 8005a4c: 4013 ands r3, r2 + 8005a4e: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 8005a50: 683b ldr r3, [r7, #0] + 8005a52: 685b ldr r3, [r3, #4] + 8005a54: f003 0203 and.w r2, r3, #3 + 8005a58: 69fb ldr r3, [r7, #28] + 8005a5a: 005b lsls r3, r3, #1 + 8005a5c: fa02 f303 lsl.w r3, r2, r3 + 8005a60: 69ba ldr r2, [r7, #24] + 8005a62: 4313 orrs r3, r2 + 8005a64: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 8005a66: 687b ldr r3, [r7, #4] + 8005a68: 69ba ldr r2, [r7, #24] + 8005a6a: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8005a6c: 683b ldr r3, [r7, #0] + 8005a6e: 685b ldr r3, [r3, #4] + 8005a70: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005a74: 2b00 cmp r3, #0 + 8005a76: f000 80be beq.w 8005bf6 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8005a7a: 4b65 ldr r3, [pc, #404] ; (8005c10 ) + 8005a7c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005a7e: 4a64 ldr r2, [pc, #400] ; (8005c10 ) + 8005a80: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8005a84: 6453 str r3, [r2, #68] ; 0x44 + 8005a86: 4b62 ldr r3, [pc, #392] ; (8005c10 ) + 8005a88: 6c5b ldr r3, [r3, #68] ; 0x44 + 8005a8a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8005a8e: 60fb str r3, [r7, #12] + 8005a90: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2]; + 8005a92: 4a60 ldr r2, [pc, #384] ; (8005c14 ) + 8005a94: 69fb ldr r3, [r7, #28] + 8005a96: 089b lsrs r3, r3, #2 + 8005a98: 3302 adds r3, #2 + 8005a9a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8005a9e: 61bb str r3, [r7, #24] + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 8005aa0: 69fb ldr r3, [r7, #28] + 8005aa2: f003 0303 and.w r3, r3, #3 + 8005aa6: 009b lsls r3, r3, #2 + 8005aa8: 220f movs r2, #15 + 8005aaa: fa02 f303 lsl.w r3, r2, r3 + 8005aae: 43db mvns r3, r3 + 8005ab0: 69ba ldr r2, [r7, #24] + 8005ab2: 4013 ands r3, r2 + 8005ab4: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 8005ab6: 687b ldr r3, [r7, #4] + 8005ab8: 4a57 ldr r2, [pc, #348] ; (8005c18 ) + 8005aba: 4293 cmp r3, r2 + 8005abc: d037 beq.n 8005b2e + 8005abe: 687b ldr r3, [r7, #4] + 8005ac0: 4a56 ldr r2, [pc, #344] ; (8005c1c ) + 8005ac2: 4293 cmp r3, r2 + 8005ac4: d031 beq.n 8005b2a + 8005ac6: 687b ldr r3, [r7, #4] + 8005ac8: 4a55 ldr r2, [pc, #340] ; (8005c20 ) + 8005aca: 4293 cmp r3, r2 + 8005acc: d02b beq.n 8005b26 + 8005ace: 687b ldr r3, [r7, #4] + 8005ad0: 4a54 ldr r2, [pc, #336] ; (8005c24 ) + 8005ad2: 4293 cmp r3, r2 + 8005ad4: d025 beq.n 8005b22 + 8005ad6: 687b ldr r3, [r7, #4] + 8005ad8: 4a53 ldr r2, [pc, #332] ; (8005c28 ) + 8005ada: 4293 cmp r3, r2 + 8005adc: d01f beq.n 8005b1e + 8005ade: 687b ldr r3, [r7, #4] + 8005ae0: 4a52 ldr r2, [pc, #328] ; (8005c2c ) + 8005ae2: 4293 cmp r3, r2 + 8005ae4: d019 beq.n 8005b1a + 8005ae6: 687b ldr r3, [r7, #4] + 8005ae8: 4a51 ldr r2, [pc, #324] ; (8005c30 ) + 8005aea: 4293 cmp r3, r2 + 8005aec: d013 beq.n 8005b16 + 8005aee: 687b ldr r3, [r7, #4] + 8005af0: 4a50 ldr r2, [pc, #320] ; (8005c34 ) + 8005af2: 4293 cmp r3, r2 + 8005af4: d00d beq.n 8005b12 + 8005af6: 687b ldr r3, [r7, #4] + 8005af8: 4a4f ldr r2, [pc, #316] ; (8005c38 ) + 8005afa: 4293 cmp r3, r2 + 8005afc: d007 beq.n 8005b0e + 8005afe: 687b ldr r3, [r7, #4] + 8005b00: 4a4e ldr r2, [pc, #312] ; (8005c3c ) + 8005b02: 4293 cmp r3, r2 + 8005b04: d101 bne.n 8005b0a + 8005b06: 2309 movs r3, #9 + 8005b08: e012 b.n 8005b30 + 8005b0a: 230a movs r3, #10 + 8005b0c: e010 b.n 8005b30 + 8005b0e: 2308 movs r3, #8 + 8005b10: e00e b.n 8005b30 + 8005b12: 2307 movs r3, #7 + 8005b14: e00c b.n 8005b30 + 8005b16: 2306 movs r3, #6 + 8005b18: e00a b.n 8005b30 + 8005b1a: 2305 movs r3, #5 + 8005b1c: e008 b.n 8005b30 + 8005b1e: 2304 movs r3, #4 + 8005b20: e006 b.n 8005b30 + 8005b22: 2303 movs r3, #3 + 8005b24: e004 b.n 8005b30 + 8005b26: 2302 movs r3, #2 + 8005b28: e002 b.n 8005b30 + 8005b2a: 2301 movs r3, #1 + 8005b2c: e000 b.n 8005b30 + 8005b2e: 2300 movs r3, #0 + 8005b30: 69fa ldr r2, [r7, #28] + 8005b32: f002 0203 and.w r2, r2, #3 + 8005b36: 0092 lsls r2, r2, #2 + 8005b38: 4093 lsls r3, r2 + 8005b3a: 69ba ldr r2, [r7, #24] + 8005b3c: 4313 orrs r3, r2 + 8005b3e: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2] = temp; + 8005b40: 4934 ldr r1, [pc, #208] ; (8005c14 ) + 8005b42: 69fb ldr r3, [r7, #28] + 8005b44: 089b lsrs r3, r3, #2 + 8005b46: 3302 adds r3, #2 + 8005b48: 69ba ldr r2, [r7, #24] + 8005b4a: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 8005b4e: 4b3c ldr r3, [pc, #240] ; (8005c40 ) + 8005b50: 681b ldr r3, [r3, #0] + 8005b52: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8005b54: 693b ldr r3, [r7, #16] + 8005b56: 43db mvns r3, r3 + 8005b58: 69ba ldr r2, [r7, #24] + 8005b5a: 4013 ands r3, r2 + 8005b5c: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 8005b5e: 683b ldr r3, [r7, #0] + 8005b60: 685b ldr r3, [r3, #4] + 8005b62: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8005b66: 2b00 cmp r3, #0 + 8005b68: d003 beq.n 8005b72 + { + temp |= iocurrent; + 8005b6a: 69ba ldr r2, [r7, #24] + 8005b6c: 693b ldr r3, [r7, #16] + 8005b6e: 4313 orrs r3, r2 + 8005b70: 61bb str r3, [r7, #24] + } + EXTI->IMR = temp; + 8005b72: 4a33 ldr r2, [pc, #204] ; (8005c40 ) + 8005b74: 69bb ldr r3, [r7, #24] + 8005b76: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 8005b78: 4b31 ldr r3, [pc, #196] ; (8005c40 ) + 8005b7a: 685b ldr r3, [r3, #4] + 8005b7c: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8005b7e: 693b ldr r3, [r7, #16] + 8005b80: 43db mvns r3, r3 + 8005b82: 69ba ldr r2, [r7, #24] + 8005b84: 4013 ands r3, r2 + 8005b86: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 8005b88: 683b ldr r3, [r7, #0] + 8005b8a: 685b ldr r3, [r3, #4] + 8005b8c: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005b90: 2b00 cmp r3, #0 + 8005b92: d003 beq.n 8005b9c + { + temp |= iocurrent; + 8005b94: 69ba ldr r2, [r7, #24] + 8005b96: 693b ldr r3, [r7, #16] + 8005b98: 4313 orrs r3, r2 + 8005b9a: 61bb str r3, [r7, #24] + } + EXTI->EMR = temp; + 8005b9c: 4a28 ldr r2, [pc, #160] ; (8005c40 ) + 8005b9e: 69bb ldr r3, [r7, #24] + 8005ba0: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8005ba2: 4b27 ldr r3, [pc, #156] ; (8005c40 ) + 8005ba4: 689b ldr r3, [r3, #8] + 8005ba6: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8005ba8: 693b ldr r3, [r7, #16] + 8005baa: 43db mvns r3, r3 + 8005bac: 69ba ldr r2, [r7, #24] + 8005bae: 4013 ands r3, r2 + 8005bb0: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8005bb2: 683b ldr r3, [r7, #0] + 8005bb4: 685b ldr r3, [r3, #4] + 8005bb6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8005bba: 2b00 cmp r3, #0 + 8005bbc: d003 beq.n 8005bc6 + { + temp |= iocurrent; + 8005bbe: 69ba ldr r2, [r7, #24] + 8005bc0: 693b ldr r3, [r7, #16] + 8005bc2: 4313 orrs r3, r2 + 8005bc4: 61bb str r3, [r7, #24] + } + EXTI->RTSR = temp; + 8005bc6: 4a1e ldr r2, [pc, #120] ; (8005c40 ) + 8005bc8: 69bb ldr r3, [r7, #24] + 8005bca: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8005bcc: 4b1c ldr r3, [pc, #112] ; (8005c40 ) + 8005bce: 68db ldr r3, [r3, #12] + 8005bd0: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8005bd2: 693b ldr r3, [r7, #16] + 8005bd4: 43db mvns r3, r3 + 8005bd6: 69ba ldr r2, [r7, #24] + 8005bd8: 4013 ands r3, r2 + 8005bda: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8005bdc: 683b ldr r3, [r7, #0] + 8005bde: 685b ldr r3, [r3, #4] + 8005be0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8005be4: 2b00 cmp r3, #0 + 8005be6: d003 beq.n 8005bf0 + { + temp |= iocurrent; + 8005be8: 69ba ldr r2, [r7, #24] + 8005bea: 693b ldr r3, [r7, #16] + 8005bec: 4313 orrs r3, r2 + 8005bee: 61bb str r3, [r7, #24] + } + EXTI->FTSR = temp; + 8005bf0: 4a13 ldr r2, [pc, #76] ; (8005c40 ) + 8005bf2: 69bb ldr r3, [r7, #24] + 8005bf4: 60d3 str r3, [r2, #12] + for(position = 0; position < GPIO_NUMBER; position++) + 8005bf6: 69fb ldr r3, [r7, #28] + 8005bf8: 3301 adds r3, #1 + 8005bfa: 61fb str r3, [r7, #28] + 8005bfc: 69fb ldr r3, [r7, #28] + 8005bfe: 2b0f cmp r3, #15 + 8005c00: f67f ae86 bls.w 8005910 + } + } + } +} + 8005c04: bf00 nop + 8005c06: 3724 adds r7, #36 ; 0x24 + 8005c08: 46bd mov sp, r7 + 8005c0a: f85d 7b04 ldr.w r7, [sp], #4 + 8005c0e: 4770 bx lr + 8005c10: 40023800 .word 0x40023800 + 8005c14: 40013800 .word 0x40013800 + 8005c18: 40020000 .word 0x40020000 + 8005c1c: 40020400 .word 0x40020400 + 8005c20: 40020800 .word 0x40020800 + 8005c24: 40020c00 .word 0x40020c00 + 8005c28: 40021000 .word 0x40021000 + 8005c2c: 40021400 .word 0x40021400 + 8005c30: 40021800 .word 0x40021800 + 8005c34: 40021c00 .word 0x40021c00 + 8005c38: 40022000 .word 0x40022000 + 8005c3c: 40022400 .word 0x40022400 + 8005c40: 40013c00 .word 0x40013c00 + +08005c44 : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 8005c44: b480 push {r7} + 8005c46: b087 sub sp, #28 + 8005c48: af00 add r7, sp, #0 + 8005c4a: 6078 str r0, [r7, #4] + 8005c4c: 6039 str r1, [r7, #0] + uint32_t position; + uint32_t ioposition = 0x00; + 8005c4e: 2300 movs r3, #0 + 8005c50: 613b str r3, [r7, #16] + uint32_t iocurrent = 0x00; + 8005c52: 2300 movs r3, #0 + 8005c54: 60fb str r3, [r7, #12] + uint32_t tmp = 0x00; + 8005c56: 2300 movs r3, #0 + 8005c58: 60bb str r3, [r7, #8] + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + 8005c5a: 2300 movs r3, #0 + 8005c5c: 617b str r3, [r7, #20] + 8005c5e: e0d9 b.n 8005e14 + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + 8005c60: 2201 movs r2, #1 + 8005c62: 697b ldr r3, [r7, #20] + 8005c64: fa02 f303 lsl.w r3, r2, r3 + 8005c68: 613b str r3, [r7, #16] + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + 8005c6a: 683a ldr r2, [r7, #0] + 8005c6c: 693b ldr r3, [r7, #16] + 8005c6e: 4013 ands r3, r2 + 8005c70: 60fb str r3, [r7, #12] + + if(iocurrent == ioposition) + 8005c72: 68fa ldr r2, [r7, #12] + 8005c74: 693b ldr r3, [r7, #16] + 8005c76: 429a cmp r2, r3 + 8005c78: f040 80c9 bne.w 8005e0e + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2]; + 8005c7c: 4a6a ldr r2, [pc, #424] ; (8005e28 ) + 8005c7e: 697b ldr r3, [r7, #20] + 8005c80: 089b lsrs r3, r3, #2 + 8005c82: 3302 adds r3, #2 + 8005c84: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8005c88: 60bb str r3, [r7, #8] + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + 8005c8a: 697b ldr r3, [r7, #20] + 8005c8c: f003 0303 and.w r3, r3, #3 + 8005c90: 009b lsls r3, r3, #2 + 8005c92: 220f movs r2, #15 + 8005c94: fa02 f303 lsl.w r3, r2, r3 + 8005c98: 68ba ldr r2, [r7, #8] + 8005c9a: 4013 ands r3, r2 + 8005c9c: 60bb str r3, [r7, #8] + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 8005c9e: 687b ldr r3, [r7, #4] + 8005ca0: 4a62 ldr r2, [pc, #392] ; (8005e2c ) + 8005ca2: 4293 cmp r3, r2 + 8005ca4: d037 beq.n 8005d16 + 8005ca6: 687b ldr r3, [r7, #4] + 8005ca8: 4a61 ldr r2, [pc, #388] ; (8005e30 ) + 8005caa: 4293 cmp r3, r2 + 8005cac: d031 beq.n 8005d12 + 8005cae: 687b ldr r3, [r7, #4] + 8005cb0: 4a60 ldr r2, [pc, #384] ; (8005e34 ) + 8005cb2: 4293 cmp r3, r2 + 8005cb4: d02b beq.n 8005d0e + 8005cb6: 687b ldr r3, [r7, #4] + 8005cb8: 4a5f ldr r2, [pc, #380] ; (8005e38 ) + 8005cba: 4293 cmp r3, r2 + 8005cbc: d025 beq.n 8005d0a + 8005cbe: 687b ldr r3, [r7, #4] + 8005cc0: 4a5e ldr r2, [pc, #376] ; (8005e3c ) + 8005cc2: 4293 cmp r3, r2 + 8005cc4: d01f beq.n 8005d06 + 8005cc6: 687b ldr r3, [r7, #4] + 8005cc8: 4a5d ldr r2, [pc, #372] ; (8005e40 ) + 8005cca: 4293 cmp r3, r2 + 8005ccc: d019 beq.n 8005d02 + 8005cce: 687b ldr r3, [r7, #4] + 8005cd0: 4a5c ldr r2, [pc, #368] ; (8005e44 ) + 8005cd2: 4293 cmp r3, r2 + 8005cd4: d013 beq.n 8005cfe + 8005cd6: 687b ldr r3, [r7, #4] + 8005cd8: 4a5b ldr r2, [pc, #364] ; (8005e48 ) + 8005cda: 4293 cmp r3, r2 + 8005cdc: d00d beq.n 8005cfa + 8005cde: 687b ldr r3, [r7, #4] + 8005ce0: 4a5a ldr r2, [pc, #360] ; (8005e4c ) + 8005ce2: 4293 cmp r3, r2 + 8005ce4: d007 beq.n 8005cf6 + 8005ce6: 687b ldr r3, [r7, #4] + 8005ce8: 4a59 ldr r2, [pc, #356] ; (8005e50 ) + 8005cea: 4293 cmp r3, r2 + 8005cec: d101 bne.n 8005cf2 + 8005cee: 2309 movs r3, #9 + 8005cf0: e012 b.n 8005d18 + 8005cf2: 230a movs r3, #10 + 8005cf4: e010 b.n 8005d18 + 8005cf6: 2308 movs r3, #8 + 8005cf8: e00e b.n 8005d18 + 8005cfa: 2307 movs r3, #7 + 8005cfc: e00c b.n 8005d18 + 8005cfe: 2306 movs r3, #6 + 8005d00: e00a b.n 8005d18 + 8005d02: 2305 movs r3, #5 + 8005d04: e008 b.n 8005d18 + 8005d06: 2304 movs r3, #4 + 8005d08: e006 b.n 8005d18 + 8005d0a: 2303 movs r3, #3 + 8005d0c: e004 b.n 8005d18 + 8005d0e: 2302 movs r3, #2 + 8005d10: e002 b.n 8005d18 + 8005d12: 2301 movs r3, #1 + 8005d14: e000 b.n 8005d18 + 8005d16: 2300 movs r3, #0 + 8005d18: 697a ldr r2, [r7, #20] + 8005d1a: f002 0203 and.w r2, r2, #3 + 8005d1e: 0092 lsls r2, r2, #2 + 8005d20: 4093 lsls r3, r2 + 8005d22: 68ba ldr r2, [r7, #8] + 8005d24: 429a cmp r2, r3 + 8005d26: d132 bne.n 8005d8e + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + 8005d28: 4b4a ldr r3, [pc, #296] ; (8005e54 ) + 8005d2a: 681a ldr r2, [r3, #0] + 8005d2c: 68fb ldr r3, [r7, #12] + 8005d2e: 43db mvns r3, r3 + 8005d30: 4948 ldr r1, [pc, #288] ; (8005e54 ) + 8005d32: 4013 ands r3, r2 + 8005d34: 600b str r3, [r1, #0] + EXTI->EMR &= ~((uint32_t)iocurrent); + 8005d36: 4b47 ldr r3, [pc, #284] ; (8005e54 ) + 8005d38: 685a ldr r2, [r3, #4] + 8005d3a: 68fb ldr r3, [r7, #12] + 8005d3c: 43db mvns r3, r3 + 8005d3e: 4945 ldr r1, [pc, #276] ; (8005e54 ) + 8005d40: 4013 ands r3, r2 + 8005d42: 604b str r3, [r1, #4] + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + 8005d44: 4b43 ldr r3, [pc, #268] ; (8005e54 ) + 8005d46: 689a ldr r2, [r3, #8] + 8005d48: 68fb ldr r3, [r7, #12] + 8005d4a: 43db mvns r3, r3 + 8005d4c: 4941 ldr r1, [pc, #260] ; (8005e54 ) + 8005d4e: 4013 ands r3, r2 + 8005d50: 608b str r3, [r1, #8] + EXTI->FTSR &= ~((uint32_t)iocurrent); + 8005d52: 4b40 ldr r3, [pc, #256] ; (8005e54 ) + 8005d54: 68da ldr r2, [r3, #12] + 8005d56: 68fb ldr r3, [r7, #12] + 8005d58: 43db mvns r3, r3 + 8005d5a: 493e ldr r1, [pc, #248] ; (8005e54 ) + 8005d5c: 4013 ands r3, r2 + 8005d5e: 60cb str r3, [r1, #12] + + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + 8005d60: 697b ldr r3, [r7, #20] + 8005d62: f003 0303 and.w r3, r3, #3 + 8005d66: 009b lsls r3, r3, #2 + 8005d68: 220f movs r2, #15 + 8005d6a: fa02 f303 lsl.w r3, r2, r3 + 8005d6e: 60bb str r3, [r7, #8] + SYSCFG->EXTICR[position >> 2] &= ~tmp; + 8005d70: 4a2d ldr r2, [pc, #180] ; (8005e28 ) + 8005d72: 697b ldr r3, [r7, #20] + 8005d74: 089b lsrs r3, r3, #2 + 8005d76: 3302 adds r3, #2 + 8005d78: f852 1023 ldr.w r1, [r2, r3, lsl #2] + 8005d7c: 68bb ldr r3, [r7, #8] + 8005d7e: 43da mvns r2, r3 + 8005d80: 4829 ldr r0, [pc, #164] ; (8005e28 ) + 8005d82: 697b ldr r3, [r7, #20] + 8005d84: 089b lsrs r3, r3, #2 + 8005d86: 400a ands r2, r1 + 8005d88: 3302 adds r3, #2 + 8005d8a: f840 2023 str.w r2, [r0, r3, lsl #2] + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + 8005d8e: 687b ldr r3, [r7, #4] + 8005d90: 681a ldr r2, [r3, #0] + 8005d92: 697b ldr r3, [r7, #20] + 8005d94: 005b lsls r3, r3, #1 + 8005d96: 2103 movs r1, #3 + 8005d98: fa01 f303 lsl.w r3, r1, r3 + 8005d9c: 43db mvns r3, r3 + 8005d9e: 401a ands r2, r3 + 8005da0: 687b ldr r3, [r7, #4] + 8005da2: 601a str r2, [r3, #0] + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 8005da4: 697b ldr r3, [r7, #20] + 8005da6: 08da lsrs r2, r3, #3 + 8005da8: 687b ldr r3, [r7, #4] + 8005daa: 3208 adds r2, #8 + 8005dac: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8005db0: 697b ldr r3, [r7, #20] + 8005db2: f003 0307 and.w r3, r3, #7 + 8005db6: 009b lsls r3, r3, #2 + 8005db8: 220f movs r2, #15 + 8005dba: fa02 f303 lsl.w r3, r2, r3 + 8005dbe: 43db mvns r3, r3 + 8005dc0: 697a ldr r2, [r7, #20] + 8005dc2: 08d2 lsrs r2, r2, #3 + 8005dc4: 4019 ands r1, r3 + 8005dc6: 687b ldr r3, [r7, #4] + 8005dc8: 3208 adds r2, #8 + 8005dca: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 8005dce: 687b ldr r3, [r7, #4] + 8005dd0: 68da ldr r2, [r3, #12] + 8005dd2: 697b ldr r3, [r7, #20] + 8005dd4: 005b lsls r3, r3, #1 + 8005dd6: 2103 movs r1, #3 + 8005dd8: fa01 f303 lsl.w r3, r1, r3 + 8005ddc: 43db mvns r3, r3 + 8005dde: 401a ands r2, r3 + 8005de0: 687b ldr r3, [r7, #4] + 8005de2: 60da str r2, [r3, #12] + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 8005de4: 687b ldr r3, [r7, #4] + 8005de6: 685a ldr r2, [r3, #4] + 8005de8: 2101 movs r1, #1 + 8005dea: 697b ldr r3, [r7, #20] + 8005dec: fa01 f303 lsl.w r3, r1, r3 + 8005df0: 43db mvns r3, r3 + 8005df2: 401a ands r2, r3 + 8005df4: 687b ldr r3, [r7, #4] + 8005df6: 605a str r2, [r3, #4] + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 8005df8: 687b ldr r3, [r7, #4] + 8005dfa: 689a ldr r2, [r3, #8] + 8005dfc: 697b ldr r3, [r7, #20] + 8005dfe: 005b lsls r3, r3, #1 + 8005e00: 2103 movs r1, #3 + 8005e02: fa01 f303 lsl.w r3, r1, r3 + 8005e06: 43db mvns r3, r3 + 8005e08: 401a ands r2, r3 + 8005e0a: 687b ldr r3, [r7, #4] + 8005e0c: 609a str r2, [r3, #8] + for(position = 0; position < GPIO_NUMBER; position++) + 8005e0e: 697b ldr r3, [r7, #20] + 8005e10: 3301 adds r3, #1 + 8005e12: 617b str r3, [r7, #20] + 8005e14: 697b ldr r3, [r7, #20] + 8005e16: 2b0f cmp r3, #15 + 8005e18: f67f af22 bls.w 8005c60 + } + } +} + 8005e1c: bf00 nop + 8005e1e: 371c adds r7, #28 + 8005e20: 46bd mov sp, r7 + 8005e22: f85d 7b04 ldr.w r7, [sp], #4 + 8005e26: 4770 bx lr + 8005e28: 40013800 .word 0x40013800 + 8005e2c: 40020000 .word 0x40020000 + 8005e30: 40020400 .word 0x40020400 + 8005e34: 40020800 .word 0x40020800 + 8005e38: 40020c00 .word 0x40020c00 + 8005e3c: 40021000 .word 0x40021000 + 8005e40: 40021400 .word 0x40021400 + 8005e44: 40021800 .word 0x40021800 + 8005e48: 40021c00 .word 0x40021c00 + 8005e4c: 40022000 .word 0x40022000 + 8005e50: 40022400 .word 0x40022400 + 8005e54: 40013c00 .word 0x40013c00 + +08005e58 : + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + 8005e58: b480 push {r7} + 8005e5a: b085 sub sp, #20 + 8005e5c: af00 add r7, sp, #0 + 8005e5e: 6078 str r0, [r7, #4] + 8005e60: 460b mov r3, r1 + 8005e62: 807b strh r3, [r7, #2] + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 8005e64: 687b ldr r3, [r7, #4] + 8005e66: 691a ldr r2, [r3, #16] + 8005e68: 887b ldrh r3, [r7, #2] + 8005e6a: 4013 ands r3, r2 + 8005e6c: 2b00 cmp r3, #0 + 8005e6e: d002 beq.n 8005e76 + { + bitstatus = GPIO_PIN_SET; + 8005e70: 2301 movs r3, #1 + 8005e72: 73fb strb r3, [r7, #15] + 8005e74: e001 b.n 8005e7a + } + else + { + bitstatus = GPIO_PIN_RESET; + 8005e76: 2300 movs r3, #0 + 8005e78: 73fb strb r3, [r7, #15] + } + return bitstatus; + 8005e7a: 7bfb ldrb r3, [r7, #15] +} + 8005e7c: 4618 mov r0, r3 + 8005e7e: 3714 adds r7, #20 + 8005e80: 46bd mov sp, r7 + 8005e82: f85d 7b04 ldr.w r7, [sp], #4 + 8005e86: 4770 bx lr + +08005e88 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 8005e88: b480 push {r7} + 8005e8a: b083 sub sp, #12 + 8005e8c: af00 add r7, sp, #0 + 8005e8e: 6078 str r0, [r7, #4] + 8005e90: 460b mov r3, r1 + 8005e92: 807b strh r3, [r7, #2] + 8005e94: 4613 mov r3, r2 + 8005e96: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 8005e98: 787b ldrb r3, [r7, #1] + 8005e9a: 2b00 cmp r3, #0 + 8005e9c: d003 beq.n 8005ea6 + { + GPIOx->BSRR = GPIO_Pin; + 8005e9e: 887a ldrh r2, [r7, #2] + 8005ea0: 687b ldr r3, [r7, #4] + 8005ea2: 619a str r2, [r3, #24] + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + 8005ea4: e003 b.n 8005eae + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 8005ea6: 887b ldrh r3, [r7, #2] + 8005ea8: 041a lsls r2, r3, #16 + 8005eaa: 687b ldr r3, [r7, #4] + 8005eac: 619a str r2, [r3, #24] +} + 8005eae: bf00 nop + 8005eb0: 370c adds r7, #12 + 8005eb2: 46bd mov sp, r7 + 8005eb4: f85d 7b04 ldr.w r7, [sp], #4 + 8005eb8: 4770 bx lr + ... + +08005ebc : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 8005ebc: b580 push {r7, lr} + 8005ebe: b082 sub sp, #8 + 8005ec0: af00 add r7, sp, #0 + 8005ec2: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8005ec4: 687b ldr r3, [r7, #4] + 8005ec6: 2b00 cmp r3, #0 + 8005ec8: d101 bne.n 8005ece + { + return HAL_ERROR; + 8005eca: 2301 movs r3, #1 + 8005ecc: e07f b.n 8005fce + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 8005ece: 687b ldr r3, [r7, #4] + 8005ed0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8005ed4: b2db uxtb r3, r3 + 8005ed6: 2b00 cmp r3, #0 + 8005ed8: d106 bne.n 8005ee8 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 8005eda: 687b ldr r3, [r7, #4] + 8005edc: 2200 movs r2, #0 + 8005ede: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + 8005ee2: 6878 ldr r0, [r7, #4] + 8005ee4: f7fd fdb4 bl 8003a50 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 8005ee8: 687b ldr r3, [r7, #4] + 8005eea: 2224 movs r2, #36 ; 0x24 + 8005eec: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8005ef0: 687b ldr r3, [r7, #4] + 8005ef2: 681b ldr r3, [r3, #0] + 8005ef4: 681a ldr r2, [r3, #0] + 8005ef6: 687b ldr r3, [r7, #4] + 8005ef8: 681b ldr r3, [r3, #0] + 8005efa: f022 0201 bic.w r2, r2, #1 + 8005efe: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 8005f00: 687b ldr r3, [r7, #4] + 8005f02: 685a ldr r2, [r3, #4] + 8005f04: 687b ldr r3, [r7, #4] + 8005f06: 681b ldr r3, [r3, #0] + 8005f08: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 8005f0c: 611a str r2, [r3, #16] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 8005f0e: 687b ldr r3, [r7, #4] + 8005f10: 681b ldr r3, [r3, #0] + 8005f12: 689a ldr r2, [r3, #8] + 8005f14: 687b ldr r3, [r7, #4] + 8005f16: 681b ldr r3, [r3, #0] + 8005f18: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8005f1c: 609a str r2, [r3, #8] + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 8005f1e: 687b ldr r3, [r7, #4] + 8005f20: 68db ldr r3, [r3, #12] + 8005f22: 2b01 cmp r3, #1 + 8005f24: d107 bne.n 8005f36 + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 8005f26: 687b ldr r3, [r7, #4] + 8005f28: 689a ldr r2, [r3, #8] + 8005f2a: 687b ldr r3, [r7, #4] + 8005f2c: 681b ldr r3, [r3, #0] + 8005f2e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8005f32: 609a str r2, [r3, #8] + 8005f34: e006 b.n 8005f44 + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 8005f36: 687b ldr r3, [r7, #4] + 8005f38: 689a ldr r2, [r3, #8] + 8005f3a: 687b ldr r3, [r7, #4] + 8005f3c: 681b ldr r3, [r3, #0] + 8005f3e: f442 4204 orr.w r2, r2, #33792 ; 0x8400 + 8005f42: 609a str r2, [r3, #8] + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 8005f44: 687b ldr r3, [r7, #4] + 8005f46: 68db ldr r3, [r3, #12] + 8005f48: 2b02 cmp r3, #2 + 8005f4a: d104 bne.n 8005f56 + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 8005f4c: 687b ldr r3, [r7, #4] + 8005f4e: 681b ldr r3, [r3, #0] + 8005f50: f44f 6200 mov.w r2, #2048 ; 0x800 + 8005f54: 605a str r2, [r3, #4] + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 8005f56: 687b ldr r3, [r7, #4] + 8005f58: 681b ldr r3, [r3, #0] + 8005f5a: 6859 ldr r1, [r3, #4] + 8005f5c: 687b ldr r3, [r7, #4] + 8005f5e: 681a ldr r2, [r3, #0] + 8005f60: 4b1d ldr r3, [pc, #116] ; (8005fd8 ) + 8005f62: 430b orrs r3, r1 + 8005f64: 6053 str r3, [r2, #4] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 8005f66: 687b ldr r3, [r7, #4] + 8005f68: 681b ldr r3, [r3, #0] + 8005f6a: 68da ldr r2, [r3, #12] + 8005f6c: 687b ldr r3, [r7, #4] + 8005f6e: 681b ldr r3, [r3, #0] + 8005f70: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 8005f74: 60da str r2, [r3, #12] + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + 8005f76: 687b ldr r3, [r7, #4] + 8005f78: 691a ldr r2, [r3, #16] + 8005f7a: 687b ldr r3, [r7, #4] + 8005f7c: 695b ldr r3, [r3, #20] + 8005f7e: ea42 0103 orr.w r1, r2, r3 + 8005f82: 687b ldr r3, [r7, #4] + 8005f84: 699b ldr r3, [r3, #24] + 8005f86: 021a lsls r2, r3, #8 + 8005f88: 687b ldr r3, [r7, #4] + 8005f8a: 681b ldr r3, [r3, #0] + 8005f8c: 430a orrs r2, r1 + 8005f8e: 60da str r2, [r3, #12] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 8005f90: 687b ldr r3, [r7, #4] + 8005f92: 69d9 ldr r1, [r3, #28] + 8005f94: 687b ldr r3, [r7, #4] + 8005f96: 6a1a ldr r2, [r3, #32] + 8005f98: 687b ldr r3, [r7, #4] + 8005f9a: 681b ldr r3, [r3, #0] + 8005f9c: 430a orrs r2, r1 + 8005f9e: 601a str r2, [r3, #0] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 8005fa0: 687b ldr r3, [r7, #4] + 8005fa2: 681b ldr r3, [r3, #0] + 8005fa4: 681a ldr r2, [r3, #0] + 8005fa6: 687b ldr r3, [r7, #4] + 8005fa8: 681b ldr r3, [r3, #0] + 8005faa: f042 0201 orr.w r2, r2, #1 + 8005fae: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8005fb0: 687b ldr r3, [r7, #4] + 8005fb2: 2200 movs r2, #0 + 8005fb4: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8005fb6: 687b ldr r3, [r7, #4] + 8005fb8: 2220 movs r2, #32 + 8005fba: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->PreviousState = I2C_STATE_NONE; + 8005fbe: 687b ldr r3, [r7, #4] + 8005fc0: 2200 movs r2, #0 + 8005fc2: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8005fc4: 687b ldr r3, [r7, #4] + 8005fc6: 2200 movs r2, #0 + 8005fc8: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + return HAL_OK; + 8005fcc: 2300 movs r3, #0 +} + 8005fce: 4618 mov r0, r3 + 8005fd0: 3708 adds r7, #8 + 8005fd2: 46bd mov sp, r7 + 8005fd4: bd80 pop {r7, pc} + 8005fd6: bf00 nop + 8005fd8: 02008000 .word 0x02008000 + +08005fdc : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + 8005fdc: b580 push {r7, lr} + 8005fde: b082 sub sp, #8 + 8005fe0: af00 add r7, sp, #0 + 8005fe2: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8005fe4: 687b ldr r3, [r7, #4] + 8005fe6: 2b00 cmp r3, #0 + 8005fe8: d101 bne.n 8005fee + { + return HAL_ERROR; + 8005fea: 2301 movs r3, #1 + 8005fec: e021 b.n 8006032 + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + 8005fee: 687b ldr r3, [r7, #4] + 8005ff0: 2224 movs r2, #36 ; 0x24 + 8005ff2: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + 8005ff6: 687b ldr r3, [r7, #4] + 8005ff8: 681b ldr r3, [r3, #0] + 8005ffa: 681a ldr r2, [r3, #0] + 8005ffc: 687b ldr r3, [r7, #4] + 8005ffe: 681b ldr r3, [r3, #0] + 8006000: f022 0201 bic.w r2, r2, #1 + 8006004: 601a str r2, [r3, #0] + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); + 8006006: 6878 ldr r0, [r7, #4] + 8006008: f7fd fd9a bl 8003b40 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 800600c: 687b ldr r3, [r7, #4] + 800600e: 2200 movs r2, #0 + 8006010: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_RESET; + 8006012: 687b ldr r3, [r7, #4] + 8006014: 2200 movs r2, #0 + 8006016: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->PreviousState = I2C_STATE_NONE; + 800601a: 687b ldr r3, [r7, #4] + 800601c: 2200 movs r2, #0 + 800601e: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006020: 687b ldr r3, [r7, #4] + 8006022: 2200 movs r2, #0 + 8006024: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + 8006028: 687b ldr r3, [r7, #4] + 800602a: 2200 movs r2, #0 + 800602c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006030: 2300 movs r3, #0 +} + 8006032: 4618 mov r0, r3 + 8006034: 3708 adds r7, #8 + 8006036: 46bd mov sp, r7 + 8006038: bd80 pop {r7, pc} + ... + +0800603c : + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 800603c: b580 push {r7, lr} + 800603e: b088 sub sp, #32 + 8006040: af02 add r7, sp, #8 + 8006042: 60f8 str r0, [r7, #12] + 8006044: 4608 mov r0, r1 + 8006046: 4611 mov r1, r2 + 8006048: 461a mov r2, r3 + 800604a: 4603 mov r3, r0 + 800604c: 817b strh r3, [r7, #10] + 800604e: 460b mov r3, r1 + 8006050: 813b strh r3, [r7, #8] + 8006052: 4613 mov r3, r2 + 8006054: 80fb strh r3, [r7, #6] + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8006056: 68fb ldr r3, [r7, #12] + 8006058: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 800605c: b2db uxtb r3, r3 + 800605e: 2b20 cmp r3, #32 + 8006060: f040 80f9 bne.w 8006256 + { + if ((pData == NULL) || (Size == 0U)) + 8006064: 6a3b ldr r3, [r7, #32] + 8006066: 2b00 cmp r3, #0 + 8006068: d002 beq.n 8006070 + 800606a: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800606c: 2b00 cmp r3, #0 + 800606e: d105 bne.n 800607c + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 8006070: 68fb ldr r3, [r7, #12] + 8006072: f44f 7200 mov.w r2, #512 ; 0x200 + 8006076: 645a str r2, [r3, #68] ; 0x44 + return HAL_ERROR; + 8006078: 2301 movs r3, #1 + 800607a: e0ed b.n 8006258 + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 800607c: 68fb ldr r3, [r7, #12] + 800607e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8006082: 2b01 cmp r3, #1 + 8006084: d101 bne.n 800608a + 8006086: 2302 movs r3, #2 + 8006088: e0e6 b.n 8006258 + 800608a: 68fb ldr r3, [r7, #12] + 800608c: 2201 movs r2, #1 + 800608e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8006092: f7fe fa2d bl 80044f0 + 8006096: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8006098: 697b ldr r3, [r7, #20] + 800609a: 9300 str r3, [sp, #0] + 800609c: 2319 movs r3, #25 + 800609e: 2201 movs r2, #1 + 80060a0: f44f 4100 mov.w r1, #32768 ; 0x8000 + 80060a4: 68f8 ldr r0, [r7, #12] + 80060a6: f000 fad1 bl 800664c + 80060aa: 4603 mov r3, r0 + 80060ac: 2b00 cmp r3, #0 + 80060ae: d001 beq.n 80060b4 + { + return HAL_ERROR; + 80060b0: 2301 movs r3, #1 + 80060b2: e0d1 b.n 8006258 + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 80060b4: 68fb ldr r3, [r7, #12] + 80060b6: 2221 movs r2, #33 ; 0x21 + 80060b8: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MEM; + 80060bc: 68fb ldr r3, [r7, #12] + 80060be: 2240 movs r2, #64 ; 0x40 + 80060c0: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80060c4: 68fb ldr r3, [r7, #12] + 80060c6: 2200 movs r2, #0 + 80060c8: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 80060ca: 68fb ldr r3, [r7, #12] + 80060cc: 6a3a ldr r2, [r7, #32] + 80060ce: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 80060d0: 68fb ldr r3, [r7, #12] + 80060d2: 8cba ldrh r2, [r7, #36] ; 0x24 + 80060d4: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 80060d6: 68fb ldr r3, [r7, #12] + 80060d8: 2200 movs r2, #0 + 80060da: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + 80060dc: 88f8 ldrh r0, [r7, #6] + 80060de: 893a ldrh r2, [r7, #8] + 80060e0: 8979 ldrh r1, [r7, #10] + 80060e2: 697b ldr r3, [r7, #20] + 80060e4: 9301 str r3, [sp, #4] + 80060e6: 6abb ldr r3, [r7, #40] ; 0x28 + 80060e8: 9300 str r3, [sp, #0] + 80060ea: 4603 mov r3, r0 + 80060ec: 68f8 ldr r0, [r7, #12] + 80060ee: f000 f9e1 bl 80064b4 + 80060f2: 4603 mov r3, r0 + 80060f4: 2b00 cmp r3, #0 + 80060f6: d005 beq.n 8006104 + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80060f8: 68fb ldr r3, [r7, #12] + 80060fa: 2200 movs r2, #0 + 80060fc: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8006100: 2301 movs r3, #1 + 8006102: e0a9 b.n 8006258 + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8006104: 68fb ldr r3, [r7, #12] + 8006106: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006108: b29b uxth r3, r3 + 800610a: 2bff cmp r3, #255 ; 0xff + 800610c: d90e bls.n 800612c + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 800610e: 68fb ldr r3, [r7, #12] + 8006110: 22ff movs r2, #255 ; 0xff + 8006112: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 8006114: 68fb ldr r3, [r7, #12] + 8006116: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006118: b2da uxtb r2, r3 + 800611a: 8979 ldrh r1, [r7, #10] + 800611c: 2300 movs r3, #0 + 800611e: 9300 str r3, [sp, #0] + 8006120: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8006124: 68f8 ldr r0, [r7, #12] + 8006126: f000 fbb3 bl 8006890 + 800612a: e00f b.n 800614c + } + else + { + hi2c->XferSize = hi2c->XferCount; + 800612c: 68fb ldr r3, [r7, #12] + 800612e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006130: b29a uxth r2, r3 + 8006132: 68fb ldr r3, [r7, #12] + 8006134: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 8006136: 68fb ldr r3, [r7, #12] + 8006138: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800613a: b2da uxtb r2, r3 + 800613c: 8979 ldrh r1, [r7, #10] + 800613e: 2300 movs r3, #0 + 8006140: 9300 str r3, [sp, #0] + 8006142: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8006146: 68f8 ldr r0, [r7, #12] + 8006148: f000 fba2 bl 8006890 + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 800614c: 697a ldr r2, [r7, #20] + 800614e: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8006150: 68f8 ldr r0, [r7, #12] + 8006152: f000 fabb bl 80066cc + 8006156: 4603 mov r3, r0 + 8006158: 2b00 cmp r3, #0 + 800615a: d001 beq.n 8006160 + { + return HAL_ERROR; + 800615c: 2301 movs r3, #1 + 800615e: e07b b.n 8006258 + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8006160: 68fb ldr r3, [r7, #12] + 8006162: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006164: 781a ldrb r2, [r3, #0] + 8006166: 68fb ldr r3, [r7, #12] + 8006168: 681b ldr r3, [r3, #0] + 800616a: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 800616c: 68fb ldr r3, [r7, #12] + 800616e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006170: 1c5a adds r2, r3, #1 + 8006172: 68fb ldr r3, [r7, #12] + 8006174: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 8006176: 68fb ldr r3, [r7, #12] + 8006178: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800617a: b29b uxth r3, r3 + 800617c: 3b01 subs r3, #1 + 800617e: b29a uxth r2, r3 + 8006180: 68fb ldr r3, [r7, #12] + 8006182: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8006184: 68fb ldr r3, [r7, #12] + 8006186: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006188: 3b01 subs r3, #1 + 800618a: b29a uxth r2, r3 + 800618c: 68fb ldr r3, [r7, #12] + 800618e: 851a strh r2, [r3, #40] ; 0x28 + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8006190: 68fb ldr r3, [r7, #12] + 8006192: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006194: b29b uxth r3, r3 + 8006196: 2b00 cmp r3, #0 + 8006198: d034 beq.n 8006204 + 800619a: 68fb ldr r3, [r7, #12] + 800619c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800619e: 2b00 cmp r3, #0 + 80061a0: d130 bne.n 8006204 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 80061a2: 697b ldr r3, [r7, #20] + 80061a4: 9300 str r3, [sp, #0] + 80061a6: 6abb ldr r3, [r7, #40] ; 0x28 + 80061a8: 2200 movs r2, #0 + 80061aa: 2180 movs r1, #128 ; 0x80 + 80061ac: 68f8 ldr r0, [r7, #12] + 80061ae: f000 fa4d bl 800664c + 80061b2: 4603 mov r3, r0 + 80061b4: 2b00 cmp r3, #0 + 80061b6: d001 beq.n 80061bc + { + return HAL_ERROR; + 80061b8: 2301 movs r3, #1 + 80061ba: e04d b.n 8006258 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 80061bc: 68fb ldr r3, [r7, #12] + 80061be: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80061c0: b29b uxth r3, r3 + 80061c2: 2bff cmp r3, #255 ; 0xff + 80061c4: d90e bls.n 80061e4 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 80061c6: 68fb ldr r3, [r7, #12] + 80061c8: 22ff movs r2, #255 ; 0xff + 80061ca: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 80061cc: 68fb ldr r3, [r7, #12] + 80061ce: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80061d0: b2da uxtb r2, r3 + 80061d2: 8979 ldrh r1, [r7, #10] + 80061d4: 2300 movs r3, #0 + 80061d6: 9300 str r3, [sp, #0] + 80061d8: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 80061dc: 68f8 ldr r0, [r7, #12] + 80061de: f000 fb57 bl 8006890 + 80061e2: e00f b.n 8006204 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 80061e4: 68fb ldr r3, [r7, #12] + 80061e6: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80061e8: b29a uxth r2, r3 + 80061ea: 68fb ldr r3, [r7, #12] + 80061ec: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 80061ee: 68fb ldr r3, [r7, #12] + 80061f0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80061f2: b2da uxtb r2, r3 + 80061f4: 8979 ldrh r1, [r7, #10] + 80061f6: 2300 movs r3, #0 + 80061f8: 9300 str r3, [sp, #0] + 80061fa: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80061fe: 68f8 ldr r0, [r7, #12] + 8006200: f000 fb46 bl 8006890 + } + } + + } + while (hi2c->XferCount > 0U); + 8006204: 68fb ldr r3, [r7, #12] + 8006206: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006208: b29b uxth r3, r3 + 800620a: 2b00 cmp r3, #0 + 800620c: d19e bne.n 800614c + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 800620e: 697a ldr r2, [r7, #20] + 8006210: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8006212: 68f8 ldr r0, [r7, #12] + 8006214: f000 fa9a bl 800674c + 8006218: 4603 mov r3, r0 + 800621a: 2b00 cmp r3, #0 + 800621c: d001 beq.n 8006222 + { + return HAL_ERROR; + 800621e: 2301 movs r3, #1 + 8006220: e01a b.n 8006258 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8006222: 68fb ldr r3, [r7, #12] + 8006224: 681b ldr r3, [r3, #0] + 8006226: 2220 movs r2, #32 + 8006228: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 800622a: 68fb ldr r3, [r7, #12] + 800622c: 681b ldr r3, [r3, #0] + 800622e: 6859 ldr r1, [r3, #4] + 8006230: 68fb ldr r3, [r7, #12] + 8006232: 681a ldr r2, [r3, #0] + 8006234: 4b0a ldr r3, [pc, #40] ; (8006260 ) + 8006236: 400b ands r3, r1 + 8006238: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 800623a: 68fb ldr r3, [r7, #12] + 800623c: 2220 movs r2, #32 + 800623e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006242: 68fb ldr r3, [r7, #12] + 8006244: 2200 movs r2, #0 + 8006246: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800624a: 68fb ldr r3, [r7, #12] + 800624c: 2200 movs r2, #0 + 800624e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006252: 2300 movs r3, #0 + 8006254: e000 b.n 8006258 + } + else + { + return HAL_BUSY; + 8006256: 2302 movs r3, #2 + } +} + 8006258: 4618 mov r0, r3 + 800625a: 3718 adds r7, #24 + 800625c: 46bd mov sp, r7 + 800625e: bd80 pop {r7, pc} + 8006260: fe00e800 .word 0xfe00e800 + +08006264 : + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8006264: b580 push {r7, lr} + 8006266: b088 sub sp, #32 + 8006268: af02 add r7, sp, #8 + 800626a: 60f8 str r0, [r7, #12] + 800626c: 4608 mov r0, r1 + 800626e: 4611 mov r1, r2 + 8006270: 461a mov r2, r3 + 8006272: 4603 mov r3, r0 + 8006274: 817b strh r3, [r7, #10] + 8006276: 460b mov r3, r1 + 8006278: 813b strh r3, [r7, #8] + 800627a: 4613 mov r3, r2 + 800627c: 80fb strh r3, [r7, #6] + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 800627e: 68fb ldr r3, [r7, #12] + 8006280: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8006284: b2db uxtb r3, r3 + 8006286: 2b20 cmp r3, #32 + 8006288: f040 80fd bne.w 8006486 + { + if ((pData == NULL) || (Size == 0U)) + 800628c: 6a3b ldr r3, [r7, #32] + 800628e: 2b00 cmp r3, #0 + 8006290: d002 beq.n 8006298 + 8006292: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8006294: 2b00 cmp r3, #0 + 8006296: d105 bne.n 80062a4 + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 8006298: 68fb ldr r3, [r7, #12] + 800629a: f44f 7200 mov.w r2, #512 ; 0x200 + 800629e: 645a str r2, [r3, #68] ; 0x44 + return HAL_ERROR; + 80062a0: 2301 movs r3, #1 + 80062a2: e0f1 b.n 8006488 + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 80062a4: 68fb ldr r3, [r7, #12] + 80062a6: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 80062aa: 2b01 cmp r3, #1 + 80062ac: d101 bne.n 80062b2 + 80062ae: 2302 movs r3, #2 + 80062b0: e0ea b.n 8006488 + 80062b2: 68fb ldr r3, [r7, #12] + 80062b4: 2201 movs r2, #1 + 80062b6: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 80062ba: f7fe f919 bl 80044f0 + 80062be: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 80062c0: 697b ldr r3, [r7, #20] + 80062c2: 9300 str r3, [sp, #0] + 80062c4: 2319 movs r3, #25 + 80062c6: 2201 movs r2, #1 + 80062c8: f44f 4100 mov.w r1, #32768 ; 0x8000 + 80062cc: 68f8 ldr r0, [r7, #12] + 80062ce: f000 f9bd bl 800664c + 80062d2: 4603 mov r3, r0 + 80062d4: 2b00 cmp r3, #0 + 80062d6: d001 beq.n 80062dc + { + return HAL_ERROR; + 80062d8: 2301 movs r3, #1 + 80062da: e0d5 b.n 8006488 + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 80062dc: 68fb ldr r3, [r7, #12] + 80062de: 2222 movs r2, #34 ; 0x22 + 80062e0: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MEM; + 80062e4: 68fb ldr r3, [r7, #12] + 80062e6: 2240 movs r2, #64 ; 0x40 + 80062e8: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80062ec: 68fb ldr r3, [r7, #12] + 80062ee: 2200 movs r2, #0 + 80062f0: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 80062f2: 68fb ldr r3, [r7, #12] + 80062f4: 6a3a ldr r2, [r7, #32] + 80062f6: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 80062f8: 68fb ldr r3, [r7, #12] + 80062fa: 8cba ldrh r2, [r7, #36] ; 0x24 + 80062fc: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 80062fe: 68fb ldr r3, [r7, #12] + 8006300: 2200 movs r2, #0 + 8006302: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + 8006304: 88f8 ldrh r0, [r7, #6] + 8006306: 893a ldrh r2, [r7, #8] + 8006308: 8979 ldrh r1, [r7, #10] + 800630a: 697b ldr r3, [r7, #20] + 800630c: 9301 str r3, [sp, #4] + 800630e: 6abb ldr r3, [r7, #40] ; 0x28 + 8006310: 9300 str r3, [sp, #0] + 8006312: 4603 mov r3, r0 + 8006314: 68f8 ldr r0, [r7, #12] + 8006316: f000 f921 bl 800655c + 800631a: 4603 mov r3, r0 + 800631c: 2b00 cmp r3, #0 + 800631e: d005 beq.n 800632c + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006320: 68fb ldr r3, [r7, #12] + 8006322: 2200 movs r2, #0 + 8006324: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8006328: 2301 movs r3, #1 + 800632a: e0ad b.n 8006488 + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 800632c: 68fb ldr r3, [r7, #12] + 800632e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006330: b29b uxth r3, r3 + 8006332: 2bff cmp r3, #255 ; 0xff + 8006334: d90e bls.n 8006354 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8006336: 68fb ldr r3, [r7, #12] + 8006338: 22ff movs r2, #255 ; 0xff + 800633a: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + 800633c: 68fb ldr r3, [r7, #12] + 800633e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006340: b2da uxtb r2, r3 + 8006342: 8979 ldrh r1, [r7, #10] + 8006344: 4b52 ldr r3, [pc, #328] ; (8006490 ) + 8006346: 9300 str r3, [sp, #0] + 8006348: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 800634c: 68f8 ldr r0, [r7, #12] + 800634e: f000 fa9f bl 8006890 + 8006352: e00f b.n 8006374 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006354: 68fb ldr r3, [r7, #12] + 8006356: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006358: b29a uxth r2, r3 + 800635a: 68fb ldr r3, [r7, #12] + 800635c: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + 800635e: 68fb ldr r3, [r7, #12] + 8006360: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006362: b2da uxtb r2, r3 + 8006364: 8979 ldrh r1, [r7, #10] + 8006366: 4b4a ldr r3, [pc, #296] ; (8006490 ) + 8006368: 9300 str r3, [sp, #0] + 800636a: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 800636e: 68f8 ldr r0, [r7, #12] + 8006370: f000 fa8e bl 8006890 + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + 8006374: 697b ldr r3, [r7, #20] + 8006376: 9300 str r3, [sp, #0] + 8006378: 6abb ldr r3, [r7, #40] ; 0x28 + 800637a: 2200 movs r2, #0 + 800637c: 2104 movs r1, #4 + 800637e: 68f8 ldr r0, [r7, #12] + 8006380: f000 f964 bl 800664c + 8006384: 4603 mov r3, r0 + 8006386: 2b00 cmp r3, #0 + 8006388: d001 beq.n 800638e + { + return HAL_ERROR; + 800638a: 2301 movs r3, #1 + 800638c: e07c b.n 8006488 + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 800638e: 68fb ldr r3, [r7, #12] + 8006390: 681b ldr r3, [r3, #0] + 8006392: 6a5a ldr r2, [r3, #36] ; 0x24 + 8006394: 68fb ldr r3, [r7, #12] + 8006396: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006398: b2d2 uxtb r2, r2 + 800639a: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 800639c: 68fb ldr r3, [r7, #12] + 800639e: 6a5b ldr r3, [r3, #36] ; 0x24 + 80063a0: 1c5a adds r2, r3, #1 + 80063a2: 68fb ldr r3, [r7, #12] + 80063a4: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 80063a6: 68fb ldr r3, [r7, #12] + 80063a8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80063aa: 3b01 subs r3, #1 + 80063ac: b29a uxth r2, r3 + 80063ae: 68fb ldr r3, [r7, #12] + 80063b0: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 80063b2: 68fb ldr r3, [r7, #12] + 80063b4: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80063b6: b29b uxth r3, r3 + 80063b8: 3b01 subs r3, #1 + 80063ba: b29a uxth r2, r3 + 80063bc: 68fb ldr r3, [r7, #12] + 80063be: 855a strh r2, [r3, #42] ; 0x2a + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 80063c0: 68fb ldr r3, [r7, #12] + 80063c2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80063c4: b29b uxth r3, r3 + 80063c6: 2b00 cmp r3, #0 + 80063c8: d034 beq.n 8006434 + 80063ca: 68fb ldr r3, [r7, #12] + 80063cc: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80063ce: 2b00 cmp r3, #0 + 80063d0: d130 bne.n 8006434 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 80063d2: 697b ldr r3, [r7, #20] + 80063d4: 9300 str r3, [sp, #0] + 80063d6: 6abb ldr r3, [r7, #40] ; 0x28 + 80063d8: 2200 movs r2, #0 + 80063da: 2180 movs r1, #128 ; 0x80 + 80063dc: 68f8 ldr r0, [r7, #12] + 80063de: f000 f935 bl 800664c + 80063e2: 4603 mov r3, r0 + 80063e4: 2b00 cmp r3, #0 + 80063e6: d001 beq.n 80063ec + { + return HAL_ERROR; + 80063e8: 2301 movs r3, #1 + 80063ea: e04d b.n 8006488 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 80063ec: 68fb ldr r3, [r7, #12] + 80063ee: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80063f0: b29b uxth r3, r3 + 80063f2: 2bff cmp r3, #255 ; 0xff + 80063f4: d90e bls.n 8006414 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 80063f6: 68fb ldr r3, [r7, #12] + 80063f8: 22ff movs r2, #255 ; 0xff + 80063fa: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 80063fc: 68fb ldr r3, [r7, #12] + 80063fe: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006400: b2da uxtb r2, r3 + 8006402: 8979 ldrh r1, [r7, #10] + 8006404: 2300 movs r3, #0 + 8006406: 9300 str r3, [sp, #0] + 8006408: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 800640c: 68f8 ldr r0, [r7, #12] + 800640e: f000 fa3f bl 8006890 + 8006412: e00f b.n 8006434 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8006414: 68fb ldr r3, [r7, #12] + 8006416: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006418: b29a uxth r2, r3 + 800641a: 68fb ldr r3, [r7, #12] + 800641c: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 800641e: 68fb ldr r3, [r7, #12] + 8006420: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8006422: b2da uxtb r2, r3 + 8006424: 8979 ldrh r1, [r7, #10] + 8006426: 2300 movs r3, #0 + 8006428: 9300 str r3, [sp, #0] + 800642a: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 800642e: 68f8 ldr r0, [r7, #12] + 8006430: f000 fa2e bl 8006890 + } + } + } + while (hi2c->XferCount > 0U); + 8006434: 68fb ldr r3, [r7, #12] + 8006436: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8006438: b29b uxth r3, r3 + 800643a: 2b00 cmp r3, #0 + 800643c: d19a bne.n 8006374 + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 800643e: 697a ldr r2, [r7, #20] + 8006440: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8006442: 68f8 ldr r0, [r7, #12] + 8006444: f000 f982 bl 800674c + 8006448: 4603 mov r3, r0 + 800644a: 2b00 cmp r3, #0 + 800644c: d001 beq.n 8006452 + { + return HAL_ERROR; + 800644e: 2301 movs r3, #1 + 8006450: e01a b.n 8006488 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8006452: 68fb ldr r3, [r7, #12] + 8006454: 681b ldr r3, [r3, #0] + 8006456: 2220 movs r2, #32 + 8006458: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 800645a: 68fb ldr r3, [r7, #12] + 800645c: 681b ldr r3, [r3, #0] + 800645e: 6859 ldr r1, [r3, #4] + 8006460: 68fb ldr r3, [r7, #12] + 8006462: 681a ldr r2, [r3, #0] + 8006464: 4b0b ldr r3, [pc, #44] ; (8006494 ) + 8006466: 400b ands r3, r1 + 8006468: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 800646a: 68fb ldr r3, [r7, #12] + 800646c: 2220 movs r2, #32 + 800646e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006472: 68fb ldr r3, [r7, #12] + 8006474: 2200 movs r2, #0 + 8006476: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800647a: 68fb ldr r3, [r7, #12] + 800647c: 2200 movs r2, #0 + 800647e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006482: 2300 movs r3, #0 + 8006484: e000 b.n 8006488 + } + else + { + return HAL_BUSY; + 8006486: 2302 movs r3, #2 + } +} + 8006488: 4618 mov r0, r3 + 800648a: 3718 adds r7, #24 + 800648c: 46bd mov sp, r7 + 800648e: bd80 pop {r7, pc} + 8006490: 80002400 .word 0x80002400 + 8006494: fe00e800 .word 0xfe00e800 + +08006498 : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + 8006498: b480 push {r7} + 800649a: b083 sub sp, #12 + 800649c: af00 add r7, sp, #0 + 800649e: 6078 str r0, [r7, #4] + /* Return I2C handle state */ + return hi2c->State; + 80064a0: 687b ldr r3, [r7, #4] + 80064a2: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 80064a6: b2db uxtb r3, r3 +} + 80064a8: 4618 mov r0, r3 + 80064aa: 370c adds r7, #12 + 80064ac: 46bd mov sp, r7 + 80064ae: f85d 7b04 ldr.w r7, [sp], #4 + 80064b2: 4770 bx lr + +080064b4 : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + 80064b4: b580 push {r7, lr} + 80064b6: b086 sub sp, #24 + 80064b8: af02 add r7, sp, #8 + 80064ba: 60f8 str r0, [r7, #12] + 80064bc: 4608 mov r0, r1 + 80064be: 4611 mov r1, r2 + 80064c0: 461a mov r2, r3 + 80064c2: 4603 mov r3, r0 + 80064c4: 817b strh r3, [r7, #10] + 80064c6: 460b mov r3, r1 + 80064c8: 813b strh r3, [r7, #8] + 80064ca: 4613 mov r3, r2 + 80064cc: 80fb strh r3, [r7, #6] + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + 80064ce: 88fb ldrh r3, [r7, #6] + 80064d0: b2da uxtb r2, r3 + 80064d2: 8979 ldrh r1, [r7, #10] + 80064d4: 4b20 ldr r3, [pc, #128] ; (8006558 ) + 80064d6: 9300 str r3, [sp, #0] + 80064d8: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 80064dc: 68f8 ldr r0, [r7, #12] + 80064de: f000 f9d7 bl 8006890 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 80064e2: 69fa ldr r2, [r7, #28] + 80064e4: 69b9 ldr r1, [r7, #24] + 80064e6: 68f8 ldr r0, [r7, #12] + 80064e8: f000 f8f0 bl 80066cc + 80064ec: 4603 mov r3, r0 + 80064ee: 2b00 cmp r3, #0 + 80064f0: d001 beq.n 80064f6 + { + return HAL_ERROR; + 80064f2: 2301 movs r3, #1 + 80064f4: e02c b.n 8006550 + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 80064f6: 88fb ldrh r3, [r7, #6] + 80064f8: 2b01 cmp r3, #1 + 80064fa: d105 bne.n 8006508 + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 80064fc: 893b ldrh r3, [r7, #8] + 80064fe: b2da uxtb r2, r3 + 8006500: 68fb ldr r3, [r7, #12] + 8006502: 681b ldr r3, [r3, #0] + 8006504: 629a str r2, [r3, #40] ; 0x28 + 8006506: e015 b.n 8006534 + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 8006508: 893b ldrh r3, [r7, #8] + 800650a: 0a1b lsrs r3, r3, #8 + 800650c: b29b uxth r3, r3 + 800650e: b2da uxtb r2, r3 + 8006510: 68fb ldr r3, [r7, #12] + 8006512: 681b ldr r3, [r3, #0] + 8006514: 629a str r2, [r3, #40] ; 0x28 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8006516: 69fa ldr r2, [r7, #28] + 8006518: 69b9 ldr r1, [r7, #24] + 800651a: 68f8 ldr r0, [r7, #12] + 800651c: f000 f8d6 bl 80066cc + 8006520: 4603 mov r3, r0 + 8006522: 2b00 cmp r3, #0 + 8006524: d001 beq.n 800652a + { + return HAL_ERROR; + 8006526: 2301 movs r3, #1 + 8006528: e012 b.n 8006550 + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 800652a: 893b ldrh r3, [r7, #8] + 800652c: b2da uxtb r2, r3 + 800652e: 68fb ldr r3, [r7, #12] + 8006530: 681b ldr r3, [r3, #0] + 8006532: 629a str r2, [r3, #40] ; 0x28 + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + 8006534: 69fb ldr r3, [r7, #28] + 8006536: 9300 str r3, [sp, #0] + 8006538: 69bb ldr r3, [r7, #24] + 800653a: 2200 movs r2, #0 + 800653c: 2180 movs r1, #128 ; 0x80 + 800653e: 68f8 ldr r0, [r7, #12] + 8006540: f000 f884 bl 800664c + 8006544: 4603 mov r3, r0 + 8006546: 2b00 cmp r3, #0 + 8006548: d001 beq.n 800654e + { + return HAL_ERROR; + 800654a: 2301 movs r3, #1 + 800654c: e000 b.n 8006550 + } + + return HAL_OK; + 800654e: 2300 movs r3, #0 +} + 8006550: 4618 mov r0, r3 + 8006552: 3710 adds r7, #16 + 8006554: 46bd mov sp, r7 + 8006556: bd80 pop {r7, pc} + 8006558: 80002000 .word 0x80002000 + +0800655c : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + 800655c: b580 push {r7, lr} + 800655e: b086 sub sp, #24 + 8006560: af02 add r7, sp, #8 + 8006562: 60f8 str r0, [r7, #12] + 8006564: 4608 mov r0, r1 + 8006566: 4611 mov r1, r2 + 8006568: 461a mov r2, r3 + 800656a: 4603 mov r3, r0 + 800656c: 817b strh r3, [r7, #10] + 800656e: 460b mov r3, r1 + 8006570: 813b strh r3, [r7, #8] + 8006572: 4613 mov r3, r2 + 8006574: 80fb strh r3, [r7, #6] + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + 8006576: 88fb ldrh r3, [r7, #6] + 8006578: b2da uxtb r2, r3 + 800657a: 8979 ldrh r1, [r7, #10] + 800657c: 4b20 ldr r3, [pc, #128] ; (8006600 ) + 800657e: 9300 str r3, [sp, #0] + 8006580: 2300 movs r3, #0 + 8006582: 68f8 ldr r0, [r7, #12] + 8006584: f000 f984 bl 8006890 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8006588: 69fa ldr r2, [r7, #28] + 800658a: 69b9 ldr r1, [r7, #24] + 800658c: 68f8 ldr r0, [r7, #12] + 800658e: f000 f89d bl 80066cc + 8006592: 4603 mov r3, r0 + 8006594: 2b00 cmp r3, #0 + 8006596: d001 beq.n 800659c + { + return HAL_ERROR; + 8006598: 2301 movs r3, #1 + 800659a: e02c b.n 80065f6 + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 800659c: 88fb ldrh r3, [r7, #6] + 800659e: 2b01 cmp r3, #1 + 80065a0: d105 bne.n 80065ae + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 80065a2: 893b ldrh r3, [r7, #8] + 80065a4: b2da uxtb r2, r3 + 80065a6: 68fb ldr r3, [r7, #12] + 80065a8: 681b ldr r3, [r3, #0] + 80065aa: 629a str r2, [r3, #40] ; 0x28 + 80065ac: e015 b.n 80065da + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 80065ae: 893b ldrh r3, [r7, #8] + 80065b0: 0a1b lsrs r3, r3, #8 + 80065b2: b29b uxth r3, r3 + 80065b4: b2da uxtb r2, r3 + 80065b6: 68fb ldr r3, [r7, #12] + 80065b8: 681b ldr r3, [r3, #0] + 80065ba: 629a str r2, [r3, #40] ; 0x28 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 80065bc: 69fa ldr r2, [r7, #28] + 80065be: 69b9 ldr r1, [r7, #24] + 80065c0: 68f8 ldr r0, [r7, #12] + 80065c2: f000 f883 bl 80066cc + 80065c6: 4603 mov r3, r0 + 80065c8: 2b00 cmp r3, #0 + 80065ca: d001 beq.n 80065d0 + { + return HAL_ERROR; + 80065cc: 2301 movs r3, #1 + 80065ce: e012 b.n 80065f6 + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 80065d0: 893b ldrh r3, [r7, #8] + 80065d2: b2da uxtb r2, r3 + 80065d4: 68fb ldr r3, [r7, #12] + 80065d6: 681b ldr r3, [r3, #0] + 80065d8: 629a str r2, [r3, #40] ; 0x28 + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + 80065da: 69fb ldr r3, [r7, #28] + 80065dc: 9300 str r3, [sp, #0] + 80065de: 69bb ldr r3, [r7, #24] + 80065e0: 2200 movs r2, #0 + 80065e2: 2140 movs r1, #64 ; 0x40 + 80065e4: 68f8 ldr r0, [r7, #12] + 80065e6: f000 f831 bl 800664c + 80065ea: 4603 mov r3, r0 + 80065ec: 2b00 cmp r3, #0 + 80065ee: d001 beq.n 80065f4 + { + return HAL_ERROR; + 80065f0: 2301 movs r3, #1 + 80065f2: e000 b.n 80065f6 + } + + return HAL_OK; + 80065f4: 2300 movs r3, #0 +} + 80065f6: 4618 mov r0, r3 + 80065f8: 3710 adds r7, #16 + 80065fa: 46bd mov sp, r7 + 80065fc: bd80 pop {r7, pc} + 80065fe: bf00 nop + 8006600: 80002000 .word 0x80002000 + +08006604 : + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + 8006604: b480 push {r7} + 8006606: b083 sub sp, #12 + 8006608: af00 add r7, sp, #0 + 800660a: 6078 str r0, [r7, #4] + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 800660c: 687b ldr r3, [r7, #4] + 800660e: 681b ldr r3, [r3, #0] + 8006610: 699b ldr r3, [r3, #24] + 8006612: f003 0302 and.w r3, r3, #2 + 8006616: 2b02 cmp r3, #2 + 8006618: d103 bne.n 8006622 + { + hi2c->Instance->TXDR = 0x00U; + 800661a: 687b ldr r3, [r7, #4] + 800661c: 681b ldr r3, [r3, #0] + 800661e: 2200 movs r2, #0 + 8006620: 629a str r2, [r3, #40] ; 0x28 + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8006622: 687b ldr r3, [r7, #4] + 8006624: 681b ldr r3, [r3, #0] + 8006626: 699b ldr r3, [r3, #24] + 8006628: f003 0301 and.w r3, r3, #1 + 800662c: 2b01 cmp r3, #1 + 800662e: d007 beq.n 8006640 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 8006630: 687b ldr r3, [r7, #4] + 8006632: 681b ldr r3, [r3, #0] + 8006634: 699a ldr r2, [r3, #24] + 8006636: 687b ldr r3, [r7, #4] + 8006638: 681b ldr r3, [r3, #0] + 800663a: f042 0201 orr.w r2, r2, #1 + 800663e: 619a str r2, [r3, #24] + } +} + 8006640: bf00 nop + 8006642: 370c adds r7, #12 + 8006644: 46bd mov sp, r7 + 8006646: f85d 7b04 ldr.w r7, [sp], #4 + 800664a: 4770 bx lr + +0800664c : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + 800664c: b580 push {r7, lr} + 800664e: b084 sub sp, #16 + 8006650: af00 add r7, sp, #0 + 8006652: 60f8 str r0, [r7, #12] + 8006654: 60b9 str r1, [r7, #8] + 8006656: 603b str r3, [r7, #0] + 8006658: 4613 mov r3, r2 + 800665a: 71fb strb r3, [r7, #7] + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 800665c: e022 b.n 80066a4 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 800665e: 683b ldr r3, [r7, #0] + 8006660: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8006664: d01e beq.n 80066a4 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8006666: f7fd ff43 bl 80044f0 + 800666a: 4602 mov r2, r0 + 800666c: 69bb ldr r3, [r7, #24] + 800666e: 1ad3 subs r3, r2, r3 + 8006670: 683a ldr r2, [r7, #0] + 8006672: 429a cmp r2, r3 + 8006674: d302 bcc.n 800667c + 8006676: 683b ldr r3, [r7, #0] + 8006678: 2b00 cmp r3, #0 + 800667a: d113 bne.n 80066a4 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800667c: 68fb ldr r3, [r7, #12] + 800667e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006680: f043 0220 orr.w r2, r3, #32 + 8006684: 68fb ldr r3, [r7, #12] + 8006686: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8006688: 68fb ldr r3, [r7, #12] + 800668a: 2220 movs r2, #32 + 800668c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006690: 68fb ldr r3, [r7, #12] + 8006692: 2200 movs r2, #0 + 8006694: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006698: 68fb ldr r3, [r7, #12] + 800669a: 2200 movs r2, #0 + 800669c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 80066a0: 2301 movs r3, #1 + 80066a2: e00f b.n 80066c4 + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 80066a4: 68fb ldr r3, [r7, #12] + 80066a6: 681b ldr r3, [r3, #0] + 80066a8: 699a ldr r2, [r3, #24] + 80066aa: 68bb ldr r3, [r7, #8] + 80066ac: 4013 ands r3, r2 + 80066ae: 68ba ldr r2, [r7, #8] + 80066b0: 429a cmp r2, r3 + 80066b2: bf0c ite eq + 80066b4: 2301 moveq r3, #1 + 80066b6: 2300 movne r3, #0 + 80066b8: b2db uxtb r3, r3 + 80066ba: 461a mov r2, r3 + 80066bc: 79fb ldrb r3, [r7, #7] + 80066be: 429a cmp r2, r3 + 80066c0: d0cd beq.n 800665e + } + } + } + return HAL_OK; + 80066c2: 2300 movs r3, #0 +} + 80066c4: 4618 mov r0, r3 + 80066c6: 3710 adds r7, #16 + 80066c8: 46bd mov sp, r7 + 80066ca: bd80 pop {r7, pc} + +080066cc : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 80066cc: b580 push {r7, lr} + 80066ce: b084 sub sp, #16 + 80066d0: af00 add r7, sp, #0 + 80066d2: 60f8 str r0, [r7, #12] + 80066d4: 60b9 str r1, [r7, #8] + 80066d6: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 80066d8: e02c b.n 8006734 + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + 80066da: 687a ldr r2, [r7, #4] + 80066dc: 68b9 ldr r1, [r7, #8] + 80066de: 68f8 ldr r0, [r7, #12] + 80066e0: f000 f870 bl 80067c4 + 80066e4: 4603 mov r3, r0 + 80066e6: 2b00 cmp r3, #0 + 80066e8: d001 beq.n 80066ee + { + return HAL_ERROR; + 80066ea: 2301 movs r3, #1 + 80066ec: e02a b.n 8006744 + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80066ee: 68bb ldr r3, [r7, #8] + 80066f0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80066f4: d01e beq.n 8006734 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80066f6: f7fd fefb bl 80044f0 + 80066fa: 4602 mov r2, r0 + 80066fc: 687b ldr r3, [r7, #4] + 80066fe: 1ad3 subs r3, r2, r3 + 8006700: 68ba ldr r2, [r7, #8] + 8006702: 429a cmp r2, r3 + 8006704: d302 bcc.n 800670c + 8006706: 68bb ldr r3, [r7, #8] + 8006708: 2b00 cmp r3, #0 + 800670a: d113 bne.n 8006734 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800670c: 68fb ldr r3, [r7, #12] + 800670e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006710: f043 0220 orr.w r2, r3, #32 + 8006714: 68fb ldr r3, [r7, #12] + 8006716: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8006718: 68fb ldr r3, [r7, #12] + 800671a: 2220 movs r2, #32 + 800671c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006720: 68fb ldr r3, [r7, #12] + 8006722: 2200 movs r2, #0 + 8006724: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006728: 68fb ldr r3, [r7, #12] + 800672a: 2200 movs r2, #0 + 800672c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8006730: 2301 movs r3, #1 + 8006732: e007 b.n 8006744 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 8006734: 68fb ldr r3, [r7, #12] + 8006736: 681b ldr r3, [r3, #0] + 8006738: 699b ldr r3, [r3, #24] + 800673a: f003 0302 and.w r3, r3, #2 + 800673e: 2b02 cmp r3, #2 + 8006740: d1cb bne.n 80066da + } + } + } + return HAL_OK; + 8006742: 2300 movs r3, #0 +} + 8006744: 4618 mov r0, r3 + 8006746: 3710 adds r7, #16 + 8006748: 46bd mov sp, r7 + 800674a: bd80 pop {r7, pc} + +0800674c : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 800674c: b580 push {r7, lr} + 800674e: b084 sub sp, #16 + 8006750: af00 add r7, sp, #0 + 8006752: 60f8 str r0, [r7, #12] + 8006754: 60b9 str r1, [r7, #8] + 8006756: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8006758: e028 b.n 80067ac + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + 800675a: 687a ldr r2, [r7, #4] + 800675c: 68b9 ldr r1, [r7, #8] + 800675e: 68f8 ldr r0, [r7, #12] + 8006760: f000 f830 bl 80067c4 + 8006764: 4603 mov r3, r0 + 8006766: 2b00 cmp r3, #0 + 8006768: d001 beq.n 800676e + { + return HAL_ERROR; + 800676a: 2301 movs r3, #1 + 800676c: e026 b.n 80067bc + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800676e: f7fd febf bl 80044f0 + 8006772: 4602 mov r2, r0 + 8006774: 687b ldr r3, [r7, #4] + 8006776: 1ad3 subs r3, r2, r3 + 8006778: 68ba ldr r2, [r7, #8] + 800677a: 429a cmp r2, r3 + 800677c: d302 bcc.n 8006784 + 800677e: 68bb ldr r3, [r7, #8] + 8006780: 2b00 cmp r3, #0 + 8006782: d113 bne.n 80067ac + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8006784: 68fb ldr r3, [r7, #12] + 8006786: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006788: f043 0220 orr.w r2, r3, #32 + 800678c: 68fb ldr r3, [r7, #12] + 800678e: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8006790: 68fb ldr r3, [r7, #12] + 8006792: 2220 movs r2, #32 + 8006794: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006798: 68fb ldr r3, [r7, #12] + 800679a: 2200 movs r2, #0 + 800679c: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80067a0: 68fb ldr r3, [r7, #12] + 80067a2: 2200 movs r2, #0 + 80067a4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80067a8: 2301 movs r3, #1 + 80067aa: e007 b.n 80067bc + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 80067ac: 68fb ldr r3, [r7, #12] + 80067ae: 681b ldr r3, [r3, #0] + 80067b0: 699b ldr r3, [r3, #24] + 80067b2: f003 0320 and.w r3, r3, #32 + 80067b6: 2b20 cmp r3, #32 + 80067b8: d1cf bne.n 800675a + } + } + return HAL_OK; + 80067ba: 2300 movs r3, #0 +} + 80067bc: 4618 mov r0, r3 + 80067be: 3710 adds r7, #16 + 80067c0: 46bd mov sp, r7 + 80067c2: bd80 pop {r7, pc} + +080067c4 : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 80067c4: b580 push {r7, lr} + 80067c6: b084 sub sp, #16 + 80067c8: af00 add r7, sp, #0 + 80067ca: 60f8 str r0, [r7, #12] + 80067cc: 60b9 str r1, [r7, #8] + 80067ce: 607a str r2, [r7, #4] + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 80067d0: 68fb ldr r3, [r7, #12] + 80067d2: 681b ldr r3, [r3, #0] + 80067d4: 699b ldr r3, [r3, #24] + 80067d6: f003 0310 and.w r3, r3, #16 + 80067da: 2b10 cmp r3, #16 + 80067dc: d151 bne.n 8006882 + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 80067de: e022 b.n 8006826 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 80067e0: 68bb ldr r3, [r7, #8] + 80067e2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80067e6: d01e beq.n 8006826 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80067e8: f7fd fe82 bl 80044f0 + 80067ec: 4602 mov r2, r0 + 80067ee: 687b ldr r3, [r7, #4] + 80067f0: 1ad3 subs r3, r2, r3 + 80067f2: 68ba ldr r2, [r7, #8] + 80067f4: 429a cmp r2, r3 + 80067f6: d302 bcc.n 80067fe + 80067f8: 68bb ldr r3, [r7, #8] + 80067fa: 2b00 cmp r3, #0 + 80067fc: d113 bne.n 8006826 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 80067fe: 68fb ldr r3, [r7, #12] + 8006800: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006802: f043 0220 orr.w r2, r3, #32 + 8006806: 68fb ldr r3, [r7, #12] + 8006808: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 800680a: 68fb ldr r3, [r7, #12] + 800680c: 2220 movs r2, #32 + 800680e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8006812: 68fb ldr r3, [r7, #12] + 8006814: 2200 movs r2, #0 + 8006816: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800681a: 68fb ldr r3, [r7, #12] + 800681c: 2200 movs r2, #0 + 800681e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8006822: 2301 movs r3, #1 + 8006824: e02e b.n 8006884 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8006826: 68fb ldr r3, [r7, #12] + 8006828: 681b ldr r3, [r3, #0] + 800682a: 699b ldr r3, [r3, #24] + 800682c: f003 0320 and.w r3, r3, #32 + 8006830: 2b20 cmp r3, #32 + 8006832: d1d5 bne.n 80067e0 + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 8006834: 68fb ldr r3, [r7, #12] + 8006836: 681b ldr r3, [r3, #0] + 8006838: 2210 movs r2, #16 + 800683a: 61da str r2, [r3, #28] + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 800683c: 68fb ldr r3, [r7, #12] + 800683e: 681b ldr r3, [r3, #0] + 8006840: 2220 movs r2, #32 + 8006842: 61da str r2, [r3, #28] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 8006844: 68f8 ldr r0, [r7, #12] + 8006846: f7ff fedd bl 8006604 + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 800684a: 68fb ldr r3, [r7, #12] + 800684c: 681b ldr r3, [r3, #0] + 800684e: 6859 ldr r1, [r3, #4] + 8006850: 68fb ldr r3, [r7, #12] + 8006852: 681a ldr r2, [r3, #0] + 8006854: 4b0d ldr r3, [pc, #52] ; (800688c ) + 8006856: 400b ands r3, r1 + 8006858: 6053 str r3, [r2, #4] + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 800685a: 68fb ldr r3, [r7, #12] + 800685c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800685e: f043 0204 orr.w r2, r3, #4 + 8006862: 68fb ldr r3, [r7, #12] + 8006864: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8006866: 68fb ldr r3, [r7, #12] + 8006868: 2220 movs r2, #32 + 800686a: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 800686e: 68fb ldr r3, [r7, #12] + 8006870: 2200 movs r2, #0 + 8006872: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006876: 68fb ldr r3, [r7, #12] + 8006878: 2200 movs r2, #0 + 800687a: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 800687e: 2301 movs r3, #1 + 8006880: e000 b.n 8006884 + } + return HAL_OK; + 8006882: 2300 movs r3, #0 +} + 8006884: 4618 mov r0, r3 + 8006886: 3710 adds r7, #16 + 8006888: 46bd mov sp, r7 + 800688a: bd80 pop {r7, pc} + 800688c: fe00e800 .word 0xfe00e800 + +08006890 : + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + 8006890: b480 push {r7} + 8006892: b085 sub sp, #20 + 8006894: af00 add r7, sp, #0 + 8006896: 60f8 str r0, [r7, #12] + 8006898: 607b str r3, [r7, #4] + 800689a: 460b mov r3, r1 + 800689c: 817b strh r3, [r7, #10] + 800689e: 4613 mov r3, r2 + 80068a0: 727b strb r3, [r7, #9] + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + 80068a2: 68fb ldr r3, [r7, #12] + 80068a4: 681b ldr r3, [r3, #0] + 80068a6: 685a ldr r2, [r3, #4] + 80068a8: 69bb ldr r3, [r7, #24] + 80068aa: 0d5b lsrs r3, r3, #21 + 80068ac: f403 6180 and.w r1, r3, #1024 ; 0x400 + 80068b0: 4b0d ldr r3, [pc, #52] ; (80068e8 ) + 80068b2: 430b orrs r3, r1 + 80068b4: 43db mvns r3, r3 + 80068b6: ea02 0103 and.w r1, r2, r3 + 80068ba: 897b ldrh r3, [r7, #10] + 80068bc: f3c3 0209 ubfx r2, r3, #0, #10 + 80068c0: 7a7b ldrb r3, [r7, #9] + 80068c2: 041b lsls r3, r3, #16 + 80068c4: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 80068c8: 431a orrs r2, r3 + 80068ca: 687b ldr r3, [r7, #4] + 80068cc: 431a orrs r2, r3 + 80068ce: 69bb ldr r3, [r7, #24] + 80068d0: 431a orrs r2, r3 + 80068d2: 68fb ldr r3, [r7, #12] + 80068d4: 681b ldr r3, [r3, #0] + 80068d6: 430a orrs r2, r1 + 80068d8: 605a str r2, [r3, #4] + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} + 80068da: bf00 nop + 80068dc: 3714 adds r7, #20 + 80068de: 46bd mov sp, r7 + 80068e0: f85d 7b04 ldr.w r7, [sp], #4 + 80068e4: 4770 bx lr + 80068e6: bf00 nop + 80068e8: 03ff63ff .word 0x03ff63ff + +080068ec : + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + 80068ec: b480 push {r7} + 80068ee: b083 sub sp, #12 + 80068f0: af00 add r7, sp, #0 + 80068f2: 6078 str r0, [r7, #4] + 80068f4: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 80068f6: 687b ldr r3, [r7, #4] + 80068f8: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 80068fc: b2db uxtb r3, r3 + 80068fe: 2b20 cmp r3, #32 + 8006900: d138 bne.n 8006974 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8006902: 687b ldr r3, [r7, #4] + 8006904: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8006908: 2b01 cmp r3, #1 + 800690a: d101 bne.n 8006910 + 800690c: 2302 movs r3, #2 + 800690e: e032 b.n 8006976 + 8006910: 687b ldr r3, [r7, #4] + 8006912: 2201 movs r2, #1 + 8006914: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 8006918: 687b ldr r3, [r7, #4] + 800691a: 2224 movs r2, #36 ; 0x24 + 800691c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8006920: 687b ldr r3, [r7, #4] + 8006922: 681b ldr r3, [r3, #0] + 8006924: 681a ldr r2, [r3, #0] + 8006926: 687b ldr r3, [r7, #4] + 8006928: 681b ldr r3, [r3, #0] + 800692a: f022 0201 bic.w r2, r2, #1 + 800692e: 601a str r2, [r3, #0] + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 8006930: 687b ldr r3, [r7, #4] + 8006932: 681b ldr r3, [r3, #0] + 8006934: 681a ldr r2, [r3, #0] + 8006936: 687b ldr r3, [r7, #4] + 8006938: 681b ldr r3, [r3, #0] + 800693a: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 800693e: 601a str r2, [r3, #0] + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + 8006940: 687b ldr r3, [r7, #4] + 8006942: 681b ldr r3, [r3, #0] + 8006944: 6819 ldr r1, [r3, #0] + 8006946: 687b ldr r3, [r7, #4] + 8006948: 681b ldr r3, [r3, #0] + 800694a: 683a ldr r2, [r7, #0] + 800694c: 430a orrs r2, r1 + 800694e: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8006950: 687b ldr r3, [r7, #4] + 8006952: 681b ldr r3, [r3, #0] + 8006954: 681a ldr r2, [r3, #0] + 8006956: 687b ldr r3, [r7, #4] + 8006958: 681b ldr r3, [r3, #0] + 800695a: f042 0201 orr.w r2, r2, #1 + 800695e: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8006960: 687b ldr r3, [r7, #4] + 8006962: 2220 movs r2, #32 + 8006964: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006968: 687b ldr r3, [r7, #4] + 800696a: 2200 movs r2, #0 + 800696c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006970: 2300 movs r3, #0 + 8006972: e000 b.n 8006976 + } + else + { + return HAL_BUSY; + 8006974: 2302 movs r3, #2 + } +} + 8006976: 4618 mov r0, r3 + 8006978: 370c adds r7, #12 + 800697a: 46bd mov sp, r7 + 800697c: f85d 7b04 ldr.w r7, [sp], #4 + 8006980: 4770 bx lr + +08006982 : + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + 8006982: b480 push {r7} + 8006984: b085 sub sp, #20 + 8006986: af00 add r7, sp, #0 + 8006988: 6078 str r0, [r7, #4] + 800698a: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 800698c: 687b ldr r3, [r7, #4] + 800698e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8006992: b2db uxtb r3, r3 + 8006994: 2b20 cmp r3, #32 + 8006996: d139 bne.n 8006a0c + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8006998: 687b ldr r3, [r7, #4] + 800699a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 800699e: 2b01 cmp r3, #1 + 80069a0: d101 bne.n 80069a6 + 80069a2: 2302 movs r3, #2 + 80069a4: e033 b.n 8006a0e + 80069a6: 687b ldr r3, [r7, #4] + 80069a8: 2201 movs r2, #1 + 80069aa: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 80069ae: 687b ldr r3, [r7, #4] + 80069b0: 2224 movs r2, #36 ; 0x24 + 80069b2: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80069b6: 687b ldr r3, [r7, #4] + 80069b8: 681b ldr r3, [r3, #0] + 80069ba: 681a ldr r2, [r3, #0] + 80069bc: 687b ldr r3, [r7, #4] + 80069be: 681b ldr r3, [r3, #0] + 80069c0: f022 0201 bic.w r2, r2, #1 + 80069c4: 601a str r2, [r3, #0] + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + 80069c6: 687b ldr r3, [r7, #4] + 80069c8: 681b ldr r3, [r3, #0] + 80069ca: 681b ldr r3, [r3, #0] + 80069cc: 60fb str r3, [r7, #12] + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + 80069ce: 68fb ldr r3, [r7, #12] + 80069d0: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 80069d4: 60fb str r3, [r7, #12] + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + 80069d6: 683b ldr r3, [r7, #0] + 80069d8: 021b lsls r3, r3, #8 + 80069da: 68fa ldr r2, [r7, #12] + 80069dc: 4313 orrs r3, r2 + 80069de: 60fb str r3, [r7, #12] + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + 80069e0: 687b ldr r3, [r7, #4] + 80069e2: 681b ldr r3, [r3, #0] + 80069e4: 68fa ldr r2, [r7, #12] + 80069e6: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 80069e8: 687b ldr r3, [r7, #4] + 80069ea: 681b ldr r3, [r3, #0] + 80069ec: 681a ldr r2, [r3, #0] + 80069ee: 687b ldr r3, [r7, #4] + 80069f0: 681b ldr r3, [r3, #0] + 80069f2: f042 0201 orr.w r2, r2, #1 + 80069f6: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 80069f8: 687b ldr r3, [r7, #4] + 80069fa: 2220 movs r2, #32 + 80069fc: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8006a00: 687b ldr r3, [r7, #4] + 8006a02: 2200 movs r2, #0 + 8006a04: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8006a08: 2300 movs r3, #0 + 8006a0a: e000 b.n 8006a0e + } + else + { + return HAL_BUSY; + 8006a0c: 2302 movs r3, #2 + } +} + 8006a0e: 4618 mov r0, r3 + 8006a10: 3714 adds r7, #20 + 8006a12: 46bd mov sp, r7 + 8006a14: f85d 7b04 ldr.w r7, [sp], #4 + 8006a18: 4770 bx lr + ... + +08006a1c : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + 8006a1c: b580 push {r7, lr} + 8006a1e: b084 sub sp, #16 + 8006a20: af00 add r7, sp, #0 + 8006a22: 6078 str r0, [r7, #4] + uint32_t tmp, tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + 8006a24: 687b ldr r3, [r7, #4] + 8006a26: 2b00 cmp r3, #0 + 8006a28: d101 bne.n 8006a2e + { + return HAL_ERROR; + 8006a2a: 2301 movs r3, #1 + 8006a2c: e0bf b.n 8006bae + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + 8006a2e: 687b ldr r3, [r7, #4] + 8006a30: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1 + 8006a34: b2db uxtb r3, r3 + 8006a36: 2b00 cmp r3, #0 + 8006a38: d106 bne.n 8006a48 + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + 8006a3a: 687b ldr r3, [r7, #4] + 8006a3c: 2200 movs r2, #0 + 8006a3e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + 8006a42: 6878 ldr r0, [r7, #4] + 8006a44: f7fd f8b8 bl 8003bb8 + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + 8006a48: 687b ldr r3, [r7, #4] + 8006a4a: 2202 movs r2, #2 + 8006a4c: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + 8006a50: 687b ldr r3, [r7, #4] + 8006a52: 681b ldr r3, [r3, #0] + 8006a54: 699a ldr r2, [r3, #24] + 8006a56: 687b ldr r3, [r7, #4] + 8006a58: 681b ldr r3, [r3, #0] + 8006a5a: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000 + 8006a5e: 619a str r2, [r3, #24] + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8006a60: 687b ldr r3, [r7, #4] + 8006a62: 681b ldr r3, [r3, #0] + 8006a64: 6999 ldr r1, [r3, #24] + 8006a66: 687b ldr r3, [r7, #4] + 8006a68: 685a ldr r2, [r3, #4] + 8006a6a: 687b ldr r3, [r7, #4] + 8006a6c: 689b ldr r3, [r3, #8] + 8006a6e: 431a orrs r2, r3 + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + 8006a70: 687b ldr r3, [r7, #4] + 8006a72: 68db ldr r3, [r3, #12] + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8006a74: 431a orrs r2, r3 + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + 8006a76: 687b ldr r3, [r7, #4] + 8006a78: 691b ldr r3, [r3, #16] + 8006a7a: 431a orrs r2, r3 + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + 8006a7c: 687b ldr r3, [r7, #4] + 8006a7e: 681b ldr r3, [r3, #0] + 8006a80: 430a orrs r2, r1 + 8006a82: 619a str r2, [r3, #24] + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + 8006a84: 687b ldr r3, [r7, #4] + 8006a86: 681b ldr r3, [r3, #0] + 8006a88: 6899 ldr r1, [r3, #8] + 8006a8a: 687b ldr r3, [r7, #4] + 8006a8c: 681a ldr r2, [r3, #0] + 8006a8e: 4b4a ldr r3, [pc, #296] ; (8006bb8 ) + 8006a90: 400b ands r3, r1 + 8006a92: 6093 str r3, [r2, #8] + tmp = (hltdc->Init.HorizontalSync << 16U); + 8006a94: 687b ldr r3, [r7, #4] + 8006a96: 695b ldr r3, [r3, #20] + 8006a98: 041b lsls r3, r3, #16 + 8006a9a: 60fb str r3, [r7, #12] + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + 8006a9c: 687b ldr r3, [r7, #4] + 8006a9e: 681b ldr r3, [r3, #0] + 8006aa0: 6899 ldr r1, [r3, #8] + 8006aa2: 687b ldr r3, [r7, #4] + 8006aa4: 699a ldr r2, [r3, #24] + 8006aa6: 68fb ldr r3, [r7, #12] + 8006aa8: 431a orrs r2, r3 + 8006aaa: 687b ldr r3, [r7, #4] + 8006aac: 681b ldr r3, [r3, #0] + 8006aae: 430a orrs r2, r1 + 8006ab0: 609a str r2, [r3, #8] + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + 8006ab2: 687b ldr r3, [r7, #4] + 8006ab4: 681b ldr r3, [r3, #0] + 8006ab6: 68d9 ldr r1, [r3, #12] + 8006ab8: 687b ldr r3, [r7, #4] + 8006aba: 681a ldr r2, [r3, #0] + 8006abc: 4b3e ldr r3, [pc, #248] ; (8006bb8 ) + 8006abe: 400b ands r3, r1 + 8006ac0: 60d3 str r3, [r2, #12] + tmp = (hltdc->Init.AccumulatedHBP << 16U); + 8006ac2: 687b ldr r3, [r7, #4] + 8006ac4: 69db ldr r3, [r3, #28] + 8006ac6: 041b lsls r3, r3, #16 + 8006ac8: 60fb str r3, [r7, #12] + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + 8006aca: 687b ldr r3, [r7, #4] + 8006acc: 681b ldr r3, [r3, #0] + 8006ace: 68d9 ldr r1, [r3, #12] + 8006ad0: 687b ldr r3, [r7, #4] + 8006ad2: 6a1a ldr r2, [r3, #32] + 8006ad4: 68fb ldr r3, [r7, #12] + 8006ad6: 431a orrs r2, r3 + 8006ad8: 687b ldr r3, [r7, #4] + 8006ada: 681b ldr r3, [r3, #0] + 8006adc: 430a orrs r2, r1 + 8006ade: 60da str r2, [r3, #12] + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + 8006ae0: 687b ldr r3, [r7, #4] + 8006ae2: 681b ldr r3, [r3, #0] + 8006ae4: 6919 ldr r1, [r3, #16] + 8006ae6: 687b ldr r3, [r7, #4] + 8006ae8: 681a ldr r2, [r3, #0] + 8006aea: 4b33 ldr r3, [pc, #204] ; (8006bb8 ) + 8006aec: 400b ands r3, r1 + 8006aee: 6113 str r3, [r2, #16] + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + 8006af0: 687b ldr r3, [r7, #4] + 8006af2: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006af4: 041b lsls r3, r3, #16 + 8006af6: 60fb str r3, [r7, #12] + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + 8006af8: 687b ldr r3, [r7, #4] + 8006afa: 681b ldr r3, [r3, #0] + 8006afc: 6919 ldr r1, [r3, #16] + 8006afe: 687b ldr r3, [r7, #4] + 8006b00: 6a9a ldr r2, [r3, #40] ; 0x28 + 8006b02: 68fb ldr r3, [r7, #12] + 8006b04: 431a orrs r2, r3 + 8006b06: 687b ldr r3, [r7, #4] + 8006b08: 681b ldr r3, [r3, #0] + 8006b0a: 430a orrs r2, r1 + 8006b0c: 611a str r2, [r3, #16] + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + 8006b0e: 687b ldr r3, [r7, #4] + 8006b10: 681b ldr r3, [r3, #0] + 8006b12: 6959 ldr r1, [r3, #20] + 8006b14: 687b ldr r3, [r7, #4] + 8006b16: 681a ldr r2, [r3, #0] + 8006b18: 4b27 ldr r3, [pc, #156] ; (8006bb8 ) + 8006b1a: 400b ands r3, r1 + 8006b1c: 6153 str r3, [r2, #20] + tmp = (hltdc->Init.TotalWidth << 16U); + 8006b1e: 687b ldr r3, [r7, #4] + 8006b20: 6adb ldr r3, [r3, #44] ; 0x2c + 8006b22: 041b lsls r3, r3, #16 + 8006b24: 60fb str r3, [r7, #12] + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + 8006b26: 687b ldr r3, [r7, #4] + 8006b28: 681b ldr r3, [r3, #0] + 8006b2a: 6959 ldr r1, [r3, #20] + 8006b2c: 687b ldr r3, [r7, #4] + 8006b2e: 6b1a ldr r2, [r3, #48] ; 0x30 + 8006b30: 68fb ldr r3, [r7, #12] + 8006b32: 431a orrs r2, r3 + 8006b34: 687b ldr r3, [r7, #4] + 8006b36: 681b ldr r3, [r3, #0] + 8006b38: 430a orrs r2, r1 + 8006b3a: 615a str r2, [r3, #20] + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + 8006b3c: 687b ldr r3, [r7, #4] + 8006b3e: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 + 8006b42: 021b lsls r3, r3, #8 + 8006b44: 60fb str r3, [r7, #12] + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + 8006b46: 687b ldr r3, [r7, #4] + 8006b48: f893 3036 ldrb.w r3, [r3, #54] ; 0x36 + 8006b4c: 041b lsls r3, r3, #16 + 8006b4e: 60bb str r3, [r7, #8] + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + 8006b50: 687b ldr r3, [r7, #4] + 8006b52: 681b ldr r3, [r3, #0] + 8006b54: 6ada ldr r2, [r3, #44] ; 0x2c + 8006b56: 687b ldr r3, [r7, #4] + 8006b58: 681b ldr r3, [r3, #0] + 8006b5a: f002 427f and.w r2, r2, #4278190080 ; 0xff000000 + 8006b5e: 62da str r2, [r3, #44] ; 0x2c + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + 8006b60: 687b ldr r3, [r7, #4] + 8006b62: 681b ldr r3, [r3, #0] + 8006b64: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8006b66: 68ba ldr r2, [r7, #8] + 8006b68: 68fb ldr r3, [r7, #12] + 8006b6a: 4313 orrs r3, r2 + 8006b6c: 687a ldr r2, [r7, #4] + 8006b6e: f892 2034 ldrb.w r2, [r2, #52] ; 0x34 + 8006b72: 431a orrs r2, r3 + 8006b74: 687b ldr r3, [r7, #4] + 8006b76: 681b ldr r3, [r3, #0] + 8006b78: 430a orrs r2, r1 + 8006b7a: 62da str r2, [r3, #44] ; 0x2c + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + 8006b7c: 687b ldr r3, [r7, #4] + 8006b7e: 681b ldr r3, [r3, #0] + 8006b80: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006b82: 687b ldr r3, [r7, #4] + 8006b84: 681b ldr r3, [r3, #0] + 8006b86: f042 0206 orr.w r2, r2, #6 + 8006b8a: 635a str r2, [r3, #52] ; 0x34 + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + 8006b8c: 687b ldr r3, [r7, #4] + 8006b8e: 681b ldr r3, [r3, #0] + 8006b90: 699a ldr r2, [r3, #24] + 8006b92: 687b ldr r3, [r7, #4] + 8006b94: 681b ldr r3, [r3, #0] + 8006b96: f042 0201 orr.w r2, r2, #1 + 8006b9a: 619a str r2, [r3, #24] + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + 8006b9c: 687b ldr r3, [r7, #4] + 8006b9e: 2200 movs r2, #0 + 8006ba0: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + 8006ba4: 687b ldr r3, [r7, #4] + 8006ba6: 2201 movs r2, #1 + 8006ba8: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + return HAL_OK; + 8006bac: 2300 movs r3, #0 +} + 8006bae: 4618 mov r0, r3 + 8006bb0: 3710 adds r7, #16 + 8006bb2: 46bd mov sp, r7 + 8006bb4: bd80 pop {r7, pc} + 8006bb6: bf00 nop + 8006bb8: f000f800 .word 0xf000f800 + +08006bbc : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + 8006bbc: b580 push {r7, lr} + 8006bbe: b084 sub sp, #16 + 8006bc0: af00 add r7, sp, #0 + 8006bc2: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + 8006bc4: 687b ldr r3, [r7, #4] + 8006bc6: 681b ldr r3, [r3, #0] + 8006bc8: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006bca: 60fb str r3, [r7, #12] + uint32_t itsources = READ_REG(hltdc->Instance->IER); + 8006bcc: 687b ldr r3, [r7, #4] + 8006bce: 681b ldr r3, [r3, #0] + 8006bd0: 6b5b ldr r3, [r3, #52] ; 0x34 + 8006bd2: 60bb str r3, [r7, #8] + + /* Transfer Error Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) + 8006bd4: 68fb ldr r3, [r7, #12] + 8006bd6: f003 0304 and.w r3, r3, #4 + 8006bda: 2b00 cmp r3, #0 + 8006bdc: d023 beq.n 8006c26 + 8006bde: 68bb ldr r3, [r7, #8] + 8006be0: f003 0304 and.w r3, r3, #4 + 8006be4: 2b00 cmp r3, #0 + 8006be6: d01e beq.n 8006c26 + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + 8006be8: 687b ldr r3, [r7, #4] + 8006bea: 681b ldr r3, [r3, #0] + 8006bec: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006bee: 687b ldr r3, [r7, #4] + 8006bf0: 681b ldr r3, [r3, #0] + 8006bf2: f022 0204 bic.w r2, r2, #4 + 8006bf6: 635a str r2, [r3, #52] ; 0x34 + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + 8006bf8: 687b ldr r3, [r7, #4] + 8006bfa: 681b ldr r3, [r3, #0] + 8006bfc: 2204 movs r2, #4 + 8006bfe: 63da str r2, [r3, #60] ; 0x3c + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + 8006c00: 687b ldr r3, [r7, #4] + 8006c02: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 + 8006c06: f043 0201 orr.w r2, r3, #1 + 8006c0a: 687b ldr r3, [r7, #4] + 8006c0c: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + 8006c10: 687b ldr r3, [r7, #4] + 8006c12: 2204 movs r2, #4 + 8006c14: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 8006c18: 687b ldr r3, [r7, #4] + 8006c1a: 2200 movs r2, #0 + 8006c1c: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); + 8006c20: 6878 ldr r0, [r7, #4] + 8006c22: f000 f86f bl 8006d04 +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* FIFO underrun Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) + 8006c26: 68fb ldr r3, [r7, #12] + 8006c28: f003 0302 and.w r3, r3, #2 + 8006c2c: 2b00 cmp r3, #0 + 8006c2e: d023 beq.n 8006c78 + 8006c30: 68bb ldr r3, [r7, #8] + 8006c32: f003 0302 and.w r3, r3, #2 + 8006c36: 2b00 cmp r3, #0 + 8006c38: d01e beq.n 8006c78 + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + 8006c3a: 687b ldr r3, [r7, #4] + 8006c3c: 681b ldr r3, [r3, #0] + 8006c3e: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006c40: 687b ldr r3, [r7, #4] + 8006c42: 681b ldr r3, [r3, #0] + 8006c44: f022 0202 bic.w r2, r2, #2 + 8006c48: 635a str r2, [r3, #52] ; 0x34 + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + 8006c4a: 687b ldr r3, [r7, #4] + 8006c4c: 681b ldr r3, [r3, #0] + 8006c4e: 2202 movs r2, #2 + 8006c50: 63da str r2, [r3, #60] ; 0x3c + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + 8006c52: 687b ldr r3, [r7, #4] + 8006c54: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 + 8006c58: f043 0202 orr.w r2, r3, #2 + 8006c5c: 687b ldr r3, [r7, #4] + 8006c5e: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + 8006c62: 687b ldr r3, [r7, #4] + 8006c64: 2204 movs r2, #4 + 8006c66: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 8006c6a: 687b ldr r3, [r7, #4] + 8006c6c: 2200 movs r2, #0 + 8006c6e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); + 8006c72: 6878 ldr r0, [r7, #4] + 8006c74: f000 f846 bl 8006d04 +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Line Interrupt management ************************************************/ + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) + 8006c78: 68fb ldr r3, [r7, #12] + 8006c7a: f003 0301 and.w r3, r3, #1 + 8006c7e: 2b00 cmp r3, #0 + 8006c80: d01b beq.n 8006cba + 8006c82: 68bb ldr r3, [r7, #8] + 8006c84: f003 0301 and.w r3, r3, #1 + 8006c88: 2b00 cmp r3, #0 + 8006c8a: d016 beq.n 8006cba + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + 8006c8c: 687b ldr r3, [r7, #4] + 8006c8e: 681b ldr r3, [r3, #0] + 8006c90: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006c92: 687b ldr r3, [r7, #4] + 8006c94: 681b ldr r3, [r3, #0] + 8006c96: f022 0201 bic.w r2, r2, #1 + 8006c9a: 635a str r2, [r3, #52] ; 0x34 + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + 8006c9c: 687b ldr r3, [r7, #4] + 8006c9e: 681b ldr r3, [r3, #0] + 8006ca0: 2201 movs r2, #1 + 8006ca2: 63da str r2, [r3, #60] ; 0x3c + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + 8006ca4: 687b ldr r3, [r7, #4] + 8006ca6: 2201 movs r2, #1 + 8006ca8: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 8006cac: 687b ldr r3, [r7, #4] + 8006cae: 2200 movs r2, #0 + 8006cb0: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ + HAL_LTDC_LineEventCallback(hltdc); + 8006cb4: 6878 ldr r0, [r7, #4] + 8006cb6: f000 f82f bl 8006d18 +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Register reload Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) + 8006cba: 68fb ldr r3, [r7, #12] + 8006cbc: f003 0308 and.w r3, r3, #8 + 8006cc0: 2b00 cmp r3, #0 + 8006cc2: d01b beq.n 8006cfc + 8006cc4: 68bb ldr r3, [r7, #8] + 8006cc6: f003 0308 and.w r3, r3, #8 + 8006cca: 2b00 cmp r3, #0 + 8006ccc: d016 beq.n 8006cfc + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + 8006cce: 687b ldr r3, [r7, #4] + 8006cd0: 681b ldr r3, [r3, #0] + 8006cd2: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006cd4: 687b ldr r3, [r7, #4] + 8006cd6: 681b ldr r3, [r3, #0] + 8006cd8: f022 0208 bic.w r2, r2, #8 + 8006cdc: 635a str r2, [r3, #52] ; 0x34 + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + 8006cde: 687b ldr r3, [r7, #4] + 8006ce0: 681b ldr r3, [r3, #0] + 8006ce2: 2208 movs r2, #8 + 8006ce4: 63da str r2, [r3, #60] ; 0x3c + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + 8006ce6: 687b ldr r3, [r7, #4] + 8006ce8: 2201 movs r2, #1 + 8006cea: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 8006cee: 687b ldr r3, [r7, #4] + 8006cf0: 2200 movs r2, #0 + 8006cf2: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ + HAL_LTDC_ReloadEventCallback(hltdc); + 8006cf6: 6878 ldr r0, [r7, #4] + 8006cf8: f000 f818 bl 8006d2c +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } +} + 8006cfc: bf00 nop + 8006cfe: 3710 adds r7, #16 + 8006d00: 46bd mov sp, r7 + 8006d02: bd80 pop {r7, pc} + +08006d04 : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + 8006d04: b480 push {r7} + 8006d06: b083 sub sp, #12 + 8006d08: af00 add r7, sp, #0 + 8006d0a: 6078 str r0, [r7, #4] + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + 8006d0c: bf00 nop + 8006d0e: 370c adds r7, #12 + 8006d10: 46bd mov sp, r7 + 8006d12: f85d 7b04 ldr.w r7, [sp], #4 + 8006d16: 4770 bx lr + +08006d18 : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + 8006d18: b480 push {r7} + 8006d1a: b083 sub sp, #12 + 8006d1c: af00 add r7, sp, #0 + 8006d1e: 6078 str r0, [r7, #4] + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + 8006d20: bf00 nop + 8006d22: 370c adds r7, #12 + 8006d24: 46bd mov sp, r7 + 8006d26: f85d 7b04 ldr.w r7, [sp], #4 + 8006d2a: 4770 bx lr + +08006d2c : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + 8006d2c: b480 push {r7} + 8006d2e: b083 sub sp, #12 + 8006d30: af00 add r7, sp, #0 + 8006d32: 6078 str r0, [r7, #4] + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + 8006d34: bf00 nop + 8006d36: 370c adds r7, #12 + 8006d38: 46bd mov sp, r7 + 8006d3a: f85d 7b04 ldr.w r7, [sp], #4 + 8006d3e: 4770 bx lr + +08006d40 : + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + 8006d40: b5b0 push {r4, r5, r7, lr} + 8006d42: b084 sub sp, #16 + 8006d44: af00 add r7, sp, #0 + 8006d46: 60f8 str r0, [r7, #12] + 8006d48: 60b9 str r1, [r7, #8] + 8006d4a: 607a str r2, [r7, #4] + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + 8006d4c: 68fb ldr r3, [r7, #12] + 8006d4e: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0 + 8006d52: 2b01 cmp r3, #1 + 8006d54: d101 bne.n 8006d5a + 8006d56: 2302 movs r3, #2 + 8006d58: e02c b.n 8006db4 + 8006d5a: 68fb ldr r3, [r7, #12] + 8006d5c: 2201 movs r2, #1 + 8006d5e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + 8006d62: 68fb ldr r3, [r7, #12] + 8006d64: 2202 movs r2, #2 + 8006d66: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + 8006d6a: 68fa ldr r2, [r7, #12] + 8006d6c: 687b ldr r3, [r7, #4] + 8006d6e: 2134 movs r1, #52 ; 0x34 + 8006d70: fb01 f303 mul.w r3, r1, r3 + 8006d74: 4413 add r3, r2 + 8006d76: f103 0238 add.w r2, r3, #56 ; 0x38 + 8006d7a: 68bb ldr r3, [r7, #8] + 8006d7c: 4614 mov r4, r2 + 8006d7e: 461d mov r5, r3 + 8006d80: cd0f ldmia r5!, {r0, r1, r2, r3} + 8006d82: c40f stmia r4!, {r0, r1, r2, r3} + 8006d84: cd0f ldmia r5!, {r0, r1, r2, r3} + 8006d86: c40f stmia r4!, {r0, r1, r2, r3} + 8006d88: cd0f ldmia r5!, {r0, r1, r2, r3} + 8006d8a: c40f stmia r4!, {r0, r1, r2, r3} + 8006d8c: 682b ldr r3, [r5, #0] + 8006d8e: 6023 str r3, [r4, #0] + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + 8006d90: 687a ldr r2, [r7, #4] + 8006d92: 68b9 ldr r1, [r7, #8] + 8006d94: 68f8 ldr r0, [r7, #12] + 8006d96: f000 f81f bl 8006dd8 + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + 8006d9a: 68fb ldr r3, [r7, #12] + 8006d9c: 681b ldr r3, [r3, #0] + 8006d9e: 2201 movs r2, #1 + 8006da0: 625a str r2, [r3, #36] ; 0x24 + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + 8006da2: 68fb ldr r3, [r7, #12] + 8006da4: 2201 movs r2, #1 + 8006da6: f883 20a1 strb.w r2, [r3, #161] ; 0xa1 + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + 8006daa: 68fb ldr r3, [r7, #12] + 8006dac: 2200 movs r2, #0 + 8006dae: f883 20a0 strb.w r2, [r3, #160] ; 0xa0 + + return HAL_OK; + 8006db2: 2300 movs r3, #0 +} + 8006db4: 4618 mov r0, r3 + 8006db6: 3710 adds r7, #16 + 8006db8: 46bd mov sp, r7 + 8006dba: bdb0 pop {r4, r5, r7, pc} + +08006dbc : + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + 8006dbc: b480 push {r7} + 8006dbe: b083 sub sp, #12 + 8006dc0: af00 add r7, sp, #0 + 8006dc2: 6078 str r0, [r7, #4] + return hltdc->State; + 8006dc4: 687b ldr r3, [r7, #4] + 8006dc6: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1 + 8006dca: b2db uxtb r3, r3 +} + 8006dcc: 4618 mov r0, r3 + 8006dce: 370c adds r7, #12 + 8006dd0: 46bd mov sp, r7 + 8006dd2: f85d 7b04 ldr.w r7, [sp], #4 + 8006dd6: 4770 bx lr + +08006dd8 : + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + 8006dd8: b480 push {r7} + 8006dda: b089 sub sp, #36 ; 0x24 + 8006ddc: af00 add r7, sp, #0 + 8006dde: 60f8 str r0, [r7, #12] + 8006de0: 60b9 str r1, [r7, #8] + 8006de2: 607a str r2, [r7, #4] + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + 8006de4: 68bb ldr r3, [r7, #8] + 8006de6: 685a ldr r2, [r3, #4] + 8006de8: 68fb ldr r3, [r7, #12] + 8006dea: 681b ldr r3, [r3, #0] + 8006dec: 68db ldr r3, [r3, #12] + 8006dee: 0c1b lsrs r3, r3, #16 + 8006df0: f3c3 030b ubfx r3, r3, #0, #12 + 8006df4: 4413 add r3, r2 + 8006df6: 041b lsls r3, r3, #16 + 8006df8: 61fb str r3, [r7, #28] + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + 8006dfa: 68fb ldr r3, [r7, #12] + 8006dfc: 681b ldr r3, [r3, #0] + 8006dfe: 461a mov r2, r3 + 8006e00: 687b ldr r3, [r7, #4] + 8006e02: 01db lsls r3, r3, #7 + 8006e04: 4413 add r3, r2 + 8006e06: 3384 adds r3, #132 ; 0x84 + 8006e08: 685b ldr r3, [r3, #4] + 8006e0a: 68fa ldr r2, [r7, #12] + 8006e0c: 6812 ldr r2, [r2, #0] + 8006e0e: 4611 mov r1, r2 + 8006e10: 687a ldr r2, [r7, #4] + 8006e12: 01d2 lsls r2, r2, #7 + 8006e14: 440a add r2, r1 + 8006e16: 3284 adds r2, #132 ; 0x84 + 8006e18: f403 4370 and.w r3, r3, #61440 ; 0xf000 + 8006e1c: 6053 str r3, [r2, #4] + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + 8006e1e: 68bb ldr r3, [r7, #8] + 8006e20: 681a ldr r2, [r3, #0] + 8006e22: 68fb ldr r3, [r7, #12] + 8006e24: 681b ldr r3, [r3, #0] + 8006e26: 68db ldr r3, [r3, #12] + 8006e28: 0c1b lsrs r3, r3, #16 + 8006e2a: f3c3 030b ubfx r3, r3, #0, #12 + 8006e2e: 4413 add r3, r2 + 8006e30: 1c5a adds r2, r3, #1 + 8006e32: 68fb ldr r3, [r7, #12] + 8006e34: 681b ldr r3, [r3, #0] + 8006e36: 4619 mov r1, r3 + 8006e38: 687b ldr r3, [r7, #4] + 8006e3a: 01db lsls r3, r3, #7 + 8006e3c: 440b add r3, r1 + 8006e3e: 3384 adds r3, #132 ; 0x84 + 8006e40: 4619 mov r1, r3 + 8006e42: 69fb ldr r3, [r7, #28] + 8006e44: 4313 orrs r3, r2 + 8006e46: 604b str r3, [r1, #4] + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + 8006e48: 68bb ldr r3, [r7, #8] + 8006e4a: 68da ldr r2, [r3, #12] + 8006e4c: 68fb ldr r3, [r7, #12] + 8006e4e: 681b ldr r3, [r3, #0] + 8006e50: 68db ldr r3, [r3, #12] + 8006e52: f3c3 030a ubfx r3, r3, #0, #11 + 8006e56: 4413 add r3, r2 + 8006e58: 041b lsls r3, r3, #16 + 8006e5a: 61fb str r3, [r7, #28] + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + 8006e5c: 68fb ldr r3, [r7, #12] + 8006e5e: 681b ldr r3, [r3, #0] + 8006e60: 461a mov r2, r3 + 8006e62: 687b ldr r3, [r7, #4] + 8006e64: 01db lsls r3, r3, #7 + 8006e66: 4413 add r3, r2 + 8006e68: 3384 adds r3, #132 ; 0x84 + 8006e6a: 689b ldr r3, [r3, #8] + 8006e6c: 68fa ldr r2, [r7, #12] + 8006e6e: 6812 ldr r2, [r2, #0] + 8006e70: 4611 mov r1, r2 + 8006e72: 687a ldr r2, [r7, #4] + 8006e74: 01d2 lsls r2, r2, #7 + 8006e76: 440a add r2, r1 + 8006e78: 3284 adds r2, #132 ; 0x84 + 8006e7a: f403 4370 and.w r3, r3, #61440 ; 0xf000 + 8006e7e: 6093 str r3, [r2, #8] + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + 8006e80: 68bb ldr r3, [r7, #8] + 8006e82: 689a ldr r2, [r3, #8] + 8006e84: 68fb ldr r3, [r7, #12] + 8006e86: 681b ldr r3, [r3, #0] + 8006e88: 68db ldr r3, [r3, #12] + 8006e8a: f3c3 030a ubfx r3, r3, #0, #11 + 8006e8e: 4413 add r3, r2 + 8006e90: 1c5a adds r2, r3, #1 + 8006e92: 68fb ldr r3, [r7, #12] + 8006e94: 681b ldr r3, [r3, #0] + 8006e96: 4619 mov r1, r3 + 8006e98: 687b ldr r3, [r7, #4] + 8006e9a: 01db lsls r3, r3, #7 + 8006e9c: 440b add r3, r1 + 8006e9e: 3384 adds r3, #132 ; 0x84 + 8006ea0: 4619 mov r1, r3 + 8006ea2: 69fb ldr r3, [r7, #28] + 8006ea4: 4313 orrs r3, r2 + 8006ea6: 608b str r3, [r1, #8] + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + 8006ea8: 68fb ldr r3, [r7, #12] + 8006eaa: 681b ldr r3, [r3, #0] + 8006eac: 461a mov r2, r3 + 8006eae: 687b ldr r3, [r7, #4] + 8006eb0: 01db lsls r3, r3, #7 + 8006eb2: 4413 add r3, r2 + 8006eb4: 3384 adds r3, #132 ; 0x84 + 8006eb6: 691b ldr r3, [r3, #16] + 8006eb8: 68fa ldr r2, [r7, #12] + 8006eba: 6812 ldr r2, [r2, #0] + 8006ebc: 4611 mov r1, r2 + 8006ebe: 687a ldr r2, [r7, #4] + 8006ec0: 01d2 lsls r2, r2, #7 + 8006ec2: 440a add r2, r1 + 8006ec4: 3284 adds r2, #132 ; 0x84 + 8006ec6: f023 0307 bic.w r3, r3, #7 + 8006eca: 6113 str r3, [r2, #16] + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + 8006ecc: 68fb ldr r3, [r7, #12] + 8006ece: 681b ldr r3, [r3, #0] + 8006ed0: 461a mov r2, r3 + 8006ed2: 687b ldr r3, [r7, #4] + 8006ed4: 01db lsls r3, r3, #7 + 8006ed6: 4413 add r3, r2 + 8006ed8: 3384 adds r3, #132 ; 0x84 + 8006eda: 461a mov r2, r3 + 8006edc: 68bb ldr r3, [r7, #8] + 8006ede: 691b ldr r3, [r3, #16] + 8006ee0: 6113 str r3, [r2, #16] + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + 8006ee2: 68bb ldr r3, [r7, #8] + 8006ee4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8006ee8: 021b lsls r3, r3, #8 + 8006eea: 61fb str r3, [r7, #28] + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + 8006eec: 68bb ldr r3, [r7, #8] + 8006eee: f893 3032 ldrb.w r3, [r3, #50] ; 0x32 + 8006ef2: 041b lsls r3, r3, #16 + 8006ef4: 61bb str r3, [r7, #24] + tmp2 = (pLayerCfg->Alpha0 << 24U); + 8006ef6: 68bb ldr r3, [r7, #8] + 8006ef8: 699b ldr r3, [r3, #24] + 8006efa: 061b lsls r3, r3, #24 + 8006efc: 617b str r3, [r7, #20] + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + 8006efe: 68fb ldr r3, [r7, #12] + 8006f00: 681b ldr r3, [r3, #0] + 8006f02: 461a mov r2, r3 + 8006f04: 687b ldr r3, [r7, #4] + 8006f06: 01db lsls r3, r3, #7 + 8006f08: 4413 add r3, r2 + 8006f0a: 3384 adds r3, #132 ; 0x84 + 8006f0c: 699b ldr r3, [r3, #24] + 8006f0e: 68fb ldr r3, [r7, #12] + 8006f10: 681b ldr r3, [r3, #0] + 8006f12: 461a mov r2, r3 + 8006f14: 687b ldr r3, [r7, #4] + 8006f16: 01db lsls r3, r3, #7 + 8006f18: 4413 add r3, r2 + 8006f1a: 3384 adds r3, #132 ; 0x84 + 8006f1c: 461a mov r2, r3 + 8006f1e: 2300 movs r3, #0 + 8006f20: 6193 str r3, [r2, #24] + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + 8006f22: 68bb ldr r3, [r7, #8] + 8006f24: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8006f28: 461a mov r2, r3 + 8006f2a: 69fb ldr r3, [r7, #28] + 8006f2c: 431a orrs r2, r3 + 8006f2e: 69bb ldr r3, [r7, #24] + 8006f30: 431a orrs r2, r3 + 8006f32: 68fb ldr r3, [r7, #12] + 8006f34: 681b ldr r3, [r3, #0] + 8006f36: 4619 mov r1, r3 + 8006f38: 687b ldr r3, [r7, #4] + 8006f3a: 01db lsls r3, r3, #7 + 8006f3c: 440b add r3, r1 + 8006f3e: 3384 adds r3, #132 ; 0x84 + 8006f40: 4619 mov r1, r3 + 8006f42: 697b ldr r3, [r7, #20] + 8006f44: 4313 orrs r3, r2 + 8006f46: 618b str r3, [r1, #24] + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + 8006f48: 68fb ldr r3, [r7, #12] + 8006f4a: 681b ldr r3, [r3, #0] + 8006f4c: 461a mov r2, r3 + 8006f4e: 687b ldr r3, [r7, #4] + 8006f50: 01db lsls r3, r3, #7 + 8006f52: 4413 add r3, r2 + 8006f54: 3384 adds r3, #132 ; 0x84 + 8006f56: 695b ldr r3, [r3, #20] + 8006f58: 68fa ldr r2, [r7, #12] + 8006f5a: 6812 ldr r2, [r2, #0] + 8006f5c: 4611 mov r1, r2 + 8006f5e: 687a ldr r2, [r7, #4] + 8006f60: 01d2 lsls r2, r2, #7 + 8006f62: 440a add r2, r1 + 8006f64: 3284 adds r2, #132 ; 0x84 + 8006f66: f023 03ff bic.w r3, r3, #255 ; 0xff + 8006f6a: 6153 str r3, [r2, #20] + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + 8006f6c: 68fb ldr r3, [r7, #12] + 8006f6e: 681b ldr r3, [r3, #0] + 8006f70: 461a mov r2, r3 + 8006f72: 687b ldr r3, [r7, #4] + 8006f74: 01db lsls r3, r3, #7 + 8006f76: 4413 add r3, r2 + 8006f78: 3384 adds r3, #132 ; 0x84 + 8006f7a: 461a mov r2, r3 + 8006f7c: 68bb ldr r3, [r7, #8] + 8006f7e: 695b ldr r3, [r3, #20] + 8006f80: 6153 str r3, [r2, #20] + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + 8006f82: 68fb ldr r3, [r7, #12] + 8006f84: 681b ldr r3, [r3, #0] + 8006f86: 461a mov r2, r3 + 8006f88: 687b ldr r3, [r7, #4] + 8006f8a: 01db lsls r3, r3, #7 + 8006f8c: 4413 add r3, r2 + 8006f8e: 3384 adds r3, #132 ; 0x84 + 8006f90: 69da ldr r2, [r3, #28] + 8006f92: 68fb ldr r3, [r7, #12] + 8006f94: 681b ldr r3, [r3, #0] + 8006f96: 4619 mov r1, r3 + 8006f98: 687b ldr r3, [r7, #4] + 8006f9a: 01db lsls r3, r3, #7 + 8006f9c: 440b add r3, r1 + 8006f9e: 3384 adds r3, #132 ; 0x84 + 8006fa0: 4619 mov r1, r3 + 8006fa2: 4b58 ldr r3, [pc, #352] ; (8007104 ) + 8006fa4: 4013 ands r3, r2 + 8006fa6: 61cb str r3, [r1, #28] + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + 8006fa8: 68bb ldr r3, [r7, #8] + 8006faa: 69da ldr r2, [r3, #28] + 8006fac: 68bb ldr r3, [r7, #8] + 8006fae: 6a1b ldr r3, [r3, #32] + 8006fb0: 68f9 ldr r1, [r7, #12] + 8006fb2: 6809 ldr r1, [r1, #0] + 8006fb4: 4608 mov r0, r1 + 8006fb6: 6879 ldr r1, [r7, #4] + 8006fb8: 01c9 lsls r1, r1, #7 + 8006fba: 4401 add r1, r0 + 8006fbc: 3184 adds r1, #132 ; 0x84 + 8006fbe: 4313 orrs r3, r2 + 8006fc0: 61cb str r3, [r1, #28] + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + 8006fc2: 68fb ldr r3, [r7, #12] + 8006fc4: 681b ldr r3, [r3, #0] + 8006fc6: 461a mov r2, r3 + 8006fc8: 687b ldr r3, [r7, #4] + 8006fca: 01db lsls r3, r3, #7 + 8006fcc: 4413 add r3, r2 + 8006fce: 3384 adds r3, #132 ; 0x84 + 8006fd0: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006fd2: 68fb ldr r3, [r7, #12] + 8006fd4: 681b ldr r3, [r3, #0] + 8006fd6: 461a mov r2, r3 + 8006fd8: 687b ldr r3, [r7, #4] + 8006fda: 01db lsls r3, r3, #7 + 8006fdc: 4413 add r3, r2 + 8006fde: 3384 adds r3, #132 ; 0x84 + 8006fe0: 461a mov r2, r3 + 8006fe2: 2300 movs r3, #0 + 8006fe4: 6293 str r3, [r2, #40] ; 0x28 + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + 8006fe6: 68fb ldr r3, [r7, #12] + 8006fe8: 681b ldr r3, [r3, #0] + 8006fea: 461a mov r2, r3 + 8006fec: 687b ldr r3, [r7, #4] + 8006fee: 01db lsls r3, r3, #7 + 8006ff0: 4413 add r3, r2 + 8006ff2: 3384 adds r3, #132 ; 0x84 + 8006ff4: 461a mov r2, r3 + 8006ff6: 68bb ldr r3, [r7, #8] + 8006ff8: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006ffa: 6293 str r3, [r2, #40] ; 0x28 + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + 8006ffc: 68bb ldr r3, [r7, #8] + 8006ffe: 691b ldr r3, [r3, #16] + 8007000: 2b00 cmp r3, #0 + 8007002: d102 bne.n 800700a + { + tmp = 4U; + 8007004: 2304 movs r3, #4 + 8007006: 61fb str r3, [r7, #28] + 8007008: e01b b.n 8007042 + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + 800700a: 68bb ldr r3, [r7, #8] + 800700c: 691b ldr r3, [r3, #16] + 800700e: 2b01 cmp r3, #1 + 8007010: d102 bne.n 8007018 + { + tmp = 3U; + 8007012: 2303 movs r3, #3 + 8007014: 61fb str r3, [r7, #28] + 8007016: e014 b.n 8007042 + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + 8007018: 68bb ldr r3, [r7, #8] + 800701a: 691b ldr r3, [r3, #16] + 800701c: 2b04 cmp r3, #4 + 800701e: d00b beq.n 8007038 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + 8007020: 68bb ldr r3, [r7, #8] + 8007022: 691b ldr r3, [r3, #16] + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + 8007024: 2b02 cmp r3, #2 + 8007026: d007 beq.n 8007038 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + 8007028: 68bb ldr r3, [r7, #8] + 800702a: 691b ldr r3, [r3, #16] + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + 800702c: 2b03 cmp r3, #3 + 800702e: d003 beq.n 8007038 + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + 8007030: 68bb ldr r3, [r7, #8] + 8007032: 691b ldr r3, [r3, #16] + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + 8007034: 2b07 cmp r3, #7 + 8007036: d102 bne.n 800703e + { + tmp = 2U; + 8007038: 2302 movs r3, #2 + 800703a: 61fb str r3, [r7, #28] + 800703c: e001 b.n 8007042 + } + else + { + tmp = 1U; + 800703e: 2301 movs r3, #1 + 8007040: 61fb str r3, [r7, #28] + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + 8007042: 68fb ldr r3, [r7, #12] + 8007044: 681b ldr r3, [r3, #0] + 8007046: 461a mov r2, r3 + 8007048: 687b ldr r3, [r7, #4] + 800704a: 01db lsls r3, r3, #7 + 800704c: 4413 add r3, r2 + 800704e: 3384 adds r3, #132 ; 0x84 + 8007050: 6adb ldr r3, [r3, #44] ; 0x2c + 8007052: 68fa ldr r2, [r7, #12] + 8007054: 6812 ldr r2, [r2, #0] + 8007056: 4611 mov r1, r2 + 8007058: 687a ldr r2, [r7, #4] + 800705a: 01d2 lsls r2, r2, #7 + 800705c: 440a add r2, r1 + 800705e: 3284 adds r2, #132 ; 0x84 + 8007060: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000 + 8007064: 62d3 str r3, [r2, #44] ; 0x2c + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + 8007066: 68bb ldr r3, [r7, #8] + 8007068: 6a9b ldr r3, [r3, #40] ; 0x28 + 800706a: 69fa ldr r2, [r7, #28] + 800706c: fb02 f303 mul.w r3, r2, r3 + 8007070: 041a lsls r2, r3, #16 + 8007072: 68bb ldr r3, [r7, #8] + 8007074: 6859 ldr r1, [r3, #4] + 8007076: 68bb ldr r3, [r7, #8] + 8007078: 681b ldr r3, [r3, #0] + 800707a: 1acb subs r3, r1, r3 + 800707c: 69f9 ldr r1, [r7, #28] + 800707e: fb01 f303 mul.w r3, r1, r3 + 8007082: 3303 adds r3, #3 + 8007084: 68f9 ldr r1, [r7, #12] + 8007086: 6809 ldr r1, [r1, #0] + 8007088: 4608 mov r0, r1 + 800708a: 6879 ldr r1, [r7, #4] + 800708c: 01c9 lsls r1, r1, #7 + 800708e: 4401 add r1, r0 + 8007090: 3184 adds r1, #132 ; 0x84 + 8007092: 4313 orrs r3, r2 + 8007094: 62cb str r3, [r1, #44] ; 0x2c + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + 8007096: 68fb ldr r3, [r7, #12] + 8007098: 681b ldr r3, [r3, #0] + 800709a: 461a mov r2, r3 + 800709c: 687b ldr r3, [r7, #4] + 800709e: 01db lsls r3, r3, #7 + 80070a0: 4413 add r3, r2 + 80070a2: 3384 adds r3, #132 ; 0x84 + 80070a4: 6b1a ldr r2, [r3, #48] ; 0x30 + 80070a6: 68fb ldr r3, [r7, #12] + 80070a8: 681b ldr r3, [r3, #0] + 80070aa: 4619 mov r1, r3 + 80070ac: 687b ldr r3, [r7, #4] + 80070ae: 01db lsls r3, r3, #7 + 80070b0: 440b add r3, r1 + 80070b2: 3384 adds r3, #132 ; 0x84 + 80070b4: 4619 mov r1, r3 + 80070b6: 4b14 ldr r3, [pc, #80] ; (8007108 ) + 80070b8: 4013 ands r3, r2 + 80070ba: 630b str r3, [r1, #48] ; 0x30 + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + 80070bc: 68fb ldr r3, [r7, #12] + 80070be: 681b ldr r3, [r3, #0] + 80070c0: 461a mov r2, r3 + 80070c2: 687b ldr r3, [r7, #4] + 80070c4: 01db lsls r3, r3, #7 + 80070c6: 4413 add r3, r2 + 80070c8: 3384 adds r3, #132 ; 0x84 + 80070ca: 461a mov r2, r3 + 80070cc: 68bb ldr r3, [r7, #8] + 80070ce: 6adb ldr r3, [r3, #44] ; 0x2c + 80070d0: 6313 str r3, [r2, #48] ; 0x30 + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; + 80070d2: 68fb ldr r3, [r7, #12] + 80070d4: 681b ldr r3, [r3, #0] + 80070d6: 461a mov r2, r3 + 80070d8: 687b ldr r3, [r7, #4] + 80070da: 01db lsls r3, r3, #7 + 80070dc: 4413 add r3, r2 + 80070de: 3384 adds r3, #132 ; 0x84 + 80070e0: 681b ldr r3, [r3, #0] + 80070e2: 68fa ldr r2, [r7, #12] + 80070e4: 6812 ldr r2, [r2, #0] + 80070e6: 4611 mov r1, r2 + 80070e8: 687a ldr r2, [r7, #4] + 80070ea: 01d2 lsls r2, r2, #7 + 80070ec: 440a add r2, r1 + 80070ee: 3284 adds r2, #132 ; 0x84 + 80070f0: f043 0301 orr.w r3, r3, #1 + 80070f4: 6013 str r3, [r2, #0] +} + 80070f6: bf00 nop + 80070f8: 3724 adds r7, #36 ; 0x24 + 80070fa: 46bd mov sp, r7 + 80070fc: f85d 7b04 ldr.w r7, [sp], #4 + 8007100: 4770 bx lr + 8007102: bf00 nop + 8007104: fffff8f8 .word 0xfffff8f8 + 8007108: fffff800 .word 0xfffff800 + +0800710c : + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 800710c: b480 push {r7} + 800710e: af00 add r7, sp, #0 + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 8007110: 4b05 ldr r3, [pc, #20] ; (8007128 ) + 8007112: 681b ldr r3, [r3, #0] + 8007114: 4a04 ldr r2, [pc, #16] ; (8007128 ) + 8007116: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800711a: 6013 str r3, [r2, #0] +} + 800711c: bf00 nop + 800711e: 46bd mov sp, r7 + 8007120: f85d 7b04 ldr.w r7, [sp], #4 + 8007124: 4770 bx lr + 8007126: bf00 nop + 8007128: 40007000 .word 0x40007000 + +0800712c : + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + 800712c: b580 push {r7, lr} + 800712e: b082 sub sp, #8 + 8007130: af00 add r7, sp, #0 + uint32_t tickstart = 0; + 8007132: 2300 movs r3, #0 + 8007134: 607b str r3, [r7, #4] + + __HAL_RCC_PWR_CLK_ENABLE(); + 8007136: 4b23 ldr r3, [pc, #140] ; (80071c4 ) + 8007138: 6c1b ldr r3, [r3, #64] ; 0x40 + 800713a: 4a22 ldr r2, [pc, #136] ; (80071c4 ) + 800713c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8007140: 6413 str r3, [r2, #64] ; 0x40 + 8007142: 4b20 ldr r3, [pc, #128] ; (80071c4 ) + 8007144: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007146: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800714a: 603b str r3, [r7, #0] + 800714c: 683b ldr r3, [r7, #0] + + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + 800714e: 4b1e ldr r3, [pc, #120] ; (80071c8 ) + 8007150: 681b ldr r3, [r3, #0] + 8007152: 4a1d ldr r2, [pc, #116] ; (80071c8 ) + 8007154: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007158: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800715a: f7fd f9c9 bl 80044f0 + 800715e: 6078 str r0, [r7, #4] + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 8007160: e009 b.n 8007176 + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 8007162: f7fd f9c5 bl 80044f0 + 8007166: 4602 mov r2, r0 + 8007168: 687b ldr r3, [r7, #4] + 800716a: 1ad3 subs r3, r2, r3 + 800716c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8007170: d901 bls.n 8007176 + { + return HAL_TIMEOUT; + 8007172: 2303 movs r3, #3 + 8007174: e022 b.n 80071bc + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 8007176: 4b14 ldr r3, [pc, #80] ; (80071c8 ) + 8007178: 685b ldr r3, [r3, #4] + 800717a: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800717e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8007182: d1ee bne.n 8007162 + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + 8007184: 4b10 ldr r3, [pc, #64] ; (80071c8 ) + 8007186: 681b ldr r3, [r3, #0] + 8007188: 4a0f ldr r2, [pc, #60] ; (80071c8 ) + 800718a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800718e: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8007190: f7fd f9ae bl 80044f0 + 8007194: 6078 str r0, [r7, #4] + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 8007196: e009 b.n 80071ac + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 8007198: f7fd f9aa bl 80044f0 + 800719c: 4602 mov r2, r0 + 800719e: 687b ldr r3, [r7, #4] + 80071a0: 1ad3 subs r3, r2, r3 + 80071a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 80071a6: d901 bls.n 80071ac + { + return HAL_TIMEOUT; + 80071a8: 2303 movs r3, #3 + 80071aa: e007 b.n 80071bc + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 80071ac: 4b06 ldr r3, [pc, #24] ; (80071c8 ) + 80071ae: 685b ldr r3, [r3, #4] + 80071b0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80071b4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 80071b8: d1ee bne.n 8007198 + } + } + return HAL_OK; + 80071ba: 2300 movs r3, #0 +} + 80071bc: 4618 mov r0, r3 + 80071be: 3708 adds r7, #8 + 80071c0: 46bd mov sp, r7 + 80071c2: bd80 pop {r7, pc} + 80071c4: 40023800 .word 0x40023800 + 80071c8: 40007000 .word 0x40007000 + +080071cc : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80071cc: b580 push {r7, lr} + 80071ce: b086 sub sp, #24 + 80071d0: af00 add r7, sp, #0 + 80071d2: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t pll_config; + FlagStatus pwrclkchanged = RESET; + 80071d4: 2300 movs r3, #0 + 80071d6: 75fb strb r3, [r7, #23] + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 80071d8: 687b ldr r3, [r7, #4] + 80071da: 2b00 cmp r3, #0 + 80071dc: d101 bne.n 80071e2 + { + return HAL_ERROR; + 80071de: 2301 movs r3, #1 + 80071e0: e291 b.n 8007706 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80071e2: 687b ldr r3, [r7, #4] + 80071e4: 681b ldr r3, [r3, #0] + 80071e6: f003 0301 and.w r3, r3, #1 + 80071ea: 2b00 cmp r3, #0 + 80071ec: f000 8087 beq.w 80072fe + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 80071f0: 4b96 ldr r3, [pc, #600] ; (800744c ) + 80071f2: 689b ldr r3, [r3, #8] + 80071f4: f003 030c and.w r3, r3, #12 + 80071f8: 2b04 cmp r3, #4 + 80071fa: d00c beq.n 8007216 + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 80071fc: 4b93 ldr r3, [pc, #588] ; (800744c ) + 80071fe: 689b ldr r3, [r3, #8] + 8007200: f003 030c and.w r3, r3, #12 + 8007204: 2b08 cmp r3, #8 + 8007206: d112 bne.n 800722e + 8007208: 4b90 ldr r3, [pc, #576] ; (800744c ) + 800720a: 685b ldr r3, [r3, #4] + 800720c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8007210: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8007214: d10b bne.n 800722e + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8007216: 4b8d ldr r3, [pc, #564] ; (800744c ) + 8007218: 681b ldr r3, [r3, #0] + 800721a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800721e: 2b00 cmp r3, #0 + 8007220: d06c beq.n 80072fc + 8007222: 687b ldr r3, [r7, #4] + 8007224: 685b ldr r3, [r3, #4] + 8007226: 2b00 cmp r3, #0 + 8007228: d168 bne.n 80072fc + { + return HAL_ERROR; + 800722a: 2301 movs r3, #1 + 800722c: e26b b.n 8007706 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800722e: 687b ldr r3, [r7, #4] + 8007230: 685b ldr r3, [r3, #4] + 8007232: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8007236: d106 bne.n 8007246 + 8007238: 4b84 ldr r3, [pc, #528] ; (800744c ) + 800723a: 681b ldr r3, [r3, #0] + 800723c: 4a83 ldr r2, [pc, #524] ; (800744c ) + 800723e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007242: 6013 str r3, [r2, #0] + 8007244: e02e b.n 80072a4 + 8007246: 687b ldr r3, [r7, #4] + 8007248: 685b ldr r3, [r3, #4] + 800724a: 2b00 cmp r3, #0 + 800724c: d10c bne.n 8007268 + 800724e: 4b7f ldr r3, [pc, #508] ; (800744c ) + 8007250: 681b ldr r3, [r3, #0] + 8007252: 4a7e ldr r2, [pc, #504] ; (800744c ) + 8007254: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007258: 6013 str r3, [r2, #0] + 800725a: 4b7c ldr r3, [pc, #496] ; (800744c ) + 800725c: 681b ldr r3, [r3, #0] + 800725e: 4a7b ldr r2, [pc, #492] ; (800744c ) + 8007260: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8007264: 6013 str r3, [r2, #0] + 8007266: e01d b.n 80072a4 + 8007268: 687b ldr r3, [r7, #4] + 800726a: 685b ldr r3, [r3, #4] + 800726c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8007270: d10c bne.n 800728c + 8007272: 4b76 ldr r3, [pc, #472] ; (800744c ) + 8007274: 681b ldr r3, [r3, #0] + 8007276: 4a75 ldr r2, [pc, #468] ; (800744c ) + 8007278: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 800727c: 6013 str r3, [r2, #0] + 800727e: 4b73 ldr r3, [pc, #460] ; (800744c ) + 8007280: 681b ldr r3, [r3, #0] + 8007282: 4a72 ldr r2, [pc, #456] ; (800744c ) + 8007284: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007288: 6013 str r3, [r2, #0] + 800728a: e00b b.n 80072a4 + 800728c: 4b6f ldr r3, [pc, #444] ; (800744c ) + 800728e: 681b ldr r3, [r3, #0] + 8007290: 4a6e ldr r2, [pc, #440] ; (800744c ) + 8007292: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007296: 6013 str r3, [r2, #0] + 8007298: 4b6c ldr r3, [pc, #432] ; (800744c ) + 800729a: 681b ldr r3, [r3, #0] + 800729c: 4a6b ldr r2, [pc, #428] ; (800744c ) + 800729e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80072a2: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 80072a4: 687b ldr r3, [r7, #4] + 80072a6: 685b ldr r3, [r3, #4] + 80072a8: 2b00 cmp r3, #0 + 80072aa: d013 beq.n 80072d4 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80072ac: f7fd f920 bl 80044f0 + 80072b0: 6138 str r0, [r7, #16] + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80072b2: e008 b.n 80072c6 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80072b4: f7fd f91c bl 80044f0 + 80072b8: 4602 mov r2, r0 + 80072ba: 693b ldr r3, [r7, #16] + 80072bc: 1ad3 subs r3, r2, r3 + 80072be: 2b64 cmp r3, #100 ; 0x64 + 80072c0: d901 bls.n 80072c6 + { + return HAL_TIMEOUT; + 80072c2: 2303 movs r3, #3 + 80072c4: e21f b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80072c6: 4b61 ldr r3, [pc, #388] ; (800744c ) + 80072c8: 681b ldr r3, [r3, #0] + 80072ca: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80072ce: 2b00 cmp r3, #0 + 80072d0: d0f0 beq.n 80072b4 + 80072d2: e014 b.n 80072fe + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80072d4: f7fd f90c bl 80044f0 + 80072d8: 6138 str r0, [r7, #16] + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 80072da: e008 b.n 80072ee + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 80072dc: f7fd f908 bl 80044f0 + 80072e0: 4602 mov r2, r0 + 80072e2: 693b ldr r3, [r7, #16] + 80072e4: 1ad3 subs r3, r2, r3 + 80072e6: 2b64 cmp r3, #100 ; 0x64 + 80072e8: d901 bls.n 80072ee + { + return HAL_TIMEOUT; + 80072ea: 2303 movs r3, #3 + 80072ec: e20b b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 80072ee: 4b57 ldr r3, [pc, #348] ; (800744c ) + 80072f0: 681b ldr r3, [r3, #0] + 80072f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80072f6: 2b00 cmp r3, #0 + 80072f8: d1f0 bne.n 80072dc + 80072fa: e000 b.n 80072fe + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80072fc: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80072fe: 687b ldr r3, [r7, #4] + 8007300: 681b ldr r3, [r3, #0] + 8007302: f003 0302 and.w r3, r3, #2 + 8007306: 2b00 cmp r3, #0 + 8007308: d069 beq.n 80073de + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 800730a: 4b50 ldr r3, [pc, #320] ; (800744c ) + 800730c: 689b ldr r3, [r3, #8] + 800730e: f003 030c and.w r3, r3, #12 + 8007312: 2b00 cmp r3, #0 + 8007314: d00b beq.n 800732e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8007316: 4b4d ldr r3, [pc, #308] ; (800744c ) + 8007318: 689b ldr r3, [r3, #8] + 800731a: f003 030c and.w r3, r3, #12 + 800731e: 2b08 cmp r3, #8 + 8007320: d11c bne.n 800735c + 8007322: 4b4a ldr r3, [pc, #296] ; (800744c ) + 8007324: 685b ldr r3, [r3, #4] + 8007326: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800732a: 2b00 cmp r3, #0 + 800732c: d116 bne.n 800735c + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800732e: 4b47 ldr r3, [pc, #284] ; (800744c ) + 8007330: 681b ldr r3, [r3, #0] + 8007332: f003 0302 and.w r3, r3, #2 + 8007336: 2b00 cmp r3, #0 + 8007338: d005 beq.n 8007346 + 800733a: 687b ldr r3, [r7, #4] + 800733c: 68db ldr r3, [r3, #12] + 800733e: 2b01 cmp r3, #1 + 8007340: d001 beq.n 8007346 + { + return HAL_ERROR; + 8007342: 2301 movs r3, #1 + 8007344: e1df b.n 8007706 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8007346: 4b41 ldr r3, [pc, #260] ; (800744c ) + 8007348: 681b ldr r3, [r3, #0] + 800734a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800734e: 687b ldr r3, [r7, #4] + 8007350: 691b ldr r3, [r3, #16] + 8007352: 00db lsls r3, r3, #3 + 8007354: 493d ldr r1, [pc, #244] ; (800744c ) + 8007356: 4313 orrs r3, r2 + 8007358: 600b str r3, [r1, #0] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800735a: e040 b.n 80073de + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + 800735c: 687b ldr r3, [r7, #4] + 800735e: 68db ldr r3, [r3, #12] + 8007360: 2b00 cmp r3, #0 + 8007362: d023 beq.n 80073ac + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8007364: 4b39 ldr r3, [pc, #228] ; (800744c ) + 8007366: 681b ldr r3, [r3, #0] + 8007368: 4a38 ldr r2, [pc, #224] ; (800744c ) + 800736a: f043 0301 orr.w r3, r3, #1 + 800736e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007370: f7fd f8be bl 80044f0 + 8007374: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8007376: e008 b.n 800738a + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8007378: f7fd f8ba bl 80044f0 + 800737c: 4602 mov r2, r0 + 800737e: 693b ldr r3, [r7, #16] + 8007380: 1ad3 subs r3, r2, r3 + 8007382: 2b02 cmp r3, #2 + 8007384: d901 bls.n 800738a + { + return HAL_TIMEOUT; + 8007386: 2303 movs r3, #3 + 8007388: e1bd b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800738a: 4b30 ldr r3, [pc, #192] ; (800744c ) + 800738c: 681b ldr r3, [r3, #0] + 800738e: f003 0302 and.w r3, r3, #2 + 8007392: 2b00 cmp r3, #0 + 8007394: d0f0 beq.n 8007378 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8007396: 4b2d ldr r3, [pc, #180] ; (800744c ) + 8007398: 681b ldr r3, [r3, #0] + 800739a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800739e: 687b ldr r3, [r7, #4] + 80073a0: 691b ldr r3, [r3, #16] + 80073a2: 00db lsls r3, r3, #3 + 80073a4: 4929 ldr r1, [pc, #164] ; (800744c ) + 80073a6: 4313 orrs r3, r2 + 80073a8: 600b str r3, [r1, #0] + 80073aa: e018 b.n 80073de + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 80073ac: 4b27 ldr r3, [pc, #156] ; (800744c ) + 80073ae: 681b ldr r3, [r3, #0] + 80073b0: 4a26 ldr r2, [pc, #152] ; (800744c ) + 80073b2: f023 0301 bic.w r3, r3, #1 + 80073b6: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80073b8: f7fd f89a bl 80044f0 + 80073bc: 6138 str r0, [r7, #16] + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80073be: e008 b.n 80073d2 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80073c0: f7fd f896 bl 80044f0 + 80073c4: 4602 mov r2, r0 + 80073c6: 693b ldr r3, [r7, #16] + 80073c8: 1ad3 subs r3, r2, r3 + 80073ca: 2b02 cmp r3, #2 + 80073cc: d901 bls.n 80073d2 + { + return HAL_TIMEOUT; + 80073ce: 2303 movs r3, #3 + 80073d0: e199 b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80073d2: 4b1e ldr r3, [pc, #120] ; (800744c ) + 80073d4: 681b ldr r3, [r3, #0] + 80073d6: f003 0302 and.w r3, r3, #2 + 80073da: 2b00 cmp r3, #0 + 80073dc: d1f0 bne.n 80073c0 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 80073de: 687b ldr r3, [r7, #4] + 80073e0: 681b ldr r3, [r3, #0] + 80073e2: f003 0308 and.w r3, r3, #8 + 80073e6: 2b00 cmp r3, #0 + 80073e8: d038 beq.n 800745c + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + 80073ea: 687b ldr r3, [r7, #4] + 80073ec: 695b ldr r3, [r3, #20] + 80073ee: 2b00 cmp r3, #0 + 80073f0: d019 beq.n 8007426 + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 80073f2: 4b16 ldr r3, [pc, #88] ; (800744c ) + 80073f4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80073f6: 4a15 ldr r2, [pc, #84] ; (800744c ) + 80073f8: f043 0301 orr.w r3, r3, #1 + 80073fc: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80073fe: f7fd f877 bl 80044f0 + 8007402: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8007404: e008 b.n 8007418 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8007406: f7fd f873 bl 80044f0 + 800740a: 4602 mov r2, r0 + 800740c: 693b ldr r3, [r7, #16] + 800740e: 1ad3 subs r3, r2, r3 + 8007410: 2b02 cmp r3, #2 + 8007412: d901 bls.n 8007418 + { + return HAL_TIMEOUT; + 8007414: 2303 movs r3, #3 + 8007416: e176 b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8007418: 4b0c ldr r3, [pc, #48] ; (800744c ) + 800741a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800741c: f003 0302 and.w r3, r3, #2 + 8007420: 2b00 cmp r3, #0 + 8007422: d0f0 beq.n 8007406 + 8007424: e01a b.n 800745c + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8007426: 4b09 ldr r3, [pc, #36] ; (800744c ) + 8007428: 6f5b ldr r3, [r3, #116] ; 0x74 + 800742a: 4a08 ldr r2, [pc, #32] ; (800744c ) + 800742c: f023 0301 bic.w r3, r3, #1 + 8007430: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007432: f7fd f85d bl 80044f0 + 8007436: 6138 str r0, [r7, #16] + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8007438: e00a b.n 8007450 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800743a: f7fd f859 bl 80044f0 + 800743e: 4602 mov r2, r0 + 8007440: 693b ldr r3, [r7, #16] + 8007442: 1ad3 subs r3, r2, r3 + 8007444: 2b02 cmp r3, #2 + 8007446: d903 bls.n 8007450 + { + return HAL_TIMEOUT; + 8007448: 2303 movs r3, #3 + 800744a: e15c b.n 8007706 + 800744c: 40023800 .word 0x40023800 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8007450: 4b91 ldr r3, [pc, #580] ; (8007698 ) + 8007452: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007454: f003 0302 and.w r3, r3, #2 + 8007458: 2b00 cmp r3, #0 + 800745a: d1ee bne.n 800743a + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800745c: 687b ldr r3, [r7, #4] + 800745e: 681b ldr r3, [r3, #0] + 8007460: f003 0304 and.w r3, r3, #4 + 8007464: 2b00 cmp r3, #0 + 8007466: f000 80a4 beq.w 80075b2 + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800746a: 4b8b ldr r3, [pc, #556] ; (8007698 ) + 800746c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800746e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8007472: 2b00 cmp r3, #0 + 8007474: d10d bne.n 8007492 + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8007476: 4b88 ldr r3, [pc, #544] ; (8007698 ) + 8007478: 6c1b ldr r3, [r3, #64] ; 0x40 + 800747a: 4a87 ldr r2, [pc, #540] ; (8007698 ) + 800747c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8007480: 6413 str r3, [r2, #64] ; 0x40 + 8007482: 4b85 ldr r3, [pc, #532] ; (8007698 ) + 8007484: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007486: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800748a: 60bb str r3, [r7, #8] + 800748c: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 800748e: 2301 movs r3, #1 + 8007490: 75fb strb r3, [r7, #23] + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 8007492: 4b82 ldr r3, [pc, #520] ; (800769c ) + 8007494: 681b ldr r3, [r3, #0] + 8007496: f403 7380 and.w r3, r3, #256 ; 0x100 + 800749a: 2b00 cmp r3, #0 + 800749c: d118 bne.n 80074d0 + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 800749e: 4b7f ldr r3, [pc, #508] ; (800769c ) + 80074a0: 681b ldr r3, [r3, #0] + 80074a2: 4a7e ldr r2, [pc, #504] ; (800769c ) + 80074a4: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80074a8: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80074aa: f7fd f821 bl 80044f0 + 80074ae: 6138 str r0, [r7, #16] + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80074b0: e008 b.n 80074c4 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80074b2: f7fd f81d bl 80044f0 + 80074b6: 4602 mov r2, r0 + 80074b8: 693b ldr r3, [r7, #16] + 80074ba: 1ad3 subs r3, r2, r3 + 80074bc: 2b64 cmp r3, #100 ; 0x64 + 80074be: d901 bls.n 80074c4 + { + return HAL_TIMEOUT; + 80074c0: 2303 movs r3, #3 + 80074c2: e120 b.n 8007706 + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 80074c4: 4b75 ldr r3, [pc, #468] ; (800769c ) + 80074c6: 681b ldr r3, [r3, #0] + 80074c8: f403 7380 and.w r3, r3, #256 ; 0x100 + 80074cc: 2b00 cmp r3, #0 + 80074ce: d0f0 beq.n 80074b2 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80074d0: 687b ldr r3, [r7, #4] + 80074d2: 689b ldr r3, [r3, #8] + 80074d4: 2b01 cmp r3, #1 + 80074d6: d106 bne.n 80074e6 + 80074d8: 4b6f ldr r3, [pc, #444] ; (8007698 ) + 80074da: 6f1b ldr r3, [r3, #112] ; 0x70 + 80074dc: 4a6e ldr r2, [pc, #440] ; (8007698 ) + 80074de: f043 0301 orr.w r3, r3, #1 + 80074e2: 6713 str r3, [r2, #112] ; 0x70 + 80074e4: e02d b.n 8007542 + 80074e6: 687b ldr r3, [r7, #4] + 80074e8: 689b ldr r3, [r3, #8] + 80074ea: 2b00 cmp r3, #0 + 80074ec: d10c bne.n 8007508 + 80074ee: 4b6a ldr r3, [pc, #424] ; (8007698 ) + 80074f0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80074f2: 4a69 ldr r2, [pc, #420] ; (8007698 ) + 80074f4: f023 0301 bic.w r3, r3, #1 + 80074f8: 6713 str r3, [r2, #112] ; 0x70 + 80074fa: 4b67 ldr r3, [pc, #412] ; (8007698 ) + 80074fc: 6f1b ldr r3, [r3, #112] ; 0x70 + 80074fe: 4a66 ldr r2, [pc, #408] ; (8007698 ) + 8007500: f023 0304 bic.w r3, r3, #4 + 8007504: 6713 str r3, [r2, #112] ; 0x70 + 8007506: e01c b.n 8007542 + 8007508: 687b ldr r3, [r7, #4] + 800750a: 689b ldr r3, [r3, #8] + 800750c: 2b05 cmp r3, #5 + 800750e: d10c bne.n 800752a + 8007510: 4b61 ldr r3, [pc, #388] ; (8007698 ) + 8007512: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007514: 4a60 ldr r2, [pc, #384] ; (8007698 ) + 8007516: f043 0304 orr.w r3, r3, #4 + 800751a: 6713 str r3, [r2, #112] ; 0x70 + 800751c: 4b5e ldr r3, [pc, #376] ; (8007698 ) + 800751e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007520: 4a5d ldr r2, [pc, #372] ; (8007698 ) + 8007522: f043 0301 orr.w r3, r3, #1 + 8007526: 6713 str r3, [r2, #112] ; 0x70 + 8007528: e00b b.n 8007542 + 800752a: 4b5b ldr r3, [pc, #364] ; (8007698 ) + 800752c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800752e: 4a5a ldr r2, [pc, #360] ; (8007698 ) + 8007530: f023 0301 bic.w r3, r3, #1 + 8007534: 6713 str r3, [r2, #112] ; 0x70 + 8007536: 4b58 ldr r3, [pc, #352] ; (8007698 ) + 8007538: 6f1b ldr r3, [r3, #112] ; 0x70 + 800753a: 4a57 ldr r2, [pc, #348] ; (8007698 ) + 800753c: f023 0304 bic.w r3, r3, #4 + 8007540: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8007542: 687b ldr r3, [r7, #4] + 8007544: 689b ldr r3, [r3, #8] + 8007546: 2b00 cmp r3, #0 + 8007548: d015 beq.n 8007576 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800754a: f7fc ffd1 bl 80044f0 + 800754e: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007550: e00a b.n 8007568 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8007552: f7fc ffcd bl 80044f0 + 8007556: 4602 mov r2, r0 + 8007558: 693b ldr r3, [r7, #16] + 800755a: 1ad3 subs r3, r2, r3 + 800755c: f241 3288 movw r2, #5000 ; 0x1388 + 8007560: 4293 cmp r3, r2 + 8007562: d901 bls.n 8007568 + { + return HAL_TIMEOUT; + 8007564: 2303 movs r3, #3 + 8007566: e0ce b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007568: 4b4b ldr r3, [pc, #300] ; (8007698 ) + 800756a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800756c: f003 0302 and.w r3, r3, #2 + 8007570: 2b00 cmp r3, #0 + 8007572: d0ee beq.n 8007552 + 8007574: e014 b.n 80075a0 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007576: f7fc ffbb bl 80044f0 + 800757a: 6138 str r0, [r7, #16] + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 800757c: e00a b.n 8007594 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 800757e: f7fc ffb7 bl 80044f0 + 8007582: 4602 mov r2, r0 + 8007584: 693b ldr r3, [r7, #16] + 8007586: 1ad3 subs r3, r2, r3 + 8007588: f241 3288 movw r2, #5000 ; 0x1388 + 800758c: 4293 cmp r3, r2 + 800758e: d901 bls.n 8007594 + { + return HAL_TIMEOUT; + 8007590: 2303 movs r3, #3 + 8007592: e0b8 b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8007594: 4b40 ldr r3, [pc, #256] ; (8007698 ) + 8007596: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007598: f003 0302 and.w r3, r3, #2 + 800759c: 2b00 cmp r3, #0 + 800759e: d1ee bne.n 800757e + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + 80075a0: 7dfb ldrb r3, [r7, #23] + 80075a2: 2b01 cmp r3, #1 + 80075a4: d105 bne.n 80075b2 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 80075a6: 4b3c ldr r3, [pc, #240] ; (8007698 ) + 80075a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80075aa: 4a3b ldr r2, [pc, #236] ; (8007698 ) + 80075ac: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80075b0: 6413 str r3, [r2, #64] ; 0x40 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 80075b2: 687b ldr r3, [r7, #4] + 80075b4: 699b ldr r3, [r3, #24] + 80075b6: 2b00 cmp r3, #0 + 80075b8: f000 80a4 beq.w 8007704 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80075bc: 4b36 ldr r3, [pc, #216] ; (8007698 ) + 80075be: 689b ldr r3, [r3, #8] + 80075c0: f003 030c and.w r3, r3, #12 + 80075c4: 2b08 cmp r3, #8 + 80075c6: d06b beq.n 80076a0 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80075c8: 687b ldr r3, [r7, #4] + 80075ca: 699b ldr r3, [r3, #24] + 80075cc: 2b02 cmp r3, #2 + 80075ce: d149 bne.n 8007664 +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80075d0: 4b31 ldr r3, [pc, #196] ; (8007698 ) + 80075d2: 681b ldr r3, [r3, #0] + 80075d4: 4a30 ldr r2, [pc, #192] ; (8007698 ) + 80075d6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80075da: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80075dc: f7fc ff88 bl 80044f0 + 80075e0: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80075e2: e008 b.n 80075f6 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80075e4: f7fc ff84 bl 80044f0 + 80075e8: 4602 mov r2, r0 + 80075ea: 693b ldr r3, [r7, #16] + 80075ec: 1ad3 subs r3, r2, r3 + 80075ee: 2b02 cmp r3, #2 + 80075f0: d901 bls.n 80075f6 + { + return HAL_TIMEOUT; + 80075f2: 2303 movs r3, #3 + 80075f4: e087 b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80075f6: 4b28 ldr r3, [pc, #160] ; (8007698 ) + 80075f8: 681b ldr r3, [r3, #0] + 80075fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80075fe: 2b00 cmp r3, #0 + 8007600: d1f0 bne.n 80075e4 + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8007602: 687b ldr r3, [r7, #4] + 8007604: 69da ldr r2, [r3, #28] + 8007606: 687b ldr r3, [r7, #4] + 8007608: 6a1b ldr r3, [r3, #32] + 800760a: 431a orrs r2, r3 + 800760c: 687b ldr r3, [r7, #4] + 800760e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007610: 019b lsls r3, r3, #6 + 8007612: 431a orrs r2, r3 + 8007614: 687b ldr r3, [r7, #4] + 8007616: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007618: 085b lsrs r3, r3, #1 + 800761a: 3b01 subs r3, #1 + 800761c: 041b lsls r3, r3, #16 + 800761e: 431a orrs r2, r3 + 8007620: 687b ldr r3, [r7, #4] + 8007622: 6adb ldr r3, [r3, #44] ; 0x2c + 8007624: 061b lsls r3, r3, #24 + 8007626: 4313 orrs r3, r2 + 8007628: 4a1b ldr r2, [pc, #108] ; (8007698 ) + 800762a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 800762e: 6053 str r3, [r2, #4] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8007630: 4b19 ldr r3, [pc, #100] ; (8007698 ) + 8007632: 681b ldr r3, [r3, #0] + 8007634: 4a18 ldr r2, [pc, #96] ; (8007698 ) + 8007636: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 800763a: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800763c: f7fc ff58 bl 80044f0 + 8007640: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007642: e008 b.n 8007656 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8007644: f7fc ff54 bl 80044f0 + 8007648: 4602 mov r2, r0 + 800764a: 693b ldr r3, [r7, #16] + 800764c: 1ad3 subs r3, r2, r3 + 800764e: 2b02 cmp r3, #2 + 8007650: d901 bls.n 8007656 + { + return HAL_TIMEOUT; + 8007652: 2303 movs r3, #3 + 8007654: e057 b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8007656: 4b10 ldr r3, [pc, #64] ; (8007698 ) + 8007658: 681b ldr r3, [r3, #0] + 800765a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800765e: 2b00 cmp r3, #0 + 8007660: d0f0 beq.n 8007644 + 8007662: e04f b.n 8007704 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8007664: 4b0c ldr r3, [pc, #48] ; (8007698 ) + 8007666: 681b ldr r3, [r3, #0] + 8007668: 4a0b ldr r2, [pc, #44] ; (8007698 ) + 800766a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 800766e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007670: f7fc ff3e bl 80044f0 + 8007674: 6138 str r0, [r7, #16] + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8007676: e008 b.n 800768a + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8007678: f7fc ff3a bl 80044f0 + 800767c: 4602 mov r2, r0 + 800767e: 693b ldr r3, [r7, #16] + 8007680: 1ad3 subs r3, r2, r3 + 8007682: 2b02 cmp r3, #2 + 8007684: d901 bls.n 800768a + { + return HAL_TIMEOUT; + 8007686: 2303 movs r3, #3 + 8007688: e03d b.n 8007706 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800768a: 4b03 ldr r3, [pc, #12] ; (8007698 ) + 800768c: 681b ldr r3, [r3, #0] + 800768e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8007692: 2b00 cmp r3, #0 + 8007694: d1f0 bne.n 8007678 + 8007696: e035 b.n 8007704 + 8007698: 40023800 .word 0x40023800 + 800769c: 40007000 .word 0x40007000 + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 80076a0: 4b1b ldr r3, [pc, #108] ; (8007710 ) + 80076a2: 685b ldr r3, [r3, #4] + 80076a4: 60fb str r3, [r7, #12] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 80076a6: 687b ldr r3, [r7, #4] + 80076a8: 699b ldr r3, [r3, #24] + 80076aa: 2b01 cmp r3, #1 + 80076ac: d028 beq.n 8007700 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80076ae: 68fb ldr r3, [r7, #12] + 80076b0: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 80076b4: 687b ldr r3, [r7, #4] + 80076b6: 69db ldr r3, [r3, #28] + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 80076b8: 429a cmp r2, r3 + 80076ba: d121 bne.n 8007700 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 80076bc: 68fb ldr r3, [r7, #12] + 80076be: f003 023f and.w r2, r3, #63 ; 0x3f + 80076c2: 687b ldr r3, [r7, #4] + 80076c4: 6a1b ldr r3, [r3, #32] + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80076c6: 429a cmp r2, r3 + 80076c8: d11a bne.n 8007700 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 80076ca: 68fa ldr r2, [r7, #12] + 80076cc: f647 73c0 movw r3, #32704 ; 0x7fc0 + 80076d0: 4013 ands r3, r2 + 80076d2: 687a ldr r2, [r7, #4] + 80076d4: 6a52 ldr r2, [r2, #36] ; 0x24 + 80076d6: 0192 lsls r2, r2, #6 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 80076d8: 4293 cmp r3, r2 + 80076da: d111 bne.n 8007700 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + 80076dc: 68fb ldr r3, [r7, #12] + 80076de: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 80076e2: 687b ldr r3, [r7, #4] + 80076e4: 6a9b ldr r3, [r3, #40] ; 0x28 + 80076e6: 085b lsrs r3, r3, #1 + 80076e8: 3b01 subs r3, #1 + 80076ea: 041b lsls r3, r3, #16 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + 80076ec: 429a cmp r2, r3 + 80076ee: d107 bne.n 8007700 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) + 80076f0: 68fb ldr r3, [r7, #12] + 80076f2: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 80076f6: 687b ldr r3, [r7, #4] + 80076f8: 6adb ldr r3, [r3, #44] ; 0x2c + 80076fa: 061b lsls r3, r3, #24 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + 80076fc: 429a cmp r2, r3 + 80076fe: d001 beq.n 8007704 +#endif + { + return HAL_ERROR; + 8007700: 2301 movs r3, #1 + 8007702: e000 b.n 8007706 + } + } + } + return HAL_OK; + 8007704: 2300 movs r3, #0 +} + 8007706: 4618 mov r0, r3 + 8007708: 3718 adds r7, #24 + 800770a: 46bd mov sp, r7 + 800770c: bd80 pop {r7, pc} + 800770e: bf00 nop + 8007710: 40023800 .word 0x40023800 + +08007714 : + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8007714: b580 push {r7, lr} + 8007716: b084 sub sp, #16 + 8007718: af00 add r7, sp, #0 + 800771a: 6078 str r0, [r7, #4] + 800771c: 6039 str r1, [r7, #0] + uint32_t tickstart = 0; + 800771e: 2300 movs r3, #0 + 8007720: 60fb str r3, [r7, #12] + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8007722: 687b ldr r3, [r7, #4] + 8007724: 2b00 cmp r3, #0 + 8007726: d101 bne.n 800772c + { + return HAL_ERROR; + 8007728: 2301 movs r3, #1 + 800772a: e0d0 b.n 80078ce + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 800772c: 4b6a ldr r3, [pc, #424] ; (80078d8 ) + 800772e: 681b ldr r3, [r3, #0] + 8007730: f003 030f and.w r3, r3, #15 + 8007734: 683a ldr r2, [r7, #0] + 8007736: 429a cmp r2, r3 + 8007738: d910 bls.n 800775c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800773a: 4b67 ldr r3, [pc, #412] ; (80078d8 ) + 800773c: 681b ldr r3, [r3, #0] + 800773e: f023 020f bic.w r2, r3, #15 + 8007742: 4965 ldr r1, [pc, #404] ; (80078d8 ) + 8007744: 683b ldr r3, [r7, #0] + 8007746: 4313 orrs r3, r2 + 8007748: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 800774a: 4b63 ldr r3, [pc, #396] ; (80078d8 ) + 800774c: 681b ldr r3, [r3, #0] + 800774e: f003 030f and.w r3, r3, #15 + 8007752: 683a ldr r2, [r7, #0] + 8007754: 429a cmp r2, r3 + 8007756: d001 beq.n 800775c + { + return HAL_ERROR; + 8007758: 2301 movs r3, #1 + 800775a: e0b8 b.n 80078ce + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 800775c: 687b ldr r3, [r7, #4] + 800775e: 681b ldr r3, [r3, #0] + 8007760: f003 0302 and.w r3, r3, #2 + 8007764: 2b00 cmp r3, #0 + 8007766: d020 beq.n 80077aa + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8007768: 687b ldr r3, [r7, #4] + 800776a: 681b ldr r3, [r3, #0] + 800776c: f003 0304 and.w r3, r3, #4 + 8007770: 2b00 cmp r3, #0 + 8007772: d005 beq.n 8007780 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8007774: 4b59 ldr r3, [pc, #356] ; (80078dc ) + 8007776: 689b ldr r3, [r3, #8] + 8007778: 4a58 ldr r2, [pc, #352] ; (80078dc ) + 800777a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 800777e: 6093 str r3, [r2, #8] + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8007780: 687b ldr r3, [r7, #4] + 8007782: 681b ldr r3, [r3, #0] + 8007784: f003 0308 and.w r3, r3, #8 + 8007788: 2b00 cmp r3, #0 + 800778a: d005 beq.n 8007798 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 800778c: 4b53 ldr r3, [pc, #332] ; (80078dc ) + 800778e: 689b ldr r3, [r3, #8] + 8007790: 4a52 ldr r2, [pc, #328] ; (80078dc ) + 8007792: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8007796: 6093 str r3, [r2, #8] + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8007798: 4b50 ldr r3, [pc, #320] ; (80078dc ) + 800779a: 689b ldr r3, [r3, #8] + 800779c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80077a0: 687b ldr r3, [r7, #4] + 80077a2: 689b ldr r3, [r3, #8] + 80077a4: 494d ldr r1, [pc, #308] ; (80078dc ) + 80077a6: 4313 orrs r3, r2 + 80077a8: 608b str r3, [r1, #8] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 80077aa: 687b ldr r3, [r7, #4] + 80077ac: 681b ldr r3, [r3, #0] + 80077ae: f003 0301 and.w r3, r3, #1 + 80077b2: 2b00 cmp r3, #0 + 80077b4: d040 beq.n 8007838 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80077b6: 687b ldr r3, [r7, #4] + 80077b8: 685b ldr r3, [r3, #4] + 80077ba: 2b01 cmp r3, #1 + 80077bc: d107 bne.n 80077ce + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80077be: 4b47 ldr r3, [pc, #284] ; (80078dc ) + 80077c0: 681b ldr r3, [r3, #0] + 80077c2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80077c6: 2b00 cmp r3, #0 + 80077c8: d115 bne.n 80077f6 + { + return HAL_ERROR; + 80077ca: 2301 movs r3, #1 + 80077cc: e07f b.n 80078ce + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80077ce: 687b ldr r3, [r7, #4] + 80077d0: 685b ldr r3, [r3, #4] + 80077d2: 2b02 cmp r3, #2 + 80077d4: d107 bne.n 80077e6 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80077d6: 4b41 ldr r3, [pc, #260] ; (80078dc ) + 80077d8: 681b ldr r3, [r3, #0] + 80077da: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80077de: 2b00 cmp r3, #0 + 80077e0: d109 bne.n 80077f6 + { + return HAL_ERROR; + 80077e2: 2301 movs r3, #1 + 80077e4: e073 b.n 80078ce + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80077e6: 4b3d ldr r3, [pc, #244] ; (80078dc ) + 80077e8: 681b ldr r3, [r3, #0] + 80077ea: f003 0302 and.w r3, r3, #2 + 80077ee: 2b00 cmp r3, #0 + 80077f0: d101 bne.n 80077f6 + { + return HAL_ERROR; + 80077f2: 2301 movs r3, #1 + 80077f4: e06b b.n 80078ce + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 80077f6: 4b39 ldr r3, [pc, #228] ; (80078dc ) + 80077f8: 689b ldr r3, [r3, #8] + 80077fa: f023 0203 bic.w r2, r3, #3 + 80077fe: 687b ldr r3, [r7, #4] + 8007800: 685b ldr r3, [r3, #4] + 8007802: 4936 ldr r1, [pc, #216] ; (80078dc ) + 8007804: 4313 orrs r3, r2 + 8007806: 608b str r3, [r1, #8] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007808: f7fc fe72 bl 80044f0 + 800780c: 60f8 str r0, [r7, #12] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800780e: e00a b.n 8007826 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8007810: f7fc fe6e bl 80044f0 + 8007814: 4602 mov r2, r0 + 8007816: 68fb ldr r3, [r7, #12] + 8007818: 1ad3 subs r3, r2, r3 + 800781a: f241 3288 movw r2, #5000 ; 0x1388 + 800781e: 4293 cmp r3, r2 + 8007820: d901 bls.n 8007826 + { + return HAL_TIMEOUT; + 8007822: 2303 movs r3, #3 + 8007824: e053 b.n 80078ce + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8007826: 4b2d ldr r3, [pc, #180] ; (80078dc ) + 8007828: 689b ldr r3, [r3, #8] + 800782a: f003 020c and.w r2, r3, #12 + 800782e: 687b ldr r3, [r7, #4] + 8007830: 685b ldr r3, [r3, #4] + 8007832: 009b lsls r3, r3, #2 + 8007834: 429a cmp r2, r3 + 8007836: d1eb bne.n 8007810 + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8007838: 4b27 ldr r3, [pc, #156] ; (80078d8 ) + 800783a: 681b ldr r3, [r3, #0] + 800783c: f003 030f and.w r3, r3, #15 + 8007840: 683a ldr r2, [r7, #0] + 8007842: 429a cmp r2, r3 + 8007844: d210 bcs.n 8007868 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8007846: 4b24 ldr r3, [pc, #144] ; (80078d8 ) + 8007848: 681b ldr r3, [r3, #0] + 800784a: f023 020f bic.w r2, r3, #15 + 800784e: 4922 ldr r1, [pc, #136] ; (80078d8 ) + 8007850: 683b ldr r3, [r7, #0] + 8007852: 4313 orrs r3, r2 + 8007854: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8007856: 4b20 ldr r3, [pc, #128] ; (80078d8 ) + 8007858: 681b ldr r3, [r3, #0] + 800785a: f003 030f and.w r3, r3, #15 + 800785e: 683a ldr r2, [r7, #0] + 8007860: 429a cmp r2, r3 + 8007862: d001 beq.n 8007868 + { + return HAL_ERROR; + 8007864: 2301 movs r3, #1 + 8007866: e032 b.n 80078ce + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8007868: 687b ldr r3, [r7, #4] + 800786a: 681b ldr r3, [r3, #0] + 800786c: f003 0304 and.w r3, r3, #4 + 8007870: 2b00 cmp r3, #0 + 8007872: d008 beq.n 8007886 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 8007874: 4b19 ldr r3, [pc, #100] ; (80078dc ) + 8007876: 689b ldr r3, [r3, #8] + 8007878: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 800787c: 687b ldr r3, [r7, #4] + 800787e: 68db ldr r3, [r3, #12] + 8007880: 4916 ldr r1, [pc, #88] ; (80078dc ) + 8007882: 4313 orrs r3, r2 + 8007884: 608b str r3, [r1, #8] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8007886: 687b ldr r3, [r7, #4] + 8007888: 681b ldr r3, [r3, #0] + 800788a: f003 0308 and.w r3, r3, #8 + 800788e: 2b00 cmp r3, #0 + 8007890: d009 beq.n 80078a6 + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8007892: 4b12 ldr r3, [pc, #72] ; (80078dc ) + 8007894: 689b ldr r3, [r3, #8] + 8007896: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 800789a: 687b ldr r3, [r7, #4] + 800789c: 691b ldr r3, [r3, #16] + 800789e: 00db lsls r3, r3, #3 + 80078a0: 490e ldr r1, [pc, #56] ; (80078dc ) + 80078a2: 4313 orrs r3, r2 + 80078a4: 608b str r3, [r1, #8] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + 80078a6: f000 f821 bl 80078ec + 80078aa: 4601 mov r1, r0 + 80078ac: 4b0b ldr r3, [pc, #44] ; (80078dc ) + 80078ae: 689b ldr r3, [r3, #8] + 80078b0: 091b lsrs r3, r3, #4 + 80078b2: f003 030f and.w r3, r3, #15 + 80078b6: 4a0a ldr r2, [pc, #40] ; (80078e0 ) + 80078b8: 5cd3 ldrb r3, [r2, r3] + 80078ba: fa21 f303 lsr.w r3, r1, r3 + 80078be: 4a09 ldr r2, [pc, #36] ; (80078e4 ) + 80078c0: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + 80078c2: 4b09 ldr r3, [pc, #36] ; (80078e8 ) + 80078c4: 681b ldr r3, [r3, #0] + 80078c6: 4618 mov r0, r3 + 80078c8: f7fc fcf6 bl 80042b8 + + return HAL_OK; + 80078cc: 2300 movs r3, #0 +} + 80078ce: 4618 mov r0, r3 + 80078d0: 3710 adds r7, #16 + 80078d2: 46bd mov sp, r7 + 80078d4: bd80 pop {r7, pc} + 80078d6: bf00 nop + 80078d8: 40023c00 .word 0x40023c00 + 80078dc: 40023800 .word 0x40023800 + 80078e0: 0800e370 .word 0x0800e370 + 80078e4: 2000003c .word 0x2000003c + 80078e8: 20000040 .word 0x20000040 + +080078ec : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80078ec: b5f0 push {r4, r5, r6, r7, lr} + 80078ee: b085 sub sp, #20 + 80078f0: af00 add r7, sp, #0 + uint32_t pllm = 0, pllvco = 0, pllp = 0; + 80078f2: 2300 movs r3, #0 + 80078f4: 607b str r3, [r7, #4] + 80078f6: 2300 movs r3, #0 + 80078f8: 60fb str r3, [r7, #12] + 80078fa: 2300 movs r3, #0 + 80078fc: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0; + 80078fe: 2300 movs r3, #0 + 8007900: 60bb str r3, [r7, #8] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + 8007902: 4b50 ldr r3, [pc, #320] ; (8007a44 ) + 8007904: 689b ldr r3, [r3, #8] + 8007906: f003 030c and.w r3, r3, #12 + 800790a: 2b04 cmp r3, #4 + 800790c: d007 beq.n 800791e + 800790e: 2b08 cmp r3, #8 + 8007910: d008 beq.n 8007924 + 8007912: 2b00 cmp r3, #0 + 8007914: f040 808d bne.w 8007a32 + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + 8007918: 4b4b ldr r3, [pc, #300] ; (8007a48 ) + 800791a: 60bb str r3, [r7, #8] + break; + 800791c: e08c b.n 8007a38 + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + 800791e: 4b4b ldr r3, [pc, #300] ; (8007a4c ) + 8007920: 60bb str r3, [r7, #8] + break; + 8007922: e089 b.n 8007a38 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 8007924: 4b47 ldr r3, [pc, #284] ; (8007a44 ) + 8007926: 685b ldr r3, [r3, #4] + 8007928: f003 033f and.w r3, r3, #63 ; 0x3f + 800792c: 607b str r3, [r7, #4] + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 800792e: 4b45 ldr r3, [pc, #276] ; (8007a44 ) + 8007930: 685b ldr r3, [r3, #4] + 8007932: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8007936: 2b00 cmp r3, #0 + 8007938: d023 beq.n 8007982 + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 800793a: 4b42 ldr r3, [pc, #264] ; (8007a44 ) + 800793c: 685b ldr r3, [r3, #4] + 800793e: 099b lsrs r3, r3, #6 + 8007940: f04f 0400 mov.w r4, #0 + 8007944: f240 11ff movw r1, #511 ; 0x1ff + 8007948: f04f 0200 mov.w r2, #0 + 800794c: ea03 0501 and.w r5, r3, r1 + 8007950: ea04 0602 and.w r6, r4, r2 + 8007954: 4a3d ldr r2, [pc, #244] ; (8007a4c ) + 8007956: fb02 f106 mul.w r1, r2, r6 + 800795a: 2200 movs r2, #0 + 800795c: fb02 f205 mul.w r2, r2, r5 + 8007960: 440a add r2, r1 + 8007962: 493a ldr r1, [pc, #232] ; (8007a4c ) + 8007964: fba5 0101 umull r0, r1, r5, r1 + 8007968: 1853 adds r3, r2, r1 + 800796a: 4619 mov r1, r3 + 800796c: 687b ldr r3, [r7, #4] + 800796e: f04f 0400 mov.w r4, #0 + 8007972: 461a mov r2, r3 + 8007974: 4623 mov r3, r4 + 8007976: f7f8 fc9b bl 80002b0 <__aeabi_uldivmod> + 800797a: 4603 mov r3, r0 + 800797c: 460c mov r4, r1 + 800797e: 60fb str r3, [r7, #12] + 8007980: e049 b.n 8007a16 + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8007982: 4b30 ldr r3, [pc, #192] ; (8007a44 ) + 8007984: 685b ldr r3, [r3, #4] + 8007986: 099b lsrs r3, r3, #6 + 8007988: f04f 0400 mov.w r4, #0 + 800798c: f240 11ff movw r1, #511 ; 0x1ff + 8007990: f04f 0200 mov.w r2, #0 + 8007994: ea03 0501 and.w r5, r3, r1 + 8007998: ea04 0602 and.w r6, r4, r2 + 800799c: 4629 mov r1, r5 + 800799e: 4632 mov r2, r6 + 80079a0: f04f 0300 mov.w r3, #0 + 80079a4: f04f 0400 mov.w r4, #0 + 80079a8: 0154 lsls r4, r2, #5 + 80079aa: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 80079ae: 014b lsls r3, r1, #5 + 80079b0: 4619 mov r1, r3 + 80079b2: 4622 mov r2, r4 + 80079b4: 1b49 subs r1, r1, r5 + 80079b6: eb62 0206 sbc.w r2, r2, r6 + 80079ba: f04f 0300 mov.w r3, #0 + 80079be: f04f 0400 mov.w r4, #0 + 80079c2: 0194 lsls r4, r2, #6 + 80079c4: ea44 6491 orr.w r4, r4, r1, lsr #26 + 80079c8: 018b lsls r3, r1, #6 + 80079ca: 1a5b subs r3, r3, r1 + 80079cc: eb64 0402 sbc.w r4, r4, r2 + 80079d0: f04f 0100 mov.w r1, #0 + 80079d4: f04f 0200 mov.w r2, #0 + 80079d8: 00e2 lsls r2, r4, #3 + 80079da: ea42 7253 orr.w r2, r2, r3, lsr #29 + 80079de: 00d9 lsls r1, r3, #3 + 80079e0: 460b mov r3, r1 + 80079e2: 4614 mov r4, r2 + 80079e4: 195b adds r3, r3, r5 + 80079e6: eb44 0406 adc.w r4, r4, r6 + 80079ea: f04f 0100 mov.w r1, #0 + 80079ee: f04f 0200 mov.w r2, #0 + 80079f2: 02a2 lsls r2, r4, #10 + 80079f4: ea42 5293 orr.w r2, r2, r3, lsr #22 + 80079f8: 0299 lsls r1, r3, #10 + 80079fa: 460b mov r3, r1 + 80079fc: 4614 mov r4, r2 + 80079fe: 4618 mov r0, r3 + 8007a00: 4621 mov r1, r4 + 8007a02: 687b ldr r3, [r7, #4] + 8007a04: f04f 0400 mov.w r4, #0 + 8007a08: 461a mov r2, r3 + 8007a0a: 4623 mov r3, r4 + 8007a0c: f7f8 fc50 bl 80002b0 <__aeabi_uldivmod> + 8007a10: 4603 mov r3, r0 + 8007a12: 460c mov r4, r1 + 8007a14: 60fb str r3, [r7, #12] + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + 8007a16: 4b0b ldr r3, [pc, #44] ; (8007a44 ) + 8007a18: 685b ldr r3, [r3, #4] + 8007a1a: 0c1b lsrs r3, r3, #16 + 8007a1c: f003 0303 and.w r3, r3, #3 + 8007a20: 3301 adds r3, #1 + 8007a22: 005b lsls r3, r3, #1 + 8007a24: 603b str r3, [r7, #0] + + sysclockfreq = pllvco / pllp; + 8007a26: 68fa ldr r2, [r7, #12] + 8007a28: 683b ldr r3, [r7, #0] + 8007a2a: fbb2 f3f3 udiv r3, r2, r3 + 8007a2e: 60bb str r3, [r7, #8] + break; + 8007a30: e002 b.n 8007a38 + } + default: + { + sysclockfreq = HSI_VALUE; + 8007a32: 4b05 ldr r3, [pc, #20] ; (8007a48 ) + 8007a34: 60bb str r3, [r7, #8] + break; + 8007a36: bf00 nop + } + } + return sysclockfreq; + 8007a38: 68bb ldr r3, [r7, #8] +} + 8007a3a: 4618 mov r0, r3 + 8007a3c: 3714 adds r7, #20 + 8007a3e: 46bd mov sp, r7 + 8007a40: bdf0 pop {r4, r5, r6, r7, pc} + 8007a42: bf00 nop + 8007a44: 40023800 .word 0x40023800 + 8007a48: 00f42400 .word 0x00f42400 + 8007a4c: 017d7840 .word 0x017d7840 + +08007a50 : + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8007a50: b480 push {r7} + 8007a52: af00 add r7, sp, #0 + return SystemCoreClock; + 8007a54: 4b03 ldr r3, [pc, #12] ; (8007a64 ) + 8007a56: 681b ldr r3, [r3, #0] +} + 8007a58: 4618 mov r0, r3 + 8007a5a: 46bd mov sp, r7 + 8007a5c: f85d 7b04 ldr.w r7, [sp], #4 + 8007a60: 4770 bx lr + 8007a62: bf00 nop + 8007a64: 2000003c .word 0x2000003c + +08007a68 : + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8007a68: b580 push {r7, lr} + 8007a6a: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); + 8007a6c: f7ff fff0 bl 8007a50 + 8007a70: 4601 mov r1, r0 + 8007a72: 4b05 ldr r3, [pc, #20] ; (8007a88 ) + 8007a74: 689b ldr r3, [r3, #8] + 8007a76: 0a9b lsrs r3, r3, #10 + 8007a78: f003 0307 and.w r3, r3, #7 + 8007a7c: 4a03 ldr r2, [pc, #12] ; (8007a8c ) + 8007a7e: 5cd3 ldrb r3, [r2, r3] + 8007a80: fa21 f303 lsr.w r3, r1, r3 +} + 8007a84: 4618 mov r0, r3 + 8007a86: bd80 pop {r7, pc} + 8007a88: 40023800 .word 0x40023800 + 8007a8c: 0800e380 .word 0x0800e380 + +08007a90 : + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 8007a90: b580 push {r7, lr} + 8007a92: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); + 8007a94: f7ff ffdc bl 8007a50 + 8007a98: 4601 mov r1, r0 + 8007a9a: 4b05 ldr r3, [pc, #20] ; (8007ab0 ) + 8007a9c: 689b ldr r3, [r3, #8] + 8007a9e: 0b5b lsrs r3, r3, #13 + 8007aa0: f003 0307 and.w r3, r3, #7 + 8007aa4: 4a03 ldr r2, [pc, #12] ; (8007ab4 ) + 8007aa6: 5cd3 ldrb r3, [r2, r3] + 8007aa8: fa21 f303 lsr.w r3, r1, r3 +} + 8007aac: 4618 mov r0, r3 + 8007aae: bd80 pop {r7, pc} + 8007ab0: 40023800 .word 0x40023800 + 8007ab4: 0800e380 .word 0x0800e380 + +08007ab8 : + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + 8007ab8: b480 push {r7} + 8007aba: b083 sub sp, #12 + 8007abc: af00 add r7, sp, #0 + 8007abe: 6078 str r0, [r7, #4] + 8007ac0: 6039 str r1, [r7, #0] + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + 8007ac2: 687b ldr r3, [r7, #4] + 8007ac4: 220f movs r2, #15 + 8007ac6: 601a str r2, [r3, #0] + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 8007ac8: 4b12 ldr r3, [pc, #72] ; (8007b14 ) + 8007aca: 689b ldr r3, [r3, #8] + 8007acc: f003 0203 and.w r2, r3, #3 + 8007ad0: 687b ldr r3, [r7, #4] + 8007ad2: 605a str r2, [r3, #4] + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 8007ad4: 4b0f ldr r3, [pc, #60] ; (8007b14 ) + 8007ad6: 689b ldr r3, [r3, #8] + 8007ad8: f003 02f0 and.w r2, r3, #240 ; 0xf0 + 8007adc: 687b ldr r3, [r7, #4] + 8007ade: 609a str r2, [r3, #8] + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 8007ae0: 4b0c ldr r3, [pc, #48] ; (8007b14 ) + 8007ae2: 689b ldr r3, [r3, #8] + 8007ae4: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 8007ae8: 687b ldr r3, [r7, #4] + 8007aea: 60da str r2, [r3, #12] + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + 8007aec: 4b09 ldr r3, [pc, #36] ; (8007b14 ) + 8007aee: 689b ldr r3, [r3, #8] + 8007af0: 08db lsrs r3, r3, #3 + 8007af2: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 8007af6: 687b ldr r3, [r7, #4] + 8007af8: 611a str r2, [r3, #16] + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 8007afa: 4b07 ldr r3, [pc, #28] ; (8007b18 ) + 8007afc: 681b ldr r3, [r3, #0] + 8007afe: f003 020f and.w r2, r3, #15 + 8007b02: 683b ldr r3, [r7, #0] + 8007b04: 601a str r2, [r3, #0] +} + 8007b06: bf00 nop + 8007b08: 370c adds r7, #12 + 8007b0a: 46bd mov sp, r7 + 8007b0c: f85d 7b04 ldr.w r7, [sp], #4 + 8007b10: 4770 bx lr + 8007b12: bf00 nop + 8007b14: 40023800 .word 0x40023800 + 8007b18: 40023c00 .word 0x40023c00 + +08007b1c : + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8007b1c: b580 push {r7, lr} + 8007b1e: b088 sub sp, #32 + 8007b20: af00 add r7, sp, #0 + 8007b22: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 8007b24: 2300 movs r3, #0 + 8007b26: 617b str r3, [r7, #20] + uint32_t tmpreg0 = 0; + 8007b28: 2300 movs r3, #0 + 8007b2a: 613b str r3, [r7, #16] + uint32_t tmpreg1 = 0; + 8007b2c: 2300 movs r3, #0 + 8007b2e: 60fb str r3, [r7, #12] + uint32_t plli2sused = 0; + 8007b30: 2300 movs r3, #0 + 8007b32: 61fb str r3, [r7, #28] + uint32_t pllsaiused = 0; + 8007b34: 2300 movs r3, #0 + 8007b36: 61bb str r3, [r7, #24] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 8007b38: 687b ldr r3, [r7, #4] + 8007b3a: 681b ldr r3, [r3, #0] + 8007b3c: f003 0301 and.w r3, r3, #1 + 8007b40: 2b00 cmp r3, #0 + 8007b42: d012 beq.n 8007b6a + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 8007b44: 4b69 ldr r3, [pc, #420] ; (8007cec ) + 8007b46: 689b ldr r3, [r3, #8] + 8007b48: 4a68 ldr r2, [pc, #416] ; (8007cec ) + 8007b4a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8007b4e: 6093 str r3, [r2, #8] + 8007b50: 4b66 ldr r3, [pc, #408] ; (8007cec ) + 8007b52: 689a ldr r2, [r3, #8] + 8007b54: 687b ldr r3, [r7, #4] + 8007b56: 6b5b ldr r3, [r3, #52] ; 0x34 + 8007b58: 4964 ldr r1, [pc, #400] ; (8007cec ) + 8007b5a: 4313 orrs r3, r2 + 8007b5c: 608b str r3, [r1, #8] + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 8007b5e: 687b ldr r3, [r7, #4] + 8007b60: 6b5b ldr r3, [r3, #52] ; 0x34 + 8007b62: 2b00 cmp r3, #0 + 8007b64: d101 bne.n 8007b6a + { + plli2sused = 1; + 8007b66: 2301 movs r3, #1 + 8007b68: 61fb str r3, [r7, #28] + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 8007b6a: 687b ldr r3, [r7, #4] + 8007b6c: 681b ldr r3, [r3, #0] + 8007b6e: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8007b72: 2b00 cmp r3, #0 + 8007b74: d017 beq.n 8007ba6 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 8007b76: 4b5d ldr r3, [pc, #372] ; (8007cec ) + 8007b78: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8007b7c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8007b80: 687b ldr r3, [r7, #4] + 8007b82: 6bdb ldr r3, [r3, #60] ; 0x3c + 8007b84: 4959 ldr r1, [pc, #356] ; (8007cec ) + 8007b86: 4313 orrs r3, r2 + 8007b88: f8c1 308c str.w r3, [r1, #140] ; 0x8c + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 8007b8c: 687b ldr r3, [r7, #4] + 8007b8e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8007b90: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8007b94: d101 bne.n 8007b9a + { + plli2sused = 1; + 8007b96: 2301 movs r3, #1 + 8007b98: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 8007b9a: 687b ldr r3, [r7, #4] + 8007b9c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8007b9e: 2b00 cmp r3, #0 + 8007ba0: d101 bne.n 8007ba6 + { + pllsaiused = 1; + 8007ba2: 2301 movs r3, #1 + 8007ba4: 61bb str r3, [r7, #24] + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 8007ba6: 687b ldr r3, [r7, #4] + 8007ba8: 681b ldr r3, [r3, #0] + 8007baa: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8007bae: 2b00 cmp r3, #0 + 8007bb0: d017 beq.n 8007be2 + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 8007bb2: 4b4e ldr r3, [pc, #312] ; (8007cec ) + 8007bb4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8007bb8: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8007bbc: 687b ldr r3, [r7, #4] + 8007bbe: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007bc0: 494a ldr r1, [pc, #296] ; (8007cec ) + 8007bc2: 4313 orrs r3, r2 + 8007bc4: f8c1 308c str.w r3, [r1, #140] ; 0x8c + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 8007bc8: 687b ldr r3, [r7, #4] + 8007bca: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007bcc: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8007bd0: d101 bne.n 8007bd6 + { + plli2sused = 1; + 8007bd2: 2301 movs r3, #1 + 8007bd4: 61fb str r3, [r7, #28] + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 8007bd6: 687b ldr r3, [r7, #4] + 8007bd8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007bda: 2b00 cmp r3, #0 + 8007bdc: d101 bne.n 8007be2 + { + pllsaiused = 1; + 8007bde: 2301 movs r3, #1 + 8007be0: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 8007be2: 687b ldr r3, [r7, #4] + 8007be4: 681b ldr r3, [r3, #0] + 8007be6: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8007bea: 2b00 cmp r3, #0 + 8007bec: d001 beq.n 8007bf2 + { + plli2sused = 1; + 8007bee: 2301 movs r3, #1 + 8007bf0: 61fb str r3, [r7, #28] + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8007bf2: 687b ldr r3, [r7, #4] + 8007bf4: 681b ldr r3, [r3, #0] + 8007bf6: f003 0320 and.w r3, r3, #32 + 8007bfa: 2b00 cmp r3, #0 + 8007bfc: f000 808b beq.w 8007d16 + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8007c00: 4b3a ldr r3, [pc, #232] ; (8007cec ) + 8007c02: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007c04: 4a39 ldr r2, [pc, #228] ; (8007cec ) + 8007c06: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8007c0a: 6413 str r3, [r2, #64] ; 0x40 + 8007c0c: 4b37 ldr r3, [pc, #220] ; (8007cec ) + 8007c0e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8007c10: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8007c14: 60bb str r3, [r7, #8] + 8007c16: 68bb ldr r3, [r7, #8] + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8007c18: 4b35 ldr r3, [pc, #212] ; (8007cf0 ) + 8007c1a: 681b ldr r3, [r3, #0] + 8007c1c: 4a34 ldr r2, [pc, #208] ; (8007cf0 ) + 8007c1e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8007c22: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007c24: f7fc fc64 bl 80044f0 + 8007c28: 6178 str r0, [r7, #20] + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8007c2a: e008 b.n 8007c3e + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8007c2c: f7fc fc60 bl 80044f0 + 8007c30: 4602 mov r2, r0 + 8007c32: 697b ldr r3, [r7, #20] + 8007c34: 1ad3 subs r3, r2, r3 + 8007c36: 2b64 cmp r3, #100 ; 0x64 + 8007c38: d901 bls.n 8007c3e + { + return HAL_TIMEOUT; + 8007c3a: 2303 movs r3, #3 + 8007c3c: e355 b.n 80082ea + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 8007c3e: 4b2c ldr r3, [pc, #176] ; (8007cf0 ) + 8007c40: 681b ldr r3, [r3, #0] + 8007c42: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007c46: 2b00 cmp r3, #0 + 8007c48: d0f0 beq.n 8007c2c + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8007c4a: 4b28 ldr r3, [pc, #160] ; (8007cec ) + 8007c4c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007c4e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8007c52: 613b str r3, [r7, #16] + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8007c54: 693b ldr r3, [r7, #16] + 8007c56: 2b00 cmp r3, #0 + 8007c58: d035 beq.n 8007cc6 + 8007c5a: 687b ldr r3, [r7, #4] + 8007c5c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8007c5e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8007c62: 693a ldr r2, [r7, #16] + 8007c64: 429a cmp r2, r3 + 8007c66: d02e beq.n 8007cc6 + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8007c68: 4b20 ldr r3, [pc, #128] ; (8007cec ) + 8007c6a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007c6c: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8007c70: 613b str r3, [r7, #16] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 8007c72: 4b1e ldr r3, [pc, #120] ; (8007cec ) + 8007c74: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007c76: 4a1d ldr r2, [pc, #116] ; (8007cec ) + 8007c78: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8007c7c: 6713 str r3, [r2, #112] ; 0x70 + __HAL_RCC_BACKUPRESET_RELEASE(); + 8007c7e: 4b1b ldr r3, [pc, #108] ; (8007cec ) + 8007c80: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007c82: 4a1a ldr r2, [pc, #104] ; (8007cec ) + 8007c84: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8007c88: 6713 str r3, [r2, #112] ; 0x70 + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + 8007c8a: 4a18 ldr r2, [pc, #96] ; (8007cec ) + 8007c8c: 693b ldr r3, [r7, #16] + 8007c8e: 6713 str r3, [r2, #112] ; 0x70 + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8007c90: 4b16 ldr r3, [pc, #88] ; (8007cec ) + 8007c92: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007c94: f003 0301 and.w r3, r3, #1 + 8007c98: 2b01 cmp r3, #1 + 8007c9a: d114 bne.n 8007cc6 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007c9c: f7fc fc28 bl 80044f0 + 8007ca0: 6178 str r0, [r7, #20] + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007ca2: e00a b.n 8007cba + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8007ca4: f7fc fc24 bl 80044f0 + 8007ca8: 4602 mov r2, r0 + 8007caa: 697b ldr r3, [r7, #20] + 8007cac: 1ad3 subs r3, r2, r3 + 8007cae: f241 3288 movw r2, #5000 ; 0x1388 + 8007cb2: 4293 cmp r3, r2 + 8007cb4: d901 bls.n 8007cba + { + return HAL_TIMEOUT; + 8007cb6: 2303 movs r3, #3 + 8007cb8: e317 b.n 80082ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8007cba: 4b0c ldr r3, [pc, #48] ; (8007cec ) + 8007cbc: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007cbe: f003 0302 and.w r3, r3, #2 + 8007cc2: 2b00 cmp r3, #0 + 8007cc4: d0ee beq.n 8007ca4 + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8007cc6: 687b ldr r3, [r7, #4] + 8007cc8: 6b1b ldr r3, [r3, #48] ; 0x30 + 8007cca: f403 7340 and.w r3, r3, #768 ; 0x300 + 8007cce: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8007cd2: d111 bne.n 8007cf8 + 8007cd4: 4b05 ldr r3, [pc, #20] ; (8007cec ) + 8007cd6: 689b ldr r3, [r3, #8] + 8007cd8: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8007cdc: 687b ldr r3, [r7, #4] + 8007cde: 6b19 ldr r1, [r3, #48] ; 0x30 + 8007ce0: 4b04 ldr r3, [pc, #16] ; (8007cf4 ) + 8007ce2: 400b ands r3, r1 + 8007ce4: 4901 ldr r1, [pc, #4] ; (8007cec ) + 8007ce6: 4313 orrs r3, r2 + 8007ce8: 608b str r3, [r1, #8] + 8007cea: e00b b.n 8007d04 + 8007cec: 40023800 .word 0x40023800 + 8007cf0: 40007000 .word 0x40007000 + 8007cf4: 0ffffcff .word 0x0ffffcff + 8007cf8: 4bb0 ldr r3, [pc, #704] ; (8007fbc ) + 8007cfa: 689b ldr r3, [r3, #8] + 8007cfc: 4aaf ldr r2, [pc, #700] ; (8007fbc ) + 8007cfe: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8007d02: 6093 str r3, [r2, #8] + 8007d04: 4bad ldr r3, [pc, #692] ; (8007fbc ) + 8007d06: 6f1a ldr r2, [r3, #112] ; 0x70 + 8007d08: 687b ldr r3, [r7, #4] + 8007d0a: 6b1b ldr r3, [r3, #48] ; 0x30 + 8007d0c: f3c3 030b ubfx r3, r3, #0, #12 + 8007d10: 49aa ldr r1, [pc, #680] ; (8007fbc ) + 8007d12: 4313 orrs r3, r2 + 8007d14: 670b str r3, [r1, #112] ; 0x70 + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 8007d16: 687b ldr r3, [r7, #4] + 8007d18: 681b ldr r3, [r3, #0] + 8007d1a: f003 0310 and.w r3, r3, #16 + 8007d1e: 2b00 cmp r3, #0 + 8007d20: d010 beq.n 8007d44 + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8007d22: 4ba6 ldr r3, [pc, #664] ; (8007fbc ) + 8007d24: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8007d28: 4aa4 ldr r2, [pc, #656] ; (8007fbc ) + 8007d2a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8007d2e: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 8007d32: 4ba2 ldr r3, [pc, #648] ; (8007fbc ) + 8007d34: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 8007d38: 687b ldr r3, [r7, #4] + 8007d3a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8007d3c: 499f ldr r1, [pc, #636] ; (8007fbc ) + 8007d3e: 4313 orrs r3, r2 + 8007d40: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8007d44: 687b ldr r3, [r7, #4] + 8007d46: 681b ldr r3, [r3, #0] + 8007d48: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8007d4c: 2b00 cmp r3, #0 + 8007d4e: d00a beq.n 8007d66 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8007d50: 4b9a ldr r3, [pc, #616] ; (8007fbc ) + 8007d52: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007d56: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8007d5a: 687b ldr r3, [r7, #4] + 8007d5c: 6e5b ldr r3, [r3, #100] ; 0x64 + 8007d5e: 4997 ldr r1, [pc, #604] ; (8007fbc ) + 8007d60: 4313 orrs r3, r2 + 8007d62: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8007d66: 687b ldr r3, [r7, #4] + 8007d68: 681b ldr r3, [r3, #0] + 8007d6a: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8007d6e: 2b00 cmp r3, #0 + 8007d70: d00a beq.n 8007d88 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8007d72: 4b92 ldr r3, [pc, #584] ; (8007fbc ) + 8007d74: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007d78: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8007d7c: 687b ldr r3, [r7, #4] + 8007d7e: 6e9b ldr r3, [r3, #104] ; 0x68 + 8007d80: 498e ldr r1, [pc, #568] ; (8007fbc ) + 8007d82: 4313 orrs r3, r2 + 8007d84: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 8007d88: 687b ldr r3, [r7, #4] + 8007d8a: 681b ldr r3, [r3, #0] + 8007d8c: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8007d90: 2b00 cmp r3, #0 + 8007d92: d00a beq.n 8007daa + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 8007d94: 4b89 ldr r3, [pc, #548] ; (8007fbc ) + 8007d96: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007d9a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8007d9e: 687b ldr r3, [r7, #4] + 8007da0: 6edb ldr r3, [r3, #108] ; 0x6c + 8007da2: 4986 ldr r1, [pc, #536] ; (8007fbc ) + 8007da4: 4313 orrs r3, r2 + 8007da6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 8007daa: 687b ldr r3, [r7, #4] + 8007dac: 681b ldr r3, [r3, #0] + 8007dae: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8007db2: 2b00 cmp r3, #0 + 8007db4: d00a beq.n 8007dcc + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 8007db6: 4b81 ldr r3, [pc, #516] ; (8007fbc ) + 8007db8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007dbc: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8007dc0: 687b ldr r3, [r7, #4] + 8007dc2: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007dc4: 497d ldr r1, [pc, #500] ; (8007fbc ) + 8007dc6: 4313 orrs r3, r2 + 8007dc8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8007dcc: 687b ldr r3, [r7, #4] + 8007dce: 681b ldr r3, [r3, #0] + 8007dd0: f003 0340 and.w r3, r3, #64 ; 0x40 + 8007dd4: 2b00 cmp r3, #0 + 8007dd6: d00a beq.n 8007dee + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8007dd8: 4b78 ldr r3, [pc, #480] ; (8007fbc ) + 8007dda: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007dde: f023 0203 bic.w r2, r3, #3 + 8007de2: 687b ldr r3, [r7, #4] + 8007de4: 6c5b ldr r3, [r3, #68] ; 0x44 + 8007de6: 4975 ldr r1, [pc, #468] ; (8007fbc ) + 8007de8: 4313 orrs r3, r2 + 8007dea: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8007dee: 687b ldr r3, [r7, #4] + 8007df0: 681b ldr r3, [r3, #0] + 8007df2: f003 0380 and.w r3, r3, #128 ; 0x80 + 8007df6: 2b00 cmp r3, #0 + 8007df8: d00a beq.n 8007e10 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8007dfa: 4b70 ldr r3, [pc, #448] ; (8007fbc ) + 8007dfc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007e00: f023 020c bic.w r2, r3, #12 + 8007e04: 687b ldr r3, [r7, #4] + 8007e06: 6c9b ldr r3, [r3, #72] ; 0x48 + 8007e08: 496c ldr r1, [pc, #432] ; (8007fbc ) + 8007e0a: 4313 orrs r3, r2 + 8007e0c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8007e10: 687b ldr r3, [r7, #4] + 8007e12: 681b ldr r3, [r3, #0] + 8007e14: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007e18: 2b00 cmp r3, #0 + 8007e1a: d00a beq.n 8007e32 + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 8007e1c: 4b67 ldr r3, [pc, #412] ; (8007fbc ) + 8007e1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007e22: f023 0230 bic.w r2, r3, #48 ; 0x30 + 8007e26: 687b ldr r3, [r7, #4] + 8007e28: 6cdb ldr r3, [r3, #76] ; 0x4c + 8007e2a: 4964 ldr r1, [pc, #400] ; (8007fbc ) + 8007e2c: 4313 orrs r3, r2 + 8007e2e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 8007e32: 687b ldr r3, [r7, #4] + 8007e34: 681b ldr r3, [r3, #0] + 8007e36: f403 7300 and.w r3, r3, #512 ; 0x200 + 8007e3a: 2b00 cmp r3, #0 + 8007e3c: d00a beq.n 8007e54 + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 8007e3e: 4b5f ldr r3, [pc, #380] ; (8007fbc ) + 8007e40: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007e44: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 8007e48: 687b ldr r3, [r7, #4] + 8007e4a: 6d1b ldr r3, [r3, #80] ; 0x50 + 8007e4c: 495b ldr r1, [pc, #364] ; (8007fbc ) + 8007e4e: 4313 orrs r3, r2 + 8007e50: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 8007e54: 687b ldr r3, [r7, #4] + 8007e56: 681b ldr r3, [r3, #0] + 8007e58: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8007e5c: 2b00 cmp r3, #0 + 8007e5e: d00a beq.n 8007e76 + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 8007e60: 4b56 ldr r3, [pc, #344] ; (8007fbc ) + 8007e62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007e66: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8007e6a: 687b ldr r3, [r7, #4] + 8007e6c: 6d5b ldr r3, [r3, #84] ; 0x54 + 8007e6e: 4953 ldr r1, [pc, #332] ; (8007fbc ) + 8007e70: 4313 orrs r3, r2 + 8007e72: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 8007e76: 687b ldr r3, [r7, #4] + 8007e78: 681b ldr r3, [r3, #0] + 8007e7a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8007e7e: 2b00 cmp r3, #0 + 8007e80: d00a beq.n 8007e98 + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 8007e82: 4b4e ldr r3, [pc, #312] ; (8007fbc ) + 8007e84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007e88: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8007e8c: 687b ldr r3, [r7, #4] + 8007e8e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8007e90: 494a ldr r1, [pc, #296] ; (8007fbc ) + 8007e92: 4313 orrs r3, r2 + 8007e94: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 8007e98: 687b ldr r3, [r7, #4] + 8007e9a: 681b ldr r3, [r3, #0] + 8007e9c: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8007ea0: 2b00 cmp r3, #0 + 8007ea2: d00a beq.n 8007eba + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 8007ea4: 4b45 ldr r3, [pc, #276] ; (8007fbc ) + 8007ea6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007eaa: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 8007eae: 687b ldr r3, [r7, #4] + 8007eb0: 6ddb ldr r3, [r3, #92] ; 0x5c + 8007eb2: 4942 ldr r1, [pc, #264] ; (8007fbc ) + 8007eb4: 4313 orrs r3, r2 + 8007eb6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 8007eba: 687b ldr r3, [r7, #4] + 8007ebc: 681b ldr r3, [r3, #0] + 8007ebe: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8007ec2: 2b00 cmp r3, #0 + 8007ec4: d00a beq.n 8007edc + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 8007ec6: 4b3d ldr r3, [pc, #244] ; (8007fbc ) + 8007ec8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007ecc: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8007ed0: 687b ldr r3, [r7, #4] + 8007ed2: 6e1b ldr r3, [r3, #96] ; 0x60 + 8007ed4: 4939 ldr r1, [pc, #228] ; (8007fbc ) + 8007ed6: 4313 orrs r3, r2 + 8007ed8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 8007edc: 687b ldr r3, [r7, #4] + 8007ede: 681b ldr r3, [r3, #0] + 8007ee0: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8007ee4: 2b00 cmp r3, #0 + 8007ee6: d00a beq.n 8007efe + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 8007ee8: 4b34 ldr r3, [pc, #208] ; (8007fbc ) + 8007eea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007eee: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8007ef2: 687b ldr r3, [r7, #4] + 8007ef4: 6f9b ldr r3, [r3, #120] ; 0x78 + 8007ef6: 4931 ldr r1, [pc, #196] ; (8007fbc ) + 8007ef8: 4313 orrs r3, r2 + 8007efa: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 8007efe: 687b ldr r3, [r7, #4] + 8007f00: 681b ldr r3, [r3, #0] + 8007f02: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8007f06: 2b00 cmp r3, #0 + 8007f08: d011 beq.n 8007f2e + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 8007f0a: 4b2c ldr r3, [pc, #176] ; (8007fbc ) + 8007f0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007f10: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8007f14: 687b ldr r3, [r7, #4] + 8007f16: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007f18: 4928 ldr r1, [pc, #160] ; (8007fbc ) + 8007f1a: 4313 orrs r3, r2 + 8007f1c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 8007f20: 687b ldr r3, [r7, #4] + 8007f22: 6fdb ldr r3, [r3, #124] ; 0x7c + 8007f24: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8007f28: d101 bne.n 8007f2e + { + pllsaiused = 1; + 8007f2a: 2301 movs r3, #1 + 8007f2c: 61bb str r3, [r7, #24] + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 8007f2e: 687b ldr r3, [r7, #4] + 8007f30: 681b ldr r3, [r3, #0] + 8007f32: f003 0308 and.w r3, r3, #8 + 8007f36: 2b00 cmp r3, #0 + 8007f38: d001 beq.n 8007f3e + { + pllsaiused = 1; + 8007f3a: 2301 movs r3, #1 + 8007f3c: 61bb str r3, [r7, #24] + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 8007f3e: 687b ldr r3, [r7, #4] + 8007f40: 681b ldr r3, [r3, #0] + 8007f42: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8007f46: 2b00 cmp r3, #0 + 8007f48: d00a beq.n 8007f60 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 8007f4a: 4b1c ldr r3, [pc, #112] ; (8007fbc ) + 8007f4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007f50: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 8007f54: 687b ldr r3, [r7, #4] + 8007f56: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007f58: 4918 ldr r1, [pc, #96] ; (8007fbc ) + 8007f5a: 4313 orrs r3, r2 + 8007f5c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 8007f60: 687b ldr r3, [r7, #4] + 8007f62: 681b ldr r3, [r3, #0] + 8007f64: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8007f68: 2b00 cmp r3, #0 + 8007f6a: d00b beq.n 8007f84 + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 8007f6c: 4b13 ldr r3, [pc, #76] ; (8007fbc ) + 8007f6e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007f72: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 8007f76: 687b ldr r3, [r7, #4] + 8007f78: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8007f7c: 490f ldr r1, [pc, #60] ; (8007fbc ) + 8007f7e: 4313 orrs r3, r2 + 8007f80: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + 8007f84: 69fb ldr r3, [r7, #28] + 8007f86: 2b01 cmp r3, #1 + 8007f88: d005 beq.n 8007f96 + 8007f8a: 687b ldr r3, [r7, #4] + 8007f8c: 681b ldr r3, [r3, #0] + 8007f8e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8007f92: f040 80d8 bne.w 8008146 + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 8007f96: 4b09 ldr r3, [pc, #36] ; (8007fbc ) + 8007f98: 681b ldr r3, [r3, #0] + 8007f9a: 4a08 ldr r2, [pc, #32] ; (8007fbc ) + 8007f9c: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8007fa0: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8007fa2: f7fc faa5 bl 80044f0 + 8007fa6: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8007fa8: e00a b.n 8007fc0 + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 8007faa: f7fc faa1 bl 80044f0 + 8007fae: 4602 mov r2, r0 + 8007fb0: 697b ldr r3, [r7, #20] + 8007fb2: 1ad3 subs r3, r2, r3 + 8007fb4: 2b64 cmp r3, #100 ; 0x64 + 8007fb6: d903 bls.n 8007fc0 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8007fb8: 2303 movs r3, #3 + 8007fba: e196 b.n 80082ea + 8007fbc: 40023800 .word 0x40023800 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8007fc0: 4b6c ldr r3, [pc, #432] ; (8008174 ) + 8007fc2: 681b ldr r3, [r3, #0] + 8007fc4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8007fc8: 2b00 cmp r3, #0 + 8007fca: d1ee bne.n 8007faa + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + 8007fcc: 687b ldr r3, [r7, #4] + 8007fce: 681b ldr r3, [r3, #0] + 8007fd0: f003 0301 and.w r3, r3, #1 + 8007fd4: 2b00 cmp r3, #0 + 8007fd6: d021 beq.n 800801c + 8007fd8: 687b ldr r3, [r7, #4] + 8007fda: 6b5b ldr r3, [r3, #52] ; 0x34 + 8007fdc: 2b00 cmp r3, #0 + 8007fde: d11d bne.n 800801c + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 8007fe0: 4b64 ldr r3, [pc, #400] ; (8008174 ) + 8007fe2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8007fe6: 0c1b lsrs r3, r3, #16 + 8007fe8: f003 0303 and.w r3, r3, #3 + 8007fec: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 8007fee: 4b61 ldr r3, [pc, #388] ; (8008174 ) + 8007ff0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8007ff4: 0e1b lsrs r3, r3, #24 + 8007ff6: f003 030f and.w r3, r3, #15 + 8007ffa: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + 8007ffc: 687b ldr r3, [r7, #4] + 8007ffe: 685b ldr r3, [r3, #4] + 8008000: 019a lsls r2, r3, #6 + 8008002: 693b ldr r3, [r7, #16] + 8008004: 041b lsls r3, r3, #16 + 8008006: 431a orrs r2, r3 + 8008008: 68fb ldr r3, [r7, #12] + 800800a: 061b lsls r3, r3, #24 + 800800c: 431a orrs r2, r3 + 800800e: 687b ldr r3, [r7, #4] + 8008010: 689b ldr r3, [r3, #8] + 8008012: 071b lsls r3, r3, #28 + 8008014: 4957 ldr r1, [pc, #348] ; (8008174 ) + 8008016: 4313 orrs r3, r2 + 8008018: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 800801c: 687b ldr r3, [r7, #4] + 800801e: 681b ldr r3, [r3, #0] + 8008020: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8008024: 2b00 cmp r3, #0 + 8008026: d004 beq.n 8008032 + 8008028: 687b ldr r3, [r7, #4] + 800802a: 6bdb ldr r3, [r3, #60] ; 0x3c + 800802c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8008030: d00a beq.n 8008048 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 8008032: 687b ldr r3, [r7, #4] + 8008034: 681b ldr r3, [r3, #0] + 8008036: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + 800803a: 2b00 cmp r3, #0 + 800803c: d02e beq.n 800809c + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + 800803e: 687b ldr r3, [r7, #4] + 8008040: 6c1b ldr r3, [r3, #64] ; 0x40 + 8008042: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8008046: d129 bne.n 800809c + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 8008048: 4b4a ldr r3, [pc, #296] ; (8008174 ) + 800804a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800804e: 0c1b lsrs r3, r3, #16 + 8008050: f003 0303 and.w r3, r3, #3 + 8008054: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 8008056: 4b47 ldr r3, [pc, #284] ; (8008174 ) + 8008058: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800805c: 0f1b lsrs r3, r3, #28 + 800805e: f003 0307 and.w r3, r3, #7 + 8008062: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + 8008064: 687b ldr r3, [r7, #4] + 8008066: 685b ldr r3, [r3, #4] + 8008068: 019a lsls r2, r3, #6 + 800806a: 693b ldr r3, [r7, #16] + 800806c: 041b lsls r3, r3, #16 + 800806e: 431a orrs r2, r3 + 8008070: 687b ldr r3, [r7, #4] + 8008072: 68db ldr r3, [r3, #12] + 8008074: 061b lsls r3, r3, #24 + 8008076: 431a orrs r2, r3 + 8008078: 68fb ldr r3, [r7, #12] + 800807a: 071b lsls r3, r3, #28 + 800807c: 493d ldr r1, [pc, #244] ; (8008174 ) + 800807e: 4313 orrs r3, r2 + 8008080: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 8008084: 4b3b ldr r3, [pc, #236] ; (8008174 ) + 8008086: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800808a: f023 021f bic.w r2, r3, #31 + 800808e: 687b ldr r3, [r7, #4] + 8008090: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008092: 3b01 subs r3, #1 + 8008094: 4937 ldr r1, [pc, #220] ; (8008174 ) + 8008096: 4313 orrs r3, r2 + 8008098: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 800809c: 687b ldr r3, [r7, #4] + 800809e: 681b ldr r3, [r3, #0] + 80080a0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 80080a4: 2b00 cmp r3, #0 + 80080a6: d01d beq.n 80080e4 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 80080a8: 4b32 ldr r3, [pc, #200] ; (8008174 ) + 80080aa: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80080ae: 0e1b lsrs r3, r3, #24 + 80080b0: f003 030f and.w r3, r3, #15 + 80080b4: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 80080b6: 4b2f ldr r3, [pc, #188] ; (8008174 ) + 80080b8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80080bc: 0f1b lsrs r3, r3, #28 + 80080be: f003 0307 and.w r3, r3, #7 + 80080c2: 60fb str r3, [r7, #12] + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + 80080c4: 687b ldr r3, [r7, #4] + 80080c6: 685b ldr r3, [r3, #4] + 80080c8: 019a lsls r2, r3, #6 + 80080ca: 687b ldr r3, [r7, #4] + 80080cc: 691b ldr r3, [r3, #16] + 80080ce: 041b lsls r3, r3, #16 + 80080d0: 431a orrs r2, r3 + 80080d2: 693b ldr r3, [r7, #16] + 80080d4: 061b lsls r3, r3, #24 + 80080d6: 431a orrs r2, r3 + 80080d8: 68fb ldr r3, [r7, #12] + 80080da: 071b lsls r3, r3, #28 + 80080dc: 4925 ldr r1, [pc, #148] ; (8008174 ) + 80080de: 4313 orrs r3, r2 + 80080e0: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 80080e4: 687b ldr r3, [r7, #4] + 80080e6: 681b ldr r3, [r3, #0] + 80080e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80080ec: 2b00 cmp r3, #0 + 80080ee: d011 beq.n 8008114 + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + 80080f0: 687b ldr r3, [r7, #4] + 80080f2: 685b ldr r3, [r3, #4] + 80080f4: 019a lsls r2, r3, #6 + 80080f6: 687b ldr r3, [r7, #4] + 80080f8: 691b ldr r3, [r3, #16] + 80080fa: 041b lsls r3, r3, #16 + 80080fc: 431a orrs r2, r3 + 80080fe: 687b ldr r3, [r7, #4] + 8008100: 68db ldr r3, [r3, #12] + 8008102: 061b lsls r3, r3, #24 + 8008104: 431a orrs r2, r3 + 8008106: 687b ldr r3, [r7, #4] + 8008108: 689b ldr r3, [r3, #8] + 800810a: 071b lsls r3, r3, #28 + 800810c: 4919 ldr r1, [pc, #100] ; (8008174 ) + 800810e: 4313 orrs r3, r2 + 8008110: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 8008114: 4b17 ldr r3, [pc, #92] ; (8008174 ) + 8008116: 681b ldr r3, [r3, #0] + 8008118: 4a16 ldr r2, [pc, #88] ; (8008174 ) + 800811a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 800811e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8008120: f7fc f9e6 bl 80044f0 + 8008124: 6178 str r0, [r7, #20] + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8008126: e008 b.n 800813a + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 8008128: f7fc f9e2 bl 80044f0 + 800812c: 4602 mov r2, r0 + 800812e: 697b ldr r3, [r7, #20] + 8008130: 1ad3 subs r3, r2, r3 + 8008132: 2b64 cmp r3, #100 ; 0x64 + 8008134: d901 bls.n 800813a + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8008136: 2303 movs r3, #3 + 8008138: e0d7 b.n 80082ea + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 800813a: 4b0e ldr r3, [pc, #56] ; (8008174 ) + 800813c: 681b ldr r3, [r3, #0] + 800813e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8008142: 2b00 cmp r3, #0 + 8008144: d0f0 beq.n 8008128 + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + 8008146: 69bb ldr r3, [r7, #24] + 8008148: 2b01 cmp r3, #1 + 800814a: f040 80cd bne.w 80082e8 + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + 800814e: 4b09 ldr r3, [pc, #36] ; (8008174 ) + 8008150: 681b ldr r3, [r3, #0] + 8008152: 4a08 ldr r2, [pc, #32] ; (8008174 ) + 8008154: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8008158: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800815a: f7fc f9c9 bl 80044f0 + 800815e: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8008160: e00a b.n 8008178 + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 8008162: f7fc f9c5 bl 80044f0 + 8008166: 4602 mov r2, r0 + 8008168: 697b ldr r3, [r7, #20] + 800816a: 1ad3 subs r3, r2, r3 + 800816c: 2b64 cmp r3, #100 ; 0x64 + 800816e: d903 bls.n 8008178 + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8008170: 2303 movs r3, #3 + 8008172: e0ba b.n 80082ea + 8008174: 40023800 .word 0x40023800 + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 8008178: 4b5e ldr r3, [pc, #376] ; (80082f4 ) + 800817a: 681b ldr r3, [r3, #0] + 800817c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8008180: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8008184: d0ed beq.n 8008162 + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 8008186: 687b ldr r3, [r7, #4] + 8008188: 681b ldr r3, [r3, #0] + 800818a: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 800818e: 2b00 cmp r3, #0 + 8008190: d003 beq.n 800819a + 8008192: 687b ldr r3, [r7, #4] + 8008194: 6bdb ldr r3, [r3, #60] ; 0x3c + 8008196: 2b00 cmp r3, #0 + 8008198: d009 beq.n 80081ae + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 800819a: 687b ldr r3, [r7, #4] + 800819c: 681b ldr r3, [r3, #0] + 800819e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + 80081a2: 2b00 cmp r3, #0 + 80081a4: d02e beq.n 8008204 + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + 80081a6: 687b ldr r3, [r7, #4] + 80081a8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80081aa: 2b00 cmp r3, #0 + 80081ac: d12a bne.n 8008204 + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 80081ae: 4b51 ldr r3, [pc, #324] ; (80082f4 ) + 80081b0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80081b4: 0c1b lsrs r3, r3, #16 + 80081b6: f003 0303 and.w r3, r3, #3 + 80081ba: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 80081bc: 4b4d ldr r3, [pc, #308] ; (80082f4 ) + 80081be: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80081c2: 0f1b lsrs r3, r3, #28 + 80081c4: f003 0307 and.w r3, r3, #7 + 80081c8: 60fb str r3, [r7, #12] + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + 80081ca: 687b ldr r3, [r7, #4] + 80081cc: 695b ldr r3, [r3, #20] + 80081ce: 019a lsls r2, r3, #6 + 80081d0: 693b ldr r3, [r7, #16] + 80081d2: 041b lsls r3, r3, #16 + 80081d4: 431a orrs r2, r3 + 80081d6: 687b ldr r3, [r7, #4] + 80081d8: 699b ldr r3, [r3, #24] + 80081da: 061b lsls r3, r3, #24 + 80081dc: 431a orrs r2, r3 + 80081de: 68fb ldr r3, [r7, #12] + 80081e0: 071b lsls r3, r3, #28 + 80081e2: 4944 ldr r1, [pc, #272] ; (80082f4 ) + 80081e4: 4313 orrs r3, r2 + 80081e6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 80081ea: 4b42 ldr r3, [pc, #264] ; (80082f4 ) + 80081ec: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80081f0: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 80081f4: 687b ldr r3, [r7, #4] + 80081f6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80081f8: 3b01 subs r3, #1 + 80081fa: 021b lsls r3, r3, #8 + 80081fc: 493d ldr r1, [pc, #244] ; (80082f4 ) + 80081fe: 4313 orrs r3, r2 + 8008200: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + 8008204: 687b ldr r3, [r7, #4] + 8008206: 681b ldr r3, [r3, #0] + 8008208: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800820c: 2b00 cmp r3, #0 + 800820e: d022 beq.n 8008256 + 8008210: 687b ldr r3, [r7, #4] + 8008212: 6fdb ldr r3, [r3, #124] ; 0x7c + 8008214: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8008218: d11d bne.n 8008256 + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 800821a: 4b36 ldr r3, [pc, #216] ; (80082f4 ) + 800821c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008220: 0e1b lsrs r3, r3, #24 + 8008222: f003 030f and.w r3, r3, #15 + 8008226: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 8008228: 4b32 ldr r3, [pc, #200] ; (80082f4 ) + 800822a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800822e: 0f1b lsrs r3, r3, #28 + 8008230: f003 0307 and.w r3, r3, #7 + 8008234: 60fb str r3, [r7, #12] + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + 8008236: 687b ldr r3, [r7, #4] + 8008238: 695b ldr r3, [r3, #20] + 800823a: 019a lsls r2, r3, #6 + 800823c: 687b ldr r3, [r7, #4] + 800823e: 6a1b ldr r3, [r3, #32] + 8008240: 041b lsls r3, r3, #16 + 8008242: 431a orrs r2, r3 + 8008244: 693b ldr r3, [r7, #16] + 8008246: 061b lsls r3, r3, #24 + 8008248: 431a orrs r2, r3 + 800824a: 68fb ldr r3, [r7, #12] + 800824c: 071b lsls r3, r3, #28 + 800824e: 4929 ldr r1, [pc, #164] ; (80082f4 ) + 8008250: 4313 orrs r3, r2 + 8008252: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 8008256: 687b ldr r3, [r7, #4] + 8008258: 681b ldr r3, [r3, #0] + 800825a: f003 0308 and.w r3, r3, #8 + 800825e: 2b00 cmp r3, #0 + 8008260: d028 beq.n 80082b4 + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 8008262: 4b24 ldr r3, [pc, #144] ; (80082f4 ) + 8008264: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008268: 0e1b lsrs r3, r3, #24 + 800826a: f003 030f and.w r3, r3, #15 + 800826e: 613b str r3, [r7, #16] + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 8008270: 4b20 ldr r3, [pc, #128] ; (80082f4 ) + 8008272: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8008276: 0c1b lsrs r3, r3, #16 + 8008278: f003 0303 and.w r3, r3, #3 + 800827c: 60fb str r3, [r7, #12] + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + 800827e: 687b ldr r3, [r7, #4] + 8008280: 695b ldr r3, [r3, #20] + 8008282: 019a lsls r2, r3, #6 + 8008284: 68fb ldr r3, [r7, #12] + 8008286: 041b lsls r3, r3, #16 + 8008288: 431a orrs r2, r3 + 800828a: 693b ldr r3, [r7, #16] + 800828c: 061b lsls r3, r3, #24 + 800828e: 431a orrs r2, r3 + 8008290: 687b ldr r3, [r7, #4] + 8008292: 69db ldr r3, [r3, #28] + 8008294: 071b lsls r3, r3, #28 + 8008296: 4917 ldr r1, [pc, #92] ; (80082f4 ) + 8008298: 4313 orrs r3, r2 + 800829a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 800829e: 4b15 ldr r3, [pc, #84] ; (80082f4 ) + 80082a0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80082a4: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 80082a8: 687b ldr r3, [r7, #4] + 80082aa: 6adb ldr r3, [r3, #44] ; 0x2c + 80082ac: 4911 ldr r1, [pc, #68] ; (80082f4 ) + 80082ae: 4313 orrs r3, r2 + 80082b0: f8c1 308c str.w r3, [r1, #140] ; 0x8c + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + 80082b4: 4b0f ldr r3, [pc, #60] ; (80082f4 ) + 80082b6: 681b ldr r3, [r3, #0] + 80082b8: 4a0e ldr r2, [pc, #56] ; (80082f4 ) + 80082ba: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80082be: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80082c0: f7fc f916 bl 80044f0 + 80082c4: 6178 str r0, [r7, #20] + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 80082c6: e008 b.n 80082da + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 80082c8: f7fc f912 bl 80044f0 + 80082cc: 4602 mov r2, r0 + 80082ce: 697b ldr r3, [r7, #20] + 80082d0: 1ad3 subs r3, r2, r3 + 80082d2: 2b64 cmp r3, #100 ; 0x64 + 80082d4: d901 bls.n 80082da + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 80082d6: 2303 movs r3, #3 + 80082d8: e007 b.n 80082ea + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 80082da: 4b06 ldr r3, [pc, #24] ; (80082f4 ) + 80082dc: 681b ldr r3, [r3, #0] + 80082de: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 80082e2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 80082e6: d1ef bne.n 80082c8 + } + } + } + return HAL_OK; + 80082e8: 2300 movs r3, #0 +} + 80082ea: 4618 mov r0, r3 + 80082ec: 3720 adds r7, #32 + 80082ee: 46bd mov sp, r7 + 80082f0: bd80 pop {r7, pc} + 80082f2: bf00 nop + 80082f4: 40023800 .word 0x40023800 + +080082f8 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 80082f8: b580 push {r7, lr} + 80082fa: b082 sub sp, #8 + 80082fc: af00 add r7, sp, #0 + 80082fe: 6078 str r0, [r7, #4] + /* Check the RTC peripheral state */ + if(hrtc == NULL) + 8008300: 687b ldr r3, [r7, #4] + 8008302: 2b00 cmp r3, #0 + 8008304: d101 bne.n 800830a + { + return HAL_ERROR; + 8008306: 2301 movs r3, #1 + 8008308: e06b b.n 80083e2 + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if(hrtc->State == HAL_RTC_STATE_RESET) + 800830a: 687b ldr r3, [r7, #4] + 800830c: 7f5b ldrb r3, [r3, #29] + 800830e: b2db uxtb r3, r3 + 8008310: 2b00 cmp r3, #0 + 8008312: d105 bne.n 8008320 + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 8008314: 687b ldr r3, [r7, #4] + 8008316: 2200 movs r2, #0 + 8008318: 771a strb r2, [r3, #28] + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 800831a: 6878 ldr r0, [r7, #4] + 800831c: f7fb fd14 bl 8003d48 + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 8008320: 687b ldr r3, [r7, #4] + 8008322: 2202 movs r2, #2 + 8008324: 775a strb r2, [r3, #29] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008326: 687b ldr r3, [r7, #4] + 8008328: 681b ldr r3, [r3, #0] + 800832a: 22ca movs r2, #202 ; 0xca + 800832c: 625a str r2, [r3, #36] ; 0x24 + 800832e: 687b ldr r3, [r7, #4] + 8008330: 681b ldr r3, [r3, #0] + 8008332: 2253 movs r2, #83 ; 0x53 + 8008334: 625a str r2, [r3, #36] ; 0x24 + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 8008336: 6878 ldr r0, [r7, #4] + 8008338: f000 fb00 bl 800893c + 800833c: 4603 mov r3, r0 + 800833e: 2b00 cmp r3, #0 + 8008340: d008 beq.n 8008354 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008342: 687b ldr r3, [r7, #4] + 8008344: 681b ldr r3, [r3, #0] + 8008346: 22ff movs r2, #255 ; 0xff + 8008348: 625a str r2, [r3, #36] ; 0x24 + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 800834a: 687b ldr r3, [r7, #4] + 800834c: 2204 movs r2, #4 + 800834e: 775a strb r2, [r3, #29] + + return HAL_ERROR; + 8008350: 2301 movs r3, #1 + 8008352: e046 b.n 80083e2 + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + 8008354: 687b ldr r3, [r7, #4] + 8008356: 681b ldr r3, [r3, #0] + 8008358: 6899 ldr r1, [r3, #8] + 800835a: 687b ldr r3, [r7, #4] + 800835c: 681a ldr r2, [r3, #0] + 800835e: 4b23 ldr r3, [pc, #140] ; (80083ec ) + 8008360: 400b ands r3, r1 + 8008362: 6093 str r3, [r2, #8] + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + 8008364: 687b ldr r3, [r7, #4] + 8008366: 681b ldr r3, [r3, #0] + 8008368: 6899 ldr r1, [r3, #8] + 800836a: 687b ldr r3, [r7, #4] + 800836c: 685a ldr r2, [r3, #4] + 800836e: 687b ldr r3, [r7, #4] + 8008370: 691b ldr r3, [r3, #16] + 8008372: 431a orrs r2, r3 + 8008374: 687b ldr r3, [r7, #4] + 8008376: 695b ldr r3, [r3, #20] + 8008378: 431a orrs r2, r3 + 800837a: 687b ldr r3, [r7, #4] + 800837c: 681b ldr r3, [r3, #0] + 800837e: 430a orrs r2, r1 + 8008380: 609a str r2, [r3, #8] + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + 8008382: 687b ldr r3, [r7, #4] + 8008384: 681b ldr r3, [r3, #0] + 8008386: 687a ldr r2, [r7, #4] + 8008388: 68d2 ldr r2, [r2, #12] + 800838a: 611a str r2, [r3, #16] + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + 800838c: 687b ldr r3, [r7, #4] + 800838e: 681b ldr r3, [r3, #0] + 8008390: 6919 ldr r1, [r3, #16] + 8008392: 687b ldr r3, [r7, #4] + 8008394: 689b ldr r3, [r3, #8] + 8008396: 041a lsls r2, r3, #16 + 8008398: 687b ldr r3, [r7, #4] + 800839a: 681b ldr r3, [r3, #0] + 800839c: 430a orrs r2, r1 + 800839e: 611a str r2, [r3, #16] + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 80083a0: 687b ldr r3, [r7, #4] + 80083a2: 681b ldr r3, [r3, #0] + 80083a4: 68da ldr r2, [r3, #12] + 80083a6: 687b ldr r3, [r7, #4] + 80083a8: 681b ldr r3, [r3, #0] + 80083aa: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80083ae: 60da str r2, [r3, #12] + + hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE; + 80083b0: 687b ldr r3, [r7, #4] + 80083b2: 681b ldr r3, [r3, #0] + 80083b4: 6cda ldr r2, [r3, #76] ; 0x4c + 80083b6: 687b ldr r3, [r7, #4] + 80083b8: 681b ldr r3, [r3, #0] + 80083ba: f022 0208 bic.w r2, r2, #8 + 80083be: 64da str r2, [r3, #76] ; 0x4c + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); + 80083c0: 687b ldr r3, [r7, #4] + 80083c2: 681b ldr r3, [r3, #0] + 80083c4: 6cd9 ldr r1, [r3, #76] ; 0x4c + 80083c6: 687b ldr r3, [r7, #4] + 80083c8: 699a ldr r2, [r3, #24] + 80083ca: 687b ldr r3, [r7, #4] + 80083cc: 681b ldr r3, [r3, #0] + 80083ce: 430a orrs r2, r1 + 80083d0: 64da str r2, [r3, #76] ; 0x4c + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80083d2: 687b ldr r3, [r7, #4] + 80083d4: 681b ldr r3, [r3, #0] + 80083d6: 22ff movs r2, #255 ; 0xff + 80083d8: 625a str r2, [r3, #36] ; 0x24 + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80083da: 687b ldr r3, [r7, #4] + 80083dc: 2201 movs r2, #1 + 80083de: 775a strb r2, [r3, #29] + + return HAL_OK; + 80083e0: 2300 movs r3, #0 + } +} + 80083e2: 4618 mov r0, r3 + 80083e4: 3708 adds r7, #8 + 80083e6: 46bd mov sp, r7 + 80083e8: bd80 pop {r7, pc} + 80083ea: bf00 nop + 80083ec: ff8fffbf .word 0xff8fffbf + +080083f0 : + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + 80083f0: b590 push {r4, r7, lr} + 80083f2: b087 sub sp, #28 + 80083f4: af00 add r7, sp, #0 + 80083f6: 60f8 str r0, [r7, #12] + 80083f8: 60b9 str r1, [r7, #8] + 80083fa: 607a str r2, [r7, #4] + uint32_t tmpreg = 0; + 80083fc: 2300 movs r3, #0 + 80083fe: 617b str r3, [r7, #20] + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8008400: 68fb ldr r3, [r7, #12] + 8008402: 7f1b ldrb r3, [r3, #28] + 8008404: 2b01 cmp r3, #1 + 8008406: d101 bne.n 800840c + 8008408: 2302 movs r3, #2 + 800840a: e0a8 b.n 800855e + 800840c: 68fb ldr r3, [r7, #12] + 800840e: 2201 movs r2, #1 + 8008410: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8008412: 68fb ldr r3, [r7, #12] + 8008414: 2202 movs r2, #2 + 8008416: 775a strb r2, [r3, #29] + + if(Format == RTC_FORMAT_BIN) + 8008418: 687b ldr r3, [r7, #4] + 800841a: 2b00 cmp r3, #0 + 800841c: d126 bne.n 800846c + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 800841e: 68fb ldr r3, [r7, #12] + 8008420: 681b ldr r3, [r3, #0] + 8008422: 689b ldr r3, [r3, #8] + 8008424: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008428: 2b00 cmp r3, #0 + 800842a: d102 bne.n 8008432 + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + 800842c: 68bb ldr r3, [r7, #8] + 800842e: 2200 movs r2, #0 + 8008430: 731a strb r2, [r3, #12] + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + 8008432: 68bb ldr r3, [r7, #8] + 8008434: 781b ldrb r3, [r3, #0] + 8008436: 4618 mov r0, r3 + 8008438: f000 faac bl 8008994 + 800843c: 4603 mov r3, r0 + 800843e: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + 8008440: 68bb ldr r3, [r7, #8] + 8008442: 785b ldrb r3, [r3, #1] + 8008444: 4618 mov r0, r3 + 8008446: f000 faa5 bl 8008994 + 800844a: 4603 mov r3, r0 + 800844c: 021b lsls r3, r3, #8 + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + 800844e: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + 8008450: 68bb ldr r3, [r7, #8] + 8008452: 789b ldrb r3, [r3, #2] + 8008454: 4618 mov r0, r3 + 8008456: f000 fa9d bl 8008994 + 800845a: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + 800845c: ea44 0203 orr.w r2, r4, r3 + (((uint32_t)sTime->TimeFormat) << 16)); + 8008460: 68bb ldr r3, [r7, #8] + 8008462: 7b1b ldrb r3, [r3, #12] + 8008464: 041b lsls r3, r3, #16 + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + 8008466: 4313 orrs r3, r2 + 8008468: 617b str r3, [r7, #20] + 800846a: e018 b.n 800849e + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 800846c: 68fb ldr r3, [r7, #12] + 800846e: 681b ldr r3, [r3, #0] + 8008470: 689b ldr r3, [r3, #8] + 8008472: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008476: 2b00 cmp r3, #0 + 8008478: d102 bne.n 8008480 + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + 800847a: 68bb ldr r3, [r7, #8] + 800847c: 2200 movs r2, #0 + 800847e: 731a strb r2, [r3, #12] + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + 8008480: 68bb ldr r3, [r7, #8] + 8008482: 781b ldrb r3, [r3, #0] + 8008484: 041a lsls r2, r3, #16 + ((uint32_t)(sTime->Minutes) << 8) | \ + 8008486: 68bb ldr r3, [r7, #8] + 8008488: 785b ldrb r3, [r3, #1] + 800848a: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + 800848c: 4313 orrs r3, r2 + ((uint32_t)sTime->Seconds) | \ + 800848e: 68ba ldr r2, [r7, #8] + 8008490: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sTime->Minutes) << 8) | \ + 8008492: 431a orrs r2, r3 + ((uint32_t)(sTime->TimeFormat) << 16)); + 8008494: 68bb ldr r3, [r7, #8] + 8008496: 7b1b ldrb r3, [r3, #12] + 8008498: 041b lsls r3, r3, #16 + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + 800849a: 4313 orrs r3, r2 + 800849c: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 800849e: 68fb ldr r3, [r7, #12] + 80084a0: 681b ldr r3, [r3, #0] + 80084a2: 22ca movs r2, #202 ; 0xca + 80084a4: 625a str r2, [r3, #36] ; 0x24 + 80084a6: 68fb ldr r3, [r7, #12] + 80084a8: 681b ldr r3, [r3, #0] + 80084aa: 2253 movs r2, #83 ; 0x53 + 80084ac: 625a str r2, [r3, #36] ; 0x24 + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 80084ae: 68f8 ldr r0, [r7, #12] + 80084b0: f000 fa44 bl 800893c + 80084b4: 4603 mov r3, r0 + 80084b6: 2b00 cmp r3, #0 + 80084b8: d00b beq.n 80084d2 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80084ba: 68fb ldr r3, [r7, #12] + 80084bc: 681b ldr r3, [r3, #0] + 80084be: 22ff movs r2, #255 ; 0xff + 80084c0: 625a str r2, [r3, #36] ; 0x24 + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + 80084c2: 68fb ldr r3, [r7, #12] + 80084c4: 2204 movs r2, #4 + 80084c6: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80084c8: 68fb ldr r3, [r7, #12] + 80084ca: 2200 movs r2, #0 + 80084cc: 771a strb r2, [r3, #28] + + return HAL_ERROR; + 80084ce: 2301 movs r3, #1 + 80084d0: e045 b.n 800855e + } + else + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + 80084d2: 68fb ldr r3, [r7, #12] + 80084d4: 681a ldr r2, [r3, #0] + 80084d6: 6979 ldr r1, [r7, #20] + 80084d8: 4b23 ldr r3, [pc, #140] ; (8008568 ) + 80084da: 400b ands r3, r1 + 80084dc: 6013 str r3, [r2, #0] + + /* Clear the bits to be configured */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; + 80084de: 68fb ldr r3, [r7, #12] + 80084e0: 681b ldr r3, [r3, #0] + 80084e2: 689a ldr r2, [r3, #8] + 80084e4: 68fb ldr r3, [r7, #12] + 80084e6: 681b ldr r3, [r3, #0] + 80084e8: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 80084ec: 609a str r2, [r3, #8] + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + 80084ee: 68fb ldr r3, [r7, #12] + 80084f0: 681b ldr r3, [r3, #0] + 80084f2: 6899 ldr r1, [r3, #8] + 80084f4: 68bb ldr r3, [r7, #8] + 80084f6: 691a ldr r2, [r3, #16] + 80084f8: 68bb ldr r3, [r7, #8] + 80084fa: 695b ldr r3, [r3, #20] + 80084fc: 431a orrs r2, r3 + 80084fe: 68fb ldr r3, [r7, #12] + 8008500: 681b ldr r3, [r3, #0] + 8008502: 430a orrs r2, r1 + 8008504: 609a str r2, [r3, #8] + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 8008506: 68fb ldr r3, [r7, #12] + 8008508: 681b ldr r3, [r3, #0] + 800850a: 68da ldr r2, [r3, #12] + 800850c: 68fb ldr r3, [r7, #12] + 800850e: 681b ldr r3, [r3, #0] + 8008510: f022 0280 bic.w r2, r2, #128 ; 0x80 + 8008514: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 8008516: 68fb ldr r3, [r7, #12] + 8008518: 681b ldr r3, [r3, #0] + 800851a: 689b ldr r3, [r3, #8] + 800851c: f003 0320 and.w r3, r3, #32 + 8008520: 2b00 cmp r3, #0 + 8008522: d111 bne.n 8008548 + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8008524: 68f8 ldr r0, [r7, #12] + 8008526: f000 f9e1 bl 80088ec + 800852a: 4603 mov r3, r0 + 800852c: 2b00 cmp r3, #0 + 800852e: d00b beq.n 8008548 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008530: 68fb ldr r3, [r7, #12] + 8008532: 681b ldr r3, [r3, #0] + 8008534: 22ff movs r2, #255 ; 0xff + 8008536: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_ERROR; + 8008538: 68fb ldr r3, [r7, #12] + 800853a: 2204 movs r2, #4 + 800853c: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800853e: 68fb ldr r3, [r7, #12] + 8008540: 2200 movs r2, #0 + 8008542: 771a strb r2, [r3, #28] + + return HAL_ERROR; + 8008544: 2301 movs r3, #1 + 8008546: e00a b.n 800855e + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008548: 68fb ldr r3, [r7, #12] + 800854a: 681b ldr r3, [r3, #0] + 800854c: 22ff movs r2, #255 ; 0xff + 800854e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8008550: 68fb ldr r3, [r7, #12] + 8008552: 2201 movs r2, #1 + 8008554: 775a strb r2, [r3, #29] + + __HAL_UNLOCK(hrtc); + 8008556: 68fb ldr r3, [r7, #12] + 8008558: 2200 movs r2, #0 + 800855a: 771a strb r2, [r3, #28] + + return HAL_OK; + 800855c: 2300 movs r3, #0 + } +} + 800855e: 4618 mov r0, r3 + 8008560: 371c adds r7, #28 + 8008562: 46bd mov sp, r7 + 8008564: bd90 pop {r4, r7, pc} + 8008566: bf00 nop + 8008568: 007f7f7f .word 0x007f7f7f + +0800856c : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + 800856c: b590 push {r4, r7, lr} + 800856e: b087 sub sp, #28 + 8008570: af00 add r7, sp, #0 + 8008572: 60f8 str r0, [r7, #12] + 8008574: 60b9 str r1, [r7, #8] + 8008576: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0; + 8008578: 2300 movs r3, #0 + 800857a: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 800857c: 68fb ldr r3, [r7, #12] + 800857e: 7f1b ldrb r3, [r3, #28] + 8008580: 2b01 cmp r3, #1 + 8008582: d101 bne.n 8008588 + 8008584: 2302 movs r3, #2 + 8008586: e092 b.n 80086ae + 8008588: 68fb ldr r3, [r7, #12] + 800858a: 2201 movs r2, #1 + 800858c: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 800858e: 68fb ldr r3, [r7, #12] + 8008590: 2202 movs r2, #2 + 8008592: 775a strb r2, [r3, #29] + + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 8008594: 687b ldr r3, [r7, #4] + 8008596: 2b00 cmp r3, #0 + 8008598: d10e bne.n 80085b8 + 800859a: 68bb ldr r3, [r7, #8] + 800859c: 785b ldrb r3, [r3, #1] + 800859e: f003 0310 and.w r3, r3, #16 + 80085a2: 2b00 cmp r3, #0 + 80085a4: d008 beq.n 80085b8 + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + 80085a6: 68bb ldr r3, [r7, #8] + 80085a8: 785b ldrb r3, [r3, #1] + 80085aa: f023 0310 bic.w r3, r3, #16 + 80085ae: b2db uxtb r3, r3 + 80085b0: 330a adds r3, #10 + 80085b2: b2da uxtb r2, r3 + 80085b4: 68bb ldr r3, [r7, #8] + 80085b6: 705a strb r2, [r3, #1] + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if(Format == RTC_FORMAT_BIN) + 80085b8: 687b ldr r3, [r7, #4] + 80085ba: 2b00 cmp r3, #0 + 80085bc: d11c bne.n 80085f8 + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + 80085be: 68bb ldr r3, [r7, #8] + 80085c0: 78db ldrb r3, [r3, #3] + 80085c2: 4618 mov r0, r3 + 80085c4: f000 f9e6 bl 8008994 + 80085c8: 4603 mov r3, r0 + 80085ca: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + 80085cc: 68bb ldr r3, [r7, #8] + 80085ce: 785b ldrb r3, [r3, #1] + 80085d0: 4618 mov r0, r3 + 80085d2: f000 f9df bl 8008994 + 80085d6: 4603 mov r3, r0 + 80085d8: 021b lsls r3, r3, #8 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + 80085da: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 80085dc: 68bb ldr r3, [r7, #8] + 80085de: 789b ldrb r3, [r3, #2] + 80085e0: 4618 mov r0, r3 + 80085e2: f000 f9d7 bl 8008994 + 80085e6: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + 80085e8: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sDate->WeekDay << 13)); + 80085ec: 68bb ldr r3, [r7, #8] + 80085ee: 781b ldrb r3, [r3, #0] + 80085f0: 035b lsls r3, r3, #13 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + 80085f2: 4313 orrs r3, r2 + 80085f4: 617b str r3, [r7, #20] + 80085f6: e00e b.n 8008616 + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + 80085f8: 68bb ldr r3, [r7, #8] + 80085fa: 78db ldrb r3, [r3, #3] + 80085fc: 041a lsls r2, r3, #16 + (((uint32_t)sDate->Month) << 8) | \ + 80085fe: 68bb ldr r3, [r7, #8] + 8008600: 785b ldrb r3, [r3, #1] + 8008602: 021b lsls r3, r3, #8 + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + 8008604: 4313 orrs r3, r2 + ((uint32_t)sDate->Date) | \ + 8008606: 68ba ldr r2, [r7, #8] + 8008608: 7892 ldrb r2, [r2, #2] + (((uint32_t)sDate->Month) << 8) | \ + 800860a: 431a orrs r2, r3 + (((uint32_t)sDate->WeekDay) << 13)); + 800860c: 68bb ldr r3, [r7, #8] + 800860e: 781b ldrb r3, [r3, #0] + 8008610: 035b lsls r3, r3, #13 + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + 8008612: 4313 orrs r3, r2 + 8008614: 617b str r3, [r7, #20] + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008616: 68fb ldr r3, [r7, #12] + 8008618: 681b ldr r3, [r3, #0] + 800861a: 22ca movs r2, #202 ; 0xca + 800861c: 625a str r2, [r3, #36] ; 0x24 + 800861e: 68fb ldr r3, [r7, #12] + 8008620: 681b ldr r3, [r3, #0] + 8008622: 2253 movs r2, #83 ; 0x53 + 8008624: 625a str r2, [r3, #36] ; 0x24 + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 8008626: 68f8 ldr r0, [r7, #12] + 8008628: f000 f988 bl 800893c + 800862c: 4603 mov r3, r0 + 800862e: 2b00 cmp r3, #0 + 8008630: d00b beq.n 800864a + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008632: 68fb ldr r3, [r7, #12] + 8008634: 681b ldr r3, [r3, #0] + 8008636: 22ff movs r2, #255 ; 0xff + 8008638: 625a str r2, [r3, #36] ; 0x24 + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + 800863a: 68fb ldr r3, [r7, #12] + 800863c: 2204 movs r2, #4 + 800863e: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008640: 68fb ldr r3, [r7, #12] + 8008642: 2200 movs r2, #0 + 8008644: 771a strb r2, [r3, #28] + + return HAL_ERROR; + 8008646: 2301 movs r3, #1 + 8008648: e031 b.n 80086ae + } + else + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + 800864a: 68fb ldr r3, [r7, #12] + 800864c: 681a ldr r2, [r3, #0] + 800864e: 6979 ldr r1, [r7, #20] + 8008650: 4b19 ldr r3, [pc, #100] ; (80086b8 ) + 8008652: 400b ands r3, r1 + 8008654: 6053 str r3, [r2, #4] + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 8008656: 68fb ldr r3, [r7, #12] + 8008658: 681b ldr r3, [r3, #0] + 800865a: 68da ldr r2, [r3, #12] + 800865c: 68fb ldr r3, [r7, #12] + 800865e: 681b ldr r3, [r3, #0] + 8008660: f022 0280 bic.w r2, r2, #128 ; 0x80 + 8008664: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 8008666: 68fb ldr r3, [r7, #12] + 8008668: 681b ldr r3, [r3, #0] + 800866a: 689b ldr r3, [r3, #8] + 800866c: f003 0320 and.w r3, r3, #32 + 8008670: 2b00 cmp r3, #0 + 8008672: d111 bne.n 8008698 + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8008674: 68f8 ldr r0, [r7, #12] + 8008676: f000 f939 bl 80088ec + 800867a: 4603 mov r3, r0 + 800867c: 2b00 cmp r3, #0 + 800867e: d00b beq.n 8008698 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008680: 68fb ldr r3, [r7, #12] + 8008682: 681b ldr r3, [r3, #0] + 8008684: 22ff movs r2, #255 ; 0xff + 8008686: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_ERROR; + 8008688: 68fb ldr r3, [r7, #12] + 800868a: 2204 movs r2, #4 + 800868c: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800868e: 68fb ldr r3, [r7, #12] + 8008690: 2200 movs r2, #0 + 8008692: 771a strb r2, [r3, #28] + + return HAL_ERROR; + 8008694: 2301 movs r3, #1 + 8008696: e00a b.n 80086ae + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008698: 68fb ldr r3, [r7, #12] + 800869a: 681b ldr r3, [r3, #0] + 800869c: 22ff movs r2, #255 ; 0xff + 800869e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY ; + 80086a0: 68fb ldr r3, [r7, #12] + 80086a2: 2201 movs r2, #1 + 80086a4: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80086a6: 68fb ldr r3, [r7, #12] + 80086a8: 2200 movs r2, #0 + 80086aa: 771a strb r2, [r3, #28] + + return HAL_OK; + 80086ac: 2300 movs r3, #0 + } +} + 80086ae: 4618 mov r0, r3 + 80086b0: 371c adds r7, #28 + 80086b2: 46bd mov sp, r7 + 80086b4: bd90 pop {r4, r7, pc} + 80086b6: bf00 nop + 80086b8: 00ffff3f .word 0x00ffff3f + +080086bc : + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + 80086bc: b590 push {r4, r7, lr} + 80086be: b089 sub sp, #36 ; 0x24 + 80086c0: af00 add r7, sp, #0 + 80086c2: 60f8 str r0, [r7, #12] + 80086c4: 60b9 str r1, [r7, #8] + 80086c6: 607a str r2, [r7, #4] + uint32_t tickstart = 0; + 80086c8: 2300 movs r3, #0 + 80086ca: 61bb str r3, [r7, #24] + uint32_t tmpreg = 0, subsecondtmpreg = 0; + 80086cc: 2300 movs r3, #0 + 80086ce: 61fb str r3, [r7, #28] + 80086d0: 2300 movs r3, #0 + 80086d2: 617b str r3, [r7, #20] + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80086d4: 68fb ldr r3, [r7, #12] + 80086d6: 7f1b ldrb r3, [r3, #28] + 80086d8: 2b01 cmp r3, #1 + 80086da: d101 bne.n 80086e0 + 80086dc: 2302 movs r3, #2 + 80086de: e101 b.n 80088e4 + 80086e0: 68fb ldr r3, [r7, #12] + 80086e2: 2201 movs r2, #1 + 80086e4: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80086e6: 68fb ldr r3, [r7, #12] + 80086e8: 2202 movs r2, #2 + 80086ea: 775a strb r2, [r3, #29] + + if(Format == RTC_FORMAT_BIN) + 80086ec: 687b ldr r3, [r7, #4] + 80086ee: 2b00 cmp r3, #0 + 80086f0: d137 bne.n 8008762 + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 80086f2: 68fb ldr r3, [r7, #12] + 80086f4: 681b ldr r3, [r3, #0] + 80086f6: 689b ldr r3, [r3, #8] + 80086f8: f003 0340 and.w r3, r3, #64 ; 0x40 + 80086fc: 2b00 cmp r3, #0 + 80086fe: d102 bne.n 8008706 + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + 8008700: 68bb ldr r3, [r7, #8] + 8008702: 2200 movs r2, #0 + 8008704: 731a strb r2, [r3, #12] + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + 8008706: 68bb ldr r3, [r7, #8] + 8008708: 781b ldrb r3, [r3, #0] + 800870a: 4618 mov r0, r3 + 800870c: f000 f942 bl 8008994 + 8008710: 4603 mov r3, r0 + 8008712: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + 8008714: 68bb ldr r3, [r7, #8] + 8008716: 785b ldrb r3, [r3, #1] + 8008718: 4618 mov r0, r3 + 800871a: f000 f93b bl 8008994 + 800871e: 4603 mov r3, r0 + 8008720: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + 8008722: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 8008724: 68bb ldr r3, [r7, #8] + 8008726: 789b ldrb r3, [r3, #2] + 8008728: 4618 mov r0, r3 + 800872a: f000 f933 bl 8008994 + 800872e: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + 8008730: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + 8008734: 68bb ldr r3, [r7, #8] + 8008736: 7b1b ldrb r3, [r3, #12] + 8008738: 041b lsls r3, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 800873a: ea42 0403 orr.w r4, r2, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + 800873e: 68bb ldr r3, [r7, #8] + 8008740: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8008744: 4618 mov r0, r3 + 8008746: f000 f925 bl 8008994 + 800874a: 4603 mov r3, r0 + 800874c: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + 800874e: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8008752: 68bb ldr r3, [r7, #8] + 8008754: 6a1b ldr r3, [r3, #32] + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + 8008756: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 8008758: 68bb ldr r3, [r7, #8] + 800875a: 699b ldr r3, [r3, #24] + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + 800875c: 4313 orrs r3, r2 + 800875e: 61fb str r3, [r7, #28] + 8008760: e023 b.n 80087aa + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 8008762: 68fb ldr r3, [r7, #12] + 8008764: 681b ldr r3, [r3, #0] + 8008766: 689b ldr r3, [r3, #8] + 8008768: f003 0340 and.w r3, r3, #64 ; 0x40 + 800876c: 2b00 cmp r3, #0 + 800876e: d102 bne.n 8008776 + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + 8008770: 68bb ldr r3, [r7, #8] + 8008772: 2200 movs r2, #0 + 8008774: 731a strb r2, [r3, #12] + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + 8008776: 68bb ldr r3, [r7, #8] + 8008778: 781b ldrb r3, [r3, #0] + 800877a: 041a lsls r2, r3, #16 + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + 800877c: 68bb ldr r3, [r7, #8] + 800877e: 785b ldrb r3, [r3, #1] + 8008780: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + 8008782: 4313 orrs r3, r2 + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 8008784: 68ba ldr r2, [r7, #8] + 8008786: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + 8008788: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + 800878a: 68bb ldr r3, [r7, #8] + 800878c: 7b1b ldrb r3, [r3, #12] + 800878e: 041b lsls r3, r3, #16 + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 8008790: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + 8008792: 68bb ldr r3, [r7, #8] + 8008794: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8008798: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + 800879a: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 800879c: 68bb ldr r3, [r7, #8] + 800879e: 6a1b ldr r3, [r3, #32] + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + 80087a0: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 80087a2: 68bb ldr r3, [r7, #8] + 80087a4: 699b ldr r3, [r3, #24] + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + 80087a6: 4313 orrs r3, r2 + 80087a8: 61fb str r3, [r7, #28] + } + + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + 80087aa: 68bb ldr r3, [r7, #8] + 80087ac: 685a ldr r2, [r3, #4] + 80087ae: 68bb ldr r3, [r7, #8] + 80087b0: 69db ldr r3, [r3, #28] + 80087b2: 4313 orrs r3, r2 + 80087b4: 617b str r3, [r7, #20] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 80087b6: 68fb ldr r3, [r7, #12] + 80087b8: 681b ldr r3, [r3, #0] + 80087ba: 22ca movs r2, #202 ; 0xca + 80087bc: 625a str r2, [r3, #36] ; 0x24 + 80087be: 68fb ldr r3, [r7, #12] + 80087c0: 681b ldr r3, [r3, #0] + 80087c2: 2253 movs r2, #83 ; 0x53 + 80087c4: 625a str r2, [r3, #36] ; 0x24 + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + 80087c6: 68bb ldr r3, [r7, #8] + 80087c8: 6a9b ldr r3, [r3, #40] ; 0x28 + 80087ca: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80087ce: d13f bne.n 8008850 + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + 80087d0: 68fb ldr r3, [r7, #12] + 80087d2: 681b ldr r3, [r3, #0] + 80087d4: 689a ldr r2, [r3, #8] + 80087d6: 68fb ldr r3, [r7, #12] + 80087d8: 681b ldr r3, [r3, #0] + 80087da: f422 7280 bic.w r2, r2, #256 ; 0x100 + 80087de: 609a str r2, [r3, #8] + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + 80087e0: 68fb ldr r3, [r7, #12] + 80087e2: 681b ldr r3, [r3, #0] + 80087e4: 689a ldr r2, [r3, #8] + 80087e6: 68fb ldr r3, [r7, #12] + 80087e8: 681b ldr r3, [r3, #0] + 80087ea: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 80087ee: 609a str r2, [r3, #8] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80087f0: f7fb fe7e bl 80044f0 + 80087f4: 61b8 str r0, [r7, #24] + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + 80087f6: e013 b.n 8008820 + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 80087f8: f7fb fe7a bl 80044f0 + 80087fc: 4602 mov r2, r0 + 80087fe: 69bb ldr r3, [r7, #24] + 8008800: 1ad3 subs r3, r2, r3 + 8008802: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8008806: d90b bls.n 8008820 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008808: 68fb ldr r3, [r7, #12] + 800880a: 681b ldr r3, [r3, #0] + 800880c: 22ff movs r2, #255 ; 0xff + 800880e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8008810: 68fb ldr r3, [r7, #12] + 8008812: 2203 movs r2, #3 + 8008814: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008816: 68fb ldr r3, [r7, #12] + 8008818: 2200 movs r2, #0 + 800881a: 771a strb r2, [r3, #28] + + return HAL_TIMEOUT; + 800881c: 2303 movs r3, #3 + 800881e: e061 b.n 80088e4 + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + 8008820: 68fb ldr r3, [r7, #12] + 8008822: 681b ldr r3, [r3, #0] + 8008824: 68db ldr r3, [r3, #12] + 8008826: f003 0301 and.w r3, r3, #1 + 800882a: 2b00 cmp r3, #0 + 800882c: d0e4 beq.n 80087f8 + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + 800882e: 68fb ldr r3, [r7, #12] + 8008830: 681b ldr r3, [r3, #0] + 8008832: 69fa ldr r2, [r7, #28] + 8008834: 61da str r2, [r3, #28] + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + 8008836: 68fb ldr r3, [r7, #12] + 8008838: 681b ldr r3, [r3, #0] + 800883a: 697a ldr r2, [r7, #20] + 800883c: 645a str r2, [r3, #68] ; 0x44 + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + 800883e: 68fb ldr r3, [r7, #12] + 8008840: 681b ldr r3, [r3, #0] + 8008842: 689a ldr r2, [r3, #8] + 8008844: 68fb ldr r3, [r7, #12] + 8008846: 681b ldr r3, [r3, #0] + 8008848: f442 7280 orr.w r2, r2, #256 ; 0x100 + 800884c: 609a str r2, [r3, #8] + 800884e: e03e b.n 80088ce + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + 8008850: 68fb ldr r3, [r7, #12] + 8008852: 681b ldr r3, [r3, #0] + 8008854: 689a ldr r2, [r3, #8] + 8008856: 68fb ldr r3, [r7, #12] + 8008858: 681b ldr r3, [r3, #0] + 800885a: f422 7200 bic.w r2, r2, #512 ; 0x200 + 800885e: 609a str r2, [r3, #8] + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + 8008860: 68fb ldr r3, [r7, #12] + 8008862: 681b ldr r3, [r3, #0] + 8008864: 689a ldr r2, [r3, #8] + 8008866: 68fb ldr r3, [r7, #12] + 8008868: 681b ldr r3, [r3, #0] + 800886a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 800886e: 609a str r2, [r3, #8] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8008870: f7fb fe3e bl 80044f0 + 8008874: 61b8 str r0, [r7, #24] + + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + 8008876: e013 b.n 80088a0 + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 8008878: f7fb fe3a bl 80044f0 + 800887c: 4602 mov r2, r0 + 800887e: 69bb ldr r3, [r7, #24] + 8008880: 1ad3 subs r3, r2, r3 + 8008882: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8008886: d90b bls.n 80088a0 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008888: 68fb ldr r3, [r7, #12] + 800888a: 681b ldr r3, [r3, #0] + 800888c: 22ff movs r2, #255 ; 0xff + 800888e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8008890: 68fb ldr r3, [r7, #12] + 8008892: 2203 movs r2, #3 + 8008894: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008896: 68fb ldr r3, [r7, #12] + 8008898: 2200 movs r2, #0 + 800889a: 771a strb r2, [r3, #28] + + return HAL_TIMEOUT; + 800889c: 2303 movs r3, #3 + 800889e: e021 b.n 80088e4 + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + 80088a0: 68fb ldr r3, [r7, #12] + 80088a2: 681b ldr r3, [r3, #0] + 80088a4: 68db ldr r3, [r3, #12] + 80088a6: f003 0302 and.w r3, r3, #2 + 80088aa: 2b00 cmp r3, #0 + 80088ac: d0e4 beq.n 8008878 + } + } + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; + 80088ae: 68fb ldr r3, [r7, #12] + 80088b0: 681b ldr r3, [r3, #0] + 80088b2: 69fa ldr r2, [r7, #28] + 80088b4: 621a str r2, [r3, #32] + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; + 80088b6: 68fb ldr r3, [r7, #12] + 80088b8: 681b ldr r3, [r3, #0] + 80088ba: 697a ldr r2, [r7, #20] + 80088bc: 649a str r2, [r3, #72] ; 0x48 + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + 80088be: 68fb ldr r3, [r7, #12] + 80088c0: 681b ldr r3, [r3, #0] + 80088c2: 689a ldr r2, [r3, #8] + 80088c4: 68fb ldr r3, [r7, #12] + 80088c6: 681b ldr r3, [r3, #0] + 80088c8: f442 7200 orr.w r2, r2, #512 ; 0x200 + 80088cc: 609a str r2, [r3, #8] + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80088ce: 68fb ldr r3, [r7, #12] + 80088d0: 681b ldr r3, [r3, #0] + 80088d2: 22ff movs r2, #255 ; 0xff + 80088d4: 625a str r2, [r3, #36] ; 0x24 + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80088d6: 68fb ldr r3, [r7, #12] + 80088d8: 2201 movs r2, #1 + 80088da: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80088dc: 68fb ldr r3, [r7, #12] + 80088de: 2200 movs r2, #0 + 80088e0: 771a strb r2, [r3, #28] + + return HAL_OK; + 80088e2: 2300 movs r3, #0 +} + 80088e4: 4618 mov r0, r3 + 80088e6: 3724 adds r7, #36 ; 0x24 + 80088e8: 46bd mov sp, r7 + 80088ea: bd90 pop {r4, r7, pc} + +080088ec : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +{ + 80088ec: b580 push {r7, lr} + 80088ee: b084 sub sp, #16 + 80088f0: af00 add r7, sp, #0 + 80088f2: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 80088f4: 2300 movs r3, #0 + 80088f6: 60fb str r3, [r7, #12] + + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + 80088f8: 687b ldr r3, [r7, #4] + 80088fa: 681b ldr r3, [r3, #0] + 80088fc: 68da ldr r2, [r3, #12] + 80088fe: 687b ldr r3, [r7, #4] + 8008900: 681b ldr r3, [r3, #0] + 8008902: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 8008906: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8008908: f7fb fdf2 bl 80044f0 + 800890c: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + 800890e: e009 b.n 8008924 + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 8008910: f7fb fdee bl 80044f0 + 8008914: 4602 mov r2, r0 + 8008916: 68fb ldr r3, [r7, #12] + 8008918: 1ad3 subs r3, r2, r3 + 800891a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800891e: d901 bls.n 8008924 + { + return HAL_TIMEOUT; + 8008920: 2303 movs r3, #3 + 8008922: e007 b.n 8008934 + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + 8008924: 687b ldr r3, [r7, #4] + 8008926: 681b ldr r3, [r3, #0] + 8008928: 68db ldr r3, [r3, #12] + 800892a: f003 0320 and.w r3, r3, #32 + 800892e: 2b00 cmp r3, #0 + 8008930: d0ee beq.n 8008910 + } + } + + return HAL_OK; + 8008932: 2300 movs r3, #0 +} + 8008934: 4618 mov r0, r3 + 8008936: 3710 adds r7, #16 + 8008938: 46bd mov sp, r7 + 800893a: bd80 pop {r7, pc} + +0800893c : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +{ + 800893c: b580 push {r7, lr} + 800893e: b084 sub sp, #16 + 8008940: af00 add r7, sp, #0 + 8008942: 6078 str r0, [r7, #4] + uint32_t tickstart = 0; + 8008944: 2300 movs r3, #0 + 8008946: 60fb str r3, [r7, #12] + + /* Check if the Initialization mode is set */ + if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 8008948: 687b ldr r3, [r7, #4] + 800894a: 681b ldr r3, [r3, #0] + 800894c: 68db ldr r3, [r3, #12] + 800894e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008952: 2b00 cmp r3, #0 + 8008954: d119 bne.n 800898a + { + /* Set the Initialization mode */ + hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + 8008956: 687b ldr r3, [r7, #4] + 8008958: 681b ldr r3, [r3, #0] + 800895a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800895e: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8008960: f7fb fdc6 bl 80044f0 + 8008964: 60f8 str r0, [r7, #12] + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 8008966: e009 b.n 800897c + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 8008968: f7fb fdc2 bl 80044f0 + 800896c: 4602 mov r2, r0 + 800896e: 68fb ldr r3, [r7, #12] + 8008970: 1ad3 subs r3, r2, r3 + 8008972: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8008976: d901 bls.n 800897c + { + return HAL_TIMEOUT; + 8008978: 2303 movs r3, #3 + 800897a: e007 b.n 800898c + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 800897c: 687b ldr r3, [r7, #4] + 800897e: 681b ldr r3, [r3, #0] + 8008980: 68db ldr r3, [r3, #12] + 8008982: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008986: 2b00 cmp r3, #0 + 8008988: d0ee beq.n 8008968 + } + } + } + + return HAL_OK; + 800898a: 2300 movs r3, #0 +} + 800898c: 4618 mov r0, r3 + 800898e: 3710 adds r7, #16 + 8008990: 46bd mov sp, r7 + 8008992: bd80 pop {r7, pc} + +08008994 : + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + 8008994: b480 push {r7} + 8008996: b085 sub sp, #20 + 8008998: af00 add r7, sp, #0 + 800899a: 4603 mov r3, r0 + 800899c: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0; + 800899e: 2300 movs r3, #0 + 80089a0: 60fb str r3, [r7, #12] + + while(Value >= 10) + 80089a2: e005 b.n 80089b0 + { + bcdhigh++; + 80089a4: 68fb ldr r3, [r7, #12] + 80089a6: 3301 adds r3, #1 + 80089a8: 60fb str r3, [r7, #12] + Value -= 10; + 80089aa: 79fb ldrb r3, [r7, #7] + 80089ac: 3b0a subs r3, #10 + 80089ae: 71fb strb r3, [r7, #7] + while(Value >= 10) + 80089b0: 79fb ldrb r3, [r7, #7] + 80089b2: 2b09 cmp r3, #9 + 80089b4: d8f6 bhi.n 80089a4 + } + + return ((uint8_t)(bcdhigh << 4) | Value); + 80089b6: 68fb ldr r3, [r7, #12] + 80089b8: b2db uxtb r3, r3 + 80089ba: 011b lsls r3, r3, #4 + 80089bc: b2da uxtb r2, r3 + 80089be: 79fb ldrb r3, [r7, #7] + 80089c0: 4313 orrs r3, r2 + 80089c2: b2db uxtb r3, r3 +} + 80089c4: 4618 mov r0, r3 + 80089c6: 3714 adds r7, #20 + 80089c8: 46bd mov sp, r7 + 80089ca: f85d 7b04 ldr.w r7, [sp], #4 + 80089ce: 4770 bx lr + +080089d0 : + * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + 80089d0: b480 push {r7} + 80089d2: b087 sub sp, #28 + 80089d4: af00 add r7, sp, #0 + 80089d6: 60f8 str r0, [r7, #12] + 80089d8: 60b9 str r1, [r7, #8] + 80089da: 607a str r2, [r7, #4] + uint32_t tmpreg = 0; + 80089dc: 2300 movs r3, #0 + 80089de: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 80089e0: 68fb ldr r3, [r7, #12] + 80089e2: 7f1b ldrb r3, [r3, #28] + 80089e4: 2b01 cmp r3, #1 + 80089e6: d101 bne.n 80089ec + 80089e8: 2302 movs r3, #2 + 80089ea: e03e b.n 8008a6a + 80089ec: 68fb ldr r3, [r7, #12] + 80089ee: 2201 movs r2, #1 + 80089f0: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 80089f2: 68fb ldr r3, [r7, #12] + 80089f4: 2202 movs r2, #2 + 80089f6: 775a strb r2, [r3, #29] + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + 80089f8: 68fb ldr r3, [r7, #12] + 80089fa: 681b ldr r3, [r3, #0] + 80089fc: 689a ldr r2, [r3, #8] + 80089fe: 4b1e ldr r3, [pc, #120] ; (8008a78 ) + 8008a00: 4013 ands r3, r2 + 8008a02: 617b str r3, [r7, #20] + + tmpreg|= TimeStampEdge; + 8008a04: 697a ldr r2, [r7, #20] + 8008a06: 68bb ldr r3, [r7, #8] + 8008a08: 4313 orrs r3, r2 + 8008a0a: 617b str r3, [r7, #20] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8008a0c: 68fb ldr r3, [r7, #12] + 8008a0e: 681b ldr r3, [r3, #0] + 8008a10: 22ca movs r2, #202 ; 0xca + 8008a12: 625a str r2, [r3, #36] ; 0x24 + 8008a14: 68fb ldr r3, [r7, #12] + 8008a16: 681b ldr r3, [r3, #0] + 8008a18: 2253 movs r2, #83 ; 0x53 + 8008a1a: 625a str r2, [r3, #36] ; 0x24 + + hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; + 8008a1c: 68fb ldr r3, [r7, #12] + 8008a1e: 681b ldr r3, [r3, #0] + 8008a20: 6cda ldr r2, [r3, #76] ; 0x4c + 8008a22: 68fb ldr r3, [r7, #12] + 8008a24: 681b ldr r3, [r3, #0] + 8008a26: f022 0206 bic.w r2, r2, #6 + 8008a2a: 64da str r2, [r3, #76] ; 0x4c + hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); + 8008a2c: 68fb ldr r3, [r7, #12] + 8008a2e: 681b ldr r3, [r3, #0] + 8008a30: 6cd9 ldr r1, [r3, #76] ; 0x4c + 8008a32: 68fb ldr r3, [r7, #12] + 8008a34: 681b ldr r3, [r3, #0] + 8008a36: 687a ldr r2, [r7, #4] + 8008a38: 430a orrs r2, r1 + 8008a3a: 64da str r2, [r3, #76] ; 0x4c + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + 8008a3c: 68fb ldr r3, [r7, #12] + 8008a3e: 681b ldr r3, [r3, #0] + 8008a40: 697a ldr r2, [r7, #20] + 8008a42: 609a str r2, [r3, #8] + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + 8008a44: 68fb ldr r3, [r7, #12] + 8008a46: 681b ldr r3, [r3, #0] + 8008a48: 689a ldr r2, [r3, #8] + 8008a4a: 68fb ldr r3, [r7, #12] + 8008a4c: 681b ldr r3, [r3, #0] + 8008a4e: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8008a52: 609a str r2, [r3, #8] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8008a54: 68fb ldr r3, [r7, #12] + 8008a56: 681b ldr r3, [r3, #0] + 8008a58: 22ff movs r2, #255 ; 0xff + 8008a5a: 625a str r2, [r3, #36] ; 0x24 + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8008a5c: 68fb ldr r3, [r7, #12] + 8008a5e: 2201 movs r2, #1 + 8008a60: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8008a62: 68fb ldr r3, [r7, #12] + 8008a64: 2200 movs r2, #0 + 8008a66: 771a strb r2, [r3, #28] + + return HAL_OK; + 8008a68: 2300 movs r3, #0 +} + 8008a6a: 4618 mov r0, r3 + 8008a6c: 371c adds r7, #28 + 8008a6e: 46bd mov sp, r7 + 8008a70: f85d 7b04 ldr.w r7, [sp], #4 + 8008a74: 4770 bx lr + 8008a76: bf00 nop + 8008a78: fffff7f7 .word 0xfffff7f7 + +08008a7c : + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + 8008a7c: b580 push {r7, lr} + 8008a7e: b082 sub sp, #8 + 8008a80: af00 add r7, sp, #0 + 8008a82: 6078 str r0, [r7, #4] + 8008a84: 6039 str r1, [r7, #0] + /* Check the SDRAM handle parameter */ + if(hsdram == NULL) + 8008a86: 687b ldr r3, [r7, #4] + 8008a88: 2b00 cmp r3, #0 + 8008a8a: d101 bne.n 8008a90 + { + return HAL_ERROR; + 8008a8c: 2301 movs r3, #1 + 8008a8e: e025 b.n 8008adc + } + + if(hsdram->State == HAL_SDRAM_STATE_RESET) + 8008a90: 687b ldr r3, [r7, #4] + 8008a92: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8008a96: b2db uxtb r3, r3 + 8008a98: 2b00 cmp r3, #0 + 8008a9a: d106 bne.n 8008aaa + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; + 8008a9c: 687b ldr r3, [r7, #4] + 8008a9e: 2200 movs r2, #0 + 8008aa0: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); + 8008aa4: 6878 ldr r0, [r7, #4] + 8008aa6: f7fb fbfd bl 80042a4 +#endif + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 8008aaa: 687b ldr r3, [r7, #4] + 8008aac: 2202 movs r2, #2 + 8008aae: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Initialize SDRAM control Interface */ + FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + 8008ab2: 687b ldr r3, [r7, #4] + 8008ab4: 681a ldr r2, [r3, #0] + 8008ab6: 687b ldr r3, [r7, #4] + 8008ab8: 3304 adds r3, #4 + 8008aba: 4619 mov r1, r3 + 8008abc: 4610 mov r0, r2 + 8008abe: f001 fe61 bl 800a784 + + /* Initialize SDRAM timing Interface */ + FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + 8008ac2: 687b ldr r3, [r7, #4] + 8008ac4: 6818 ldr r0, [r3, #0] + 8008ac6: 687b ldr r3, [r7, #4] + 8008ac8: 685b ldr r3, [r3, #4] + 8008aca: 461a mov r2, r3 + 8008acc: 6839 ldr r1, [r7, #0] + 8008ace: f001 fecb bl 800a868 + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + 8008ad2: 687b ldr r3, [r7, #4] + 8008ad4: 2201 movs r2, #1 + 8008ad6: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8008ada: 2300 movs r3, #0 +} + 8008adc: 4618 mov r0, r3 + 8008ade: 3708 adds r7, #8 + 8008ae0: 46bd mov sp, r7 + 8008ae2: bd80 pop {r7, pc} + +08008ae4 : + * @param Command SDRAM command structure + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + 8008ae4: b580 push {r7, lr} + 8008ae6: b084 sub sp, #16 + 8008ae8: af00 add r7, sp, #0 + 8008aea: 60f8 str r0, [r7, #12] + 8008aec: 60b9 str r1, [r7, #8] + 8008aee: 607a str r2, [r7, #4] + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + 8008af0: 68fb ldr r3, [r7, #12] + 8008af2: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8008af6: b2db uxtb r3, r3 + 8008af8: 2b02 cmp r3, #2 + 8008afa: d101 bne.n 8008b00 + { + return HAL_BUSY; + 8008afc: 2302 movs r3, #2 + 8008afe: e018 b.n 8008b32 + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 8008b00: 68fb ldr r3, [r7, #12] + 8008b02: 2202 movs r2, #2 + 8008b04: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Send SDRAM command */ + FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + 8008b08: 68fb ldr r3, [r7, #12] + 8008b0a: 681b ldr r3, [r3, #0] + 8008b0c: 687a ldr r2, [r7, #4] + 8008b0e: 68b9 ldr r1, [r7, #8] + 8008b10: 4618 mov r0, r3 + 8008b12: f001 ff29 bl 800a968 + + /* Update the SDRAM controller state state */ + if(Command->CommandMode == FMC_SDRAM_CMD_PALL) + 8008b16: 68bb ldr r3, [r7, #8] + 8008b18: 681b ldr r3, [r3, #0] + 8008b1a: 2b02 cmp r3, #2 + 8008b1c: d104 bne.n 8008b28 + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + 8008b1e: 68fb ldr r3, [r7, #12] + 8008b20: 2205 movs r2, #5 + 8008b22: f883 202c strb.w r2, [r3, #44] ; 0x2c + 8008b26: e003 b.n 8008b30 + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + 8008b28: 68fb ldr r3, [r7, #12] + 8008b2a: 2201 movs r2, #1 + 8008b2c: f883 202c strb.w r2, [r3, #44] ; 0x2c + } + + return HAL_OK; + 8008b30: 2300 movs r3, #0 +} + 8008b32: 4618 mov r0, r3 + 8008b34: 3710 adds r7, #16 + 8008b36: 46bd mov sp, r7 + 8008b38: bd80 pop {r7, pc} + +08008b3a : + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + 8008b3a: b580 push {r7, lr} + 8008b3c: b082 sub sp, #8 + 8008b3e: af00 add r7, sp, #0 + 8008b40: 6078 str r0, [r7, #4] + 8008b42: 6039 str r1, [r7, #0] + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + 8008b44: 687b ldr r3, [r7, #4] + 8008b46: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8008b4a: b2db uxtb r3, r3 + 8008b4c: 2b02 cmp r3, #2 + 8008b4e: d101 bne.n 8008b54 + { + return HAL_BUSY; + 8008b50: 2302 movs r3, #2 + 8008b52: e00e b.n 8008b72 + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + 8008b54: 687b ldr r3, [r7, #4] + 8008b56: 2202 movs r2, #2 + 8008b58: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Program the refresh rate */ + FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + 8008b5c: 687b ldr r3, [r7, #4] + 8008b5e: 681b ldr r3, [r3, #0] + 8008b60: 6839 ldr r1, [r7, #0] + 8008b62: 4618 mov r0, r3 + 8008b64: f001 ff21 bl 800a9aa + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + 8008b68: 687b ldr r3, [r7, #4] + 8008b6a: 2201 movs r2, #1 + 8008b6c: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8008b70: 2300 movs r3, #0 +} + 8008b72: 4618 mov r0, r3 + 8008b74: 3708 adds r7, #8 + 8008b76: 46bd mov sp, r7 + 8008b78: bd80 pop {r7, pc} + +08008b7a : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8008b7a: b580 push {r7, lr} + 8008b7c: b084 sub sp, #16 + 8008b7e: af00 add r7, sp, #0 + 8008b80: 6078 str r0, [r7, #4] + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8008b82: 687b ldr r3, [r7, #4] + 8008b84: 2b00 cmp r3, #0 + 8008b86: d101 bne.n 8008b8c + { + return HAL_ERROR; + 8008b88: 2301 movs r3, #1 + 8008b8a: e084 b.n 8008c96 + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8008b8c: 687b ldr r3, [r7, #4] + 8008b8e: 2200 movs r2, #0 + 8008b90: 629a str r2, [r3, #40] ; 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8008b92: 687b ldr r3, [r7, #4] + 8008b94: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 8008b98: b2db uxtb r3, r3 + 8008b9a: 2b00 cmp r3, #0 + 8008b9c: d106 bne.n 8008bac + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8008b9e: 687b ldr r3, [r7, #4] + 8008ba0: 2200 movs r2, #0 + 8008ba2: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8008ba6: 6878 ldr r0, [r7, #4] + 8008ba8: f7fb f8e8 bl 8003d7c +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8008bac: 687b ldr r3, [r7, #4] + 8008bae: 2202 movs r2, #2 + 8008bb0: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8008bb4: 687b ldr r3, [r7, #4] + 8008bb6: 681b ldr r3, [r3, #0] + 8008bb8: 681a ldr r2, [r3, #0] + 8008bba: 687b ldr r3, [r7, #4] + 8008bbc: 681b ldr r3, [r3, #0] + 8008bbe: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8008bc2: 601a str r2, [r3, #0] + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 8008bc4: 687b ldr r3, [r7, #4] + 8008bc6: 68db ldr r3, [r3, #12] + 8008bc8: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8008bcc: d902 bls.n 8008bd4 + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + 8008bce: 2300 movs r3, #0 + 8008bd0: 60fb str r3, [r7, #12] + 8008bd2: e002 b.n 8008bda + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + 8008bd4: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8008bd8: 60fb str r3, [r7, #12] + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 8008bda: 687b ldr r3, [r7, #4] + 8008bdc: 68db ldr r3, [r3, #12] + 8008bde: f5b3 6f70 cmp.w r3, #3840 ; 0xf00 + 8008be2: d007 beq.n 8008bf4 + 8008be4: 687b ldr r3, [r7, #4] + 8008be6: 68db ldr r3, [r3, #12] + 8008be8: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8008bec: d002 beq.n 8008bf4 + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8008bee: 687b ldr r3, [r7, #4] + 8008bf0: 2200 movs r2, #0 + 8008bf2: 629a str r2, [r3, #40] ; 0x28 + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + 8008bf4: 687b ldr r3, [r7, #4] + 8008bf6: 6b1b ldr r3, [r3, #48] ; 0x30 + 8008bf8: 2b00 cmp r3, #0 + 8008bfa: d10b bne.n 8008c14 + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 8008bfc: 687b ldr r3, [r7, #4] + 8008bfe: 68db ldr r3, [r3, #12] + 8008c00: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8008c04: d903 bls.n 8008c0e + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + 8008c06: 687b ldr r3, [r7, #4] + 8008c08: 2202 movs r2, #2 + 8008c0a: 631a str r2, [r3, #48] ; 0x30 + 8008c0c: e002 b.n 8008c14 + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + 8008c0e: 687b ldr r3, [r7, #4] + 8008c10: 2201 movs r2, #1 + 8008c12: 631a str r2, [r3, #48] ; 0x30 + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | + 8008c14: 687b ldr r3, [r7, #4] + 8008c16: 685a ldr r2, [r3, #4] + 8008c18: 687b ldr r3, [r7, #4] + 8008c1a: 689b ldr r3, [r3, #8] + 8008c1c: 431a orrs r2, r3 + 8008c1e: 687b ldr r3, [r7, #4] + 8008c20: 691b ldr r3, [r3, #16] + 8008c22: 431a orrs r2, r3 + 8008c24: 687b ldr r3, [r7, #4] + 8008c26: 695b ldr r3, [r3, #20] + 8008c28: 431a orrs r2, r3 + 8008c2a: 687b ldr r3, [r7, #4] + 8008c2c: 699b ldr r3, [r3, #24] + 8008c2e: f403 7300 and.w r3, r3, #512 ; 0x200 + 8008c32: 431a orrs r2, r3 + 8008c34: 687b ldr r3, [r7, #4] + 8008c36: 69db ldr r3, [r3, #28] + 8008c38: 431a orrs r2, r3 + 8008c3a: 687b ldr r3, [r7, #4] + 8008c3c: 6a1b ldr r3, [r3, #32] + 8008c3e: ea42 0103 orr.w r1, r2, r3 + 8008c42: 687b ldr r3, [r7, #4] + 8008c44: 6a9a ldr r2, [r3, #40] ; 0x28 + 8008c46: 687b ldr r3, [r7, #4] + 8008c48: 681b ldr r3, [r3, #0] + 8008c4a: 430a orrs r2, r1 + 8008c4c: 601a str r2, [r3, #0] + hspi->Instance->CR1 |= SPI_CR1_CRCL; + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | + 8008c4e: 687b ldr r3, [r7, #4] + 8008c50: 699b ldr r3, [r3, #24] + 8008c52: 0c1b lsrs r3, r3, #16 + 8008c54: f003 0204 and.w r2, r3, #4 + 8008c58: 687b ldr r3, [r7, #4] + 8008c5a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8008c5c: 431a orrs r2, r3 + 8008c5e: 687b ldr r3, [r7, #4] + 8008c60: 6b5b ldr r3, [r3, #52] ; 0x34 + 8008c62: 431a orrs r2, r3 + 8008c64: 687b ldr r3, [r7, #4] + 8008c66: 68db ldr r3, [r3, #12] + 8008c68: ea42 0103 orr.w r1, r2, r3 + 8008c6c: 687b ldr r3, [r7, #4] + 8008c6e: 681b ldr r3, [r3, #0] + 8008c70: 68fa ldr r2, [r7, #12] + 8008c72: 430a orrs r2, r1 + 8008c74: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8008c76: 687b ldr r3, [r7, #4] + 8008c78: 681b ldr r3, [r3, #0] + 8008c7a: 69da ldr r2, [r3, #28] + 8008c7c: 687b ldr r3, [r7, #4] + 8008c7e: 681b ldr r3, [r3, #0] + 8008c80: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8008c84: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8008c86: 687b ldr r3, [r7, #4] + 8008c88: 2200 movs r2, #0 + 8008c8a: 661a str r2, [r3, #96] ; 0x60 + hspi->State = HAL_SPI_STATE_READY; + 8008c8c: 687b ldr r3, [r7, #4] + 8008c8e: 2201 movs r2, #1 + 8008c90: f883 205d strb.w r2, [r3, #93] ; 0x5d + + return HAL_OK; + 8008c94: 2300 movs r3, #0 +} + 8008c96: 4618 mov r0, r3 + 8008c98: 3710 adds r7, #16 + 8008c9a: 46bd mov sp, r7 + 8008c9c: bd80 pop {r7, pc} + +08008c9e : + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + 8008c9e: b580 push {r7, lr} + 8008ca0: b082 sub sp, #8 + 8008ca2: af00 add r7, sp, #0 + 8008ca4: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8008ca6: 687b ldr r3, [r7, #4] + 8008ca8: 2b00 cmp r3, #0 + 8008caa: d101 bne.n 8008cb0 + { + return HAL_ERROR; + 8008cac: 2301 movs r3, #1 + 8008cae: e01d b.n 8008cec + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8008cb0: 687b ldr r3, [r7, #4] + 8008cb2: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8008cb6: b2db uxtb r3, r3 + 8008cb8: 2b00 cmp r3, #0 + 8008cba: d106 bne.n 8008cca + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8008cbc: 687b ldr r3, [r7, #4] + 8008cbe: 2200 movs r2, #0 + 8008cc0: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); + 8008cc4: 6878 ldr r0, [r7, #4] + 8008cc6: f7fb f8cb bl 8003e60 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8008cca: 687b ldr r3, [r7, #4] + 8008ccc: 2202 movs r2, #2 + 8008cce: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8008cd2: 687b ldr r3, [r7, #4] + 8008cd4: 681a ldr r2, [r3, #0] + 8008cd6: 687b ldr r3, [r7, #4] + 8008cd8: 3304 adds r3, #4 + 8008cda: 4619 mov r1, r3 + 8008cdc: 4610 mov r0, r2 + 8008cde: f000 fbc3 bl 8009468 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8008ce2: 687b ldr r3, [r7, #4] + 8008ce4: 2201 movs r2, #1 + 8008ce6: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8008cea: 2300 movs r3, #0 +} + 8008cec: 4618 mov r0, r3 + 8008cee: 3708 adds r7, #8 + 8008cf0: 46bd mov sp, r7 + 8008cf2: bd80 pop {r7, pc} + +08008cf4 : + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + 8008cf4: b480 push {r7} + 8008cf6: b085 sub sp, #20 + 8008cf8: af00 add r7, sp, #0 + 8008cfa: 6078 str r0, [r7, #4] + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 8008cfc: 687b ldr r3, [r7, #4] + 8008cfe: 681b ldr r3, [r3, #0] + 8008d00: 68da ldr r2, [r3, #12] + 8008d02: 687b ldr r3, [r7, #4] + 8008d04: 681b ldr r3, [r3, #0] + 8008d06: f042 0201 orr.w r2, r2, #1 + 8008d0a: 60da str r2, [r3, #12] + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 8008d0c: 687b ldr r3, [r7, #4] + 8008d0e: 681b ldr r3, [r3, #0] + 8008d10: 689a ldr r2, [r3, #8] + 8008d12: 4b0c ldr r3, [pc, #48] ; (8008d44 ) + 8008d14: 4013 ands r3, r2 + 8008d16: 60fb str r3, [r7, #12] + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8008d18: 68fb ldr r3, [r7, #12] + 8008d1a: 2b06 cmp r3, #6 + 8008d1c: d00b beq.n 8008d36 + 8008d1e: 68fb ldr r3, [r7, #12] + 8008d20: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8008d24: d007 beq.n 8008d36 + { + __HAL_TIM_ENABLE(htim); + 8008d26: 687b ldr r3, [r7, #4] + 8008d28: 681b ldr r3, [r3, #0] + 8008d2a: 681a ldr r2, [r3, #0] + 8008d2c: 687b ldr r3, [r7, #4] + 8008d2e: 681b ldr r3, [r3, #0] + 8008d30: f042 0201 orr.w r2, r2, #1 + 8008d34: 601a str r2, [r3, #0] + } + + /* Return function status */ + return HAL_OK; + 8008d36: 2300 movs r3, #0 +} + 8008d38: 4618 mov r0, r3 + 8008d3a: 3714 adds r7, #20 + 8008d3c: 46bd mov sp, r7 + 8008d3e: f85d 7b04 ldr.w r7, [sp], #4 + 8008d42: 4770 bx lr + 8008d44: 00010007 .word 0x00010007 + +08008d48 : + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + 8008d48: b580 push {r7, lr} + 8008d4a: b082 sub sp, #8 + 8008d4c: af00 add r7, sp, #0 + 8008d4e: 6078 str r0, [r7, #4] + /* Check the TIM handle allocation */ + if (htim == NULL) + 8008d50: 687b ldr r3, [r7, #4] + 8008d52: 2b00 cmp r3, #0 + 8008d54: d101 bne.n 8008d5a + { + return HAL_ERROR; + 8008d56: 2301 movs r3, #1 + 8008d58: e01d b.n 8008d96 + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + 8008d5a: 687b ldr r3, [r7, #4] + 8008d5c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8008d60: b2db uxtb r3, r3 + 8008d62: 2b00 cmp r3, #0 + 8008d64: d106 bne.n 8008d74 + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + 8008d66: 687b ldr r3, [r7, #4] + 8008d68: 2200 movs r2, #0 + 8008d6a: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + 8008d6e: 6878 ldr r0, [r7, #4] + 8008d70: f000 f815 bl 8008d9e +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + 8008d74: 687b ldr r3, [r7, #4] + 8008d76: 2202 movs r2, #2 + 8008d78: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8008d7c: 687b ldr r3, [r7, #4] + 8008d7e: 681a ldr r2, [r3, #0] + 8008d80: 687b ldr r3, [r7, #4] + 8008d82: 3304 adds r3, #4 + 8008d84: 4619 mov r1, r3 + 8008d86: 4610 mov r0, r2 + 8008d88: f000 fb6e bl 8009468 + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + 8008d8c: 687b ldr r3, [r7, #4] + 8008d8e: 2201 movs r2, #1 + 8008d90: f883 203d strb.w r2, [r3, #61] ; 0x3d + + return HAL_OK; + 8008d94: 2300 movs r3, #0 +} + 8008d96: 4618 mov r0, r3 + 8008d98: 3708 adds r7, #8 + 8008d9a: 46bd mov sp, r7 + 8008d9c: bd80 pop {r7, pc} + +08008d9e : + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + 8008d9e: b480 push {r7} + 8008da0: b083 sub sp, #12 + 8008da2: af00 add r7, sp, #0 + 8008da4: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + 8008da6: bf00 nop + 8008da8: 370c adds r7, #12 + 8008daa: 46bd mov sp, r7 + 8008dac: f85d 7b04 ldr.w r7, [sp], #4 + 8008db0: 4770 bx lr + +08008db2 : + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + 8008db2: b580 push {r7, lr} + 8008db4: b082 sub sp, #8 + 8008db6: af00 add r7, sp, #0 + 8008db8: 6078 str r0, [r7, #4] + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 8008dba: 687b ldr r3, [r7, #4] + 8008dbc: 681b ldr r3, [r3, #0] + 8008dbe: 691b ldr r3, [r3, #16] + 8008dc0: f003 0302 and.w r3, r3, #2 + 8008dc4: 2b02 cmp r3, #2 + 8008dc6: d122 bne.n 8008e0e + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 8008dc8: 687b ldr r3, [r7, #4] + 8008dca: 681b ldr r3, [r3, #0] + 8008dcc: 68db ldr r3, [r3, #12] + 8008dce: f003 0302 and.w r3, r3, #2 + 8008dd2: 2b02 cmp r3, #2 + 8008dd4: d11b bne.n 8008e0e + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 8008dd6: 687b ldr r3, [r7, #4] + 8008dd8: 681b ldr r3, [r3, #0] + 8008dda: f06f 0202 mvn.w r2, #2 + 8008dde: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 8008de0: 687b ldr r3, [r7, #4] + 8008de2: 2201 movs r2, #1 + 8008de4: 771a strb r2, [r3, #28] + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 8008de6: 687b ldr r3, [r7, #4] + 8008de8: 681b ldr r3, [r3, #0] + 8008dea: 699b ldr r3, [r3, #24] + 8008dec: f003 0303 and.w r3, r3, #3 + 8008df0: 2b00 cmp r3, #0 + 8008df2: d003 beq.n 8008dfc + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8008df4: 6878 ldr r0, [r7, #4] + 8008df6: f000 fb19 bl 800942c + 8008dfa: e005 b.n 8008e08 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8008dfc: 6878 ldr r0, [r7, #4] + 8008dfe: f000 fb0b bl 8009418 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8008e02: 6878 ldr r0, [r7, #4] + 8008e04: f000 fb1c bl 8009440 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8008e08: 687b ldr r3, [r7, #4] + 8008e0a: 2200 movs r2, #0 + 8008e0c: 771a strb r2, [r3, #28] + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 8008e0e: 687b ldr r3, [r7, #4] + 8008e10: 681b ldr r3, [r3, #0] + 8008e12: 691b ldr r3, [r3, #16] + 8008e14: f003 0304 and.w r3, r3, #4 + 8008e18: 2b04 cmp r3, #4 + 8008e1a: d122 bne.n 8008e62 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 8008e1c: 687b ldr r3, [r7, #4] + 8008e1e: 681b ldr r3, [r3, #0] + 8008e20: 68db ldr r3, [r3, #12] + 8008e22: f003 0304 and.w r3, r3, #4 + 8008e26: 2b04 cmp r3, #4 + 8008e28: d11b bne.n 8008e62 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 8008e2a: 687b ldr r3, [r7, #4] + 8008e2c: 681b ldr r3, [r3, #0] + 8008e2e: f06f 0204 mvn.w r2, #4 + 8008e32: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 8008e34: 687b ldr r3, [r7, #4] + 8008e36: 2202 movs r2, #2 + 8008e38: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 8008e3a: 687b ldr r3, [r7, #4] + 8008e3c: 681b ldr r3, [r3, #0] + 8008e3e: 699b ldr r3, [r3, #24] + 8008e40: f403 7340 and.w r3, r3, #768 ; 0x300 + 8008e44: 2b00 cmp r3, #0 + 8008e46: d003 beq.n 8008e50 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8008e48: 6878 ldr r0, [r7, #4] + 8008e4a: f000 faef bl 800942c + 8008e4e: e005 b.n 8008e5c + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8008e50: 6878 ldr r0, [r7, #4] + 8008e52: f000 fae1 bl 8009418 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8008e56: 6878 ldr r0, [r7, #4] + 8008e58: f000 faf2 bl 8009440 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8008e5c: 687b ldr r3, [r7, #4] + 8008e5e: 2200 movs r2, #0 + 8008e60: 771a strb r2, [r3, #28] + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 8008e62: 687b ldr r3, [r7, #4] + 8008e64: 681b ldr r3, [r3, #0] + 8008e66: 691b ldr r3, [r3, #16] + 8008e68: f003 0308 and.w r3, r3, #8 + 8008e6c: 2b08 cmp r3, #8 + 8008e6e: d122 bne.n 8008eb6 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 8008e70: 687b ldr r3, [r7, #4] + 8008e72: 681b ldr r3, [r3, #0] + 8008e74: 68db ldr r3, [r3, #12] + 8008e76: f003 0308 and.w r3, r3, #8 + 8008e7a: 2b08 cmp r3, #8 + 8008e7c: d11b bne.n 8008eb6 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 8008e7e: 687b ldr r3, [r7, #4] + 8008e80: 681b ldr r3, [r3, #0] + 8008e82: f06f 0208 mvn.w r2, #8 + 8008e86: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 8008e88: 687b ldr r3, [r7, #4] + 8008e8a: 2204 movs r2, #4 + 8008e8c: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 8008e8e: 687b ldr r3, [r7, #4] + 8008e90: 681b ldr r3, [r3, #0] + 8008e92: 69db ldr r3, [r3, #28] + 8008e94: f003 0303 and.w r3, r3, #3 + 8008e98: 2b00 cmp r3, #0 + 8008e9a: d003 beq.n 8008ea4 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8008e9c: 6878 ldr r0, [r7, #4] + 8008e9e: f000 fac5 bl 800942c + 8008ea2: e005 b.n 8008eb0 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8008ea4: 6878 ldr r0, [r7, #4] + 8008ea6: f000 fab7 bl 8009418 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8008eaa: 6878 ldr r0, [r7, #4] + 8008eac: f000 fac8 bl 8009440 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8008eb0: 687b ldr r3, [r7, #4] + 8008eb2: 2200 movs r2, #0 + 8008eb4: 771a strb r2, [r3, #28] + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 8008eb6: 687b ldr r3, [r7, #4] + 8008eb8: 681b ldr r3, [r3, #0] + 8008eba: 691b ldr r3, [r3, #16] + 8008ebc: f003 0310 and.w r3, r3, #16 + 8008ec0: 2b10 cmp r3, #16 + 8008ec2: d122 bne.n 8008f0a + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 8008ec4: 687b ldr r3, [r7, #4] + 8008ec6: 681b ldr r3, [r3, #0] + 8008ec8: 68db ldr r3, [r3, #12] + 8008eca: f003 0310 and.w r3, r3, #16 + 8008ece: 2b10 cmp r3, #16 + 8008ed0: d11b bne.n 8008f0a + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 8008ed2: 687b ldr r3, [r7, #4] + 8008ed4: 681b ldr r3, [r3, #0] + 8008ed6: f06f 0210 mvn.w r2, #16 + 8008eda: 611a str r2, [r3, #16] + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 8008edc: 687b ldr r3, [r7, #4] + 8008ede: 2208 movs r2, #8 + 8008ee0: 771a strb r2, [r3, #28] + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 8008ee2: 687b ldr r3, [r7, #4] + 8008ee4: 681b ldr r3, [r3, #0] + 8008ee6: 69db ldr r3, [r3, #28] + 8008ee8: f403 7340 and.w r3, r3, #768 ; 0x300 + 8008eec: 2b00 cmp r3, #0 + 8008eee: d003 beq.n 8008ef8 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); + 8008ef0: 6878 ldr r0, [r7, #4] + 8008ef2: f000 fa9b bl 800942c + 8008ef6: e005 b.n 8008f04 + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + 8008ef8: 6878 ldr r0, [r7, #4] + 8008efa: f000 fa8d bl 8009418 + HAL_TIM_PWM_PulseFinishedCallback(htim); + 8008efe: 6878 ldr r0, [r7, #4] + 8008f00: f000 fa9e bl 8009440 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 8008f04: 687b ldr r3, [r7, #4] + 8008f06: 2200 movs r2, #0 + 8008f08: 771a strb r2, [r3, #28] + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 8008f0a: 687b ldr r3, [r7, #4] + 8008f0c: 681b ldr r3, [r3, #0] + 8008f0e: 691b ldr r3, [r3, #16] + 8008f10: f003 0301 and.w r3, r3, #1 + 8008f14: 2b01 cmp r3, #1 + 8008f16: d10e bne.n 8008f36 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 8008f18: 687b ldr r3, [r7, #4] + 8008f1a: 681b ldr r3, [r3, #0] + 8008f1c: 68db ldr r3, [r3, #12] + 8008f1e: f003 0301 and.w r3, r3, #1 + 8008f22: 2b01 cmp r3, #1 + 8008f24: d107 bne.n 8008f36 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 8008f26: 687b ldr r3, [r7, #4] + 8008f28: 681b ldr r3, [r3, #0] + 8008f2a: f06f 0201 mvn.w r2, #1 + 8008f2e: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); + 8008f30: 6878 ldr r0, [r7, #4] + 8008f32: f7f8 ffbf bl 8001eb4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 8008f36: 687b ldr r3, [r7, #4] + 8008f38: 681b ldr r3, [r3, #0] + 8008f3a: 691b ldr r3, [r3, #16] + 8008f3c: f003 0380 and.w r3, r3, #128 ; 0x80 + 8008f40: 2b80 cmp r3, #128 ; 0x80 + 8008f42: d10e bne.n 8008f62 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 8008f44: 687b ldr r3, [r7, #4] + 8008f46: 681b ldr r3, [r3, #0] + 8008f48: 68db ldr r3, [r3, #12] + 8008f4a: f003 0380 and.w r3, r3, #128 ; 0x80 + 8008f4e: 2b80 cmp r3, #128 ; 0x80 + 8008f50: d107 bne.n 8008f62 + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 8008f52: 687b ldr r3, [r7, #4] + 8008f54: 681b ldr r3, [r3, #0] + 8008f56: f06f 0280 mvn.w r2, #128 ; 0x80 + 8008f5a: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); + 8008f5c: 6878 ldr r0, [r7, #4] + 8008f5e: f000 ffb9 bl 8009ed4 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 8008f62: 687b ldr r3, [r7, #4] + 8008f64: 681b ldr r3, [r3, #0] + 8008f66: 691b ldr r3, [r3, #16] + 8008f68: f403 7380 and.w r3, r3, #256 ; 0x100 + 8008f6c: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8008f70: d10e bne.n 8008f90 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 8008f72: 687b ldr r3, [r7, #4] + 8008f74: 681b ldr r3, [r3, #0] + 8008f76: 68db ldr r3, [r3, #12] + 8008f78: f003 0380 and.w r3, r3, #128 ; 0x80 + 8008f7c: 2b80 cmp r3, #128 ; 0x80 + 8008f7e: d107 bne.n 8008f90 + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + 8008f80: 687b ldr r3, [r7, #4] + 8008f82: 681b ldr r3, [r3, #0] + 8008f84: f46f 7280 mvn.w r2, #256 ; 0x100 + 8008f88: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); + 8008f8a: 6878 ldr r0, [r7, #4] + 8008f8c: f000 ffac bl 8009ee8 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 8008f90: 687b ldr r3, [r7, #4] + 8008f92: 681b ldr r3, [r3, #0] + 8008f94: 691b ldr r3, [r3, #16] + 8008f96: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008f9a: 2b40 cmp r3, #64 ; 0x40 + 8008f9c: d10e bne.n 8008fbc + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 8008f9e: 687b ldr r3, [r7, #4] + 8008fa0: 681b ldr r3, [r3, #0] + 8008fa2: 68db ldr r3, [r3, #12] + 8008fa4: f003 0340 and.w r3, r3, #64 ; 0x40 + 8008fa8: 2b40 cmp r3, #64 ; 0x40 + 8008faa: d107 bne.n 8008fbc + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 8008fac: 687b ldr r3, [r7, #4] + 8008fae: 681b ldr r3, [r3, #0] + 8008fb0: f06f 0240 mvn.w r2, #64 ; 0x40 + 8008fb4: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); + 8008fb6: 6878 ldr r0, [r7, #4] + 8008fb8: f000 fa4c bl 8009454 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + 8008fbc: 687b ldr r3, [r7, #4] + 8008fbe: 681b ldr r3, [r3, #0] + 8008fc0: 691b ldr r3, [r3, #16] + 8008fc2: f003 0320 and.w r3, r3, #32 + 8008fc6: 2b20 cmp r3, #32 + 8008fc8: d10e bne.n 8008fe8 + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 8008fca: 687b ldr r3, [r7, #4] + 8008fcc: 681b ldr r3, [r3, #0] + 8008fce: 68db ldr r3, [r3, #12] + 8008fd0: f003 0320 and.w r3, r3, #32 + 8008fd4: 2b20 cmp r3, #32 + 8008fd6: d107 bne.n 8008fe8 + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 8008fd8: 687b ldr r3, [r7, #4] + 8008fda: 681b ldr r3, [r3, #0] + 8008fdc: f06f 0220 mvn.w r2, #32 + 8008fe0: 611a str r2, [r3, #16] +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); + 8008fe2: 6878 ldr r0, [r7, #4] + 8008fe4: f000 ff6c bl 8009ec0 +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + 8008fe8: bf00 nop + 8008fea: 3708 adds r7, #8 + 8008fec: 46bd mov sp, r7 + 8008fee: bd80 pop {r7, pc} + +08008ff0 : + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + 8008ff0: b580 push {r7, lr} + 8008ff2: b084 sub sp, #16 + 8008ff4: af00 add r7, sp, #0 + 8008ff6: 60f8 str r0, [r7, #12] + 8008ff8: 60b9 str r1, [r7, #8] + 8008ffa: 607a str r2, [r7, #4] + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + 8008ffc: 68fb ldr r3, [r7, #12] + 8008ffe: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8009002: 2b01 cmp r3, #1 + 8009004: d101 bne.n 800900a + 8009006: 2302 movs r3, #2 + 8009008: e105 b.n 8009216 + 800900a: 68fb ldr r3, [r7, #12] + 800900c: 2201 movs r2, #1 + 800900e: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8009012: 68fb ldr r3, [r7, #12] + 8009014: 2202 movs r2, #2 + 8009016: f883 203d strb.w r2, [r3, #61] ; 0x3d + + switch (Channel) + 800901a: 687b ldr r3, [r7, #4] + 800901c: 2b14 cmp r3, #20 + 800901e: f200 80f0 bhi.w 8009202 + 8009022: a201 add r2, pc, #4 ; (adr r2, 8009028 ) + 8009024: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009028: 0800907d .word 0x0800907d + 800902c: 08009203 .word 0x08009203 + 8009030: 08009203 .word 0x08009203 + 8009034: 08009203 .word 0x08009203 + 8009038: 080090bd .word 0x080090bd + 800903c: 08009203 .word 0x08009203 + 8009040: 08009203 .word 0x08009203 + 8009044: 08009203 .word 0x08009203 + 8009048: 080090ff .word 0x080090ff + 800904c: 08009203 .word 0x08009203 + 8009050: 08009203 .word 0x08009203 + 8009054: 08009203 .word 0x08009203 + 8009058: 0800913f .word 0x0800913f + 800905c: 08009203 .word 0x08009203 + 8009060: 08009203 .word 0x08009203 + 8009064: 08009203 .word 0x08009203 + 8009068: 08009181 .word 0x08009181 + 800906c: 08009203 .word 0x08009203 + 8009070: 08009203 .word 0x08009203 + 8009074: 08009203 .word 0x08009203 + 8009078: 080091c1 .word 0x080091c1 + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + 800907c: 68fb ldr r3, [r7, #12] + 800907e: 681b ldr r3, [r3, #0] + 8009080: 68b9 ldr r1, [r7, #8] + 8009082: 4618 mov r0, r3 + 8009084: f000 fa90 bl 80095a8 + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 8009088: 68fb ldr r3, [r7, #12] + 800908a: 681b ldr r3, [r3, #0] + 800908c: 699a ldr r2, [r3, #24] + 800908e: 68fb ldr r3, [r7, #12] + 8009090: 681b ldr r3, [r3, #0] + 8009092: f042 0208 orr.w r2, r2, #8 + 8009096: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 8009098: 68fb ldr r3, [r7, #12] + 800909a: 681b ldr r3, [r3, #0] + 800909c: 699a ldr r2, [r3, #24] + 800909e: 68fb ldr r3, [r7, #12] + 80090a0: 681b ldr r3, [r3, #0] + 80090a2: f022 0204 bic.w r2, r2, #4 + 80090a6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode; + 80090a8: 68fb ldr r3, [r7, #12] + 80090aa: 681b ldr r3, [r3, #0] + 80090ac: 6999 ldr r1, [r3, #24] + 80090ae: 68bb ldr r3, [r7, #8] + 80090b0: 691a ldr r2, [r3, #16] + 80090b2: 68fb ldr r3, [r7, #12] + 80090b4: 681b ldr r3, [r3, #0] + 80090b6: 430a orrs r2, r1 + 80090b8: 619a str r2, [r3, #24] + break; + 80090ba: e0a3 b.n 8009204 + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + 80090bc: 68fb ldr r3, [r7, #12] + 80090be: 681b ldr r3, [r3, #0] + 80090c0: 68b9 ldr r1, [r7, #8] + 80090c2: 4618 mov r0, r3 + 80090c4: f000 fae2 bl 800968c + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + 80090c8: 68fb ldr r3, [r7, #12] + 80090ca: 681b ldr r3, [r3, #0] + 80090cc: 699a ldr r2, [r3, #24] + 80090ce: 68fb ldr r3, [r7, #12] + 80090d0: 681b ldr r3, [r3, #0] + 80090d2: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 80090d6: 619a str r2, [r3, #24] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 80090d8: 68fb ldr r3, [r7, #12] + 80090da: 681b ldr r3, [r3, #0] + 80090dc: 699a ldr r2, [r3, #24] + 80090de: 68fb ldr r3, [r7, #12] + 80090e0: 681b ldr r3, [r3, #0] + 80090e2: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 80090e6: 619a str r2, [r3, #24] + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 80090e8: 68fb ldr r3, [r7, #12] + 80090ea: 681b ldr r3, [r3, #0] + 80090ec: 6999 ldr r1, [r3, #24] + 80090ee: 68bb ldr r3, [r7, #8] + 80090f0: 691b ldr r3, [r3, #16] + 80090f2: 021a lsls r2, r3, #8 + 80090f4: 68fb ldr r3, [r7, #12] + 80090f6: 681b ldr r3, [r3, #0] + 80090f8: 430a orrs r2, r1 + 80090fa: 619a str r2, [r3, #24] + break; + 80090fc: e082 b.n 8009204 + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + 80090fe: 68fb ldr r3, [r7, #12] + 8009100: 681b ldr r3, [r3, #0] + 8009102: 68b9 ldr r1, [r7, #8] + 8009104: 4618 mov r0, r3 + 8009106: f000 fb39 bl 800977c + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 800910a: 68fb ldr r3, [r7, #12] + 800910c: 681b ldr r3, [r3, #0] + 800910e: 69da ldr r2, [r3, #28] + 8009110: 68fb ldr r3, [r7, #12] + 8009112: 681b ldr r3, [r3, #0] + 8009114: f042 0208 orr.w r2, r2, #8 + 8009118: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 800911a: 68fb ldr r3, [r7, #12] + 800911c: 681b ldr r3, [r3, #0] + 800911e: 69da ldr r2, [r3, #28] + 8009120: 68fb ldr r3, [r7, #12] + 8009122: 681b ldr r3, [r3, #0] + 8009124: f022 0204 bic.w r2, r2, #4 + 8009128: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode; + 800912a: 68fb ldr r3, [r7, #12] + 800912c: 681b ldr r3, [r3, #0] + 800912e: 69d9 ldr r1, [r3, #28] + 8009130: 68bb ldr r3, [r7, #8] + 8009132: 691a ldr r2, [r3, #16] + 8009134: 68fb ldr r3, [r7, #12] + 8009136: 681b ldr r3, [r3, #0] + 8009138: 430a orrs r2, r1 + 800913a: 61da str r2, [r3, #28] + break; + 800913c: e062 b.n 8009204 + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + 800913e: 68fb ldr r3, [r7, #12] + 8009140: 681b ldr r3, [r3, #0] + 8009142: 68b9 ldr r1, [r7, #8] + 8009144: 4618 mov r0, r3 + 8009146: f000 fb8f bl 8009868 + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 800914a: 68fb ldr r3, [r7, #12] + 800914c: 681b ldr r3, [r3, #0] + 800914e: 69da ldr r2, [r3, #28] + 8009150: 68fb ldr r3, [r7, #12] + 8009152: 681b ldr r3, [r3, #0] + 8009154: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 8009158: 61da str r2, [r3, #28] + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 800915a: 68fb ldr r3, [r7, #12] + 800915c: 681b ldr r3, [r3, #0] + 800915e: 69da ldr r2, [r3, #28] + 8009160: 68fb ldr r3, [r7, #12] + 8009162: 681b ldr r3, [r3, #0] + 8009164: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 8009168: 61da str r2, [r3, #28] + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 800916a: 68fb ldr r3, [r7, #12] + 800916c: 681b ldr r3, [r3, #0] + 800916e: 69d9 ldr r1, [r3, #28] + 8009170: 68bb ldr r3, [r7, #8] + 8009172: 691b ldr r3, [r3, #16] + 8009174: 021a lsls r2, r3, #8 + 8009176: 68fb ldr r3, [r7, #12] + 8009178: 681b ldr r3, [r3, #0] + 800917a: 430a orrs r2, r1 + 800917c: 61da str r2, [r3, #28] + break; + 800917e: e041 b.n 8009204 + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + 8009180: 68fb ldr r3, [r7, #12] + 8009182: 681b ldr r3, [r3, #0] + 8009184: 68b9 ldr r1, [r7, #8] + 8009186: 4618 mov r0, r3 + 8009188: f000 fbc6 bl 8009918 + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + 800918c: 68fb ldr r3, [r7, #12] + 800918e: 681b ldr r3, [r3, #0] + 8009190: 6d5a ldr r2, [r3, #84] ; 0x54 + 8009192: 68fb ldr r3, [r7, #12] + 8009194: 681b ldr r3, [r3, #0] + 8009196: f042 0208 orr.w r2, r2, #8 + 800919a: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + 800919c: 68fb ldr r3, [r7, #12] + 800919e: 681b ldr r3, [r3, #0] + 80091a0: 6d5a ldr r2, [r3, #84] ; 0x54 + 80091a2: 68fb ldr r3, [r7, #12] + 80091a4: 681b ldr r3, [r3, #0] + 80091a6: f022 0204 bic.w r2, r2, #4 + 80091aa: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode; + 80091ac: 68fb ldr r3, [r7, #12] + 80091ae: 681b ldr r3, [r3, #0] + 80091b0: 6d59 ldr r1, [r3, #84] ; 0x54 + 80091b2: 68bb ldr r3, [r7, #8] + 80091b4: 691a ldr r2, [r3, #16] + 80091b6: 68fb ldr r3, [r7, #12] + 80091b8: 681b ldr r3, [r3, #0] + 80091ba: 430a orrs r2, r1 + 80091bc: 655a str r2, [r3, #84] ; 0x54 + break; + 80091be: e021 b.n 8009204 + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + 80091c0: 68fb ldr r3, [r7, #12] + 80091c2: 681b ldr r3, [r3, #0] + 80091c4: 68b9 ldr r1, [r7, #8] + 80091c6: 4618 mov r0, r3 + 80091c8: f000 fbf8 bl 80099bc + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + 80091cc: 68fb ldr r3, [r7, #12] + 80091ce: 681b ldr r3, [r3, #0] + 80091d0: 6d5a ldr r2, [r3, #84] ; 0x54 + 80091d2: 68fb ldr r3, [r7, #12] + 80091d4: 681b ldr r3, [r3, #0] + 80091d6: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 80091da: 655a str r2, [r3, #84] ; 0x54 + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + 80091dc: 68fb ldr r3, [r7, #12] + 80091de: 681b ldr r3, [r3, #0] + 80091e0: 6d5a ldr r2, [r3, #84] ; 0x54 + 80091e2: 68fb ldr r3, [r7, #12] + 80091e4: 681b ldr r3, [r3, #0] + 80091e6: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 80091ea: 655a str r2, [r3, #84] ; 0x54 + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 80091ec: 68fb ldr r3, [r7, #12] + 80091ee: 681b ldr r3, [r3, #0] + 80091f0: 6d59 ldr r1, [r3, #84] ; 0x54 + 80091f2: 68bb ldr r3, [r7, #8] + 80091f4: 691b ldr r3, [r3, #16] + 80091f6: 021a lsls r2, r3, #8 + 80091f8: 68fb ldr r3, [r7, #12] + 80091fa: 681b ldr r3, [r3, #0] + 80091fc: 430a orrs r2, r1 + 80091fe: 655a str r2, [r3, #84] ; 0x54 + break; + 8009200: e000 b.n 8009204 + } + + default: + break; + 8009202: bf00 nop + } + + htim->State = HAL_TIM_STATE_READY; + 8009204: 68fb ldr r3, [r7, #12] + 8009206: 2201 movs r2, #1 + 8009208: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 800920c: 68fb ldr r3, [r7, #12] + 800920e: 2200 movs r2, #0 + 8009210: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8009214: 2300 movs r3, #0 +} + 8009216: 4618 mov r0, r3 + 8009218: 3710 adds r7, #16 + 800921a: 46bd mov sp, r7 + 800921c: bd80 pop {r7, pc} + 800921e: bf00 nop + +08009220 : + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + 8009220: b580 push {r7, lr} + 8009222: b084 sub sp, #16 + 8009224: af00 add r7, sp, #0 + 8009226: 6078 str r0, [r7, #4] + 8009228: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + 800922a: 687b ldr r3, [r7, #4] + 800922c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8009230: 2b01 cmp r3, #1 + 8009232: d101 bne.n 8009238 + 8009234: 2302 movs r3, #2 + 8009236: e0a6 b.n 8009386 + 8009238: 687b ldr r3, [r7, #4] + 800923a: 2201 movs r2, #1 + 800923c: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 8009240: 687b ldr r3, [r7, #4] + 8009242: 2202 movs r2, #2 + 8009244: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + 8009248: 687b ldr r3, [r7, #4] + 800924a: 681b ldr r3, [r3, #0] + 800924c: 689b ldr r3, [r3, #8] + 800924e: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 8009250: 68fa ldr r2, [r7, #12] + 8009252: 4b4f ldr r3, [pc, #316] ; (8009390 ) + 8009254: 4013 ands r3, r2 + 8009256: 60fb str r3, [r7, #12] + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8009258: 68fb ldr r3, [r7, #12] + 800925a: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 800925e: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 8009260: 687b ldr r3, [r7, #4] + 8009262: 681b ldr r3, [r3, #0] + 8009264: 68fa ldr r2, [r7, #12] + 8009266: 609a str r2, [r3, #8] + + switch (sClockSourceConfig->ClockSource) + 8009268: 683b ldr r3, [r7, #0] + 800926a: 681b ldr r3, [r3, #0] + 800926c: 2b40 cmp r3, #64 ; 0x40 + 800926e: d067 beq.n 8009340 + 8009270: 2b40 cmp r3, #64 ; 0x40 + 8009272: d80b bhi.n 800928c + 8009274: 2b10 cmp r3, #16 + 8009276: d073 beq.n 8009360 + 8009278: 2b10 cmp r3, #16 + 800927a: d802 bhi.n 8009282 + 800927c: 2b00 cmp r3, #0 + 800927e: d06f beq.n 8009360 + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + 8009280: e078 b.n 8009374 + switch (sClockSourceConfig->ClockSource) + 8009282: 2b20 cmp r3, #32 + 8009284: d06c beq.n 8009360 + 8009286: 2b30 cmp r3, #48 ; 0x30 + 8009288: d06a beq.n 8009360 + break; + 800928a: e073 b.n 8009374 + switch (sClockSourceConfig->ClockSource) + 800928c: 2b70 cmp r3, #112 ; 0x70 + 800928e: d00d beq.n 80092ac + 8009290: 2b70 cmp r3, #112 ; 0x70 + 8009292: d804 bhi.n 800929e + 8009294: 2b50 cmp r3, #80 ; 0x50 + 8009296: d033 beq.n 8009300 + 8009298: 2b60 cmp r3, #96 ; 0x60 + 800929a: d041 beq.n 8009320 + break; + 800929c: e06a b.n 8009374 + switch (sClockSourceConfig->ClockSource) + 800929e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80092a2: d066 beq.n 8009372 + 80092a4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 80092a8: d017 beq.n 80092da + break; + 80092aa: e063 b.n 8009374 + TIM_ETR_SetConfig(htim->Instance, + 80092ac: 687b ldr r3, [r7, #4] + 80092ae: 6818 ldr r0, [r3, #0] + 80092b0: 683b ldr r3, [r7, #0] + 80092b2: 6899 ldr r1, [r3, #8] + 80092b4: 683b ldr r3, [r7, #0] + 80092b6: 685a ldr r2, [r3, #4] + 80092b8: 683b ldr r3, [r7, #0] + 80092ba: 68db ldr r3, [r3, #12] + 80092bc: f000 fcd4 bl 8009c68 + tmpsmcr = htim->Instance->SMCR; + 80092c0: 687b ldr r3, [r7, #4] + 80092c2: 681b ldr r3, [r3, #0] + 80092c4: 689b ldr r3, [r3, #8] + 80092c6: 60fb str r3, [r7, #12] + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 80092c8: 68fb ldr r3, [r7, #12] + 80092ca: f043 0377 orr.w r3, r3, #119 ; 0x77 + 80092ce: 60fb str r3, [r7, #12] + htim->Instance->SMCR = tmpsmcr; + 80092d0: 687b ldr r3, [r7, #4] + 80092d2: 681b ldr r3, [r3, #0] + 80092d4: 68fa ldr r2, [r7, #12] + 80092d6: 609a str r2, [r3, #8] + break; + 80092d8: e04c b.n 8009374 + TIM_ETR_SetConfig(htim->Instance, + 80092da: 687b ldr r3, [r7, #4] + 80092dc: 6818 ldr r0, [r3, #0] + 80092de: 683b ldr r3, [r7, #0] + 80092e0: 6899 ldr r1, [r3, #8] + 80092e2: 683b ldr r3, [r7, #0] + 80092e4: 685a ldr r2, [r3, #4] + 80092e6: 683b ldr r3, [r7, #0] + 80092e8: 68db ldr r3, [r3, #12] + 80092ea: f000 fcbd bl 8009c68 + htim->Instance->SMCR |= TIM_SMCR_ECE; + 80092ee: 687b ldr r3, [r7, #4] + 80092f0: 681b ldr r3, [r3, #0] + 80092f2: 689a ldr r2, [r3, #8] + 80092f4: 687b ldr r3, [r7, #4] + 80092f6: 681b ldr r3, [r3, #0] + 80092f8: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 80092fc: 609a str r2, [r3, #8] + break; + 80092fe: e039 b.n 8009374 + TIM_TI1_ConfigInputStage(htim->Instance, + 8009300: 687b ldr r3, [r7, #4] + 8009302: 6818 ldr r0, [r3, #0] + 8009304: 683b ldr r3, [r7, #0] + 8009306: 6859 ldr r1, [r3, #4] + 8009308: 683b ldr r3, [r7, #0] + 800930a: 68db ldr r3, [r3, #12] + 800930c: 461a mov r2, r3 + 800930e: f000 fc31 bl 8009b74 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 8009312: 687b ldr r3, [r7, #4] + 8009314: 681b ldr r3, [r3, #0] + 8009316: 2150 movs r1, #80 ; 0x50 + 8009318: 4618 mov r0, r3 + 800931a: f000 fc8a bl 8009c32 + break; + 800931e: e029 b.n 8009374 + TIM_TI2_ConfigInputStage(htim->Instance, + 8009320: 687b ldr r3, [r7, #4] + 8009322: 6818 ldr r0, [r3, #0] + 8009324: 683b ldr r3, [r7, #0] + 8009326: 6859 ldr r1, [r3, #4] + 8009328: 683b ldr r3, [r7, #0] + 800932a: 68db ldr r3, [r3, #12] + 800932c: 461a mov r2, r3 + 800932e: f000 fc50 bl 8009bd2 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 8009332: 687b ldr r3, [r7, #4] + 8009334: 681b ldr r3, [r3, #0] + 8009336: 2160 movs r1, #96 ; 0x60 + 8009338: 4618 mov r0, r3 + 800933a: f000 fc7a bl 8009c32 + break; + 800933e: e019 b.n 8009374 + TIM_TI1_ConfigInputStage(htim->Instance, + 8009340: 687b ldr r3, [r7, #4] + 8009342: 6818 ldr r0, [r3, #0] + 8009344: 683b ldr r3, [r7, #0] + 8009346: 6859 ldr r1, [r3, #4] + 8009348: 683b ldr r3, [r7, #0] + 800934a: 68db ldr r3, [r3, #12] + 800934c: 461a mov r2, r3 + 800934e: f000 fc11 bl 8009b74 + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 8009352: 687b ldr r3, [r7, #4] + 8009354: 681b ldr r3, [r3, #0] + 8009356: 2140 movs r1, #64 ; 0x40 + 8009358: 4618 mov r0, r3 + 800935a: f000 fc6a bl 8009c32 + break; + 800935e: e009 b.n 8009374 + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 8009360: 687b ldr r3, [r7, #4] + 8009362: 681a ldr r2, [r3, #0] + 8009364: 683b ldr r3, [r7, #0] + 8009366: 681b ldr r3, [r3, #0] + 8009368: 4619 mov r1, r3 + 800936a: 4610 mov r0, r2 + 800936c: f000 fc61 bl 8009c32 + break; + 8009370: e000 b.n 8009374 + break; + 8009372: bf00 nop + } + htim->State = HAL_TIM_STATE_READY; + 8009374: 687b ldr r3, [r7, #4] + 8009376: 2201 movs r2, #1 + 8009378: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 800937c: 687b ldr r3, [r7, #4] + 800937e: 2200 movs r2, #0 + 8009380: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8009384: 2300 movs r3, #0 +} + 8009386: 4618 mov r0, r3 + 8009388: 3710 adds r7, #16 + 800938a: 46bd mov sp, r7 + 800938c: bd80 pop {r7, pc} + 800938e: bf00 nop + 8009390: fffeff88 .word 0xfffeff88 + +08009394 : + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + 8009394: b580 push {r7, lr} + 8009396: b082 sub sp, #8 + 8009398: af00 add r7, sp, #0 + 800939a: 6078 str r0, [r7, #4] + 800939c: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + 800939e: 687b ldr r3, [r7, #4] + 80093a0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80093a4: 2b01 cmp r3, #1 + 80093a6: d101 bne.n 80093ac + 80093a8: 2302 movs r3, #2 + 80093aa: e031 b.n 8009410 + 80093ac: 687b ldr r3, [r7, #4] + 80093ae: 2201 movs r2, #1 + 80093b0: f883 203c strb.w r2, [r3, #60] ; 0x3c + + htim->State = HAL_TIM_STATE_BUSY; + 80093b4: 687b ldr r3, [r7, #4] + 80093b6: 2202 movs r2, #2 + 80093b8: f883 203d strb.w r2, [r3, #61] ; 0x3d + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + 80093bc: 6839 ldr r1, [r7, #0] + 80093be: 6878 ldr r0, [r7, #4] + 80093c0: f000 fb50 bl 8009a64 + 80093c4: 4603 mov r3, r0 + 80093c6: 2b00 cmp r3, #0 + 80093c8: d009 beq.n 80093de + { + htim->State = HAL_TIM_STATE_READY; + 80093ca: 687b ldr r3, [r7, #4] + 80093cc: 2201 movs r2, #1 + 80093ce: f883 203d strb.w r2, [r3, #61] ; 0x3d + __HAL_UNLOCK(htim); + 80093d2: 687b ldr r3, [r7, #4] + 80093d4: 2200 movs r2, #0 + 80093d6: f883 203c strb.w r2, [r3, #60] ; 0x3c + return HAL_ERROR; + 80093da: 2301 movs r3, #1 + 80093dc: e018 b.n 8009410 + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + 80093de: 687b ldr r3, [r7, #4] + 80093e0: 681b ldr r3, [r3, #0] + 80093e2: 68da ldr r2, [r3, #12] + 80093e4: 687b ldr r3, [r7, #4] + 80093e6: 681b ldr r3, [r3, #0] + 80093e8: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80093ec: 60da str r2, [r3, #12] + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + 80093ee: 687b ldr r3, [r7, #4] + 80093f0: 681b ldr r3, [r3, #0] + 80093f2: 68da ldr r2, [r3, #12] + 80093f4: 687b ldr r3, [r7, #4] + 80093f6: 681b ldr r3, [r3, #0] + 80093f8: f422 4280 bic.w r2, r2, #16384 ; 0x4000 + 80093fc: 60da str r2, [r3, #12] + + htim->State = HAL_TIM_STATE_READY; + 80093fe: 687b ldr r3, [r7, #4] + 8009400: 2201 movs r2, #1 + 8009402: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8009406: 687b ldr r3, [r7, #4] + 8009408: 2200 movs r2, #0 + 800940a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 800940e: 2300 movs r3, #0 +} + 8009410: 4618 mov r0, r3 + 8009412: 3708 adds r7, #8 + 8009414: 46bd mov sp, r7 + 8009416: bd80 pop {r7, pc} + +08009418 : + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8009418: b480 push {r7} + 800941a: b083 sub sp, #12 + 800941c: af00 add r7, sp, #0 + 800941e: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + 8009420: bf00 nop + 8009422: 370c adds r7, #12 + 8009424: 46bd mov sp, r7 + 8009426: f85d 7b04 ldr.w r7, [sp], #4 + 800942a: 4770 bx lr + +0800942c : + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + 800942c: b480 push {r7} + 800942e: b083 sub sp, #12 + 8009430: af00 add r7, sp, #0 + 8009432: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + 8009434: bf00 nop + 8009436: 370c adds r7, #12 + 8009438: 46bd mov sp, r7 + 800943a: f85d 7b04 ldr.w r7, [sp], #4 + 800943e: 4770 bx lr + +08009440 : + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + 8009440: b480 push {r7} + 8009442: b083 sub sp, #12 + 8009444: af00 add r7, sp, #0 + 8009446: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + 8009448: bf00 nop + 800944a: 370c adds r7, #12 + 800944c: 46bd mov sp, r7 + 800944e: f85d 7b04 ldr.w r7, [sp], #4 + 8009452: 4770 bx lr + +08009454 : + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + 8009454: b480 push {r7} + 8009456: b083 sub sp, #12 + 8009458: af00 add r7, sp, #0 + 800945a: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + 800945c: bf00 nop + 800945e: 370c adds r7, #12 + 8009460: 46bd mov sp, r7 + 8009462: f85d 7b04 ldr.w r7, [sp], #4 + 8009466: 4770 bx lr + +08009468 : + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + 8009468: b480 push {r7} + 800946a: b085 sub sp, #20 + 800946c: af00 add r7, sp, #0 + 800946e: 6078 str r0, [r7, #4] + 8009470: 6039 str r1, [r7, #0] + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + 8009472: 687b ldr r3, [r7, #4] + 8009474: 681b ldr r3, [r3, #0] + 8009476: 60fb str r3, [r7, #12] + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 8009478: 687b ldr r3, [r7, #4] + 800947a: 4a40 ldr r2, [pc, #256] ; (800957c ) + 800947c: 4293 cmp r3, r2 + 800947e: d013 beq.n 80094a8 + 8009480: 687b ldr r3, [r7, #4] + 8009482: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8009486: d00f beq.n 80094a8 + 8009488: 687b ldr r3, [r7, #4] + 800948a: 4a3d ldr r2, [pc, #244] ; (8009580 ) + 800948c: 4293 cmp r3, r2 + 800948e: d00b beq.n 80094a8 + 8009490: 687b ldr r3, [r7, #4] + 8009492: 4a3c ldr r2, [pc, #240] ; (8009584 ) + 8009494: 4293 cmp r3, r2 + 8009496: d007 beq.n 80094a8 + 8009498: 687b ldr r3, [r7, #4] + 800949a: 4a3b ldr r2, [pc, #236] ; (8009588 ) + 800949c: 4293 cmp r3, r2 + 800949e: d003 beq.n 80094a8 + 80094a0: 687b ldr r3, [r7, #4] + 80094a2: 4a3a ldr r2, [pc, #232] ; (800958c ) + 80094a4: 4293 cmp r3, r2 + 80094a6: d108 bne.n 80094ba + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 80094a8: 68fb ldr r3, [r7, #12] + 80094aa: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80094ae: 60fb str r3, [r7, #12] + tmpcr1 |= Structure->CounterMode; + 80094b0: 683b ldr r3, [r7, #0] + 80094b2: 685b ldr r3, [r3, #4] + 80094b4: 68fa ldr r2, [r7, #12] + 80094b6: 4313 orrs r3, r2 + 80094b8: 60fb str r3, [r7, #12] + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 80094ba: 687b ldr r3, [r7, #4] + 80094bc: 4a2f ldr r2, [pc, #188] ; (800957c ) + 80094be: 4293 cmp r3, r2 + 80094c0: d02b beq.n 800951a + 80094c2: 687b ldr r3, [r7, #4] + 80094c4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 80094c8: d027 beq.n 800951a + 80094ca: 687b ldr r3, [r7, #4] + 80094cc: 4a2c ldr r2, [pc, #176] ; (8009580 ) + 80094ce: 4293 cmp r3, r2 + 80094d0: d023 beq.n 800951a + 80094d2: 687b ldr r3, [r7, #4] + 80094d4: 4a2b ldr r2, [pc, #172] ; (8009584 ) + 80094d6: 4293 cmp r3, r2 + 80094d8: d01f beq.n 800951a + 80094da: 687b ldr r3, [r7, #4] + 80094dc: 4a2a ldr r2, [pc, #168] ; (8009588 ) + 80094de: 4293 cmp r3, r2 + 80094e0: d01b beq.n 800951a + 80094e2: 687b ldr r3, [r7, #4] + 80094e4: 4a29 ldr r2, [pc, #164] ; (800958c ) + 80094e6: 4293 cmp r3, r2 + 80094e8: d017 beq.n 800951a + 80094ea: 687b ldr r3, [r7, #4] + 80094ec: 4a28 ldr r2, [pc, #160] ; (8009590 ) + 80094ee: 4293 cmp r3, r2 + 80094f0: d013 beq.n 800951a + 80094f2: 687b ldr r3, [r7, #4] + 80094f4: 4a27 ldr r2, [pc, #156] ; (8009594 ) + 80094f6: 4293 cmp r3, r2 + 80094f8: d00f beq.n 800951a + 80094fa: 687b ldr r3, [r7, #4] + 80094fc: 4a26 ldr r2, [pc, #152] ; (8009598 ) + 80094fe: 4293 cmp r3, r2 + 8009500: d00b beq.n 800951a + 8009502: 687b ldr r3, [r7, #4] + 8009504: 4a25 ldr r2, [pc, #148] ; (800959c ) + 8009506: 4293 cmp r3, r2 + 8009508: d007 beq.n 800951a + 800950a: 687b ldr r3, [r7, #4] + 800950c: 4a24 ldr r2, [pc, #144] ; (80095a0 ) + 800950e: 4293 cmp r3, r2 + 8009510: d003 beq.n 800951a + 8009512: 687b ldr r3, [r7, #4] + 8009514: 4a23 ldr r2, [pc, #140] ; (80095a4 ) + 8009516: 4293 cmp r3, r2 + 8009518: d108 bne.n 800952c + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + 800951a: 68fb ldr r3, [r7, #12] + 800951c: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8009520: 60fb str r3, [r7, #12] + tmpcr1 |= (uint32_t)Structure->ClockDivision; + 8009522: 683b ldr r3, [r7, #0] + 8009524: 68db ldr r3, [r3, #12] + 8009526: 68fa ldr r2, [r7, #12] + 8009528: 4313 orrs r3, r2 + 800952a: 60fb str r3, [r7, #12] + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 800952c: 68fb ldr r3, [r7, #12] + 800952e: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8009532: 683b ldr r3, [r7, #0] + 8009534: 695b ldr r3, [r3, #20] + 8009536: 4313 orrs r3, r2 + 8009538: 60fb str r3, [r7, #12] + + TIMx->CR1 = tmpcr1; + 800953a: 687b ldr r3, [r7, #4] + 800953c: 68fa ldr r2, [r7, #12] + 800953e: 601a str r2, [r3, #0] + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + 8009540: 683b ldr r3, [r7, #0] + 8009542: 689a ldr r2, [r3, #8] + 8009544: 687b ldr r3, [r7, #4] + 8009546: 62da str r2, [r3, #44] ; 0x2c + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + 8009548: 683b ldr r3, [r7, #0] + 800954a: 681a ldr r2, [r3, #0] + 800954c: 687b ldr r3, [r7, #4] + 800954e: 629a str r2, [r3, #40] ; 0x28 + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 8009550: 687b ldr r3, [r7, #4] + 8009552: 4a0a ldr r2, [pc, #40] ; (800957c ) + 8009554: 4293 cmp r3, r2 + 8009556: d003 beq.n 8009560 + 8009558: 687b ldr r3, [r7, #4] + 800955a: 4a0c ldr r2, [pc, #48] ; (800958c ) + 800955c: 4293 cmp r3, r2 + 800955e: d103 bne.n 8009568 + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + 8009560: 683b ldr r3, [r7, #0] + 8009562: 691a ldr r2, [r3, #16] + 8009564: 687b ldr r3, [r7, #4] + 8009566: 631a str r2, [r3, #48] ; 0x30 + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + 8009568: 687b ldr r3, [r7, #4] + 800956a: 2201 movs r2, #1 + 800956c: 615a str r2, [r3, #20] +} + 800956e: bf00 nop + 8009570: 3714 adds r7, #20 + 8009572: 46bd mov sp, r7 + 8009574: f85d 7b04 ldr.w r7, [sp], #4 + 8009578: 4770 bx lr + 800957a: bf00 nop + 800957c: 40010000 .word 0x40010000 + 8009580: 40000400 .word 0x40000400 + 8009584: 40000800 .word 0x40000800 + 8009588: 40000c00 .word 0x40000c00 + 800958c: 40010400 .word 0x40010400 + 8009590: 40014000 .word 0x40014000 + 8009594: 40014400 .word 0x40014400 + 8009598: 40014800 .word 0x40014800 + 800959c: 40001800 .word 0x40001800 + 80095a0: 40001c00 .word 0x40001c00 + 80095a4: 40002000 .word 0x40002000 + +080095a8 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 80095a8: b480 push {r7} + 80095aa: b087 sub sp, #28 + 80095ac: af00 add r7, sp, #0 + 80095ae: 6078 str r0, [r7, #4] + 80095b0: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + 80095b2: 687b ldr r3, [r7, #4] + 80095b4: 6a1b ldr r3, [r3, #32] + 80095b6: f023 0201 bic.w r2, r3, #1 + 80095ba: 687b ldr r3, [r7, #4] + 80095bc: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80095be: 687b ldr r3, [r7, #4] + 80095c0: 6a1b ldr r3, [r3, #32] + 80095c2: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80095c4: 687b ldr r3, [r7, #4] + 80095c6: 685b ldr r3, [r3, #4] + 80095c8: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 80095ca: 687b ldr r3, [r7, #4] + 80095cc: 699b ldr r3, [r3, #24] + 80095ce: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + 80095d0: 68fa ldr r2, [r7, #12] + 80095d2: 4b2b ldr r3, [pc, #172] ; (8009680 ) + 80095d4: 4013 ands r3, r2 + 80095d6: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC1S; + 80095d8: 68fb ldr r3, [r7, #12] + 80095da: f023 0303 bic.w r3, r3, #3 + 80095de: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80095e0: 683b ldr r3, [r7, #0] + 80095e2: 681b ldr r3, [r3, #0] + 80095e4: 68fa ldr r2, [r7, #12] + 80095e6: 4313 orrs r3, r2 + 80095e8: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + 80095ea: 697b ldr r3, [r7, #20] + 80095ec: f023 0302 bic.w r3, r3, #2 + 80095f0: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + 80095f2: 683b ldr r3, [r7, #0] + 80095f4: 689b ldr r3, [r3, #8] + 80095f6: 697a ldr r2, [r7, #20] + 80095f8: 4313 orrs r3, r2 + 80095fa: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 80095fc: 687b ldr r3, [r7, #4] + 80095fe: 4a21 ldr r2, [pc, #132] ; (8009684 ) + 8009600: 4293 cmp r3, r2 + 8009602: d003 beq.n 800960c + 8009604: 687b ldr r3, [r7, #4] + 8009606: 4a20 ldr r2, [pc, #128] ; (8009688 ) + 8009608: 4293 cmp r3, r2 + 800960a: d10c bne.n 8009626 + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + 800960c: 697b ldr r3, [r7, #20] + 800960e: f023 0308 bic.w r3, r3, #8 + 8009612: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + 8009614: 683b ldr r3, [r7, #0] + 8009616: 68db ldr r3, [r3, #12] + 8009618: 697a ldr r2, [r7, #20] + 800961a: 4313 orrs r3, r2 + 800961c: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + 800961e: 697b ldr r3, [r7, #20] + 8009620: f023 0304 bic.w r3, r3, #4 + 8009624: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8009626: 687b ldr r3, [r7, #4] + 8009628: 4a16 ldr r2, [pc, #88] ; (8009684 ) + 800962a: 4293 cmp r3, r2 + 800962c: d003 beq.n 8009636 + 800962e: 687b ldr r3, [r7, #4] + 8009630: 4a15 ldr r2, [pc, #84] ; (8009688 ) + 8009632: 4293 cmp r3, r2 + 8009634: d111 bne.n 800965a + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + 8009636: 693b ldr r3, [r7, #16] + 8009638: f423 7380 bic.w r3, r3, #256 ; 0x100 + 800963c: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS1N; + 800963e: 693b ldr r3, [r7, #16] + 8009640: f423 7300 bic.w r3, r3, #512 ; 0x200 + 8009644: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + 8009646: 683b ldr r3, [r7, #0] + 8009648: 695b ldr r3, [r3, #20] + 800964a: 693a ldr r2, [r7, #16] + 800964c: 4313 orrs r3, r2 + 800964e: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + 8009650: 683b ldr r3, [r7, #0] + 8009652: 699b ldr r3, [r3, #24] + 8009654: 693a ldr r2, [r7, #16] + 8009656: 4313 orrs r3, r2 + 8009658: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800965a: 687b ldr r3, [r7, #4] + 800965c: 693a ldr r2, [r7, #16] + 800965e: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 8009660: 687b ldr r3, [r7, #4] + 8009662: 68fa ldr r2, [r7, #12] + 8009664: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + 8009666: 683b ldr r3, [r7, #0] + 8009668: 685a ldr r2, [r3, #4] + 800966a: 687b ldr r3, [r7, #4] + 800966c: 635a str r2, [r3, #52] ; 0x34 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800966e: 687b ldr r3, [r7, #4] + 8009670: 697a ldr r2, [r7, #20] + 8009672: 621a str r2, [r3, #32] +} + 8009674: bf00 nop + 8009676: 371c adds r7, #28 + 8009678: 46bd mov sp, r7 + 800967a: f85d 7b04 ldr.w r7, [sp], #4 + 800967e: 4770 bx lr + 8009680: fffeff8f .word 0xfffeff8f + 8009684: 40010000 .word 0x40010000 + 8009688: 40010400 .word 0x40010400 + +0800968c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 800968c: b480 push {r7} + 800968e: b087 sub sp, #28 + 8009690: af00 add r7, sp, #0 + 8009692: 6078 str r0, [r7, #4] + 8009694: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8009696: 687b ldr r3, [r7, #4] + 8009698: 6a1b ldr r3, [r3, #32] + 800969a: f023 0210 bic.w r2, r3, #16 + 800969e: 687b ldr r3, [r7, #4] + 80096a0: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80096a2: 687b ldr r3, [r7, #4] + 80096a4: 6a1b ldr r3, [r3, #32] + 80096a6: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80096a8: 687b ldr r3, [r7, #4] + 80096aa: 685b ldr r3, [r3, #4] + 80096ac: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + 80096ae: 687b ldr r3, [r7, #4] + 80096b0: 699b ldr r3, [r3, #24] + 80096b2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + 80096b4: 68fa ldr r2, [r7, #12] + 80096b6: 4b2e ldr r3, [pc, #184] ; (8009770 ) + 80096b8: 4013 ands r3, r2 + 80096ba: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR1_CC2S; + 80096bc: 68fb ldr r3, [r7, #12] + 80096be: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80096c2: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80096c4: 683b ldr r3, [r7, #0] + 80096c6: 681b ldr r3, [r3, #0] + 80096c8: 021b lsls r3, r3, #8 + 80096ca: 68fa ldr r2, [r7, #12] + 80096cc: 4313 orrs r3, r2 + 80096ce: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + 80096d0: 697b ldr r3, [r7, #20] + 80096d2: f023 0320 bic.w r3, r3, #32 + 80096d6: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + 80096d8: 683b ldr r3, [r7, #0] + 80096da: 689b ldr r3, [r3, #8] + 80096dc: 011b lsls r3, r3, #4 + 80096de: 697a ldr r2, [r7, #20] + 80096e0: 4313 orrs r3, r2 + 80096e2: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 80096e4: 687b ldr r3, [r7, #4] + 80096e6: 4a23 ldr r2, [pc, #140] ; (8009774 ) + 80096e8: 4293 cmp r3, r2 + 80096ea: d003 beq.n 80096f4 + 80096ec: 687b ldr r3, [r7, #4] + 80096ee: 4a22 ldr r2, [pc, #136] ; (8009778 ) + 80096f0: 4293 cmp r3, r2 + 80096f2: d10d bne.n 8009710 + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + 80096f4: 697b ldr r3, [r7, #20] + 80096f6: f023 0380 bic.w r3, r3, #128 ; 0x80 + 80096fa: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + 80096fc: 683b ldr r3, [r7, #0] + 80096fe: 68db ldr r3, [r3, #12] + 8009700: 011b lsls r3, r3, #4 + 8009702: 697a ldr r2, [r7, #20] + 8009704: 4313 orrs r3, r2 + 8009706: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + 8009708: 697b ldr r3, [r7, #20] + 800970a: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800970e: 617b str r3, [r7, #20] + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8009710: 687b ldr r3, [r7, #4] + 8009712: 4a18 ldr r2, [pc, #96] ; (8009774 ) + 8009714: 4293 cmp r3, r2 + 8009716: d003 beq.n 8009720 + 8009718: 687b ldr r3, [r7, #4] + 800971a: 4a17 ldr r2, [pc, #92] ; (8009778 ) + 800971c: 4293 cmp r3, r2 + 800971e: d113 bne.n 8009748 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + 8009720: 693b ldr r3, [r7, #16] + 8009722: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8009726: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS2N; + 8009728: 693b ldr r3, [r7, #16] + 800972a: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 800972e: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + 8009730: 683b ldr r3, [r7, #0] + 8009732: 695b ldr r3, [r3, #20] + 8009734: 009b lsls r3, r3, #2 + 8009736: 693a ldr r2, [r7, #16] + 8009738: 4313 orrs r3, r2 + 800973a: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 800973c: 683b ldr r3, [r7, #0] + 800973e: 699b ldr r3, [r3, #24] + 8009740: 009b lsls r3, r3, #2 + 8009742: 693a ldr r2, [r7, #16] + 8009744: 4313 orrs r3, r2 + 8009746: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8009748: 687b ldr r3, [r7, #4] + 800974a: 693a ldr r2, [r7, #16] + 800974c: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + 800974e: 687b ldr r3, [r7, #4] + 8009750: 68fa ldr r2, [r7, #12] + 8009752: 619a str r2, [r3, #24] + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + 8009754: 683b ldr r3, [r7, #0] + 8009756: 685a ldr r2, [r3, #4] + 8009758: 687b ldr r3, [r7, #4] + 800975a: 639a str r2, [r3, #56] ; 0x38 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800975c: 687b ldr r3, [r7, #4] + 800975e: 697a ldr r2, [r7, #20] + 8009760: 621a str r2, [r3, #32] +} + 8009762: bf00 nop + 8009764: 371c adds r7, #28 + 8009766: 46bd mov sp, r7 + 8009768: f85d 7b04 ldr.w r7, [sp], #4 + 800976c: 4770 bx lr + 800976e: bf00 nop + 8009770: feff8fff .word 0xfeff8fff + 8009774: 40010000 .word 0x40010000 + 8009778: 40010400 .word 0x40010400 + +0800977c : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 800977c: b480 push {r7} + 800977e: b087 sub sp, #28 + 8009780: af00 add r7, sp, #0 + 8009782: 6078 str r0, [r7, #4] + 8009784: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + 8009786: 687b ldr r3, [r7, #4] + 8009788: 6a1b ldr r3, [r3, #32] + 800978a: f423 7280 bic.w r2, r3, #256 ; 0x100 + 800978e: 687b ldr r3, [r7, #4] + 8009790: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 8009792: 687b ldr r3, [r7, #4] + 8009794: 6a1b ldr r3, [r3, #32] + 8009796: 617b str r3, [r7, #20] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8009798: 687b ldr r3, [r7, #4] + 800979a: 685b ldr r3, [r3, #4] + 800979c: 613b str r3, [r7, #16] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 800979e: 687b ldr r3, [r7, #4] + 80097a0: 69db ldr r3, [r3, #28] + 80097a2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + 80097a4: 68fa ldr r2, [r7, #12] + 80097a6: 4b2d ldr r3, [pc, #180] ; (800985c ) + 80097a8: 4013 ands r3, r2 + 80097aa: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC3S; + 80097ac: 68fb ldr r3, [r7, #12] + 80097ae: f023 0303 bic.w r3, r3, #3 + 80097b2: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 80097b4: 683b ldr r3, [r7, #0] + 80097b6: 681b ldr r3, [r3, #0] + 80097b8: 68fa ldr r2, [r7, #12] + 80097ba: 4313 orrs r3, r2 + 80097bc: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + 80097be: 697b ldr r3, [r7, #20] + 80097c0: f423 7300 bic.w r3, r3, #512 ; 0x200 + 80097c4: 617b str r3, [r7, #20] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + 80097c6: 683b ldr r3, [r7, #0] + 80097c8: 689b ldr r3, [r3, #8] + 80097ca: 021b lsls r3, r3, #8 + 80097cc: 697a ldr r2, [r7, #20] + 80097ce: 4313 orrs r3, r2 + 80097d0: 617b str r3, [r7, #20] + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 80097d2: 687b ldr r3, [r7, #4] + 80097d4: 4a22 ldr r2, [pc, #136] ; (8009860 ) + 80097d6: 4293 cmp r3, r2 + 80097d8: d003 beq.n 80097e2 + 80097da: 687b ldr r3, [r7, #4] + 80097dc: 4a21 ldr r2, [pc, #132] ; (8009864 ) + 80097de: 4293 cmp r3, r2 + 80097e0: d10d bne.n 80097fe + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + 80097e2: 697b ldr r3, [r7, #20] + 80097e4: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 80097e8: 617b str r3, [r7, #20] + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + 80097ea: 683b ldr r3, [r7, #0] + 80097ec: 68db ldr r3, [r3, #12] + 80097ee: 021b lsls r3, r3, #8 + 80097f0: 697a ldr r2, [r7, #20] + 80097f2: 4313 orrs r3, r2 + 80097f4: 617b str r3, [r7, #20] + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + 80097f6: 697b ldr r3, [r7, #20] + 80097f8: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 80097fc: 617b str r3, [r7, #20] + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80097fe: 687b ldr r3, [r7, #4] + 8009800: 4a17 ldr r2, [pc, #92] ; (8009860 ) + 8009802: 4293 cmp r3, r2 + 8009804: d003 beq.n 800980e + 8009806: 687b ldr r3, [r7, #4] + 8009808: 4a16 ldr r2, [pc, #88] ; (8009864 ) + 800980a: 4293 cmp r3, r2 + 800980c: d113 bne.n 8009836 + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + 800980e: 693b ldr r3, [r7, #16] + 8009810: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8009814: 613b str r3, [r7, #16] + tmpcr2 &= ~TIM_CR2_OIS3N; + 8009816: 693b ldr r3, [r7, #16] + 8009818: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 800981c: 613b str r3, [r7, #16] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + 800981e: 683b ldr r3, [r7, #0] + 8009820: 695b ldr r3, [r3, #20] + 8009822: 011b lsls r3, r3, #4 + 8009824: 693a ldr r2, [r7, #16] + 8009826: 4313 orrs r3, r2 + 8009828: 613b str r3, [r7, #16] + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 800982a: 683b ldr r3, [r7, #0] + 800982c: 699b ldr r3, [r3, #24] + 800982e: 011b lsls r3, r3, #4 + 8009830: 693a ldr r2, [r7, #16] + 8009832: 4313 orrs r3, r2 + 8009834: 613b str r3, [r7, #16] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8009836: 687b ldr r3, [r7, #4] + 8009838: 693a ldr r2, [r7, #16] + 800983a: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 800983c: 687b ldr r3, [r7, #4] + 800983e: 68fa ldr r2, [r7, #12] + 8009840: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + 8009842: 683b ldr r3, [r7, #0] + 8009844: 685a ldr r2, [r3, #4] + 8009846: 687b ldr r3, [r7, #4] + 8009848: 63da str r2, [r3, #60] ; 0x3c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800984a: 687b ldr r3, [r7, #4] + 800984c: 697a ldr r2, [r7, #20] + 800984e: 621a str r2, [r3, #32] +} + 8009850: bf00 nop + 8009852: 371c adds r7, #28 + 8009854: 46bd mov sp, r7 + 8009856: f85d 7b04 ldr.w r7, [sp], #4 + 800985a: 4770 bx lr + 800985c: fffeff8f .word 0xfffeff8f + 8009860: 40010000 .word 0x40010000 + 8009864: 40010400 .word 0x40010400 + +08009868 : + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + 8009868: b480 push {r7} + 800986a: b087 sub sp, #28 + 800986c: af00 add r7, sp, #0 + 800986e: 6078 str r0, [r7, #4] + 8009870: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + 8009872: 687b ldr r3, [r7, #4] + 8009874: 6a1b ldr r3, [r3, #32] + 8009876: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 800987a: 687b ldr r3, [r7, #4] + 800987c: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800987e: 687b ldr r3, [r7, #4] + 8009880: 6a1b ldr r3, [r3, #32] + 8009882: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8009884: 687b ldr r3, [r7, #4] + 8009886: 685b ldr r3, [r3, #4] + 8009888: 617b str r3, [r7, #20] + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + 800988a: 687b ldr r3, [r7, #4] + 800988c: 69db ldr r3, [r3, #28] + 800988e: 60fb str r3, [r7, #12] + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + 8009890: 68fa ldr r2, [r7, #12] + 8009892: 4b1e ldr r3, [pc, #120] ; (800990c ) + 8009894: 4013 ands r3, r2 + 8009896: 60fb str r3, [r7, #12] + tmpccmrx &= ~TIM_CCMR2_CC4S; + 8009898: 68fb ldr r3, [r7, #12] + 800989a: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800989e: 60fb str r3, [r7, #12] + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80098a0: 683b ldr r3, [r7, #0] + 80098a2: 681b ldr r3, [r3, #0] + 80098a4: 021b lsls r3, r3, #8 + 80098a6: 68fa ldr r2, [r7, #12] + 80098a8: 4313 orrs r3, r2 + 80098aa: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + 80098ac: 693b ldr r3, [r7, #16] + 80098ae: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 80098b2: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + 80098b4: 683b ldr r3, [r7, #0] + 80098b6: 689b ldr r3, [r3, #8] + 80098b8: 031b lsls r3, r3, #12 + 80098ba: 693a ldr r2, [r7, #16] + 80098bc: 4313 orrs r3, r2 + 80098be: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 80098c0: 687b ldr r3, [r7, #4] + 80098c2: 4a13 ldr r2, [pc, #76] ; (8009910 ) + 80098c4: 4293 cmp r3, r2 + 80098c6: d003 beq.n 80098d0 + 80098c8: 687b ldr r3, [r7, #4] + 80098ca: 4a12 ldr r2, [pc, #72] ; (8009914 ) + 80098cc: 4293 cmp r3, r2 + 80098ce: d109 bne.n 80098e4 + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + 80098d0: 697b ldr r3, [r7, #20] + 80098d2: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 80098d6: 617b str r3, [r7, #20] + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + 80098d8: 683b ldr r3, [r7, #0] + 80098da: 695b ldr r3, [r3, #20] + 80098dc: 019b lsls r3, r3, #6 + 80098de: 697a ldr r2, [r7, #20] + 80098e0: 4313 orrs r3, r2 + 80098e2: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 80098e4: 687b ldr r3, [r7, #4] + 80098e6: 697a ldr r2, [r7, #20] + 80098e8: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + 80098ea: 687b ldr r3, [r7, #4] + 80098ec: 68fa ldr r2, [r7, #12] + 80098ee: 61da str r2, [r3, #28] + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + 80098f0: 683b ldr r3, [r7, #0] + 80098f2: 685a ldr r2, [r3, #4] + 80098f4: 687b ldr r3, [r7, #4] + 80098f6: 641a str r2, [r3, #64] ; 0x40 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 80098f8: 687b ldr r3, [r7, #4] + 80098fa: 693a ldr r2, [r7, #16] + 80098fc: 621a str r2, [r3, #32] +} + 80098fe: bf00 nop + 8009900: 371c adds r7, #28 + 8009902: 46bd mov sp, r7 + 8009904: f85d 7b04 ldr.w r7, [sp], #4 + 8009908: 4770 bx lr + 800990a: bf00 nop + 800990c: feff8fff .word 0xfeff8fff + 8009910: 40010000 .word 0x40010000 + 8009914: 40010400 .word 0x40010400 + +08009918 : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 8009918: b480 push {r7} + 800991a: b087 sub sp, #28 + 800991c: af00 add r7, sp, #0 + 800991e: 6078 str r0, [r7, #4] + 8009920: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + 8009922: 687b ldr r3, [r7, #4] + 8009924: 6a1b ldr r3, [r3, #32] + 8009926: f423 3280 bic.w r2, r3, #65536 ; 0x10000 + 800992a: 687b ldr r3, [r7, #4] + 800992c: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 800992e: 687b ldr r3, [r7, #4] + 8009930: 6a1b ldr r3, [r3, #32] + 8009932: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 8009934: 687b ldr r3, [r7, #4] + 8009936: 685b ldr r3, [r3, #4] + 8009938: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 800993a: 687b ldr r3, [r7, #4] + 800993c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800993e: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + 8009940: 68fa ldr r2, [r7, #12] + 8009942: 4b1b ldr r3, [pc, #108] ; (80099b0 ) + 8009944: 4013 ands r3, r2 + 8009946: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + 8009948: 683b ldr r3, [r7, #0] + 800994a: 681b ldr r3, [r3, #0] + 800994c: 68fa ldr r2, [r7, #12] + 800994e: 4313 orrs r3, r2 + 8009950: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + 8009952: 693b ldr r3, [r7, #16] + 8009954: f423 3300 bic.w r3, r3, #131072 ; 0x20000 + 8009958: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + 800995a: 683b ldr r3, [r7, #0] + 800995c: 689b ldr r3, [r3, #8] + 800995e: 041b lsls r3, r3, #16 + 8009960: 693a ldr r2, [r7, #16] + 8009962: 4313 orrs r3, r2 + 8009964: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8009966: 687b ldr r3, [r7, #4] + 8009968: 4a12 ldr r2, [pc, #72] ; (80099b4 ) + 800996a: 4293 cmp r3, r2 + 800996c: d003 beq.n 8009976 + 800996e: 687b ldr r3, [r7, #4] + 8009970: 4a11 ldr r2, [pc, #68] ; (80099b8 ) + 8009972: 4293 cmp r3, r2 + 8009974: d109 bne.n 800998a + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + 8009976: 697b ldr r3, [r7, #20] + 8009978: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800997c: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + 800997e: 683b ldr r3, [r7, #0] + 8009980: 695b ldr r3, [r3, #20] + 8009982: 021b lsls r3, r3, #8 + 8009984: 697a ldr r2, [r7, #20] + 8009986: 4313 orrs r3, r2 + 8009988: 617b str r3, [r7, #20] + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 800998a: 687b ldr r3, [r7, #4] + 800998c: 697a ldr r2, [r7, #20] + 800998e: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 8009990: 687b ldr r3, [r7, #4] + 8009992: 68fa ldr r2, [r7, #12] + 8009994: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + 8009996: 683b ldr r3, [r7, #0] + 8009998: 685a ldr r2, [r3, #4] + 800999a: 687b ldr r3, [r7, #4] + 800999c: 659a str r2, [r3, #88] ; 0x58 + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 800999e: 687b ldr r3, [r7, #4] + 80099a0: 693a ldr r2, [r7, #16] + 80099a2: 621a str r2, [r3, #32] +} + 80099a4: bf00 nop + 80099a6: 371c adds r7, #28 + 80099a8: 46bd mov sp, r7 + 80099aa: f85d 7b04 ldr.w r7, [sp], #4 + 80099ae: 4770 bx lr + 80099b0: fffeff8f .word 0xfffeff8f + 80099b4: 40010000 .word 0x40010000 + 80099b8: 40010400 .word 0x40010400 + +080099bc : + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + 80099bc: b480 push {r7} + 80099be: b087 sub sp, #28 + 80099c0: af00 add r7, sp, #0 + 80099c2: 6078 str r0, [r7, #4] + 80099c4: 6039 str r1, [r7, #0] + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + 80099c6: 687b ldr r3, [r7, #4] + 80099c8: 6a1b ldr r3, [r3, #32] + 80099ca: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 80099ce: 687b ldr r3, [r7, #4] + 80099d0: 621a str r2, [r3, #32] + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + 80099d2: 687b ldr r3, [r7, #4] + 80099d4: 6a1b ldr r3, [r3, #32] + 80099d6: 613b str r3, [r7, #16] + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + 80099d8: 687b ldr r3, [r7, #4] + 80099da: 685b ldr r3, [r3, #4] + 80099dc: 617b str r3, [r7, #20] + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + 80099de: 687b ldr r3, [r7, #4] + 80099e0: 6d5b ldr r3, [r3, #84] ; 0x54 + 80099e2: 60fb str r3, [r7, #12] + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + 80099e4: 68fa ldr r2, [r7, #12] + 80099e6: 4b1c ldr r3, [pc, #112] ; (8009a58 ) + 80099e8: 4013 ands r3, r2 + 80099ea: 60fb str r3, [r7, #12] + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + 80099ec: 683b ldr r3, [r7, #0] + 80099ee: 681b ldr r3, [r3, #0] + 80099f0: 021b lsls r3, r3, #8 + 80099f2: 68fa ldr r2, [r7, #12] + 80099f4: 4313 orrs r3, r2 + 80099f6: 60fb str r3, [r7, #12] + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 80099f8: 693b ldr r3, [r7, #16] + 80099fa: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 80099fe: 613b str r3, [r7, #16] + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + 8009a00: 683b ldr r3, [r7, #0] + 8009a02: 689b ldr r3, [r3, #8] + 8009a04: 051b lsls r3, r3, #20 + 8009a06: 693a ldr r2, [r7, #16] + 8009a08: 4313 orrs r3, r2 + 8009a0a: 613b str r3, [r7, #16] + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + 8009a0c: 687b ldr r3, [r7, #4] + 8009a0e: 4a13 ldr r2, [pc, #76] ; (8009a5c ) + 8009a10: 4293 cmp r3, r2 + 8009a12: d003 beq.n 8009a1c + 8009a14: 687b ldr r3, [r7, #4] + 8009a16: 4a12 ldr r2, [pc, #72] ; (8009a60 ) + 8009a18: 4293 cmp r3, r2 + 8009a1a: d109 bne.n 8009a30 + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + 8009a1c: 697b ldr r3, [r7, #20] + 8009a1e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8009a22: 617b str r3, [r7, #20] + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + 8009a24: 683b ldr r3, [r7, #0] + 8009a26: 695b ldr r3, [r3, #20] + 8009a28: 029b lsls r3, r3, #10 + 8009a2a: 697a ldr r2, [r7, #20] + 8009a2c: 4313 orrs r3, r2 + 8009a2e: 617b str r3, [r7, #20] + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + 8009a30: 687b ldr r3, [r7, #4] + 8009a32: 697a ldr r2, [r7, #20] + 8009a34: 605a str r2, [r3, #4] + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + 8009a36: 687b ldr r3, [r7, #4] + 8009a38: 68fa ldr r2, [r7, #12] + 8009a3a: 655a str r2, [r3, #84] ; 0x54 + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + 8009a3c: 683b ldr r3, [r7, #0] + 8009a3e: 685a ldr r2, [r3, #4] + 8009a40: 687b ldr r3, [r7, #4] + 8009a42: 65da str r2, [r3, #92] ; 0x5c + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; + 8009a44: 687b ldr r3, [r7, #4] + 8009a46: 693a ldr r2, [r7, #16] + 8009a48: 621a str r2, [r3, #32] +} + 8009a4a: bf00 nop + 8009a4c: 371c adds r7, #28 + 8009a4e: 46bd mov sp, r7 + 8009a50: f85d 7b04 ldr.w r7, [sp], #4 + 8009a54: 4770 bx lr + 8009a56: bf00 nop + 8009a58: feff8fff .word 0xfeff8fff + 8009a5c: 40010000 .word 0x40010000 + 8009a60: 40010400 .word 0x40010400 + +08009a64 : + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + 8009a64: b580 push {r7, lr} + 8009a66: b086 sub sp, #24 + 8009a68: af00 add r7, sp, #0 + 8009a6a: 6078 str r0, [r7, #4] + 8009a6c: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8009a6e: 687b ldr r3, [r7, #4] + 8009a70: 681b ldr r3, [r3, #0] + 8009a72: 689b ldr r3, [r3, #8] + 8009a74: 617b str r3, [r7, #20] + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8009a76: 697b ldr r3, [r7, #20] + 8009a78: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8009a7c: 617b str r3, [r7, #20] + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + 8009a7e: 683b ldr r3, [r7, #0] + 8009a80: 685b ldr r3, [r3, #4] + 8009a82: 697a ldr r2, [r7, #20] + 8009a84: 4313 orrs r3, r2 + 8009a86: 617b str r3, [r7, #20] + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + 8009a88: 697a ldr r2, [r7, #20] + 8009a8a: 4b39 ldr r3, [pc, #228] ; (8009b70 ) + 8009a8c: 4013 ands r3, r2 + 8009a8e: 617b str r3, [r7, #20] + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + 8009a90: 683b ldr r3, [r7, #0] + 8009a92: 681b ldr r3, [r3, #0] + 8009a94: 697a ldr r2, [r7, #20] + 8009a96: 4313 orrs r3, r2 + 8009a98: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8009a9a: 687b ldr r3, [r7, #4] + 8009a9c: 681b ldr r3, [r3, #0] + 8009a9e: 697a ldr r2, [r7, #20] + 8009aa0: 609a str r2, [r3, #8] + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + 8009aa2: 683b ldr r3, [r7, #0] + 8009aa4: 685b ldr r3, [r3, #4] + 8009aa6: 2b30 cmp r3, #48 ; 0x30 + 8009aa8: d05c beq.n 8009b64 + 8009aaa: 2b30 cmp r3, #48 ; 0x30 + 8009aac: d806 bhi.n 8009abc + 8009aae: 2b10 cmp r3, #16 + 8009ab0: d058 beq.n 8009b64 + 8009ab2: 2b20 cmp r3, #32 + 8009ab4: d056 beq.n 8009b64 + 8009ab6: 2b00 cmp r3, #0 + 8009ab8: d054 beq.n 8009b64 + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + 8009aba: e054 b.n 8009b66 + switch (sSlaveConfig->InputTrigger) + 8009abc: 2b50 cmp r3, #80 ; 0x50 + 8009abe: d03d beq.n 8009b3c + 8009ac0: 2b50 cmp r3, #80 ; 0x50 + 8009ac2: d802 bhi.n 8009aca + 8009ac4: 2b40 cmp r3, #64 ; 0x40 + 8009ac6: d010 beq.n 8009aea + break; + 8009ac8: e04d b.n 8009b66 + switch (sSlaveConfig->InputTrigger) + 8009aca: 2b60 cmp r3, #96 ; 0x60 + 8009acc: d040 beq.n 8009b50 + 8009ace: 2b70 cmp r3, #112 ; 0x70 + 8009ad0: d000 beq.n 8009ad4 + break; + 8009ad2: e048 b.n 8009b66 + TIM_ETR_SetConfig(htim->Instance, + 8009ad4: 687b ldr r3, [r7, #4] + 8009ad6: 6818 ldr r0, [r3, #0] + 8009ad8: 683b ldr r3, [r7, #0] + 8009ada: 68d9 ldr r1, [r3, #12] + 8009adc: 683b ldr r3, [r7, #0] + 8009ade: 689a ldr r2, [r3, #8] + 8009ae0: 683b ldr r3, [r7, #0] + 8009ae2: 691b ldr r3, [r3, #16] + 8009ae4: f000 f8c0 bl 8009c68 + break; + 8009ae8: e03d b.n 8009b66 + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + 8009aea: 683b ldr r3, [r7, #0] + 8009aec: 681b ldr r3, [r3, #0] + 8009aee: 2b05 cmp r3, #5 + 8009af0: d101 bne.n 8009af6 + return HAL_ERROR; + 8009af2: 2301 movs r3, #1 + 8009af4: e038 b.n 8009b68 + tmpccer = htim->Instance->CCER; + 8009af6: 687b ldr r3, [r7, #4] + 8009af8: 681b ldr r3, [r3, #0] + 8009afa: 6a1b ldr r3, [r3, #32] + 8009afc: 613b str r3, [r7, #16] + htim->Instance->CCER &= ~TIM_CCER_CC1E; + 8009afe: 687b ldr r3, [r7, #4] + 8009b00: 681b ldr r3, [r3, #0] + 8009b02: 6a1a ldr r2, [r3, #32] + 8009b04: 687b ldr r3, [r7, #4] + 8009b06: 681b ldr r3, [r3, #0] + 8009b08: f022 0201 bic.w r2, r2, #1 + 8009b0c: 621a str r2, [r3, #32] + tmpccmr1 = htim->Instance->CCMR1; + 8009b0e: 687b ldr r3, [r7, #4] + 8009b10: 681b ldr r3, [r3, #0] + 8009b12: 699b ldr r3, [r3, #24] + 8009b14: 60fb str r3, [r7, #12] + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8009b16: 68fb ldr r3, [r7, #12] + 8009b18: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 8009b1c: 60fb str r3, [r7, #12] + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + 8009b1e: 683b ldr r3, [r7, #0] + 8009b20: 691b ldr r3, [r3, #16] + 8009b22: 011b lsls r3, r3, #4 + 8009b24: 68fa ldr r2, [r7, #12] + 8009b26: 4313 orrs r3, r2 + 8009b28: 60fb str r3, [r7, #12] + htim->Instance->CCMR1 = tmpccmr1; + 8009b2a: 687b ldr r3, [r7, #4] + 8009b2c: 681b ldr r3, [r3, #0] + 8009b2e: 68fa ldr r2, [r7, #12] + 8009b30: 619a str r2, [r3, #24] + htim->Instance->CCER = tmpccer; + 8009b32: 687b ldr r3, [r7, #4] + 8009b34: 681b ldr r3, [r3, #0] + 8009b36: 693a ldr r2, [r7, #16] + 8009b38: 621a str r2, [r3, #32] + break; + 8009b3a: e014 b.n 8009b66 + TIM_TI1_ConfigInputStage(htim->Instance, + 8009b3c: 687b ldr r3, [r7, #4] + 8009b3e: 6818 ldr r0, [r3, #0] + 8009b40: 683b ldr r3, [r7, #0] + 8009b42: 6899 ldr r1, [r3, #8] + 8009b44: 683b ldr r3, [r7, #0] + 8009b46: 691b ldr r3, [r3, #16] + 8009b48: 461a mov r2, r3 + 8009b4a: f000 f813 bl 8009b74 + break; + 8009b4e: e00a b.n 8009b66 + TIM_TI2_ConfigInputStage(htim->Instance, + 8009b50: 687b ldr r3, [r7, #4] + 8009b52: 6818 ldr r0, [r3, #0] + 8009b54: 683b ldr r3, [r7, #0] + 8009b56: 6899 ldr r1, [r3, #8] + 8009b58: 683b ldr r3, [r7, #0] + 8009b5a: 691b ldr r3, [r3, #16] + 8009b5c: 461a mov r2, r3 + 8009b5e: f000 f838 bl 8009bd2 + break; + 8009b62: e000 b.n 8009b66 + break; + 8009b64: bf00 nop + } + return HAL_OK; + 8009b66: 2300 movs r3, #0 +} + 8009b68: 4618 mov r0, r3 + 8009b6a: 3718 adds r7, #24 + 8009b6c: 46bd mov sp, r7 + 8009b6e: bd80 pop {r7, pc} + 8009b70: fffefff8 .word 0xfffefff8 + +08009b74 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8009b74: b480 push {r7} + 8009b76: b087 sub sp, #28 + 8009b78: af00 add r7, sp, #0 + 8009b7a: 60f8 str r0, [r7, #12] + 8009b7c: 60b9 str r1, [r7, #8] + 8009b7e: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + 8009b80: 68fb ldr r3, [r7, #12] + 8009b82: 6a1b ldr r3, [r3, #32] + 8009b84: 617b str r3, [r7, #20] + TIMx->CCER &= ~TIM_CCER_CC1E; + 8009b86: 68fb ldr r3, [r7, #12] + 8009b88: 6a1b ldr r3, [r3, #32] + 8009b8a: f023 0201 bic.w r2, r3, #1 + 8009b8e: 68fb ldr r3, [r7, #12] + 8009b90: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8009b92: 68fb ldr r3, [r7, #12] + 8009b94: 699b ldr r3, [r3, #24] + 8009b96: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + 8009b98: 693b ldr r3, [r7, #16] + 8009b9a: f023 03f0 bic.w r3, r3, #240 ; 0xf0 + 8009b9e: 613b str r3, [r7, #16] + tmpccmr1 |= (TIM_ICFilter << 4U); + 8009ba0: 687b ldr r3, [r7, #4] + 8009ba2: 011b lsls r3, r3, #4 + 8009ba4: 693a ldr r2, [r7, #16] + 8009ba6: 4313 orrs r3, r2 + 8009ba8: 613b str r3, [r7, #16] + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 8009baa: 697b ldr r3, [r7, #20] + 8009bac: f023 030a bic.w r3, r3, #10 + 8009bb0: 617b str r3, [r7, #20] + tmpccer |= TIM_ICPolarity; + 8009bb2: 697a ldr r2, [r7, #20] + 8009bb4: 68bb ldr r3, [r7, #8] + 8009bb6: 4313 orrs r3, r2 + 8009bb8: 617b str r3, [r7, #20] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + 8009bba: 68fb ldr r3, [r7, #12] + 8009bbc: 693a ldr r2, [r7, #16] + 8009bbe: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8009bc0: 68fb ldr r3, [r7, #12] + 8009bc2: 697a ldr r2, [r7, #20] + 8009bc4: 621a str r2, [r3, #32] +} + 8009bc6: bf00 nop + 8009bc8: 371c adds r7, #28 + 8009bca: 46bd mov sp, r7 + 8009bcc: f85d 7b04 ldr.w r7, [sp], #4 + 8009bd0: 4770 bx lr + +08009bd2 : + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + 8009bd2: b480 push {r7} + 8009bd4: b087 sub sp, #28 + 8009bd6: af00 add r7, sp, #0 + 8009bd8: 60f8 str r0, [r7, #12] + 8009bda: 60b9 str r1, [r7, #8] + 8009bdc: 607a str r2, [r7, #4] + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + 8009bde: 68fb ldr r3, [r7, #12] + 8009be0: 6a1b ldr r3, [r3, #32] + 8009be2: f023 0210 bic.w r2, r3, #16 + 8009be6: 68fb ldr r3, [r7, #12] + 8009be8: 621a str r2, [r3, #32] + tmpccmr1 = TIMx->CCMR1; + 8009bea: 68fb ldr r3, [r7, #12] + 8009bec: 699b ldr r3, [r3, #24] + 8009bee: 617b str r3, [r7, #20] + tmpccer = TIMx->CCER; + 8009bf0: 68fb ldr r3, [r7, #12] + 8009bf2: 6a1b ldr r3, [r3, #32] + 8009bf4: 613b str r3, [r7, #16] + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + 8009bf6: 697b ldr r3, [r7, #20] + 8009bf8: f423 4370 bic.w r3, r3, #61440 ; 0xf000 + 8009bfc: 617b str r3, [r7, #20] + tmpccmr1 |= (TIM_ICFilter << 12U); + 8009bfe: 687b ldr r3, [r7, #4] + 8009c00: 031b lsls r3, r3, #12 + 8009c02: 697a ldr r2, [r7, #20] + 8009c04: 4313 orrs r3, r2 + 8009c06: 617b str r3, [r7, #20] + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 8009c08: 693b ldr r3, [r7, #16] + 8009c0a: f023 03a0 bic.w r3, r3, #160 ; 0xa0 + 8009c0e: 613b str r3, [r7, #16] + tmpccer |= (TIM_ICPolarity << 4U); + 8009c10: 68bb ldr r3, [r7, #8] + 8009c12: 011b lsls r3, r3, #4 + 8009c14: 693a ldr r2, [r7, #16] + 8009c16: 4313 orrs r3, r2 + 8009c18: 613b str r3, [r7, #16] + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + 8009c1a: 68fb ldr r3, [r7, #12] + 8009c1c: 697a ldr r2, [r7, #20] + 8009c1e: 619a str r2, [r3, #24] + TIMx->CCER = tmpccer; + 8009c20: 68fb ldr r3, [r7, #12] + 8009c22: 693a ldr r2, [r7, #16] + 8009c24: 621a str r2, [r3, #32] +} + 8009c26: bf00 nop + 8009c28: 371c adds r7, #28 + 8009c2a: 46bd mov sp, r7 + 8009c2c: f85d 7b04 ldr.w r7, [sp], #4 + 8009c30: 4770 bx lr + +08009c32 : + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + 8009c32: b480 push {r7} + 8009c34: b085 sub sp, #20 + 8009c36: af00 add r7, sp, #0 + 8009c38: 6078 str r0, [r7, #4] + 8009c3a: 6039 str r1, [r7, #0] + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + 8009c3c: 687b ldr r3, [r7, #4] + 8009c3e: 689b ldr r3, [r3, #8] + 8009c40: 60fb str r3, [r7, #12] + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + 8009c42: 68fb ldr r3, [r7, #12] + 8009c44: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8009c48: 60fb str r3, [r7, #12] + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 8009c4a: 683a ldr r2, [r7, #0] + 8009c4c: 68fb ldr r3, [r7, #12] + 8009c4e: 4313 orrs r3, r2 + 8009c50: f043 0307 orr.w r3, r3, #7 + 8009c54: 60fb str r3, [r7, #12] + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8009c56: 687b ldr r3, [r7, #4] + 8009c58: 68fa ldr r2, [r7, #12] + 8009c5a: 609a str r2, [r3, #8] +} + 8009c5c: bf00 nop + 8009c5e: 3714 adds r7, #20 + 8009c60: 46bd mov sp, r7 + 8009c62: f85d 7b04 ldr.w r7, [sp], #4 + 8009c66: 4770 bx lr + +08009c68 : + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + 8009c68: b480 push {r7} + 8009c6a: b087 sub sp, #28 + 8009c6c: af00 add r7, sp, #0 + 8009c6e: 60f8 str r0, [r7, #12] + 8009c70: 60b9 str r1, [r7, #8] + 8009c72: 607a str r2, [r7, #4] + 8009c74: 603b str r3, [r7, #0] + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + 8009c76: 68fb ldr r3, [r7, #12] + 8009c78: 689b ldr r3, [r3, #8] + 8009c7a: 617b str r3, [r7, #20] + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 8009c7c: 697b ldr r3, [r7, #20] + 8009c7e: f423 437f bic.w r3, r3, #65280 ; 0xff00 + 8009c82: 617b str r3, [r7, #20] + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 8009c84: 683b ldr r3, [r7, #0] + 8009c86: 021a lsls r2, r3, #8 + 8009c88: 687b ldr r3, [r7, #4] + 8009c8a: 431a orrs r2, r3 + 8009c8c: 68bb ldr r3, [r7, #8] + 8009c8e: 4313 orrs r3, r2 + 8009c90: 697a ldr r2, [r7, #20] + 8009c92: 4313 orrs r3, r2 + 8009c94: 617b str r3, [r7, #20] + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + 8009c96: 68fb ldr r3, [r7, #12] + 8009c98: 697a ldr r2, [r7, #20] + 8009c9a: 609a str r2, [r3, #8] +} + 8009c9c: bf00 nop + 8009c9e: 371c adds r7, #28 + 8009ca0: 46bd mov sp, r7 + 8009ca2: f85d 7b04 ldr.w r7, [sp], #4 + 8009ca6: 4770 bx lr + +08009ca8 : + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + 8009ca8: b480 push {r7} + 8009caa: b085 sub sp, #20 + 8009cac: af00 add r7, sp, #0 + 8009cae: 6078 str r0, [r7, #4] + 8009cb0: 6039 str r1, [r7, #0] + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + 8009cb2: 687b ldr r3, [r7, #4] + 8009cb4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8009cb8: 2b01 cmp r3, #1 + 8009cba: d101 bne.n 8009cc0 + 8009cbc: 2302 movs r3, #2 + 8009cbe: e06d b.n 8009d9c + 8009cc0: 687b ldr r3, [r7, #4] + 8009cc2: 2201 movs r2, #1 + 8009cc4: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + 8009cc8: 687b ldr r3, [r7, #4] + 8009cca: 2202 movs r2, #2 + 8009ccc: f883 203d strb.w r2, [r3, #61] ; 0x3d + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + 8009cd0: 687b ldr r3, [r7, #4] + 8009cd2: 681b ldr r3, [r3, #0] + 8009cd4: 685b ldr r3, [r3, #4] + 8009cd6: 60fb str r3, [r7, #12] + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + 8009cd8: 687b ldr r3, [r7, #4] + 8009cda: 681b ldr r3, [r3, #0] + 8009cdc: 689b ldr r3, [r3, #8] + 8009cde: 60bb str r3, [r7, #8] + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + 8009ce0: 687b ldr r3, [r7, #4] + 8009ce2: 681b ldr r3, [r3, #0] + 8009ce4: 4a30 ldr r2, [pc, #192] ; (8009da8 ) + 8009ce6: 4293 cmp r3, r2 + 8009ce8: d004 beq.n 8009cf4 + 8009cea: 687b ldr r3, [r7, #4] + 8009cec: 681b ldr r3, [r3, #0] + 8009cee: 4a2f ldr r2, [pc, #188] ; (8009dac ) + 8009cf0: 4293 cmp r3, r2 + 8009cf2: d108 bne.n 8009d06 + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + 8009cf4: 68fb ldr r3, [r7, #12] + 8009cf6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 + 8009cfa: 60fb str r3, [r7, #12] + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + 8009cfc: 683b ldr r3, [r7, #0] + 8009cfe: 685b ldr r3, [r3, #4] + 8009d00: 68fa ldr r2, [r7, #12] + 8009d02: 4313 orrs r3, r2 + 8009d04: 60fb str r3, [r7, #12] + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + 8009d06: 68fb ldr r3, [r7, #12] + 8009d08: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8009d0c: 60fb str r3, [r7, #12] + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 8009d0e: 683b ldr r3, [r7, #0] + 8009d10: 681b ldr r3, [r3, #0] + 8009d12: 68fa ldr r2, [r7, #12] + 8009d14: 4313 orrs r3, r2 + 8009d16: 60fb str r3, [r7, #12] + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + 8009d18: 687b ldr r3, [r7, #4] + 8009d1a: 681b ldr r3, [r3, #0] + 8009d1c: 68fa ldr r2, [r7, #12] + 8009d1e: 605a str r2, [r3, #4] + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 8009d20: 687b ldr r3, [r7, #4] + 8009d22: 681b ldr r3, [r3, #0] + 8009d24: 4a20 ldr r2, [pc, #128] ; (8009da8 ) + 8009d26: 4293 cmp r3, r2 + 8009d28: d022 beq.n 8009d70 + 8009d2a: 687b ldr r3, [r7, #4] + 8009d2c: 681b ldr r3, [r3, #0] + 8009d2e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8009d32: d01d beq.n 8009d70 + 8009d34: 687b ldr r3, [r7, #4] + 8009d36: 681b ldr r3, [r3, #0] + 8009d38: 4a1d ldr r2, [pc, #116] ; (8009db0 ) + 8009d3a: 4293 cmp r3, r2 + 8009d3c: d018 beq.n 8009d70 + 8009d3e: 687b ldr r3, [r7, #4] + 8009d40: 681b ldr r3, [r3, #0] + 8009d42: 4a1c ldr r2, [pc, #112] ; (8009db4 ) + 8009d44: 4293 cmp r3, r2 + 8009d46: d013 beq.n 8009d70 + 8009d48: 687b ldr r3, [r7, #4] + 8009d4a: 681b ldr r3, [r3, #0] + 8009d4c: 4a1a ldr r2, [pc, #104] ; (8009db8 ) + 8009d4e: 4293 cmp r3, r2 + 8009d50: d00e beq.n 8009d70 + 8009d52: 687b ldr r3, [r7, #4] + 8009d54: 681b ldr r3, [r3, #0] + 8009d56: 4a15 ldr r2, [pc, #84] ; (8009dac ) + 8009d58: 4293 cmp r3, r2 + 8009d5a: d009 beq.n 8009d70 + 8009d5c: 687b ldr r3, [r7, #4] + 8009d5e: 681b ldr r3, [r3, #0] + 8009d60: 4a16 ldr r2, [pc, #88] ; (8009dbc ) + 8009d62: 4293 cmp r3, r2 + 8009d64: d004 beq.n 8009d70 + 8009d66: 687b ldr r3, [r7, #4] + 8009d68: 681b ldr r3, [r3, #0] + 8009d6a: 4a15 ldr r2, [pc, #84] ; (8009dc0 ) + 8009d6c: 4293 cmp r3, r2 + 8009d6e: d10c bne.n 8009d8a + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + 8009d70: 68bb ldr r3, [r7, #8] + 8009d72: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8009d76: 60bb str r3, [r7, #8] + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + 8009d78: 683b ldr r3, [r7, #0] + 8009d7a: 689b ldr r3, [r3, #8] + 8009d7c: 68ba ldr r2, [r7, #8] + 8009d7e: 4313 orrs r3, r2 + 8009d80: 60bb str r3, [r7, #8] + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + 8009d82: 687b ldr r3, [r7, #4] + 8009d84: 681b ldr r3, [r3, #0] + 8009d86: 68ba ldr r2, [r7, #8] + 8009d88: 609a str r2, [r3, #8] + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + 8009d8a: 687b ldr r3, [r7, #4] + 8009d8c: 2201 movs r2, #1 + 8009d8e: f883 203d strb.w r2, [r3, #61] ; 0x3d + + __HAL_UNLOCK(htim); + 8009d92: 687b ldr r3, [r7, #4] + 8009d94: 2200 movs r2, #0 + 8009d96: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8009d9a: 2300 movs r3, #0 +} + 8009d9c: 4618 mov r0, r3 + 8009d9e: 3714 adds r7, #20 + 8009da0: 46bd mov sp, r7 + 8009da2: f85d 7b04 ldr.w r7, [sp], #4 + 8009da6: 4770 bx lr + 8009da8: 40010000 .word 0x40010000 + 8009dac: 40010400 .word 0x40010400 + 8009db0: 40000400 .word 0x40000400 + 8009db4: 40000800 .word 0x40000800 + 8009db8: 40000c00 .word 0x40000c00 + 8009dbc: 40014000 .word 0x40014000 + 8009dc0: 40001800 .word 0x40001800 + +08009dc4 : + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + 8009dc4: b480 push {r7} + 8009dc6: b085 sub sp, #20 + 8009dc8: af00 add r7, sp, #0 + 8009dca: 6078 str r0, [r7, #4] + 8009dcc: 6039 str r1, [r7, #0] + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + 8009dce: 2300 movs r3, #0 + 8009dd0: 60fb str r3, [r7, #12] + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + 8009dd2: 687b ldr r3, [r7, #4] + 8009dd4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8009dd8: 2b01 cmp r3, #1 + 8009dda: d101 bne.n 8009de0 + 8009ddc: 2302 movs r3, #2 + 8009dde: e065 b.n 8009eac + 8009de0: 687b ldr r3, [r7, #4] + 8009de2: 2201 movs r2, #1 + 8009de4: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + 8009de8: 68fb ldr r3, [r7, #12] + 8009dea: f023 02ff bic.w r2, r3, #255 ; 0xff + 8009dee: 683b ldr r3, [r7, #0] + 8009df0: 68db ldr r3, [r3, #12] + 8009df2: 4313 orrs r3, r2 + 8009df4: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + 8009df6: 68fb ldr r3, [r7, #12] + 8009df8: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8009dfc: 683b ldr r3, [r7, #0] + 8009dfe: 689b ldr r3, [r3, #8] + 8009e00: 4313 orrs r3, r2 + 8009e02: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + 8009e04: 68fb ldr r3, [r7, #12] + 8009e06: f423 6280 bic.w r2, r3, #1024 ; 0x400 + 8009e0a: 683b ldr r3, [r7, #0] + 8009e0c: 685b ldr r3, [r3, #4] + 8009e0e: 4313 orrs r3, r2 + 8009e10: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + 8009e12: 68fb ldr r3, [r7, #12] + 8009e14: f423 6200 bic.w r2, r3, #2048 ; 0x800 + 8009e18: 683b ldr r3, [r7, #0] + 8009e1a: 681b ldr r3, [r3, #0] + 8009e1c: 4313 orrs r3, r2 + 8009e1e: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + 8009e20: 68fb ldr r3, [r7, #12] + 8009e22: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 8009e26: 683b ldr r3, [r7, #0] + 8009e28: 691b ldr r3, [r3, #16] + 8009e2a: 4313 orrs r3, r2 + 8009e2c: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + 8009e2e: 68fb ldr r3, [r7, #12] + 8009e30: f423 5200 bic.w r2, r3, #8192 ; 0x2000 + 8009e34: 683b ldr r3, [r7, #0] + 8009e36: 695b ldr r3, [r3, #20] + 8009e38: 4313 orrs r3, r2 + 8009e3a: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + 8009e3c: 68fb ldr r3, [r7, #12] + 8009e3e: f423 4280 bic.w r2, r3, #16384 ; 0x4000 + 8009e42: 683b ldr r3, [r7, #0] + 8009e44: 6a9b ldr r3, [r3, #40] ; 0x28 + 8009e46: 4313 orrs r3, r2 + 8009e48: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + 8009e4a: 68fb ldr r3, [r7, #12] + 8009e4c: f423 2270 bic.w r2, r3, #983040 ; 0xf0000 + 8009e50: 683b ldr r3, [r7, #0] + 8009e52: 699b ldr r3, [r3, #24] + 8009e54: 041b lsls r3, r3, #16 + 8009e56: 4313 orrs r3, r2 + 8009e58: 60fb str r3, [r7, #12] + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + 8009e5a: 687b ldr r3, [r7, #4] + 8009e5c: 681b ldr r3, [r3, #0] + 8009e5e: 4a16 ldr r2, [pc, #88] ; (8009eb8 ) + 8009e60: 4293 cmp r3, r2 + 8009e62: d004 beq.n 8009e6e + 8009e64: 687b ldr r3, [r7, #4] + 8009e66: 681b ldr r3, [r3, #0] + 8009e68: 4a14 ldr r2, [pc, #80] ; (8009ebc ) + 8009e6a: 4293 cmp r3, r2 + 8009e6c: d115 bne.n 8009e9a + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + 8009e6e: 68fb ldr r3, [r7, #12] + 8009e70: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000 + 8009e74: 683b ldr r3, [r7, #0] + 8009e76: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009e78: 051b lsls r3, r3, #20 + 8009e7a: 4313 orrs r3, r2 + 8009e7c: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + 8009e7e: 68fb ldr r3, [r7, #12] + 8009e80: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 + 8009e84: 683b ldr r3, [r7, #0] + 8009e86: 69db ldr r3, [r3, #28] + 8009e88: 4313 orrs r3, r2 + 8009e8a: 60fb str r3, [r7, #12] + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + 8009e8c: 68fb ldr r3, [r7, #12] + 8009e8e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 8009e92: 683b ldr r3, [r7, #0] + 8009e94: 6a1b ldr r3, [r3, #32] + 8009e96: 4313 orrs r3, r2 + 8009e98: 60fb str r3, [r7, #12] + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + 8009e9a: 687b ldr r3, [r7, #4] + 8009e9c: 681b ldr r3, [r3, #0] + 8009e9e: 68fa ldr r2, [r7, #12] + 8009ea0: 645a str r2, [r3, #68] ; 0x44 + + __HAL_UNLOCK(htim); + 8009ea2: 687b ldr r3, [r7, #4] + 8009ea4: 2200 movs r2, #0 + 8009ea6: f883 203c strb.w r2, [r3, #60] ; 0x3c + + return HAL_OK; + 8009eaa: 2300 movs r3, #0 +} + 8009eac: 4618 mov r0, r3 + 8009eae: 3714 adds r7, #20 + 8009eb0: 46bd mov sp, r7 + 8009eb2: f85d 7b04 ldr.w r7, [sp], #4 + 8009eb6: 4770 bx lr + 8009eb8: 40010000 .word 0x40010000 + 8009ebc: 40010400 .word 0x40010400 + +08009ec0 : + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + 8009ec0: b480 push {r7} + 8009ec2: b083 sub sp, #12 + 8009ec4: af00 add r7, sp, #0 + 8009ec6: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} + 8009ec8: bf00 nop + 8009eca: 370c adds r7, #12 + 8009ecc: 46bd mov sp, r7 + 8009ece: f85d 7b04 ldr.w r7, [sp], #4 + 8009ed2: 4770 bx lr + +08009ed4 : + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + 8009ed4: b480 push {r7} + 8009ed6: b083 sub sp, #12 + 8009ed8: af00 add r7, sp, #0 + 8009eda: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + 8009edc: bf00 nop + 8009ede: 370c adds r7, #12 + 8009ee0: 46bd mov sp, r7 + 8009ee2: f85d 7b04 ldr.w r7, [sp], #4 + 8009ee6: 4770 bx lr + +08009ee8 : + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + 8009ee8: b480 push {r7} + 8009eea: b083 sub sp, #12 + 8009eec: af00 add r7, sp, #0 + 8009eee: 6078 str r0, [r7, #4] + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + 8009ef0: bf00 nop + 8009ef2: 370c adds r7, #12 + 8009ef4: 46bd mov sp, r7 + 8009ef6: f85d 7b04 ldr.w r7, [sp], #4 + 8009efa: 4770 bx lr + +08009efc : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8009efc: b580 push {r7, lr} + 8009efe: b082 sub sp, #8 + 8009f00: af00 add r7, sp, #0 + 8009f02: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8009f04: 687b ldr r3, [r7, #4] + 8009f06: 2b00 cmp r3, #0 + 8009f08: d101 bne.n 8009f0e + { + return HAL_ERROR; + 8009f0a: 2301 movs r3, #1 + 8009f0c: e040 b.n 8009f90 + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 8009f0e: 687b ldr r3, [r7, #4] + 8009f10: 6f5b ldr r3, [r3, #116] ; 0x74 + 8009f12: 2b00 cmp r3, #0 + 8009f14: d106 bne.n 8009f24 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8009f16: 687b ldr r3, [r7, #4] + 8009f18: 2200 movs r2, #0 + 8009f1a: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8009f1e: 6878 ldr r0, [r7, #4] + 8009f20: f7fa f86a bl 8003ff8 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8009f24: 687b ldr r3, [r7, #4] + 8009f26: 2224 movs r2, #36 ; 0x24 + 8009f28: 675a str r2, [r3, #116] ; 0x74 + + __HAL_UART_DISABLE(huart); + 8009f2a: 687b ldr r3, [r7, #4] + 8009f2c: 681b ldr r3, [r3, #0] + 8009f2e: 681a ldr r2, [r3, #0] + 8009f30: 687b ldr r3, [r7, #4] + 8009f32: 681b ldr r3, [r3, #0] + 8009f34: f022 0201 bic.w r2, r2, #1 + 8009f38: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 8009f3a: 6878 ldr r0, [r7, #4] + 8009f3c: f000 f82c bl 8009f98 + 8009f40: 4603 mov r3, r0 + 8009f42: 2b01 cmp r3, #1 + 8009f44: d101 bne.n 8009f4a + { + return HAL_ERROR; + 8009f46: 2301 movs r3, #1 + 8009f48: e022 b.n 8009f90 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 8009f4a: 687b ldr r3, [r7, #4] + 8009f4c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009f4e: 2b00 cmp r3, #0 + 8009f50: d002 beq.n 8009f58 + { + UART_AdvFeatureConfig(huart); + 8009f52: 6878 ldr r0, [r7, #4] + 8009f54: f000 faca bl 800a4ec + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8009f58: 687b ldr r3, [r7, #4] + 8009f5a: 681b ldr r3, [r3, #0] + 8009f5c: 685a ldr r2, [r3, #4] + 8009f5e: 687b ldr r3, [r7, #4] + 8009f60: 681b ldr r3, [r3, #0] + 8009f62: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8009f66: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8009f68: 687b ldr r3, [r7, #4] + 8009f6a: 681b ldr r3, [r3, #0] + 8009f6c: 689a ldr r2, [r3, #8] + 8009f6e: 687b ldr r3, [r7, #4] + 8009f70: 681b ldr r3, [r3, #0] + 8009f72: f022 022a bic.w r2, r2, #42 ; 0x2a + 8009f76: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 8009f78: 687b ldr r3, [r7, #4] + 8009f7a: 681b ldr r3, [r3, #0] + 8009f7c: 681a ldr r2, [r3, #0] + 8009f7e: 687b ldr r3, [r7, #4] + 8009f80: 681b ldr r3, [r3, #0] + 8009f82: f042 0201 orr.w r2, r2, #1 + 8009f86: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 8009f88: 6878 ldr r0, [r7, #4] + 8009f8a: f000 fb51 bl 800a630 + 8009f8e: 4603 mov r3, r0 +} + 8009f90: 4618 mov r0, r3 + 8009f92: 3708 adds r7, #8 + 8009f94: 46bd mov sp, r7 + 8009f96: bd80 pop {r7, pc} + +08009f98 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8009f98: b580 push {r7, lr} + 8009f9a: b088 sub sp, #32 + 8009f9c: af00 add r7, sp, #0 + 8009f9e: 6078 str r0, [r7, #4] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + 8009fa0: 2300 movs r3, #0 + 8009fa2: 61bb str r3, [r7, #24] + HAL_StatusTypeDef ret = HAL_OK; + 8009fa4: 2300 movs r3, #0 + 8009fa6: 75fb strb r3, [r7, #23] + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8009fa8: 687b ldr r3, [r7, #4] + 8009faa: 689a ldr r2, [r3, #8] + 8009fac: 687b ldr r3, [r7, #4] + 8009fae: 691b ldr r3, [r3, #16] + 8009fb0: 431a orrs r2, r3 + 8009fb2: 687b ldr r3, [r7, #4] + 8009fb4: 695b ldr r3, [r3, #20] + 8009fb6: 431a orrs r2, r3 + 8009fb8: 687b ldr r3, [r7, #4] + 8009fba: 69db ldr r3, [r3, #28] + 8009fbc: 4313 orrs r3, r2 + 8009fbe: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8009fc0: 687b ldr r3, [r7, #4] + 8009fc2: 681b ldr r3, [r3, #0] + 8009fc4: 681a ldr r2, [r3, #0] + 8009fc6: 4bb1 ldr r3, [pc, #708] ; (800a28c ) + 8009fc8: 4013 ands r3, r2 + 8009fca: 687a ldr r2, [r7, #4] + 8009fcc: 6812 ldr r2, [r2, #0] + 8009fce: 6939 ldr r1, [r7, #16] + 8009fd0: 430b orrs r3, r1 + 8009fd2: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 8009fd4: 687b ldr r3, [r7, #4] + 8009fd6: 681b ldr r3, [r3, #0] + 8009fd8: 685b ldr r3, [r3, #4] + 8009fda: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8009fde: 687b ldr r3, [r7, #4] + 8009fe0: 68da ldr r2, [r3, #12] + 8009fe2: 687b ldr r3, [r7, #4] + 8009fe4: 681b ldr r3, [r3, #0] + 8009fe6: 430a orrs r2, r1 + 8009fe8: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8009fea: 687b ldr r3, [r7, #4] + 8009fec: 699b ldr r3, [r3, #24] + 8009fee: 613b str r3, [r7, #16] + + tmpreg |= huart->Init.OneBitSampling; + 8009ff0: 687b ldr r3, [r7, #4] + 8009ff2: 6a1b ldr r3, [r3, #32] + 8009ff4: 693a ldr r2, [r7, #16] + 8009ff6: 4313 orrs r3, r2 + 8009ff8: 613b str r3, [r7, #16] + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 8009ffa: 687b ldr r3, [r7, #4] + 8009ffc: 681b ldr r3, [r3, #0] + 8009ffe: 689b ldr r3, [r3, #8] + 800a000: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 800a004: 687b ldr r3, [r7, #4] + 800a006: 681b ldr r3, [r3, #0] + 800a008: 693a ldr r2, [r7, #16] + 800a00a: 430a orrs r2, r1 + 800a00c: 609a str r2, [r3, #8] + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 800a00e: 687b ldr r3, [r7, #4] + 800a010: 681b ldr r3, [r3, #0] + 800a012: 4a9f ldr r2, [pc, #636] ; (800a290 ) + 800a014: 4293 cmp r3, r2 + 800a016: d121 bne.n 800a05c + 800a018: 4b9e ldr r3, [pc, #632] ; (800a294 ) + 800a01a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a01e: f003 0303 and.w r3, r3, #3 + 800a022: 2b03 cmp r3, #3 + 800a024: d816 bhi.n 800a054 + 800a026: a201 add r2, pc, #4 ; (adr r2, 800a02c ) + 800a028: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a02c: 0800a03d .word 0x0800a03d + 800a030: 0800a049 .word 0x0800a049 + 800a034: 0800a043 .word 0x0800a043 + 800a038: 0800a04f .word 0x0800a04f + 800a03c: 2301 movs r3, #1 + 800a03e: 77fb strb r3, [r7, #31] + 800a040: e151 b.n 800a2e6 + 800a042: 2302 movs r3, #2 + 800a044: 77fb strb r3, [r7, #31] + 800a046: e14e b.n 800a2e6 + 800a048: 2304 movs r3, #4 + 800a04a: 77fb strb r3, [r7, #31] + 800a04c: e14b b.n 800a2e6 + 800a04e: 2308 movs r3, #8 + 800a050: 77fb strb r3, [r7, #31] + 800a052: e148 b.n 800a2e6 + 800a054: 2310 movs r3, #16 + 800a056: 77fb strb r3, [r7, #31] + 800a058: bf00 nop + 800a05a: e144 b.n 800a2e6 + 800a05c: 687b ldr r3, [r7, #4] + 800a05e: 681b ldr r3, [r3, #0] + 800a060: 4a8d ldr r2, [pc, #564] ; (800a298 ) + 800a062: 4293 cmp r3, r2 + 800a064: d134 bne.n 800a0d0 + 800a066: 4b8b ldr r3, [pc, #556] ; (800a294 ) + 800a068: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a06c: f003 030c and.w r3, r3, #12 + 800a070: 2b0c cmp r3, #12 + 800a072: d829 bhi.n 800a0c8 + 800a074: a201 add r2, pc, #4 ; (adr r2, 800a07c ) + 800a076: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a07a: bf00 nop + 800a07c: 0800a0b1 .word 0x0800a0b1 + 800a080: 0800a0c9 .word 0x0800a0c9 + 800a084: 0800a0c9 .word 0x0800a0c9 + 800a088: 0800a0c9 .word 0x0800a0c9 + 800a08c: 0800a0bd .word 0x0800a0bd + 800a090: 0800a0c9 .word 0x0800a0c9 + 800a094: 0800a0c9 .word 0x0800a0c9 + 800a098: 0800a0c9 .word 0x0800a0c9 + 800a09c: 0800a0b7 .word 0x0800a0b7 + 800a0a0: 0800a0c9 .word 0x0800a0c9 + 800a0a4: 0800a0c9 .word 0x0800a0c9 + 800a0a8: 0800a0c9 .word 0x0800a0c9 + 800a0ac: 0800a0c3 .word 0x0800a0c3 + 800a0b0: 2300 movs r3, #0 + 800a0b2: 77fb strb r3, [r7, #31] + 800a0b4: e117 b.n 800a2e6 + 800a0b6: 2302 movs r3, #2 + 800a0b8: 77fb strb r3, [r7, #31] + 800a0ba: e114 b.n 800a2e6 + 800a0bc: 2304 movs r3, #4 + 800a0be: 77fb strb r3, [r7, #31] + 800a0c0: e111 b.n 800a2e6 + 800a0c2: 2308 movs r3, #8 + 800a0c4: 77fb strb r3, [r7, #31] + 800a0c6: e10e b.n 800a2e6 + 800a0c8: 2310 movs r3, #16 + 800a0ca: 77fb strb r3, [r7, #31] + 800a0cc: bf00 nop + 800a0ce: e10a b.n 800a2e6 + 800a0d0: 687b ldr r3, [r7, #4] + 800a0d2: 681b ldr r3, [r3, #0] + 800a0d4: 4a71 ldr r2, [pc, #452] ; (800a29c ) + 800a0d6: 4293 cmp r3, r2 + 800a0d8: d120 bne.n 800a11c + 800a0da: 4b6e ldr r3, [pc, #440] ; (800a294 ) + 800a0dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a0e0: f003 0330 and.w r3, r3, #48 ; 0x30 + 800a0e4: 2b10 cmp r3, #16 + 800a0e6: d00f beq.n 800a108 + 800a0e8: 2b10 cmp r3, #16 + 800a0ea: d802 bhi.n 800a0f2 + 800a0ec: 2b00 cmp r3, #0 + 800a0ee: d005 beq.n 800a0fc + 800a0f0: e010 b.n 800a114 + 800a0f2: 2b20 cmp r3, #32 + 800a0f4: d005 beq.n 800a102 + 800a0f6: 2b30 cmp r3, #48 ; 0x30 + 800a0f8: d009 beq.n 800a10e + 800a0fa: e00b b.n 800a114 + 800a0fc: 2300 movs r3, #0 + 800a0fe: 77fb strb r3, [r7, #31] + 800a100: e0f1 b.n 800a2e6 + 800a102: 2302 movs r3, #2 + 800a104: 77fb strb r3, [r7, #31] + 800a106: e0ee b.n 800a2e6 + 800a108: 2304 movs r3, #4 + 800a10a: 77fb strb r3, [r7, #31] + 800a10c: e0eb b.n 800a2e6 + 800a10e: 2308 movs r3, #8 + 800a110: 77fb strb r3, [r7, #31] + 800a112: e0e8 b.n 800a2e6 + 800a114: 2310 movs r3, #16 + 800a116: 77fb strb r3, [r7, #31] + 800a118: bf00 nop + 800a11a: e0e4 b.n 800a2e6 + 800a11c: 687b ldr r3, [r7, #4] + 800a11e: 681b ldr r3, [r3, #0] + 800a120: 4a5f ldr r2, [pc, #380] ; (800a2a0 ) + 800a122: 4293 cmp r3, r2 + 800a124: d120 bne.n 800a168 + 800a126: 4b5b ldr r3, [pc, #364] ; (800a294 ) + 800a128: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a12c: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 800a130: 2b40 cmp r3, #64 ; 0x40 + 800a132: d00f beq.n 800a154 + 800a134: 2b40 cmp r3, #64 ; 0x40 + 800a136: d802 bhi.n 800a13e + 800a138: 2b00 cmp r3, #0 + 800a13a: d005 beq.n 800a148 + 800a13c: e010 b.n 800a160 + 800a13e: 2b80 cmp r3, #128 ; 0x80 + 800a140: d005 beq.n 800a14e + 800a142: 2bc0 cmp r3, #192 ; 0xc0 + 800a144: d009 beq.n 800a15a + 800a146: e00b b.n 800a160 + 800a148: 2300 movs r3, #0 + 800a14a: 77fb strb r3, [r7, #31] + 800a14c: e0cb b.n 800a2e6 + 800a14e: 2302 movs r3, #2 + 800a150: 77fb strb r3, [r7, #31] + 800a152: e0c8 b.n 800a2e6 + 800a154: 2304 movs r3, #4 + 800a156: 77fb strb r3, [r7, #31] + 800a158: e0c5 b.n 800a2e6 + 800a15a: 2308 movs r3, #8 + 800a15c: 77fb strb r3, [r7, #31] + 800a15e: e0c2 b.n 800a2e6 + 800a160: 2310 movs r3, #16 + 800a162: 77fb strb r3, [r7, #31] + 800a164: bf00 nop + 800a166: e0be b.n 800a2e6 + 800a168: 687b ldr r3, [r7, #4] + 800a16a: 681b ldr r3, [r3, #0] + 800a16c: 4a4d ldr r2, [pc, #308] ; (800a2a4 ) + 800a16e: 4293 cmp r3, r2 + 800a170: d124 bne.n 800a1bc + 800a172: 4b48 ldr r3, [pc, #288] ; (800a294 ) + 800a174: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a178: f403 7340 and.w r3, r3, #768 ; 0x300 + 800a17c: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800a180: d012 beq.n 800a1a8 + 800a182: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800a186: d802 bhi.n 800a18e + 800a188: 2b00 cmp r3, #0 + 800a18a: d007 beq.n 800a19c + 800a18c: e012 b.n 800a1b4 + 800a18e: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800a192: d006 beq.n 800a1a2 + 800a194: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 800a198: d009 beq.n 800a1ae + 800a19a: e00b b.n 800a1b4 + 800a19c: 2300 movs r3, #0 + 800a19e: 77fb strb r3, [r7, #31] + 800a1a0: e0a1 b.n 800a2e6 + 800a1a2: 2302 movs r3, #2 + 800a1a4: 77fb strb r3, [r7, #31] + 800a1a6: e09e b.n 800a2e6 + 800a1a8: 2304 movs r3, #4 + 800a1aa: 77fb strb r3, [r7, #31] + 800a1ac: e09b b.n 800a2e6 + 800a1ae: 2308 movs r3, #8 + 800a1b0: 77fb strb r3, [r7, #31] + 800a1b2: e098 b.n 800a2e6 + 800a1b4: 2310 movs r3, #16 + 800a1b6: 77fb strb r3, [r7, #31] + 800a1b8: bf00 nop + 800a1ba: e094 b.n 800a2e6 + 800a1bc: 687b ldr r3, [r7, #4] + 800a1be: 681b ldr r3, [r3, #0] + 800a1c0: 4a39 ldr r2, [pc, #228] ; (800a2a8 ) + 800a1c2: 4293 cmp r3, r2 + 800a1c4: d124 bne.n 800a210 + 800a1c6: 4b33 ldr r3, [pc, #204] ; (800a294 ) + 800a1c8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a1cc: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 800a1d0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800a1d4: d012 beq.n 800a1fc + 800a1d6: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800a1da: d802 bhi.n 800a1e2 + 800a1dc: 2b00 cmp r3, #0 + 800a1de: d007 beq.n 800a1f0 + 800a1e0: e012 b.n 800a208 + 800a1e2: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800a1e6: d006 beq.n 800a1f6 + 800a1e8: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 800a1ec: d009 beq.n 800a202 + 800a1ee: e00b b.n 800a208 + 800a1f0: 2301 movs r3, #1 + 800a1f2: 77fb strb r3, [r7, #31] + 800a1f4: e077 b.n 800a2e6 + 800a1f6: 2302 movs r3, #2 + 800a1f8: 77fb strb r3, [r7, #31] + 800a1fa: e074 b.n 800a2e6 + 800a1fc: 2304 movs r3, #4 + 800a1fe: 77fb strb r3, [r7, #31] + 800a200: e071 b.n 800a2e6 + 800a202: 2308 movs r3, #8 + 800a204: 77fb strb r3, [r7, #31] + 800a206: e06e b.n 800a2e6 + 800a208: 2310 movs r3, #16 + 800a20a: 77fb strb r3, [r7, #31] + 800a20c: bf00 nop + 800a20e: e06a b.n 800a2e6 + 800a210: 687b ldr r3, [r7, #4] + 800a212: 681b ldr r3, [r3, #0] + 800a214: 4a25 ldr r2, [pc, #148] ; (800a2ac ) + 800a216: 4293 cmp r3, r2 + 800a218: d124 bne.n 800a264 + 800a21a: 4b1e ldr r3, [pc, #120] ; (800a294 ) + 800a21c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a220: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 800a224: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800a228: d012 beq.n 800a250 + 800a22a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800a22e: d802 bhi.n 800a236 + 800a230: 2b00 cmp r3, #0 + 800a232: d007 beq.n 800a244 + 800a234: e012 b.n 800a25c + 800a236: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800a23a: d006 beq.n 800a24a + 800a23c: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 800a240: d009 beq.n 800a256 + 800a242: e00b b.n 800a25c + 800a244: 2300 movs r3, #0 + 800a246: 77fb strb r3, [r7, #31] + 800a248: e04d b.n 800a2e6 + 800a24a: 2302 movs r3, #2 + 800a24c: 77fb strb r3, [r7, #31] + 800a24e: e04a b.n 800a2e6 + 800a250: 2304 movs r3, #4 + 800a252: 77fb strb r3, [r7, #31] + 800a254: e047 b.n 800a2e6 + 800a256: 2308 movs r3, #8 + 800a258: 77fb strb r3, [r7, #31] + 800a25a: e044 b.n 800a2e6 + 800a25c: 2310 movs r3, #16 + 800a25e: 77fb strb r3, [r7, #31] + 800a260: bf00 nop + 800a262: e040 b.n 800a2e6 + 800a264: 687b ldr r3, [r7, #4] + 800a266: 681b ldr r3, [r3, #0] + 800a268: 4a11 ldr r2, [pc, #68] ; (800a2b0 ) + 800a26a: 4293 cmp r3, r2 + 800a26c: d139 bne.n 800a2e2 + 800a26e: 4b09 ldr r3, [pc, #36] ; (800a294 ) + 800a270: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800a274: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 800a278: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 800a27c: d027 beq.n 800a2ce + 800a27e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 800a282: d817 bhi.n 800a2b4 + 800a284: 2b00 cmp r3, #0 + 800a286: d01c beq.n 800a2c2 + 800a288: e027 b.n 800a2da + 800a28a: bf00 nop + 800a28c: efff69f3 .word 0xefff69f3 + 800a290: 40011000 .word 0x40011000 + 800a294: 40023800 .word 0x40023800 + 800a298: 40004400 .word 0x40004400 + 800a29c: 40004800 .word 0x40004800 + 800a2a0: 40004c00 .word 0x40004c00 + 800a2a4: 40005000 .word 0x40005000 + 800a2a8: 40011400 .word 0x40011400 + 800a2ac: 40007800 .word 0x40007800 + 800a2b0: 40007c00 .word 0x40007c00 + 800a2b4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800a2b8: d006 beq.n 800a2c8 + 800a2ba: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 800a2be: d009 beq.n 800a2d4 + 800a2c0: e00b b.n 800a2da + 800a2c2: 2300 movs r3, #0 + 800a2c4: 77fb strb r3, [r7, #31] + 800a2c6: e00e b.n 800a2e6 + 800a2c8: 2302 movs r3, #2 + 800a2ca: 77fb strb r3, [r7, #31] + 800a2cc: e00b b.n 800a2e6 + 800a2ce: 2304 movs r3, #4 + 800a2d0: 77fb strb r3, [r7, #31] + 800a2d2: e008 b.n 800a2e6 + 800a2d4: 2308 movs r3, #8 + 800a2d6: 77fb strb r3, [r7, #31] + 800a2d8: e005 b.n 800a2e6 + 800a2da: 2310 movs r3, #16 + 800a2dc: 77fb strb r3, [r7, #31] + 800a2de: bf00 nop + 800a2e0: e001 b.n 800a2e6 + 800a2e2: 2310 movs r3, #16 + 800a2e4: 77fb strb r3, [r7, #31] + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 800a2e6: 687b ldr r3, [r7, #4] + 800a2e8: 69db ldr r3, [r3, #28] + 800a2ea: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800a2ee: d17f bne.n 800a3f0 + { + switch (clocksource) + 800a2f0: 7ffb ldrb r3, [r7, #31] + 800a2f2: 2b08 cmp r3, #8 + 800a2f4: d85c bhi.n 800a3b0 + 800a2f6: a201 add r2, pc, #4 ; (adr r2, 800a2fc ) + 800a2f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a2fc: 0800a321 .word 0x0800a321 + 800a300: 0800a341 .word 0x0800a341 + 800a304: 0800a361 .word 0x0800a361 + 800a308: 0800a3b1 .word 0x0800a3b1 + 800a30c: 0800a379 .word 0x0800a379 + 800a310: 0800a3b1 .word 0x0800a3b1 + 800a314: 0800a3b1 .word 0x0800a3b1 + 800a318: 0800a3b1 .word 0x0800a3b1 + 800a31c: 0800a399 .word 0x0800a399 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 800a320: f7fd fba2 bl 8007a68 + 800a324: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 800a326: 68fb ldr r3, [r7, #12] + 800a328: 005a lsls r2, r3, #1 + 800a32a: 687b ldr r3, [r7, #4] + 800a32c: 685b ldr r3, [r3, #4] + 800a32e: 085b lsrs r3, r3, #1 + 800a330: 441a add r2, r3 + 800a332: 687b ldr r3, [r7, #4] + 800a334: 685b ldr r3, [r3, #4] + 800a336: fbb2 f3f3 udiv r3, r2, r3 + 800a33a: b29b uxth r3, r3 + 800a33c: 61bb str r3, [r7, #24] + break; + 800a33e: e03a b.n 800a3b6 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 800a340: f7fd fba6 bl 8007a90 + 800a344: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 800a346: 68fb ldr r3, [r7, #12] + 800a348: 005a lsls r2, r3, #1 + 800a34a: 687b ldr r3, [r7, #4] + 800a34c: 685b ldr r3, [r3, #4] + 800a34e: 085b lsrs r3, r3, #1 + 800a350: 441a add r2, r3 + 800a352: 687b ldr r3, [r7, #4] + 800a354: 685b ldr r3, [r3, #4] + 800a356: fbb2 f3f3 udiv r3, r2, r3 + 800a35a: b29b uxth r3, r3 + 800a35c: 61bb str r3, [r7, #24] + break; + 800a35e: e02a b.n 800a3b6 + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + 800a360: 687b ldr r3, [r7, #4] + 800a362: 685b ldr r3, [r3, #4] + 800a364: 085a lsrs r2, r3, #1 + 800a366: 4b5f ldr r3, [pc, #380] ; (800a4e4 ) + 800a368: 4413 add r3, r2 + 800a36a: 687a ldr r2, [r7, #4] + 800a36c: 6852 ldr r2, [r2, #4] + 800a36e: fbb3 f3f2 udiv r3, r3, r2 + 800a372: b29b uxth r3, r3 + 800a374: 61bb str r3, [r7, #24] + break; + 800a376: e01e b.n 800a3b6 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800a378: f7fd fab8 bl 80078ec + 800a37c: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + 800a37e: 68fb ldr r3, [r7, #12] + 800a380: 005a lsls r2, r3, #1 + 800a382: 687b ldr r3, [r7, #4] + 800a384: 685b ldr r3, [r3, #4] + 800a386: 085b lsrs r3, r3, #1 + 800a388: 441a add r2, r3 + 800a38a: 687b ldr r3, [r7, #4] + 800a38c: 685b ldr r3, [r3, #4] + 800a38e: fbb2 f3f3 udiv r3, r2, r3 + 800a392: b29b uxth r3, r3 + 800a394: 61bb str r3, [r7, #24] + break; + 800a396: e00e b.n 800a3b6 + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + 800a398: 687b ldr r3, [r7, #4] + 800a39a: 685b ldr r3, [r3, #4] + 800a39c: 085b lsrs r3, r3, #1 + 800a39e: f503 3280 add.w r2, r3, #65536 ; 0x10000 + 800a3a2: 687b ldr r3, [r7, #4] + 800a3a4: 685b ldr r3, [r3, #4] + 800a3a6: fbb2 f3f3 udiv r3, r2, r3 + 800a3aa: b29b uxth r3, r3 + 800a3ac: 61bb str r3, [r7, #24] + break; + 800a3ae: e002 b.n 800a3b6 + default: + ret = HAL_ERROR; + 800a3b0: 2301 movs r3, #1 + 800a3b2: 75fb strb r3, [r7, #23] + break; + 800a3b4: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800a3b6: 69bb ldr r3, [r7, #24] + 800a3b8: 2b0f cmp r3, #15 + 800a3ba: d916 bls.n 800a3ea + 800a3bc: 69bb ldr r3, [r7, #24] + 800a3be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800a3c2: d212 bcs.n 800a3ea + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 800a3c4: 69bb ldr r3, [r7, #24] + 800a3c6: b29b uxth r3, r3 + 800a3c8: f023 030f bic.w r3, r3, #15 + 800a3cc: 817b strh r3, [r7, #10] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 800a3ce: 69bb ldr r3, [r7, #24] + 800a3d0: 085b lsrs r3, r3, #1 + 800a3d2: b29b uxth r3, r3 + 800a3d4: f003 0307 and.w r3, r3, #7 + 800a3d8: b29a uxth r2, r3 + 800a3da: 897b ldrh r3, [r7, #10] + 800a3dc: 4313 orrs r3, r2 + 800a3de: 817b strh r3, [r7, #10] + huart->Instance->BRR = brrtemp; + 800a3e0: 687b ldr r3, [r7, #4] + 800a3e2: 681b ldr r3, [r3, #0] + 800a3e4: 897a ldrh r2, [r7, #10] + 800a3e6: 60da str r2, [r3, #12] + 800a3e8: e070 b.n 800a4cc + } + else + { + ret = HAL_ERROR; + 800a3ea: 2301 movs r3, #1 + 800a3ec: 75fb strb r3, [r7, #23] + 800a3ee: e06d b.n 800a4cc + } + } + else + { + switch (clocksource) + 800a3f0: 7ffb ldrb r3, [r7, #31] + 800a3f2: 2b08 cmp r3, #8 + 800a3f4: d859 bhi.n 800a4aa + 800a3f6: a201 add r2, pc, #4 ; (adr r2, 800a3fc ) + 800a3f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800a3fc: 0800a421 .word 0x0800a421 + 800a400: 0800a43f .word 0x0800a43f + 800a404: 0800a45d .word 0x0800a45d + 800a408: 0800a4ab .word 0x0800a4ab + 800a40c: 0800a475 .word 0x0800a475 + 800a410: 0800a4ab .word 0x0800a4ab + 800a414: 0800a4ab .word 0x0800a4ab + 800a418: 0800a4ab .word 0x0800a4ab + 800a41c: 0800a493 .word 0x0800a493 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 800a420: f7fd fb22 bl 8007a68 + 800a424: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 800a426: 687b ldr r3, [r7, #4] + 800a428: 685b ldr r3, [r3, #4] + 800a42a: 085a lsrs r2, r3, #1 + 800a42c: 68fb ldr r3, [r7, #12] + 800a42e: 441a add r2, r3 + 800a430: 687b ldr r3, [r7, #4] + 800a432: 685b ldr r3, [r3, #4] + 800a434: fbb2 f3f3 udiv r3, r2, r3 + 800a438: b29b uxth r3, r3 + 800a43a: 61bb str r3, [r7, #24] + break; + 800a43c: e038 b.n 800a4b0 + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 800a43e: f7fd fb27 bl 8007a90 + 800a442: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 800a444: 687b ldr r3, [r7, #4] + 800a446: 685b ldr r3, [r3, #4] + 800a448: 085a lsrs r2, r3, #1 + 800a44a: 68fb ldr r3, [r7, #12] + 800a44c: 441a add r2, r3 + 800a44e: 687b ldr r3, [r7, #4] + 800a450: 685b ldr r3, [r3, #4] + 800a452: fbb2 f3f3 udiv r3, r2, r3 + 800a456: b29b uxth r3, r3 + 800a458: 61bb str r3, [r7, #24] + break; + 800a45a: e029 b.n 800a4b0 + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + 800a45c: 687b ldr r3, [r7, #4] + 800a45e: 685b ldr r3, [r3, #4] + 800a460: 085a lsrs r2, r3, #1 + 800a462: 4b21 ldr r3, [pc, #132] ; (800a4e8 ) + 800a464: 4413 add r3, r2 + 800a466: 687a ldr r2, [r7, #4] + 800a468: 6852 ldr r2, [r2, #4] + 800a46a: fbb3 f3f2 udiv r3, r3, r2 + 800a46e: b29b uxth r3, r3 + 800a470: 61bb str r3, [r7, #24] + break; + 800a472: e01d b.n 800a4b0 + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800a474: f7fd fa3a bl 80078ec + 800a478: 60f8 str r0, [r7, #12] + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + 800a47a: 687b ldr r3, [r7, #4] + 800a47c: 685b ldr r3, [r3, #4] + 800a47e: 085a lsrs r2, r3, #1 + 800a480: 68fb ldr r3, [r7, #12] + 800a482: 441a add r2, r3 + 800a484: 687b ldr r3, [r7, #4] + 800a486: 685b ldr r3, [r3, #4] + 800a488: fbb2 f3f3 udiv r3, r2, r3 + 800a48c: b29b uxth r3, r3 + 800a48e: 61bb str r3, [r7, #24] + break; + 800a490: e00e b.n 800a4b0 + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + 800a492: 687b ldr r3, [r7, #4] + 800a494: 685b ldr r3, [r3, #4] + 800a496: 085b lsrs r3, r3, #1 + 800a498: f503 4200 add.w r2, r3, #32768 ; 0x8000 + 800a49c: 687b ldr r3, [r7, #4] + 800a49e: 685b ldr r3, [r3, #4] + 800a4a0: fbb2 f3f3 udiv r3, r2, r3 + 800a4a4: b29b uxth r3, r3 + 800a4a6: 61bb str r3, [r7, #24] + break; + 800a4a8: e002 b.n 800a4b0 + default: + ret = HAL_ERROR; + 800a4aa: 2301 movs r3, #1 + 800a4ac: 75fb strb r3, [r7, #23] + break; + 800a4ae: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 800a4b0: 69bb ldr r3, [r7, #24] + 800a4b2: 2b0f cmp r3, #15 + 800a4b4: d908 bls.n 800a4c8 + 800a4b6: 69bb ldr r3, [r7, #24] + 800a4b8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800a4bc: d204 bcs.n 800a4c8 + { + huart->Instance->BRR = usartdiv; + 800a4be: 687b ldr r3, [r7, #4] + 800a4c0: 681b ldr r3, [r3, #0] + 800a4c2: 69ba ldr r2, [r7, #24] + 800a4c4: 60da str r2, [r3, #12] + 800a4c6: e001 b.n 800a4cc + } + else + { + ret = HAL_ERROR; + 800a4c8: 2301 movs r3, #1 + 800a4ca: 75fb strb r3, [r7, #23] + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 800a4cc: 687b ldr r3, [r7, #4] + 800a4ce: 2200 movs r2, #0 + 800a4d0: 661a str r2, [r3, #96] ; 0x60 + huart->TxISR = NULL; + 800a4d2: 687b ldr r3, [r7, #4] + 800a4d4: 2200 movs r2, #0 + 800a4d6: 665a str r2, [r3, #100] ; 0x64 + + return ret; + 800a4d8: 7dfb ldrb r3, [r7, #23] +} + 800a4da: 4618 mov r0, r3 + 800a4dc: 3720 adds r7, #32 + 800a4de: 46bd mov sp, r7 + 800a4e0: bd80 pop {r7, pc} + 800a4e2: bf00 nop + 800a4e4: 01e84800 .word 0x01e84800 + 800a4e8: 00f42400 .word 0x00f42400 + +0800a4ec : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 800a4ec: b480 push {r7} + 800a4ee: b083 sub sp, #12 + 800a4f0: af00 add r7, sp, #0 + 800a4f2: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 800a4f4: 687b ldr r3, [r7, #4] + 800a4f6: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a4f8: f003 0301 and.w r3, r3, #1 + 800a4fc: 2b00 cmp r3, #0 + 800a4fe: d00a beq.n 800a516 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 800a500: 687b ldr r3, [r7, #4] + 800a502: 681b ldr r3, [r3, #0] + 800a504: 685b ldr r3, [r3, #4] + 800a506: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 800a50a: 687b ldr r3, [r7, #4] + 800a50c: 6a9a ldr r2, [r3, #40] ; 0x28 + 800a50e: 687b ldr r3, [r7, #4] + 800a510: 681b ldr r3, [r3, #0] + 800a512: 430a orrs r2, r1 + 800a514: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 800a516: 687b ldr r3, [r7, #4] + 800a518: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a51a: f003 0302 and.w r3, r3, #2 + 800a51e: 2b00 cmp r3, #0 + 800a520: d00a beq.n 800a538 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 800a522: 687b ldr r3, [r7, #4] + 800a524: 681b ldr r3, [r3, #0] + 800a526: 685b ldr r3, [r3, #4] + 800a528: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 800a52c: 687b ldr r3, [r7, #4] + 800a52e: 6ada ldr r2, [r3, #44] ; 0x2c + 800a530: 687b ldr r3, [r7, #4] + 800a532: 681b ldr r3, [r3, #0] + 800a534: 430a orrs r2, r1 + 800a536: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 800a538: 687b ldr r3, [r7, #4] + 800a53a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a53c: f003 0304 and.w r3, r3, #4 + 800a540: 2b00 cmp r3, #0 + 800a542: d00a beq.n 800a55a + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 800a544: 687b ldr r3, [r7, #4] + 800a546: 681b ldr r3, [r3, #0] + 800a548: 685b ldr r3, [r3, #4] + 800a54a: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800a54e: 687b ldr r3, [r7, #4] + 800a550: 6b1a ldr r2, [r3, #48] ; 0x30 + 800a552: 687b ldr r3, [r7, #4] + 800a554: 681b ldr r3, [r3, #0] + 800a556: 430a orrs r2, r1 + 800a558: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 800a55a: 687b ldr r3, [r7, #4] + 800a55c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a55e: f003 0308 and.w r3, r3, #8 + 800a562: 2b00 cmp r3, #0 + 800a564: d00a beq.n 800a57c + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 800a566: 687b ldr r3, [r7, #4] + 800a568: 681b ldr r3, [r3, #0] + 800a56a: 685b ldr r3, [r3, #4] + 800a56c: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 800a570: 687b ldr r3, [r7, #4] + 800a572: 6b5a ldr r2, [r3, #52] ; 0x34 + 800a574: 687b ldr r3, [r7, #4] + 800a576: 681b ldr r3, [r3, #0] + 800a578: 430a orrs r2, r1 + 800a57a: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 800a57c: 687b ldr r3, [r7, #4] + 800a57e: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a580: f003 0310 and.w r3, r3, #16 + 800a584: 2b00 cmp r3, #0 + 800a586: d00a beq.n 800a59e + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 800a588: 687b ldr r3, [r7, #4] + 800a58a: 681b ldr r3, [r3, #0] + 800a58c: 689b ldr r3, [r3, #8] + 800a58e: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 800a592: 687b ldr r3, [r7, #4] + 800a594: 6b9a ldr r2, [r3, #56] ; 0x38 + 800a596: 687b ldr r3, [r7, #4] + 800a598: 681b ldr r3, [r3, #0] + 800a59a: 430a orrs r2, r1 + 800a59c: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 800a59e: 687b ldr r3, [r7, #4] + 800a5a0: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a5a2: f003 0320 and.w r3, r3, #32 + 800a5a6: 2b00 cmp r3, #0 + 800a5a8: d00a beq.n 800a5c0 + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 800a5aa: 687b ldr r3, [r7, #4] + 800a5ac: 681b ldr r3, [r3, #0] + 800a5ae: 689b ldr r3, [r3, #8] + 800a5b0: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 800a5b4: 687b ldr r3, [r7, #4] + 800a5b6: 6bda ldr r2, [r3, #60] ; 0x3c + 800a5b8: 687b ldr r3, [r7, #4] + 800a5ba: 681b ldr r3, [r3, #0] + 800a5bc: 430a orrs r2, r1 + 800a5be: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 800a5c0: 687b ldr r3, [r7, #4] + 800a5c2: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a5c4: f003 0340 and.w r3, r3, #64 ; 0x40 + 800a5c8: 2b00 cmp r3, #0 + 800a5ca: d01a beq.n 800a602 + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 800a5cc: 687b ldr r3, [r7, #4] + 800a5ce: 681b ldr r3, [r3, #0] + 800a5d0: 685b ldr r3, [r3, #4] + 800a5d2: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 800a5d6: 687b ldr r3, [r7, #4] + 800a5d8: 6c1a ldr r2, [r3, #64] ; 0x40 + 800a5da: 687b ldr r3, [r7, #4] + 800a5dc: 681b ldr r3, [r3, #0] + 800a5de: 430a orrs r2, r1 + 800a5e0: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 800a5e2: 687b ldr r3, [r7, #4] + 800a5e4: 6c1b ldr r3, [r3, #64] ; 0x40 + 800a5e6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 800a5ea: d10a bne.n 800a602 + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 800a5ec: 687b ldr r3, [r7, #4] + 800a5ee: 681b ldr r3, [r3, #0] + 800a5f0: 685b ldr r3, [r3, #4] + 800a5f2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 800a5f6: 687b ldr r3, [r7, #4] + 800a5f8: 6c5a ldr r2, [r3, #68] ; 0x44 + 800a5fa: 687b ldr r3, [r7, #4] + 800a5fc: 681b ldr r3, [r3, #0] + 800a5fe: 430a orrs r2, r1 + 800a600: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 800a602: 687b ldr r3, [r7, #4] + 800a604: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a606: f003 0380 and.w r3, r3, #128 ; 0x80 + 800a60a: 2b00 cmp r3, #0 + 800a60c: d00a beq.n 800a624 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 800a60e: 687b ldr r3, [r7, #4] + 800a610: 681b ldr r3, [r3, #0] + 800a612: 685b ldr r3, [r3, #4] + 800a614: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 800a618: 687b ldr r3, [r7, #4] + 800a61a: 6c9a ldr r2, [r3, #72] ; 0x48 + 800a61c: 687b ldr r3, [r7, #4] + 800a61e: 681b ldr r3, [r3, #0] + 800a620: 430a orrs r2, r1 + 800a622: 605a str r2, [r3, #4] + } +} + 800a624: bf00 nop + 800a626: 370c adds r7, #12 + 800a628: 46bd mov sp, r7 + 800a62a: f85d 7b04 ldr.w r7, [sp], #4 + 800a62e: 4770 bx lr + +0800a630 : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 800a630: b580 push {r7, lr} + 800a632: b086 sub sp, #24 + 800a634: af02 add r7, sp, #8 + 800a636: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 800a638: 687b ldr r3, [r7, #4] + 800a63a: 2200 movs r2, #0 + 800a63c: 67da str r2, [r3, #124] ; 0x7c + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + 800a63e: f7f9 ff57 bl 80044f0 + 800a642: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 800a644: 687b ldr r3, [r7, #4] + 800a646: 681b ldr r3, [r3, #0] + 800a648: 681b ldr r3, [r3, #0] + 800a64a: f003 0308 and.w r3, r3, #8 + 800a64e: 2b08 cmp r3, #8 + 800a650: d10e bne.n 800a670 + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 800a652: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 800a656: 9300 str r3, [sp, #0] + 800a658: 68fb ldr r3, [r7, #12] + 800a65a: 2200 movs r2, #0 + 800a65c: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 800a660: 6878 ldr r0, [r7, #4] + 800a662: f000 f814 bl 800a68e + 800a666: 4603 mov r3, r0 + 800a668: 2b00 cmp r3, #0 + 800a66a: d001 beq.n 800a670 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 800a66c: 2303 movs r3, #3 + 800a66e: e00a b.n 800a686 + } + } +#endif + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 800a670: 687b ldr r3, [r7, #4] + 800a672: 2220 movs r2, #32 + 800a674: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 800a676: 687b ldr r3, [r7, #4] + 800a678: 2220 movs r2, #32 + 800a67a: 679a str r2, [r3, #120] ; 0x78 + + __HAL_UNLOCK(huart); + 800a67c: 687b ldr r3, [r7, #4] + 800a67e: 2200 movs r2, #0 + 800a680: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_OK; + 800a684: 2300 movs r3, #0 +} + 800a686: 4618 mov r0, r3 + 800a688: 3710 adds r7, #16 + 800a68a: 46bd mov sp, r7 + 800a68c: bd80 pop {r7, pc} + +0800a68e : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 800a68e: b580 push {r7, lr} + 800a690: b084 sub sp, #16 + 800a692: af00 add r7, sp, #0 + 800a694: 60f8 str r0, [r7, #12] + 800a696: 60b9 str r1, [r7, #8] + 800a698: 603b str r3, [r7, #0] + 800a69a: 4613 mov r3, r2 + 800a69c: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 800a69e: e05d b.n 800a75c + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 800a6a0: 69bb ldr r3, [r7, #24] + 800a6a2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800a6a6: d059 beq.n 800a75c + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800a6a8: f7f9 ff22 bl 80044f0 + 800a6ac: 4602 mov r2, r0 + 800a6ae: 683b ldr r3, [r7, #0] + 800a6b0: 1ad3 subs r3, r2, r3 + 800a6b2: 69ba ldr r2, [r7, #24] + 800a6b4: 429a cmp r2, r3 + 800a6b6: d302 bcc.n 800a6be + 800a6b8: 69bb ldr r3, [r7, #24] + 800a6ba: 2b00 cmp r3, #0 + 800a6bc: d11b bne.n 800a6f6 + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800a6be: 68fb ldr r3, [r7, #12] + 800a6c0: 681b ldr r3, [r3, #0] + 800a6c2: 681a ldr r2, [r3, #0] + 800a6c4: 68fb ldr r3, [r7, #12] + 800a6c6: 681b ldr r3, [r3, #0] + 800a6c8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 800a6cc: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800a6ce: 68fb ldr r3, [r7, #12] + 800a6d0: 681b ldr r3, [r3, #0] + 800a6d2: 689a ldr r2, [r3, #8] + 800a6d4: 68fb ldr r3, [r7, #12] + 800a6d6: 681b ldr r3, [r3, #0] + 800a6d8: f022 0201 bic.w r2, r2, #1 + 800a6dc: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 800a6de: 68fb ldr r3, [r7, #12] + 800a6e0: 2220 movs r2, #32 + 800a6e2: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 800a6e4: 68fb ldr r3, [r7, #12] + 800a6e6: 2220 movs r2, #32 + 800a6e8: 679a str r2, [r3, #120] ; 0x78 + + __HAL_UNLOCK(huart); + 800a6ea: 68fb ldr r3, [r7, #12] + 800a6ec: 2200 movs r2, #0 + 800a6ee: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_TIMEOUT; + 800a6f2: 2303 movs r3, #3 + 800a6f4: e042 b.n 800a77c + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + 800a6f6: 68fb ldr r3, [r7, #12] + 800a6f8: 681b ldr r3, [r3, #0] + 800a6fa: 681b ldr r3, [r3, #0] + 800a6fc: f003 0304 and.w r3, r3, #4 + 800a700: 2b00 cmp r3, #0 + 800a702: d02b beq.n 800a75c + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 800a704: 68fb ldr r3, [r7, #12] + 800a706: 681b ldr r3, [r3, #0] + 800a708: 69db ldr r3, [r3, #28] + 800a70a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800a70e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800a712: d123 bne.n 800a75c + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 800a714: 68fb ldr r3, [r7, #12] + 800a716: 681b ldr r3, [r3, #0] + 800a718: f44f 6200 mov.w r2, #2048 ; 0x800 + 800a71c: 621a str r2, [r3, #32] + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 800a71e: 68fb ldr r3, [r7, #12] + 800a720: 681b ldr r3, [r3, #0] + 800a722: 681a ldr r2, [r3, #0] + 800a724: 68fb ldr r3, [r7, #12] + 800a726: 681b ldr r3, [r3, #0] + 800a728: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 800a72c: 601a str r2, [r3, #0] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800a72e: 68fb ldr r3, [r7, #12] + 800a730: 681b ldr r3, [r3, #0] + 800a732: 689a ldr r2, [r3, #8] + 800a734: 68fb ldr r3, [r7, #12] + 800a736: 681b ldr r3, [r3, #0] + 800a738: f022 0201 bic.w r2, r2, #1 + 800a73c: 609a str r2, [r3, #8] + + huart->gState = HAL_UART_STATE_READY; + 800a73e: 68fb ldr r3, [r7, #12] + 800a740: 2220 movs r2, #32 + 800a742: 675a str r2, [r3, #116] ; 0x74 + huart->RxState = HAL_UART_STATE_READY; + 800a744: 68fb ldr r3, [r7, #12] + 800a746: 2220 movs r2, #32 + 800a748: 679a str r2, [r3, #120] ; 0x78 + huart->ErrorCode = HAL_UART_ERROR_RTO; + 800a74a: 68fb ldr r3, [r7, #12] + 800a74c: 2220 movs r2, #32 + 800a74e: 67da str r2, [r3, #124] ; 0x7c + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 800a750: 68fb ldr r3, [r7, #12] + 800a752: 2200 movs r2, #0 + 800a754: f883 2070 strb.w r2, [r3, #112] ; 0x70 + + return HAL_TIMEOUT; + 800a758: 2303 movs r3, #3 + 800a75a: e00f b.n 800a77c + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 800a75c: 68fb ldr r3, [r7, #12] + 800a75e: 681b ldr r3, [r3, #0] + 800a760: 69da ldr r2, [r3, #28] + 800a762: 68bb ldr r3, [r7, #8] + 800a764: 4013 ands r3, r2 + 800a766: 68ba ldr r2, [r7, #8] + 800a768: 429a cmp r2, r3 + 800a76a: bf0c ite eq + 800a76c: 2301 moveq r3, #1 + 800a76e: 2300 movne r3, #0 + 800a770: b2db uxtb r3, r3 + 800a772: 461a mov r2, r3 + 800a774: 79fb ldrb r3, [r7, #7] + 800a776: 429a cmp r2, r3 + 800a778: d092 beq.n 800a6a0 + } + } + } + } + return HAL_OK; + 800a77a: 2300 movs r3, #0 +} + 800a77c: 4618 mov r0, r3 + 800a77e: 3710 adds r7, #16 + 800a780: 46bd mov sp, r7 + 800a782: bd80 pop {r7, pc} + +0800a784 : + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + 800a784: b480 push {r7} + 800a786: b085 sub sp, #20 + 800a788: af00 add r7, sp, #0 + 800a78a: 6078 str r0, [r7, #4] + 800a78c: 6039 str r1, [r7, #0] + uint32_t tmpr1 = 0; + 800a78e: 2300 movs r3, #0 + 800a790: 60fb str r3, [r7, #12] + uint32_t tmpr2 = 0; + 800a792: 2300 movs r3, #0 + 800a794: 60bb str r3, [r7, #8] + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank != FMC_SDRAM_BANK2) + 800a796: 683b ldr r3, [r7, #0] + 800a798: 681b ldr r3, [r3, #0] + 800a79a: 2b01 cmp r3, #1 + 800a79c: d027 beq.n 800a7ee + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + 800a79e: 687b ldr r3, [r7, #4] + 800a7a0: 681b ldr r3, [r3, #0] + 800a7a2: 60fb str r3, [r7, #12] + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + 800a7a4: 68fa ldr r2, [r7, #12] + 800a7a6: 4b2f ldr r3, [pc, #188] ; (800a864 ) + 800a7a8: 4013 ands r3, r2 + 800a7aa: 60fb str r3, [r7, #12] + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a7ac: 683b ldr r3, [r7, #0] + 800a7ae: 685a ldr r2, [r3, #4] + Init->RowBitsNumber |\ + 800a7b0: 683b ldr r3, [r7, #0] + 800a7b2: 689b ldr r3, [r3, #8] + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a7b4: 431a orrs r2, r3 + Init->MemoryDataWidth |\ + 800a7b6: 683b ldr r3, [r7, #0] + 800a7b8: 68db ldr r3, [r3, #12] + Init->RowBitsNumber |\ + 800a7ba: 431a orrs r2, r3 + Init->InternalBankNumber |\ + 800a7bc: 683b ldr r3, [r7, #0] + 800a7be: 691b ldr r3, [r3, #16] + Init->MemoryDataWidth |\ + 800a7c0: 431a orrs r2, r3 + Init->CASLatency |\ + 800a7c2: 683b ldr r3, [r7, #0] + 800a7c4: 695b ldr r3, [r3, #20] + Init->InternalBankNumber |\ + 800a7c6: 431a orrs r2, r3 + Init->WriteProtection |\ + 800a7c8: 683b ldr r3, [r7, #0] + 800a7ca: 699b ldr r3, [r3, #24] + Init->CASLatency |\ + 800a7cc: 431a orrs r2, r3 + Init->SDClockPeriod |\ + 800a7ce: 683b ldr r3, [r7, #0] + 800a7d0: 69db ldr r3, [r3, #28] + Init->WriteProtection |\ + 800a7d2: 431a orrs r2, r3 + Init->ReadBurst |\ + 800a7d4: 683b ldr r3, [r7, #0] + 800a7d6: 6a1b ldr r3, [r3, #32] + Init->SDClockPeriod |\ + 800a7d8: 431a orrs r2, r3 + Init->ReadPipeDelay + 800a7da: 683b ldr r3, [r7, #0] + 800a7dc: 6a5b ldr r3, [r3, #36] ; 0x24 + Init->ReadBurst |\ + 800a7de: 4313 orrs r3, r2 + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a7e0: 68fa ldr r2, [r7, #12] + 800a7e2: 4313 orrs r3, r2 + 800a7e4: 60fb str r3, [r7, #12] + ); + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + 800a7e6: 687b ldr r3, [r7, #4] + 800a7e8: 68fa ldr r2, [r7, #12] + 800a7ea: 601a str r2, [r3, #0] + 800a7ec: e032 b.n 800a854 + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + 800a7ee: 687b ldr r3, [r7, #4] + 800a7f0: 681b ldr r3, [r3, #0] + 800a7f2: 60fb str r3, [r7, #12] + + /* Clear SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + 800a7f4: 68fb ldr r3, [r7, #12] + 800a7f6: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00 + 800a7fa: 60fb str r3, [r7, #12] + + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + 800a7fc: 683b ldr r3, [r7, #0] + 800a7fe: 69da ldr r2, [r3, #28] + Init->ReadBurst |\ + 800a800: 683b ldr r3, [r7, #0] + 800a802: 6a1b ldr r3, [r3, #32] + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + 800a804: 431a orrs r2, r3 + Init->ReadPipeDelay); + 800a806: 683b ldr r3, [r7, #0] + 800a808: 6a5b ldr r3, [r3, #36] ; 0x24 + Init->ReadBurst |\ + 800a80a: 4313 orrs r3, r2 + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + 800a80c: 68fa ldr r2, [r7, #12] + 800a80e: 4313 orrs r3, r2 + 800a810: 60fb str r3, [r7, #12] + + tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; + 800a812: 687b ldr r3, [r7, #4] + 800a814: 685b ldr r3, [r3, #4] + 800a816: 60bb str r3, [r7, #8] + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + 800a818: 68ba ldr r2, [r7, #8] + 800a81a: 4b12 ldr r3, [pc, #72] ; (800a864 ) + 800a81c: 4013 ands r3, r2 + 800a81e: 60bb str r3, [r7, #8] + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a820: 683b ldr r3, [r7, #0] + 800a822: 685a ldr r2, [r3, #4] + Init->RowBitsNumber |\ + 800a824: 683b ldr r3, [r7, #0] + 800a826: 689b ldr r3, [r3, #8] + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a828: 431a orrs r2, r3 + Init->MemoryDataWidth |\ + 800a82a: 683b ldr r3, [r7, #0] + 800a82c: 68db ldr r3, [r3, #12] + Init->RowBitsNumber |\ + 800a82e: 431a orrs r2, r3 + Init->InternalBankNumber |\ + 800a830: 683b ldr r3, [r7, #0] + 800a832: 691b ldr r3, [r3, #16] + Init->MemoryDataWidth |\ + 800a834: 431a orrs r2, r3 + Init->CASLatency |\ + 800a836: 683b ldr r3, [r7, #0] + 800a838: 695b ldr r3, [r3, #20] + Init->InternalBankNumber |\ + 800a83a: 431a orrs r2, r3 + Init->WriteProtection); + 800a83c: 683b ldr r3, [r7, #0] + 800a83e: 699b ldr r3, [r3, #24] + Init->CASLatency |\ + 800a840: 4313 orrs r3, r2 + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + 800a842: 68ba ldr r2, [r7, #8] + 800a844: 4313 orrs r3, r2 + 800a846: 60bb str r3, [r7, #8] + + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + 800a848: 687b ldr r3, [r7, #4] + 800a84a: 68fa ldr r2, [r7, #12] + 800a84c: 601a str r2, [r3, #0] + Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; + 800a84e: 687b ldr r3, [r7, #4] + 800a850: 68ba ldr r2, [r7, #8] + 800a852: 605a str r2, [r3, #4] + } + + return HAL_OK; + 800a854: 2300 movs r3, #0 +} + 800a856: 4618 mov r0, r3 + 800a858: 3714 adds r7, #20 + 800a85a: 46bd mov sp, r7 + 800a85c: f85d 7b04 ldr.w r7, [sp], #4 + 800a860: 4770 bx lr + 800a862: bf00 nop + 800a864: ffff8000 .word 0xffff8000 + +0800a868 : + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + 800a868: b480 push {r7} + 800a86a: b087 sub sp, #28 + 800a86c: af00 add r7, sp, #0 + 800a86e: 60f8 str r0, [r7, #12] + 800a870: 60b9 str r1, [r7, #8] + 800a872: 607a str r2, [r7, #4] + uint32_t tmpr1 = 0; + 800a874: 2300 movs r3, #0 + 800a876: 617b str r3, [r7, #20] + uint32_t tmpr2 = 0; + 800a878: 2300 movs r3, #0 + 800a87a: 613b str r3, [r7, #16] + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank != FMC_SDRAM_BANK2) + 800a87c: 687b ldr r3, [r7, #4] + 800a87e: 2b01 cmp r3, #1 + 800a880: d02e beq.n 800a8e0 + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + 800a882: 68fb ldr r3, [r7, #12] + 800a884: 689b ldr r3, [r3, #8] + 800a886: 617b str r3, [r7, #20] + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + 800a888: 697b ldr r3, [r7, #20] + 800a88a: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000 + 800a88e: 617b str r3, [r7, #20] + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a890: 68bb ldr r3, [r7, #8] + 800a892: 681b ldr r3, [r3, #0] + 800a894: 1e5a subs r2, r3, #1 + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + 800a896: 68bb ldr r3, [r7, #8] + 800a898: 685b ldr r3, [r3, #4] + 800a89a: 3b01 subs r3, #1 + 800a89c: 011b lsls r3, r3, #4 + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a89e: 431a orrs r2, r3 + (((Timing->SelfRefreshTime)-1) << 8) |\ + 800a8a0: 68bb ldr r3, [r7, #8] + 800a8a2: 689b ldr r3, [r3, #8] + 800a8a4: 3b01 subs r3, #1 + 800a8a6: 021b lsls r3, r3, #8 + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + 800a8a8: 431a orrs r2, r3 + (((Timing->RowCycleDelay)-1) << 12) |\ + 800a8aa: 68bb ldr r3, [r7, #8] + 800a8ac: 68db ldr r3, [r3, #12] + 800a8ae: 3b01 subs r3, #1 + 800a8b0: 031b lsls r3, r3, #12 + (((Timing->SelfRefreshTime)-1) << 8) |\ + 800a8b2: 431a orrs r2, r3 + (((Timing->WriteRecoveryTime)-1) <<16) |\ + 800a8b4: 68bb ldr r3, [r7, #8] + 800a8b6: 691b ldr r3, [r3, #16] + 800a8b8: 3b01 subs r3, #1 + 800a8ba: 041b lsls r3, r3, #16 + (((Timing->RowCycleDelay)-1) << 12) |\ + 800a8bc: 431a orrs r2, r3 + (((Timing->RPDelay)-1) << 20) |\ + 800a8be: 68bb ldr r3, [r7, #8] + 800a8c0: 695b ldr r3, [r3, #20] + 800a8c2: 3b01 subs r3, #1 + 800a8c4: 051b lsls r3, r3, #20 + (((Timing->WriteRecoveryTime)-1) <<16) |\ + 800a8c6: 431a orrs r2, r3 + (((Timing->RCDDelay)-1) << 24)); + 800a8c8: 68bb ldr r3, [r7, #8] + 800a8ca: 699b ldr r3, [r3, #24] + 800a8cc: 3b01 subs r3, #1 + 800a8ce: 061b lsls r3, r3, #24 + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a8d0: 4313 orrs r3, r2 + 800a8d2: 697a ldr r2, [r7, #20] + 800a8d4: 4313 orrs r3, r2 + 800a8d6: 617b str r3, [r7, #20] + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + 800a8d8: 68fb ldr r3, [r7, #12] + 800a8da: 697a ldr r2, [r7, #20] + 800a8dc: 609a str r2, [r3, #8] + 800a8de: e039 b.n 800a954 + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + 800a8e0: 68fb ldr r3, [r7, #12] + 800a8e2: 689b ldr r3, [r3, #8] + 800a8e4: 617b str r3, [r7, #20] + + /* Clear TRC and TRP bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); + 800a8e6: 697a ldr r2, [r7, #20] + 800a8e8: 4b1e ldr r3, [pc, #120] ; (800a964 ) + 800a8ea: 4013 ands r3, r2 + 800a8ec: 617b str r3, [r7, #20] + + tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + 800a8ee: 68bb ldr r3, [r7, #8] + 800a8f0: 68db ldr r3, [r3, #12] + 800a8f2: 3b01 subs r3, #1 + 800a8f4: 031a lsls r2, r3, #12 + (((Timing->RPDelay)-1) << 20)); + 800a8f6: 68bb ldr r3, [r7, #8] + 800a8f8: 695b ldr r3, [r3, #20] + 800a8fa: 3b01 subs r3, #1 + 800a8fc: 051b lsls r3, r3, #20 + tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + 800a8fe: 4313 orrs r3, r2 + 800a900: 697a ldr r2, [r7, #20] + 800a902: 4313 orrs r3, r2 + 800a904: 617b str r3, [r7, #20] + + tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; + 800a906: 68fb ldr r3, [r7, #12] + 800a908: 68db ldr r3, [r3, #12] + 800a90a: 613b str r3, [r7, #16] + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + 800a90c: 693b ldr r3, [r7, #16] + 800a90e: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000 + 800a912: 613b str r3, [r7, #16] + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a914: 68bb ldr r3, [r7, #8] + 800a916: 681b ldr r3, [r3, #0] + 800a918: 1e5a subs r2, r3, #1 + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + 800a91a: 68bb ldr r3, [r7, #8] + 800a91c: 685b ldr r3, [r3, #4] + 800a91e: 3b01 subs r3, #1 + 800a920: 011b lsls r3, r3, #4 + tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a922: 431a orrs r2, r3 + (((Timing->SelfRefreshTime)-1) << 8) |\ + 800a924: 68bb ldr r3, [r7, #8] + 800a926: 689b ldr r3, [r3, #8] + 800a928: 3b01 subs r3, #1 + 800a92a: 021b lsls r3, r3, #8 + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + 800a92c: 431a orrs r2, r3 + (((Timing->WriteRecoveryTime)-1) <<16) |\ + 800a92e: 68bb ldr r3, [r7, #8] + 800a930: 691b ldr r3, [r3, #16] + 800a932: 3b01 subs r3, #1 + 800a934: 041b lsls r3, r3, #16 + (((Timing->SelfRefreshTime)-1) << 8) |\ + 800a936: 431a orrs r2, r3 + (((Timing->RCDDelay)-1) << 24)); + 800a938: 68bb ldr r3, [r7, #8] + 800a93a: 699b ldr r3, [r3, #24] + 800a93c: 3b01 subs r3, #1 + 800a93e: 061b lsls r3, r3, #24 + tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + 800a940: 4313 orrs r3, r2 + 800a942: 693a ldr r2, [r7, #16] + 800a944: 4313 orrs r3, r2 + 800a946: 613b str r3, [r7, #16] + + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + 800a948: 68fb ldr r3, [r7, #12] + 800a94a: 697a ldr r2, [r7, #20] + 800a94c: 609a str r2, [r3, #8] + Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; + 800a94e: 68fb ldr r3, [r7, #12] + 800a950: 693a ldr r2, [r7, #16] + 800a952: 60da str r2, [r3, #12] + } + + return HAL_OK; + 800a954: 2300 movs r3, #0 +} + 800a956: 4618 mov r0, r3 + 800a958: 371c adds r7, #28 + 800a95a: 46bd mov sp, r7 + 800a95c: f85d 7b04 ldr.w r7, [sp], #4 + 800a960: 4770 bx lr + 800a962: bf00 nop + 800a964: ff0f0fff .word 0xff0f0fff + +0800a968 : + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + 800a968: b480 push {r7} + 800a96a: b087 sub sp, #28 + 800a96c: af00 add r7, sp, #0 + 800a96e: 60f8 str r0, [r7, #12] + 800a970: 60b9 str r1, [r7, #8] + 800a972: 607a str r2, [r7, #4] + __IO uint32_t tmpr = 0; + 800a974: 2300 movs r3, #0 + 800a976: 617b str r3, [r7, #20] + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + tmpr = (uint32_t)((Command->CommandMode) |\ + 800a978: 68bb ldr r3, [r7, #8] + 800a97a: 681a ldr r2, [r3, #0] + (Command->CommandTarget) |\ + 800a97c: 68bb ldr r3, [r7, #8] + 800a97e: 685b ldr r3, [r3, #4] + tmpr = (uint32_t)((Command->CommandMode) |\ + 800a980: 431a orrs r2, r3 + (((Command->AutoRefreshNumber)-1) << 5) |\ + 800a982: 68bb ldr r3, [r7, #8] + 800a984: 689b ldr r3, [r3, #8] + 800a986: 3b01 subs r3, #1 + 800a988: 015b lsls r3, r3, #5 + (Command->CommandTarget) |\ + 800a98a: 431a orrs r2, r3 + ((Command->ModeRegisterDefinition) << 9) + 800a98c: 68bb ldr r3, [r7, #8] + 800a98e: 68db ldr r3, [r3, #12] + 800a990: 025b lsls r3, r3, #9 + tmpr = (uint32_t)((Command->CommandMode) |\ + 800a992: 4313 orrs r3, r2 + 800a994: 617b str r3, [r7, #20] + ); + + Device->SDCMR = tmpr; + 800a996: 697a ldr r2, [r7, #20] + 800a998: 68fb ldr r3, [r7, #12] + 800a99a: 611a str r2, [r3, #16] + + return HAL_OK; + 800a99c: 2300 movs r3, #0 +} + 800a99e: 4618 mov r0, r3 + 800a9a0: 371c adds r7, #28 + 800a9a2: 46bd mov sp, r7 + 800a9a4: f85d 7b04 ldr.w r7, [sp], #4 + 800a9a8: 4770 bx lr + +0800a9aa : + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + 800a9aa: b480 push {r7} + 800a9ac: b083 sub sp, #12 + 800a9ae: af00 add r7, sp, #0 + 800a9b0: 6078 str r0, [r7, #4] + 800a9b2: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + Device->SDRTR |= (RefreshRate<<1); + 800a9b4: 687b ldr r3, [r7, #4] + 800a9b6: 695a ldr r2, [r3, #20] + 800a9b8: 683b ldr r3, [r7, #0] + 800a9ba: 005b lsls r3, r3, #1 + 800a9bc: 431a orrs r2, r3 + 800a9be: 687b ldr r3, [r7, #4] + 800a9c0: 615a str r2, [r3, #20] + + return HAL_OK; + 800a9c2: 2300 movs r3, #0 +} + 800a9c4: 4618 mov r0, r3 + 800a9c6: 370c adds r7, #12 + 800a9c8: 46bd mov sp, r7 + 800a9ca: f85d 7b04 ldr.w r7, [sp], #4 + 800a9ce: 4770 bx lr + +0800a9d0 : + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + 800a9d0: b480 push {r7} + 800a9d2: b085 sub sp, #20 + 800a9d4: af00 add r7, sp, #0 + 800a9d6: 4603 mov r3, r0 + 800a9d8: 80fb strh r3, [r7, #6] + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + 800a9da: 2300 movs r3, #0 + 800a9dc: 60fb str r3, [r7, #12] + + if (priority != osPriorityError) { + 800a9de: f9b7 3006 ldrsh.w r3, [r7, #6] + 800a9e2: 2b84 cmp r3, #132 ; 0x84 + 800a9e4: d005 beq.n 800a9f2 + fpriority += (priority - osPriorityIdle); + 800a9e6: f9b7 2006 ldrsh.w r2, [r7, #6] + 800a9ea: 68fb ldr r3, [r7, #12] + 800a9ec: 4413 add r3, r2 + 800a9ee: 3303 adds r3, #3 + 800a9f0: 60fb str r3, [r7, #12] + } + + return fpriority; + 800a9f2: 68fb ldr r3, [r7, #12] +} + 800a9f4: 4618 mov r0, r3 + 800a9f6: 3714 adds r7, #20 + 800a9f8: 46bd mov sp, r7 + 800a9fa: f85d 7b04 ldr.w r7, [sp], #4 + 800a9fe: 4770 bx lr + +0800aa00 : +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + 800aa00: b5f0 push {r4, r5, r6, r7, lr} + 800aa02: b089 sub sp, #36 ; 0x24 + 800aa04: af04 add r7, sp, #16 + 800aa06: 6078 str r0, [r7, #4] + 800aa08: 6039 str r1, [r7, #0] + TaskHandle_t handle; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { + 800aa0a: 687b ldr r3, [r7, #4] + 800aa0c: 695b ldr r3, [r3, #20] + 800aa0e: 2b00 cmp r3, #0 + 800aa10: d020 beq.n 800aa54 + 800aa12: 687b ldr r3, [r7, #4] + 800aa14: 699b ldr r3, [r3, #24] + 800aa16: 2b00 cmp r3, #0 + 800aa18: d01c beq.n 800aa54 + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800aa1a: 687b ldr r3, [r7, #4] + 800aa1c: 685c ldr r4, [r3, #4] + 800aa1e: 687b ldr r3, [r7, #4] + 800aa20: 681d ldr r5, [r3, #0] + 800aa22: 687b ldr r3, [r7, #4] + 800aa24: 691e ldr r6, [r3, #16] + 800aa26: 687b ldr r3, [r7, #4] + 800aa28: f9b3 3008 ldrsh.w r3, [r3, #8] + 800aa2c: 4618 mov r0, r3 + 800aa2e: f7ff ffcf bl 800a9d0 + 800aa32: 4601 mov r1, r0 + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); + 800aa34: 687b ldr r3, [r7, #4] + 800aa36: 695b ldr r3, [r3, #20] + 800aa38: 687a ldr r2, [r7, #4] + 800aa3a: 6992 ldr r2, [r2, #24] + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800aa3c: 9202 str r2, [sp, #8] + 800aa3e: 9301 str r3, [sp, #4] + 800aa40: 9100 str r1, [sp, #0] + 800aa42: 683b ldr r3, [r7, #0] + 800aa44: 4632 mov r2, r6 + 800aa46: 4629 mov r1, r5 + 800aa48: 4620 mov r0, r4 + 800aa4a: f000 f8ed bl 800ac28 + 800aa4e: 4603 mov r3, r0 + 800aa50: 60fb str r3, [r7, #12] + 800aa52: e01c b.n 800aa8e + } + else { + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800aa54: 687b ldr r3, [r7, #4] + 800aa56: 685c ldr r4, [r3, #4] + 800aa58: 687b ldr r3, [r7, #4] + 800aa5a: 681d ldr r5, [r3, #0] + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + 800aa5c: 687b ldr r3, [r7, #4] + 800aa5e: 691b ldr r3, [r3, #16] + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + 800aa60: b29e uxth r6, r3 + 800aa62: 687b ldr r3, [r7, #4] + 800aa64: f9b3 3008 ldrsh.w r3, [r3, #8] + 800aa68: 4618 mov r0, r3 + 800aa6a: f7ff ffb1 bl 800a9d0 + 800aa6e: 4602 mov r2, r0 + 800aa70: f107 030c add.w r3, r7, #12 + 800aa74: 9301 str r3, [sp, #4] + 800aa76: 9200 str r2, [sp, #0] + 800aa78: 683b ldr r3, [r7, #0] + 800aa7a: 4632 mov r2, r6 + 800aa7c: 4629 mov r1, r5 + 800aa7e: 4620 mov r0, r4 + 800aa80: f000 f932 bl 800ace8 + 800aa84: 4603 mov r3, r0 + 800aa86: 2b01 cmp r3, #1 + 800aa88: d001 beq.n 800aa8e + &handle) != pdPASS) { + return NULL; + 800aa8a: 2300 movs r3, #0 + 800aa8c: e000 b.n 800aa90 + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; + 800aa8e: 68fb ldr r3, [r7, #12] +} + 800aa90: 4618 mov r0, r3 + 800aa92: 3714 adds r7, #20 + 800aa94: 46bd mov sp, r7 + 800aa96: bdf0 pop {r4, r5, r6, r7, pc} + +0800aa98 : +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ + 800aa98: b580 push {r7, lr} + 800aa9a: b084 sub sp, #16 + 800aa9c: af00 add r7, sp, #0 + 800aa9e: 6078 str r0, [r7, #4] +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + 800aaa0: 687b ldr r3, [r7, #4] + 800aaa2: 60fb str r3, [r7, #12] + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + 800aaa4: 68fb ldr r3, [r7, #12] + 800aaa6: 2b00 cmp r3, #0 + 800aaa8: d001 beq.n 800aaae + 800aaaa: 68fb ldr r3, [r7, #12] + 800aaac: e000 b.n 800aab0 + 800aaae: 2301 movs r3, #1 + 800aab0: 4618 mov r0, r3 + 800aab2: f000 fa5b bl 800af6c + + return osOK; + 800aab6: 2300 movs r3, #0 +#else + (void) millisec; + + return osErrorResource; +#endif +} + 800aab8: 4618 mov r0, r3 + 800aaba: 3710 adds r7, #16 + 800aabc: 46bd mov sp, r7 + 800aabe: bd80 pop {r7, pc} + +0800aac0 : +/*----------------------------------------------------------- + * PUBLIC LIST API documented in list.h + *----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + 800aac0: b480 push {r7} + 800aac2: b083 sub sp, #12 + 800aac4: af00 add r7, sp, #0 + 800aac6: 6078 str r0, [r7, #4] + /* The list structure contains a list item which is used to mark the + end of the list. To initialise the list the list end is inserted + as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800aac8: 687b ldr r3, [r7, #4] + 800aaca: f103 0208 add.w r2, r3, #8 + 800aace: 687b ldr r3, [r7, #4] + 800aad0: 605a str r2, [r3, #4] + + /* The list end value is the highest possible value in the list to + ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + 800aad2: 687b ldr r3, [r7, #4] + 800aad4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800aad8: 609a str r2, [r3, #8] + + /* The list end next and previous pointers point to itself so we know + when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800aada: 687b ldr r3, [r7, #4] + 800aadc: f103 0208 add.w r2, r3, #8 + 800aae0: 687b ldr r3, [r7, #4] + 800aae2: 60da str r2, [r3, #12] + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + 800aae4: 687b ldr r3, [r7, #4] + 800aae6: f103 0208 add.w r2, r3, #8 + 800aaea: 687b ldr r3, [r7, #4] + 800aaec: 611a str r2, [r3, #16] + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + 800aaee: 687b ldr r3, [r7, #4] + 800aaf0: 2200 movs r2, #0 + 800aaf2: 601a str r2, [r3, #0] + + /* Write known values into the list if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} + 800aaf4: bf00 nop + 800aaf6: 370c adds r7, #12 + 800aaf8: 46bd mov sp, r7 + 800aafa: f85d 7b04 ldr.w r7, [sp], #4 + 800aafe: 4770 bx lr + +0800ab00 : +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + 800ab00: b480 push {r7} + 800ab02: b083 sub sp, #12 + 800ab04: af00 add r7, sp, #0 + 800ab06: 6078 str r0, [r7, #4] + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + 800ab08: 687b ldr r3, [r7, #4] + 800ab0a: 2200 movs r2, #0 + 800ab0c: 611a str r2, [r3, #16] + + /* Write known values into the list item if + configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} + 800ab0e: bf00 nop + 800ab10: 370c adds r7, #12 + 800ab12: 46bd mov sp, r7 + 800ab14: f85d 7b04 ldr.w r7, [sp], #4 + 800ab18: 4770 bx lr + +0800ab1a : +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800ab1a: b480 push {r7} + 800ab1c: b085 sub sp, #20 + 800ab1e: af00 add r7, sp, #0 + 800ab20: 6078 str r0, [r7, #4] + 800ab22: 6039 str r1, [r7, #0] +ListItem_t * const pxIndex = pxList->pxIndex; + 800ab24: 687b ldr r3, [r7, #4] + 800ab26: 685b ldr r3, [r3, #4] + 800ab28: 60fb str r3, [r7, #12] + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + makes the new list item the last item to be removed by a call to + listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + 800ab2a: 683b ldr r3, [r7, #0] + 800ab2c: 68fa ldr r2, [r7, #12] + 800ab2e: 605a str r2, [r3, #4] + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + 800ab30: 68fb ldr r3, [r7, #12] + 800ab32: 689a ldr r2, [r3, #8] + 800ab34: 683b ldr r3, [r7, #0] + 800ab36: 609a str r2, [r3, #8] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + 800ab38: 68fb ldr r3, [r7, #12] + 800ab3a: 689b ldr r3, [r3, #8] + 800ab3c: 683a ldr r2, [r7, #0] + 800ab3e: 605a str r2, [r3, #4] + pxIndex->pxPrevious = pxNewListItem; + 800ab40: 68fb ldr r3, [r7, #12] + 800ab42: 683a ldr r2, [r7, #0] + 800ab44: 609a str r2, [r3, #8] + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + 800ab46: 683b ldr r3, [r7, #0] + 800ab48: 687a ldr r2, [r7, #4] + 800ab4a: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 800ab4c: 687b ldr r3, [r7, #4] + 800ab4e: 681b ldr r3, [r3, #0] + 800ab50: 1c5a adds r2, r3, #1 + 800ab52: 687b ldr r3, [r7, #4] + 800ab54: 601a str r2, [r3, #0] +} + 800ab56: bf00 nop + 800ab58: 3714 adds r7, #20 + 800ab5a: 46bd mov sp, r7 + 800ab5c: f85d 7b04 ldr.w r7, [sp], #4 + 800ab60: 4770 bx lr + +0800ab62 : +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) +{ + 800ab62: b480 push {r7} + 800ab64: b085 sub sp, #20 + 800ab66: af00 add r7, sp, #0 + 800ab68: 6078 str r0, [r7, #4] + 800ab6a: 6039 str r1, [r7, #0] +ListItem_t *pxIterator; +const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + 800ab6c: 683b ldr r3, [r7, #0] + 800ab6e: 681b ldr r3, [r3, #0] + 800ab70: 60bb str r3, [r7, #8] + new list item should be placed after it. This ensures that TCBs which are + stored in ready lists (all of which have the same xItemValue value) get a + share of the CPU. However, if the xItemValue is the same as the back marker + the iteration loop below will not end. Therefore the value is checked + first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + 800ab72: 68bb ldr r3, [r7, #8] + 800ab74: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800ab78: d103 bne.n 800ab82 + { + pxIterator = pxList->xListEnd.pxPrevious; + 800ab7a: 687b ldr r3, [r7, #4] + 800ab7c: 691b ldr r3, [r3, #16] + 800ab7e: 60fb str r3, [r7, #12] + 800ab80: e00c b.n 800ab9c + 4) Using a queue or semaphore before it has been initialised or + before the scheduler has been started (are interrupts firing + before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + 800ab82: 687b ldr r3, [r7, #4] + 800ab84: 3308 adds r3, #8 + 800ab86: 60fb str r3, [r7, #12] + 800ab88: e002 b.n 800ab90 + 800ab8a: 68fb ldr r3, [r7, #12] + 800ab8c: 685b ldr r3, [r3, #4] + 800ab8e: 60fb str r3, [r7, #12] + 800ab90: 68fb ldr r3, [r7, #12] + 800ab92: 685b ldr r3, [r3, #4] + 800ab94: 681b ldr r3, [r3, #0] + 800ab96: 68ba ldr r2, [r7, #8] + 800ab98: 429a cmp r2, r3 + 800ab9a: d2f6 bcs.n 800ab8a + /* There is nothing to do here, just iterating to the wanted + insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + 800ab9c: 68fb ldr r3, [r7, #12] + 800ab9e: 685a ldr r2, [r3, #4] + 800aba0: 683b ldr r3, [r7, #0] + 800aba2: 605a str r2, [r3, #4] + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + 800aba4: 683b ldr r3, [r7, #0] + 800aba6: 685b ldr r3, [r3, #4] + 800aba8: 683a ldr r2, [r7, #0] + 800abaa: 609a str r2, [r3, #8] + pxNewListItem->pxPrevious = pxIterator; + 800abac: 683b ldr r3, [r7, #0] + 800abae: 68fa ldr r2, [r7, #12] + 800abb0: 609a str r2, [r3, #8] + pxIterator->pxNext = pxNewListItem; + 800abb2: 68fb ldr r3, [r7, #12] + 800abb4: 683a ldr r2, [r7, #0] + 800abb6: 605a str r2, [r3, #4] + + /* Remember which list the item is in. This allows fast removal of the + item later. */ + pxNewListItem->pxContainer = pxList; + 800abb8: 683b ldr r3, [r7, #0] + 800abba: 687a ldr r2, [r7, #4] + 800abbc: 611a str r2, [r3, #16] + + ( pxList->uxNumberOfItems )++; + 800abbe: 687b ldr r3, [r7, #4] + 800abc0: 681b ldr r3, [r3, #0] + 800abc2: 1c5a adds r2, r3, #1 + 800abc4: 687b ldr r3, [r7, #4] + 800abc6: 601a str r2, [r3, #0] +} + 800abc8: bf00 nop + 800abca: 3714 adds r7, #20 + 800abcc: 46bd mov sp, r7 + 800abce: f85d 7b04 ldr.w r7, [sp], #4 + 800abd2: 4770 bx lr + +0800abd4 : +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ + 800abd4: b480 push {r7} + 800abd6: b085 sub sp, #20 + 800abd8: af00 add r7, sp, #0 + 800abda: 6078 str r0, [r7, #4] +/* The list item knows which list it is in. Obtain the list from the list +item. */ +List_t * const pxList = pxItemToRemove->pxContainer; + 800abdc: 687b ldr r3, [r7, #4] + 800abde: 691b ldr r3, [r3, #16] + 800abe0: 60fb str r3, [r7, #12] + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + 800abe2: 687b ldr r3, [r7, #4] + 800abe4: 685b ldr r3, [r3, #4] + 800abe6: 687a ldr r2, [r7, #4] + 800abe8: 6892 ldr r2, [r2, #8] + 800abea: 609a str r2, [r3, #8] + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + 800abec: 687b ldr r3, [r7, #4] + 800abee: 689b ldr r3, [r3, #8] + 800abf0: 687a ldr r2, [r7, #4] + 800abf2: 6852 ldr r2, [r2, #4] + 800abf4: 605a str r2, [r3, #4] + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + 800abf6: 68fb ldr r3, [r7, #12] + 800abf8: 685b ldr r3, [r3, #4] + 800abfa: 687a ldr r2, [r7, #4] + 800abfc: 429a cmp r2, r3 + 800abfe: d103 bne.n 800ac08 + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + 800ac00: 687b ldr r3, [r7, #4] + 800ac02: 689a ldr r2, [r3, #8] + 800ac04: 68fb ldr r3, [r7, #12] + 800ac06: 605a str r2, [r3, #4] + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + 800ac08: 687b ldr r3, [r7, #4] + 800ac0a: 2200 movs r2, #0 + 800ac0c: 611a str r2, [r3, #16] + ( pxList->uxNumberOfItems )--; + 800ac0e: 68fb ldr r3, [r7, #12] + 800ac10: 681b ldr r3, [r3, #0] + 800ac12: 1e5a subs r2, r3, #1 + 800ac14: 68fb ldr r3, [r7, #12] + 800ac16: 601a str r2, [r3, #0] + + return pxList->uxNumberOfItems; + 800ac18: 68fb ldr r3, [r7, #12] + 800ac1a: 681b ldr r3, [r3, #0] +} + 800ac1c: 4618 mov r0, r3 + 800ac1e: 3714 adds r7, #20 + 800ac20: 46bd mov sp, r7 + 800ac22: f85d 7b04 ldr.w r7, [sp], #4 + 800ac26: 4770 bx lr + +0800ac28 : + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) + { + 800ac28: b580 push {r7, lr} + 800ac2a: b08e sub sp, #56 ; 0x38 + 800ac2c: af04 add r7, sp, #16 + 800ac2e: 60f8 str r0, [r7, #12] + 800ac30: 60b9 str r1, [r7, #8] + 800ac32: 607a str r2, [r7, #4] + 800ac34: 603b str r3, [r7, #0] + TCB_t *pxNewTCB; + TaskHandle_t xReturn; + + configASSERT( puxStackBuffer != NULL ); + 800ac36: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ac38: 2b00 cmp r3, #0 + 800ac3a: d10b bne.n 800ac54 + +portFORCE_INLINE static void vPortRaiseBASEPRI( void ) +{ +uint32_t ulNewBASEPRI; + + __asm volatile + 800ac3c: f04f 0350 mov.w r3, #80 ; 0x50 + 800ac40: b672 cpsid i + 800ac42: f383 8811 msr BASEPRI, r3 + 800ac46: f3bf 8f6f isb sy + 800ac4a: f3bf 8f4f dsb sy + 800ac4e: b662 cpsie i + 800ac50: 623b str r3, [r7, #32] + 800ac52: e7fe b.n 800ac52 + configASSERT( pxTaskBuffer != NULL ); + 800ac54: 6bbb ldr r3, [r7, #56] ; 0x38 + 800ac56: 2b00 cmp r3, #0 + 800ac58: d10b bne.n 800ac72 + 800ac5a: f04f 0350 mov.w r3, #80 ; 0x50 + 800ac5e: b672 cpsid i + 800ac60: f383 8811 msr BASEPRI, r3 + 800ac64: f3bf 8f6f isb sy + 800ac68: f3bf 8f4f dsb sy + 800ac6c: b662 cpsie i + 800ac6e: 61fb str r3, [r7, #28] + 800ac70: e7fe b.n 800ac70 + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticTask_t equals the size of the real task + structure. */ + volatile size_t xSize = sizeof( StaticTask_t ); + 800ac72: 2358 movs r3, #88 ; 0x58 + 800ac74: 613b str r3, [r7, #16] + configASSERT( xSize == sizeof( TCB_t ) ); + 800ac76: 693b ldr r3, [r7, #16] + 800ac78: 2b58 cmp r3, #88 ; 0x58 + 800ac7a: d00b beq.n 800ac94 + 800ac7c: f04f 0350 mov.w r3, #80 ; 0x50 + 800ac80: b672 cpsid i + 800ac82: f383 8811 msr BASEPRI, r3 + 800ac86: f3bf 8f6f isb sy + 800ac8a: f3bf 8f4f dsb sy + 800ac8e: b662 cpsie i + 800ac90: 61bb str r3, [r7, #24] + 800ac92: e7fe b.n 800ac92 + ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ + 800ac94: 693b ldr r3, [r7, #16] + } + #endif /* configASSERT_DEFINED */ + + + if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) + 800ac96: 6bbb ldr r3, [r7, #56] ; 0x38 + 800ac98: 2b00 cmp r3, #0 + 800ac9a: d01e beq.n 800acda + 800ac9c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800ac9e: 2b00 cmp r3, #0 + 800aca0: d01b beq.n 800acda + { + /* The memory used for the task's TCB and stack are passed into this + function - use them. */ + pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + 800aca2: 6bbb ldr r3, [r7, #56] ; 0x38 + 800aca4: 627b str r3, [r7, #36] ; 0x24 + pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; + 800aca6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800aca8: 6b7a ldr r2, [r7, #52] ; 0x34 + 800acaa: 631a str r2, [r3, #48] ; 0x30 + + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + 800acac: 6a7b ldr r3, [r7, #36] ; 0x24 + 800acae: 2202 movs r2, #2 + 800acb0: f883 2055 strb.w r2, [r3, #85] ; 0x55 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); + 800acb4: 2300 movs r3, #0 + 800acb6: 9303 str r3, [sp, #12] + 800acb8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800acba: 9302 str r3, [sp, #8] + 800acbc: f107 0314 add.w r3, r7, #20 + 800acc0: 9301 str r3, [sp, #4] + 800acc2: 6b3b ldr r3, [r7, #48] ; 0x30 + 800acc4: 9300 str r3, [sp, #0] + 800acc6: 683b ldr r3, [r7, #0] + 800acc8: 687a ldr r2, [r7, #4] + 800acca: 68b9 ldr r1, [r7, #8] + 800accc: 68f8 ldr r0, [r7, #12] + 800acce: f000 f850 bl 800ad72 + prvAddNewTaskToReadyList( pxNewTCB ); + 800acd2: 6a78 ldr r0, [r7, #36] ; 0x24 + 800acd4: f000 f8e0 bl 800ae98 + 800acd8: e001 b.n 800acde + } + else + { + xReturn = NULL; + 800acda: 2300 movs r3, #0 + 800acdc: 617b str r3, [r7, #20] + } + + return xReturn; + 800acde: 697b ldr r3, [r7, #20] + } + 800ace0: 4618 mov r0, r3 + 800ace2: 3728 adds r7, #40 ; 0x28 + 800ace4: 46bd mov sp, r7 + 800ace6: bd80 pop {r7, pc} + +0800ace8 : + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) + { + 800ace8: b580 push {r7, lr} + 800acea: b08c sub sp, #48 ; 0x30 + 800acec: af04 add r7, sp, #16 + 800acee: 60f8 str r0, [r7, #12] + 800acf0: 60b9 str r1, [r7, #8] + 800acf2: 603b str r3, [r7, #0] + 800acf4: 4613 mov r3, r2 + 800acf6: 80fb strh r3, [r7, #6] + #else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + 800acf8: 88fb ldrh r3, [r7, #6] + 800acfa: 009b lsls r3, r3, #2 + 800acfc: 4618 mov r0, r3 + 800acfe: f000 fd45 bl 800b78c + 800ad02: 6178 str r0, [r7, #20] + + if( pxStack != NULL ) + 800ad04: 697b ldr r3, [r7, #20] + 800ad06: 2b00 cmp r3, #0 + 800ad08: d00e beq.n 800ad28 + { + /* Allocate space for the TCB. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + 800ad0a: 2058 movs r0, #88 ; 0x58 + 800ad0c: f000 fd3e bl 800b78c + 800ad10: 61f8 str r0, [r7, #28] + + if( pxNewTCB != NULL ) + 800ad12: 69fb ldr r3, [r7, #28] + 800ad14: 2b00 cmp r3, #0 + 800ad16: d003 beq.n 800ad20 + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + 800ad18: 69fb ldr r3, [r7, #28] + 800ad1a: 697a ldr r2, [r7, #20] + 800ad1c: 631a str r2, [r3, #48] ; 0x30 + 800ad1e: e005 b.n 800ad2c + } + else + { + /* The stack cannot be used as the TCB was not created. Free + it again. */ + vPortFree( pxStack ); + 800ad20: 6978 ldr r0, [r7, #20] + 800ad22: f000 fdff bl 800b924 + 800ad26: e001 b.n 800ad2c + } + } + else + { + pxNewTCB = NULL; + 800ad28: 2300 movs r3, #0 + 800ad2a: 61fb str r3, [r7, #28] + } + } + #endif /* portSTACK_GROWTH */ + + if( pxNewTCB != NULL ) + 800ad2c: 69fb ldr r3, [r7, #28] + 800ad2e: 2b00 cmp r3, #0 + 800ad30: d017 beq.n 800ad62 + { + #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + 800ad32: 69fb ldr r3, [r7, #28] + 800ad34: 2200 movs r2, #0 + 800ad36: f883 2055 strb.w r2, [r3, #85] ; 0x55 + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); + 800ad3a: 88fa ldrh r2, [r7, #6] + 800ad3c: 2300 movs r3, #0 + 800ad3e: 9303 str r3, [sp, #12] + 800ad40: 69fb ldr r3, [r7, #28] + 800ad42: 9302 str r3, [sp, #8] + 800ad44: 6afb ldr r3, [r7, #44] ; 0x2c + 800ad46: 9301 str r3, [sp, #4] + 800ad48: 6abb ldr r3, [r7, #40] ; 0x28 + 800ad4a: 9300 str r3, [sp, #0] + 800ad4c: 683b ldr r3, [r7, #0] + 800ad4e: 68b9 ldr r1, [r7, #8] + 800ad50: 68f8 ldr r0, [r7, #12] + 800ad52: f000 f80e bl 800ad72 + prvAddNewTaskToReadyList( pxNewTCB ); + 800ad56: 69f8 ldr r0, [r7, #28] + 800ad58: f000 f89e bl 800ae98 + xReturn = pdPASS; + 800ad5c: 2301 movs r3, #1 + 800ad5e: 61bb str r3, [r7, #24] + 800ad60: e002 b.n 800ad68 + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + 800ad62: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + 800ad66: 61bb str r3, [r7, #24] + } + + return xReturn; + 800ad68: 69bb ldr r3, [r7, #24] + } + 800ad6a: 4618 mov r0, r3 + 800ad6c: 3720 adds r7, #32 + 800ad6e: 46bd mov sp, r7 + 800ad70: bd80 pop {r7, pc} + +0800ad72 : + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t * const xRegions ) +{ + 800ad72: b580 push {r7, lr} + 800ad74: b088 sub sp, #32 + 800ad76: af00 add r7, sp, #0 + 800ad78: 60f8 str r0, [r7, #12] + 800ad7a: 60b9 str r1, [r7, #8] + 800ad7c: 607a str r2, [r7, #4] + 800ad7e: 603b str r3, [r7, #0] + + /* Avoid dependency on memset() if it is not required. */ + #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); + 800ad80: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ad82: 6b18 ldr r0, [r3, #48] ; 0x30 + 800ad84: 687b ldr r3, [r7, #4] + 800ad86: 009b lsls r3, r3, #2 + 800ad88: 461a mov r2, r3 + 800ad8a: 21a5 movs r1, #165 ; 0xa5 + 800ad8c: f000 ff17 bl 800bbbe + grows from high memory to low (as per the 80x86) or vice versa. + portSTACK_GROWTH is used to make the result positive or negative as required + by the port. */ + #if( portSTACK_GROWTH < 0 ) + { + pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); + 800ad90: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ad92: 6b1a ldr r2, [r3, #48] ; 0x30 + 800ad94: 6879 ldr r1, [r7, #4] + 800ad96: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000 + 800ad9a: 440b add r3, r1 + 800ad9c: 009b lsls r3, r3, #2 + 800ad9e: 4413 add r3, r2 + 800ada0: 61bb str r3, [r7, #24] + pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + 800ada2: 69bb ldr r3, [r7, #24] + 800ada4: f023 0307 bic.w r3, r3, #7 + 800ada8: 61bb str r3, [r7, #24] + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + 800adaa: 69bb ldr r3, [r7, #24] + 800adac: f003 0307 and.w r3, r3, #7 + 800adb0: 2b00 cmp r3, #0 + 800adb2: d00b beq.n 800adcc + 800adb4: f04f 0350 mov.w r3, #80 ; 0x50 + 800adb8: b672 cpsid i + 800adba: f383 8811 msr BASEPRI, r3 + 800adbe: f3bf 8f6f isb sy + 800adc2: f3bf 8f4f dsb sy + 800adc6: b662 cpsie i + 800adc8: 617b str r3, [r7, #20] + 800adca: e7fe b.n 800adca + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } + #endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if( pcName != NULL ) + 800adcc: 68bb ldr r3, [r7, #8] + 800adce: 2b00 cmp r3, #0 + 800add0: d01f beq.n 800ae12 + { + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 800add2: 2300 movs r3, #0 + 800add4: 61fb str r3, [r7, #28] + 800add6: e012 b.n 800adfe + { + pxNewTCB->pcTaskName[ x ] = pcName[ x ]; + 800add8: 68ba ldr r2, [r7, #8] + 800adda: 69fb ldr r3, [r7, #28] + 800addc: 4413 add r3, r2 + 800adde: 7819 ldrb r1, [r3, #0] + 800ade0: 6b3a ldr r2, [r7, #48] ; 0x30 + 800ade2: 69fb ldr r3, [r7, #28] + 800ade4: 4413 add r3, r2 + 800ade6: 3334 adds r3, #52 ; 0x34 + 800ade8: 460a mov r2, r1 + 800adea: 701a strb r2, [r3, #0] + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + configMAX_TASK_NAME_LEN characters just in case the memory after the + string is not accessible (extremely unlikely). */ + if( pcName[ x ] == ( char ) 0x00 ) + 800adec: 68ba ldr r2, [r7, #8] + 800adee: 69fb ldr r3, [r7, #28] + 800adf0: 4413 add r3, r2 + 800adf2: 781b ldrb r3, [r3, #0] + 800adf4: 2b00 cmp r3, #0 + 800adf6: d006 beq.n 800ae06 + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + 800adf8: 69fb ldr r3, [r7, #28] + 800adfa: 3301 adds r3, #1 + 800adfc: 61fb str r3, [r7, #28] + 800adfe: 69fb ldr r3, [r7, #28] + 800ae00: 2b0f cmp r3, #15 + 800ae02: d9e9 bls.n 800add8 + 800ae04: e000 b.n 800ae08 + { + break; + 800ae06: bf00 nop + } + } + + /* Ensure the name string is terminated in the case that the string length + was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; + 800ae08: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae0a: 2200 movs r2, #0 + 800ae0c: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 800ae10: e003 b.n 800ae1a + } + else + { + /* The task has not been given a name, so just ensure there is a NULL + terminator when it is read out. */ + pxNewTCB->pcTaskName[ 0 ] = 0x00; + 800ae12: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae14: 2200 movs r2, #0 + 800ae16: f883 2034 strb.w r2, [r3, #52] ; 0x34 + } + + /* This is used as an array index so must ensure it's not too large. First + remove the privilege bit if one is present. */ + if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) + 800ae1a: 6abb ldr r3, [r7, #40] ; 0x28 + 800ae1c: 2b06 cmp r3, #6 + 800ae1e: d901 bls.n 800ae24 + { + uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; + 800ae20: 2306 movs r3, #6 + 800ae22: 62bb str r3, [r7, #40] ; 0x28 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; + 800ae24: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae26: 6aba ldr r2, [r7, #40] ; 0x28 + 800ae28: 62da str r2, [r3, #44] ; 0x2c + #if ( configUSE_MUTEXES == 1 ) + { + pxNewTCB->uxBasePriority = uxPriority; + 800ae2a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae2c: 6aba ldr r2, [r7, #40] ; 0x28 + 800ae2e: 645a str r2, [r3, #68] ; 0x44 + pxNewTCB->uxMutexesHeld = 0; + 800ae30: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae32: 2200 movs r2, #0 + 800ae34: 649a str r2, [r3, #72] ; 0x48 + } + #endif /* configUSE_MUTEXES */ + + vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); + 800ae36: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae38: 3304 adds r3, #4 + 800ae3a: 4618 mov r0, r3 + 800ae3c: f7ff fe60 bl 800ab00 + vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); + 800ae40: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae42: 3318 adds r3, #24 + 800ae44: 4618 mov r0, r3 + 800ae46: f7ff fe5b bl 800ab00 + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); + 800ae4a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae4c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800ae4e: 611a str r2, [r3, #16] + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800ae50: 6abb ldr r3, [r7, #40] ; 0x28 + 800ae52: f1c3 0207 rsb r2, r3, #7 + 800ae56: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae58: 619a str r2, [r3, #24] + listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); + 800ae5a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae5c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800ae5e: 625a str r2, [r3, #36] ; 0x24 + } + #endif /* portCRITICAL_NESTING_IN_TCB */ + + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + { + pxNewTCB->pxTaskTag = NULL; + 800ae60: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae62: 2200 movs r2, #0 + 800ae64: 64da str r2, [r3, #76] ; 0x4c + } + #endif + + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + { + pxNewTCB->ulNotifiedValue = 0; + 800ae66: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae68: 2200 movs r2, #0 + 800ae6a: 651a str r2, [r3, #80] ; 0x50 + pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; + 800ae6c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae6e: 2200 movs r2, #0 + 800ae70: f883 2054 strb.w r2, [r3, #84] ; 0x54 + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); + 800ae74: 683a ldr r2, [r7, #0] + 800ae76: 68f9 ldr r1, [r7, #12] + 800ae78: 69b8 ldr r0, [r7, #24] + 800ae7a: f000 fb5b bl 800b534 + 800ae7e: 4602 mov r2, r0 + 800ae80: 6b3b ldr r3, [r7, #48] ; 0x30 + 800ae82: 601a str r2, [r3, #0] + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } + #endif /* portUSING_MPU_WRAPPERS */ + + if( pxCreatedTask != NULL ) + 800ae84: 6afb ldr r3, [r7, #44] ; 0x2c + 800ae86: 2b00 cmp r3, #0 + 800ae88: d002 beq.n 800ae90 + { + /* Pass the handle out in an anonymous way. The handle can be used to + change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; + 800ae8a: 6afb ldr r3, [r7, #44] ; 0x2c + 800ae8c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800ae8e: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800ae90: bf00 nop + 800ae92: 3720 adds r7, #32 + 800ae94: 46bd mov sp, r7 + 800ae96: bd80 pop {r7, pc} + +0800ae98 : +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) +{ + 800ae98: b580 push {r7, lr} + 800ae9a: b082 sub sp, #8 + 800ae9c: af00 add r7, sp, #0 + 800ae9e: 6078 str r0, [r7, #4] + /* Ensure interrupts don't access the task lists while the lists are being + updated. */ + taskENTER_CRITICAL(); + 800aea0: f000 fbc2 bl 800b628 + { + uxCurrentNumberOfTasks++; + 800aea4: 4b2a ldr r3, [pc, #168] ; (800af50 ) + 800aea6: 681b ldr r3, [r3, #0] + 800aea8: 3301 adds r3, #1 + 800aeaa: 4a29 ldr r2, [pc, #164] ; (800af50 ) + 800aeac: 6013 str r3, [r2, #0] + if( pxCurrentTCB == NULL ) + 800aeae: 4b29 ldr r3, [pc, #164] ; (800af54 ) + 800aeb0: 681b ldr r3, [r3, #0] + 800aeb2: 2b00 cmp r3, #0 + 800aeb4: d109 bne.n 800aeca + { + /* There are no other tasks, or all the other tasks are in + the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + 800aeb6: 4a27 ldr r2, [pc, #156] ; (800af54 ) + 800aeb8: 687b ldr r3, [r7, #4] + 800aeba: 6013 str r3, [r2, #0] + + if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) + 800aebc: 4b24 ldr r3, [pc, #144] ; (800af50 ) + 800aebe: 681b ldr r3, [r3, #0] + 800aec0: 2b01 cmp r3, #1 + 800aec2: d110 bne.n 800aee6 + { + /* This is the first task to be created so do the preliminary + initialisation required. We will not recover if this call + fails, but we will report the failure. */ + prvInitialiseTaskLists(); + 800aec4: f000 fa70 bl 800b3a8 + 800aec8: e00d b.n 800aee6 + else + { + /* If the scheduler is not already running, make this task the + current task if it is the highest priority task to be created + so far. */ + if( xSchedulerRunning == pdFALSE ) + 800aeca: 4b23 ldr r3, [pc, #140] ; (800af58 ) + 800aecc: 681b ldr r3, [r3, #0] + 800aece: 2b00 cmp r3, #0 + 800aed0: d109 bne.n 800aee6 + { + if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) + 800aed2: 4b20 ldr r3, [pc, #128] ; (800af54 ) + 800aed4: 681b ldr r3, [r3, #0] + 800aed6: 6ada ldr r2, [r3, #44] ; 0x2c + 800aed8: 687b ldr r3, [r7, #4] + 800aeda: 6adb ldr r3, [r3, #44] ; 0x2c + 800aedc: 429a cmp r2, r3 + 800aede: d802 bhi.n 800aee6 + { + pxCurrentTCB = pxNewTCB; + 800aee0: 4a1c ldr r2, [pc, #112] ; (800af54 ) + 800aee2: 687b ldr r3, [r7, #4] + 800aee4: 6013 str r3, [r2, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + 800aee6: 4b1d ldr r3, [pc, #116] ; (800af5c ) + 800aee8: 681b ldr r3, [r3, #0] + 800aeea: 3301 adds r3, #1 + 800aeec: 4a1b ldr r2, [pc, #108] ; (800af5c ) + 800aeee: 6013 str r3, [r2, #0] + pxNewTCB->uxTCBNumber = uxTaskNumber; + } + #endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE( pxNewTCB ); + + prvAddTaskToReadyList( pxNewTCB ); + 800aef0: 687b ldr r3, [r7, #4] + 800aef2: 6adb ldr r3, [r3, #44] ; 0x2c + 800aef4: 2201 movs r2, #1 + 800aef6: 409a lsls r2, r3 + 800aef8: 4b19 ldr r3, [pc, #100] ; (800af60 ) + 800aefa: 681b ldr r3, [r3, #0] + 800aefc: 4313 orrs r3, r2 + 800aefe: 4a18 ldr r2, [pc, #96] ; (800af60 ) + 800af00: 6013 str r3, [r2, #0] + 800af02: 687b ldr r3, [r7, #4] + 800af04: 6ada ldr r2, [r3, #44] ; 0x2c + 800af06: 4613 mov r3, r2 + 800af08: 009b lsls r3, r3, #2 + 800af0a: 4413 add r3, r2 + 800af0c: 009b lsls r3, r3, #2 + 800af0e: 4a15 ldr r2, [pc, #84] ; (800af64 ) + 800af10: 441a add r2, r3 + 800af12: 687b ldr r3, [r7, #4] + 800af14: 3304 adds r3, #4 + 800af16: 4619 mov r1, r3 + 800af18: 4610 mov r0, r2 + 800af1a: f7ff fdfe bl 800ab1a + + portSETUP_TCB( pxNewTCB ); + } + taskEXIT_CRITICAL(); + 800af1e: f000 fbb5 bl 800b68c + + if( xSchedulerRunning != pdFALSE ) + 800af22: 4b0d ldr r3, [pc, #52] ; (800af58 ) + 800af24: 681b ldr r3, [r3, #0] + 800af26: 2b00 cmp r3, #0 + 800af28: d00e beq.n 800af48 + { + /* If the created task is of a higher priority than the current task + then it should run now. */ + if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) + 800af2a: 4b0a ldr r3, [pc, #40] ; (800af54 ) + 800af2c: 681b ldr r3, [r3, #0] + 800af2e: 6ada ldr r2, [r3, #44] ; 0x2c + 800af30: 687b ldr r3, [r7, #4] + 800af32: 6adb ldr r3, [r3, #44] ; 0x2c + 800af34: 429a cmp r2, r3 + 800af36: d207 bcs.n 800af48 + { + taskYIELD_IF_USING_PREEMPTION(); + 800af38: 4b0b ldr r3, [pc, #44] ; (800af68 ) + 800af3a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800af3e: 601a str r2, [r3, #0] + 800af40: f3bf 8f4f dsb sy + 800af44: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800af48: bf00 nop + 800af4a: 3708 adds r7, #8 + 800af4c: 46bd mov sp, r7 + 800af4e: bd80 pop {r7, pc} + 800af50: 200003f0 .word 0x200003f0 + 800af54: 200002f4 .word 0x200002f4 + 800af58: 200003fc .word 0x200003fc + 800af5c: 2000040c .word 0x2000040c + 800af60: 200003f8 .word 0x200003f8 + 800af64: 200002f8 .word 0x200002f8 + 800af68: e000ed04 .word 0xe000ed04 + +0800af6c : +/*-----------------------------------------------------------*/ + +#if ( INCLUDE_vTaskDelay == 1 ) + + void vTaskDelay( const TickType_t xTicksToDelay ) + { + 800af6c: b580 push {r7, lr} + 800af6e: b084 sub sp, #16 + 800af70: af00 add r7, sp, #0 + 800af72: 6078 str r0, [r7, #4] + BaseType_t xAlreadyYielded = pdFALSE; + 800af74: 2300 movs r3, #0 + 800af76: 60fb str r3, [r7, #12] + + /* A delay time of zero just forces a reschedule. */ + if( xTicksToDelay > ( TickType_t ) 0U ) + 800af78: 687b ldr r3, [r7, #4] + 800af7a: 2b00 cmp r3, #0 + 800af7c: d018 beq.n 800afb0 + { + configASSERT( uxSchedulerSuspended == 0 ); + 800af7e: 4b14 ldr r3, [pc, #80] ; (800afd0 ) + 800af80: 681b ldr r3, [r3, #0] + 800af82: 2b00 cmp r3, #0 + 800af84: d00b beq.n 800af9e + 800af86: f04f 0350 mov.w r3, #80 ; 0x50 + 800af8a: b672 cpsid i + 800af8c: f383 8811 msr BASEPRI, r3 + 800af90: f3bf 8f6f isb sy + 800af94: f3bf 8f4f dsb sy + 800af98: b662 cpsie i + 800af9a: 60bb str r3, [r7, #8] + 800af9c: e7fe b.n 800af9c + vTaskSuspendAll(); + 800af9e: f000 f81b bl 800afd8 + list or removed from the blocked list until the scheduler + is resumed. + + This task cannot be in an event list as it is the currently + executing task. */ + prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); + 800afa2: 2100 movs r1, #0 + 800afa4: 6878 ldr r0, [r7, #4] + 800afa6: f000 fa5f bl 800b468 + } + xAlreadyYielded = xTaskResumeAll(); + 800afaa: f000 f823 bl 800aff4 + 800afae: 60f8 str r0, [r7, #12] + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + have put ourselves to sleep. */ + if( xAlreadyYielded == pdFALSE ) + 800afb0: 68fb ldr r3, [r7, #12] + 800afb2: 2b00 cmp r3, #0 + 800afb4: d107 bne.n 800afc6 + { + portYIELD_WITHIN_API(); + 800afb6: 4b07 ldr r3, [pc, #28] ; (800afd4 ) + 800afb8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800afbc: 601a str r2, [r3, #0] + 800afbe: f3bf 8f4f dsb sy + 800afc2: f3bf 8f6f isb sy + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + 800afc6: bf00 nop + 800afc8: 3710 adds r7, #16 + 800afca: 46bd mov sp, r7 + 800afcc: bd80 pop {r7, pc} + 800afce: bf00 nop + 800afd0: 20000414 .word 0x20000414 + 800afd4: e000ed04 .word 0xe000ed04 + +0800afd8 : + vPortEndScheduler(); +} +/*----------------------------------------------------------*/ + +void vTaskSuspendAll( void ) +{ + 800afd8: b480 push {r7} + 800afda: af00 add r7, sp, #0 + /* A critical section is not required as the variable is of type + BaseType_t. Please read Richard Barry's reply in the following link to a + post in the FreeRTOS support forum before reporting this as a bug! - + http://goo.gl/wu4acr */ + ++uxSchedulerSuspended; + 800afdc: 4b04 ldr r3, [pc, #16] ; (800aff0 ) + 800afde: 681b ldr r3, [r3, #0] + 800afe0: 3301 adds r3, #1 + 800afe2: 4a03 ldr r2, [pc, #12] ; (800aff0 ) + 800afe4: 6013 str r3, [r2, #0] + portMEMORY_BARRIER(); +} + 800afe6: bf00 nop + 800afe8: 46bd mov sp, r7 + 800afea: f85d 7b04 ldr.w r7, [sp], #4 + 800afee: 4770 bx lr + 800aff0: 20000414 .word 0x20000414 + +0800aff4 : + +#endif /* configUSE_TICKLESS_IDLE */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll( void ) +{ + 800aff4: b580 push {r7, lr} + 800aff6: b084 sub sp, #16 + 800aff8: af00 add r7, sp, #0 +TCB_t *pxTCB = NULL; + 800affa: 2300 movs r3, #0 + 800affc: 60fb str r3, [r7, #12] +BaseType_t xAlreadyYielded = pdFALSE; + 800affe: 2300 movs r3, #0 + 800b000: 60bb str r3, [r7, #8] + + /* If uxSchedulerSuspended is zero then this function does not match a + previous call to vTaskSuspendAll(). */ + configASSERT( uxSchedulerSuspended ); + 800b002: 4b42 ldr r3, [pc, #264] ; (800b10c ) + 800b004: 681b ldr r3, [r3, #0] + 800b006: 2b00 cmp r3, #0 + 800b008: d10b bne.n 800b022 + 800b00a: f04f 0350 mov.w r3, #80 ; 0x50 + 800b00e: b672 cpsid i + 800b010: f383 8811 msr BASEPRI, r3 + 800b014: f3bf 8f6f isb sy + 800b018: f3bf 8f4f dsb sy + 800b01c: b662 cpsie i + 800b01e: 603b str r3, [r7, #0] + 800b020: e7fe b.n 800b020 + /* It is possible that an ISR caused a task to be removed from an event + list while the scheduler was suspended. If this was the case then the + removed task will have been added to the xPendingReadyList. Once the + scheduler has been resumed it is safe to move all the pending ready + tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + 800b022: f000 fb01 bl 800b628 + { + --uxSchedulerSuspended; + 800b026: 4b39 ldr r3, [pc, #228] ; (800b10c ) + 800b028: 681b ldr r3, [r3, #0] + 800b02a: 3b01 subs r3, #1 + 800b02c: 4a37 ldr r2, [pc, #220] ; (800b10c ) + 800b02e: 6013 str r3, [r2, #0] + + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800b030: 4b36 ldr r3, [pc, #216] ; (800b10c ) + 800b032: 681b ldr r3, [r3, #0] + 800b034: 2b00 cmp r3, #0 + 800b036: d161 bne.n 800b0fc + { + if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) + 800b038: 4b35 ldr r3, [pc, #212] ; (800b110 ) + 800b03a: 681b ldr r3, [r3, #0] + 800b03c: 2b00 cmp r3, #0 + 800b03e: d05d beq.n 800b0fc + { + /* Move any readied tasks from the pending list into the + appropriate ready list. */ + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 800b040: e02e b.n 800b0a0 + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800b042: 4b34 ldr r3, [pc, #208] ; (800b114 ) + 800b044: 68db ldr r3, [r3, #12] + 800b046: 68db ldr r3, [r3, #12] + 800b048: 60fb str r3, [r7, #12] + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 800b04a: 68fb ldr r3, [r7, #12] + 800b04c: 3318 adds r3, #24 + 800b04e: 4618 mov r0, r3 + 800b050: f7ff fdc0 bl 800abd4 + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800b054: 68fb ldr r3, [r7, #12] + 800b056: 3304 adds r3, #4 + 800b058: 4618 mov r0, r3 + 800b05a: f7ff fdbb bl 800abd4 + prvAddTaskToReadyList( pxTCB ); + 800b05e: 68fb ldr r3, [r7, #12] + 800b060: 6adb ldr r3, [r3, #44] ; 0x2c + 800b062: 2201 movs r2, #1 + 800b064: 409a lsls r2, r3 + 800b066: 4b2c ldr r3, [pc, #176] ; (800b118 ) + 800b068: 681b ldr r3, [r3, #0] + 800b06a: 4313 orrs r3, r2 + 800b06c: 4a2a ldr r2, [pc, #168] ; (800b118 ) + 800b06e: 6013 str r3, [r2, #0] + 800b070: 68fb ldr r3, [r7, #12] + 800b072: 6ada ldr r2, [r3, #44] ; 0x2c + 800b074: 4613 mov r3, r2 + 800b076: 009b lsls r3, r3, #2 + 800b078: 4413 add r3, r2 + 800b07a: 009b lsls r3, r3, #2 + 800b07c: 4a27 ldr r2, [pc, #156] ; (800b11c ) + 800b07e: 441a add r2, r3 + 800b080: 68fb ldr r3, [r7, #12] + 800b082: 3304 adds r3, #4 + 800b084: 4619 mov r1, r3 + 800b086: 4610 mov r0, r2 + 800b088: f7ff fd47 bl 800ab1a + + /* If the moved task has a priority higher than the current + task then a yield must be performed. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800b08c: 68fb ldr r3, [r7, #12] + 800b08e: 6ada ldr r2, [r3, #44] ; 0x2c + 800b090: 4b23 ldr r3, [pc, #140] ; (800b120 ) + 800b092: 681b ldr r3, [r3, #0] + 800b094: 6adb ldr r3, [r3, #44] ; 0x2c + 800b096: 429a cmp r2, r3 + 800b098: d302 bcc.n 800b0a0 + { + xYieldPending = pdTRUE; + 800b09a: 4b22 ldr r3, [pc, #136] ; (800b124 ) + 800b09c: 2201 movs r2, #1 + 800b09e: 601a str r2, [r3, #0] + while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) + 800b0a0: 4b1c ldr r3, [pc, #112] ; (800b114 ) + 800b0a2: 681b ldr r3, [r3, #0] + 800b0a4: 2b00 cmp r3, #0 + 800b0a6: d1cc bne.n 800b042 + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( pxTCB != NULL ) + 800b0a8: 68fb ldr r3, [r7, #12] + 800b0aa: 2b00 cmp r3, #0 + 800b0ac: d001 beq.n 800b0b2 + which may have prevented the next unblock time from being + re-calculated, in which case re-calculate it now. Mainly + important for low power tickless implementations, where + this can prevent an unnecessary exit from low power + state. */ + prvResetNextTaskUnblockTime(); + 800b0ae: f000 f9bb bl 800b428 + /* If any ticks occurred while the scheduler was suspended then + they should be processed now. This ensures the tick count does + not slip, and that any delayed tasks are resumed at the correct + time. */ + { + UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */ + 800b0b2: 4b1d ldr r3, [pc, #116] ; (800b128 ) + 800b0b4: 681b ldr r3, [r3, #0] + 800b0b6: 607b str r3, [r7, #4] + + if( uxPendedCounts > ( UBaseType_t ) 0U ) + 800b0b8: 687b ldr r3, [r7, #4] + 800b0ba: 2b00 cmp r3, #0 + 800b0bc: d010 beq.n 800b0e0 + { + do + { + if( xTaskIncrementTick() != pdFALSE ) + 800b0be: f000 f837 bl 800b130 + 800b0c2: 4603 mov r3, r0 + 800b0c4: 2b00 cmp r3, #0 + 800b0c6: d002 beq.n 800b0ce + { + xYieldPending = pdTRUE; + 800b0c8: 4b16 ldr r3, [pc, #88] ; (800b124 ) + 800b0ca: 2201 movs r2, #1 + 800b0cc: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + --uxPendedCounts; + 800b0ce: 687b ldr r3, [r7, #4] + 800b0d0: 3b01 subs r3, #1 + 800b0d2: 607b str r3, [r7, #4] + } while( uxPendedCounts > ( UBaseType_t ) 0U ); + 800b0d4: 687b ldr r3, [r7, #4] + 800b0d6: 2b00 cmp r3, #0 + 800b0d8: d1f1 bne.n 800b0be + + uxPendedTicks = 0; + 800b0da: 4b13 ldr r3, [pc, #76] ; (800b128 ) + 800b0dc: 2200 movs r2, #0 + 800b0de: 601a str r2, [r3, #0] + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xYieldPending != pdFALSE ) + 800b0e0: 4b10 ldr r3, [pc, #64] ; (800b124 ) + 800b0e2: 681b ldr r3, [r3, #0] + 800b0e4: 2b00 cmp r3, #0 + 800b0e6: d009 beq.n 800b0fc + { + #if( configUSE_PREEMPTION != 0 ) + { + xAlreadyYielded = pdTRUE; + 800b0e8: 2301 movs r3, #1 + 800b0ea: 60bb str r3, [r7, #8] + } + #endif + taskYIELD_IF_USING_PREEMPTION(); + 800b0ec: 4b0f ldr r3, [pc, #60] ; (800b12c ) + 800b0ee: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b0f2: 601a str r2, [r3, #0] + 800b0f4: f3bf 8f4f dsb sy + 800b0f8: f3bf 8f6f isb sy + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + 800b0fc: f000 fac6 bl 800b68c + + return xAlreadyYielded; + 800b100: 68bb ldr r3, [r7, #8] +} + 800b102: 4618 mov r0, r3 + 800b104: 3710 adds r7, #16 + 800b106: 46bd mov sp, r7 + 800b108: bd80 pop {r7, pc} + 800b10a: bf00 nop + 800b10c: 20000414 .word 0x20000414 + 800b110: 200003f0 .word 0x200003f0 + 800b114: 200003b4 .word 0x200003b4 + 800b118: 200003f8 .word 0x200003f8 + 800b11c: 200002f8 .word 0x200002f8 + 800b120: 200002f4 .word 0x200002f4 + 800b124: 20000404 .word 0x20000404 + 800b128: 20000400 .word 0x20000400 + 800b12c: e000ed04 .word 0xe000ed04 + +0800b130 : + +#endif /* INCLUDE_xTaskAbortDelay */ +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick( void ) +{ + 800b130: b580 push {r7, lr} + 800b132: b086 sub sp, #24 + 800b134: af00 add r7, sp, #0 +TCB_t * pxTCB; +TickType_t xItemValue; +BaseType_t xSwitchRequired = pdFALSE; + 800b136: 2300 movs r3, #0 + 800b138: 617b str r3, [r7, #20] + + /* Called by the portable layer each time a tick interrupt occurs. + Increments the tick then checks to see if the new tick value will cause any + tasks to be unblocked. */ + traceTASK_INCREMENT_TICK( xTickCount ); + if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) + 800b13a: 4b4f ldr r3, [pc, #316] ; (800b278 ) + 800b13c: 681b ldr r3, [r3, #0] + 800b13e: 2b00 cmp r3, #0 + 800b140: f040 8089 bne.w 800b256 + { + /* Minor optimisation. The tick count cannot change in this + block. */ + const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; + 800b144: 4b4d ldr r3, [pc, #308] ; (800b27c ) + 800b146: 681b ldr r3, [r3, #0] + 800b148: 3301 adds r3, #1 + 800b14a: 613b str r3, [r7, #16] + + /* Increment the RTOS tick, switching the delayed and overflowed + delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + 800b14c: 4a4b ldr r2, [pc, #300] ; (800b27c ) + 800b14e: 693b ldr r3, [r7, #16] + 800b150: 6013 str r3, [r2, #0] + + if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + 800b152: 693b ldr r3, [r7, #16] + 800b154: 2b00 cmp r3, #0 + 800b156: d121 bne.n 800b19c + { + taskSWITCH_DELAYED_LISTS(); + 800b158: 4b49 ldr r3, [pc, #292] ; (800b280 ) + 800b15a: 681b ldr r3, [r3, #0] + 800b15c: 681b ldr r3, [r3, #0] + 800b15e: 2b00 cmp r3, #0 + 800b160: d00b beq.n 800b17a + 800b162: f04f 0350 mov.w r3, #80 ; 0x50 + 800b166: b672 cpsid i + 800b168: f383 8811 msr BASEPRI, r3 + 800b16c: f3bf 8f6f isb sy + 800b170: f3bf 8f4f dsb sy + 800b174: b662 cpsie i + 800b176: 603b str r3, [r7, #0] + 800b178: e7fe b.n 800b178 + 800b17a: 4b41 ldr r3, [pc, #260] ; (800b280 ) + 800b17c: 681b ldr r3, [r3, #0] + 800b17e: 60fb str r3, [r7, #12] + 800b180: 4b40 ldr r3, [pc, #256] ; (800b284 ) + 800b182: 681b ldr r3, [r3, #0] + 800b184: 4a3e ldr r2, [pc, #248] ; (800b280 ) + 800b186: 6013 str r3, [r2, #0] + 800b188: 4a3e ldr r2, [pc, #248] ; (800b284 ) + 800b18a: 68fb ldr r3, [r7, #12] + 800b18c: 6013 str r3, [r2, #0] + 800b18e: 4b3e ldr r3, [pc, #248] ; (800b288 ) + 800b190: 681b ldr r3, [r3, #0] + 800b192: 3301 adds r3, #1 + 800b194: 4a3c ldr r2, [pc, #240] ; (800b288 ) + 800b196: 6013 str r3, [r2, #0] + 800b198: f000 f946 bl 800b428 + + /* See if this tick has made a timeout expire. Tasks are stored in + the queue in the order of their wake time - meaning once one task + has been found whose block time has not expired there is no need to + look any further down the list. */ + if( xConstTickCount >= xNextTaskUnblockTime ) + 800b19c: 4b3b ldr r3, [pc, #236] ; (800b28c ) + 800b19e: 681b ldr r3, [r3, #0] + 800b1a0: 693a ldr r2, [r7, #16] + 800b1a2: 429a cmp r2, r3 + 800b1a4: d348 bcc.n 800b238 + { + for( ;; ) + { + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800b1a6: 4b36 ldr r3, [pc, #216] ; (800b280 ) + 800b1a8: 681b ldr r3, [r3, #0] + 800b1aa: 681b ldr r3, [r3, #0] + 800b1ac: 2b00 cmp r3, #0 + 800b1ae: d104 bne.n 800b1ba + /* The delayed list is empty. Set xNextTaskUnblockTime + to the maximum possible value so it is extremely + unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass + next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + 800b1b0: 4b36 ldr r3, [pc, #216] ; (800b28c ) + 800b1b2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800b1b6: 601a str r2, [r3, #0] + break; + 800b1b8: e03e b.n 800b238 + { + /* The delayed list is not empty, get the value of the + item at the head of the delayed list. This is the time + at which the task at the head of the delayed list must + be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800b1ba: 4b31 ldr r3, [pc, #196] ; (800b280 ) + 800b1bc: 681b ldr r3, [r3, #0] + 800b1be: 68db ldr r3, [r3, #12] + 800b1c0: 68db ldr r3, [r3, #12] + 800b1c2: 60bb str r3, [r7, #8] + xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); + 800b1c4: 68bb ldr r3, [r7, #8] + 800b1c6: 685b ldr r3, [r3, #4] + 800b1c8: 607b str r3, [r7, #4] + + if( xConstTickCount < xItemValue ) + 800b1ca: 693a ldr r2, [r7, #16] + 800b1cc: 687b ldr r3, [r7, #4] + 800b1ce: 429a cmp r2, r3 + 800b1d0: d203 bcs.n 800b1da + /* It is not time to unblock this item yet, but the + item value is the time at which the task at the head + of the blocked list must be removed from the Blocked + state - so record the item value in + xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + 800b1d2: 4a2e ldr r2, [pc, #184] ; (800b28c ) + 800b1d4: 687b ldr r3, [r7, #4] + 800b1d6: 6013 str r3, [r2, #0] + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + 800b1d8: e02e b.n 800b238 + { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + 800b1da: 68bb ldr r3, [r7, #8] + 800b1dc: 3304 adds r3, #4 + 800b1de: 4618 mov r0, r3 + 800b1e0: f7ff fcf8 bl 800abd4 + + /* Is the task waiting on an event also? If so remove + it from the event list. */ + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + 800b1e4: 68bb ldr r3, [r7, #8] + 800b1e6: 6a9b ldr r3, [r3, #40] ; 0x28 + 800b1e8: 2b00 cmp r3, #0 + 800b1ea: d004 beq.n 800b1f6 + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + 800b1ec: 68bb ldr r3, [r7, #8] + 800b1ee: 3318 adds r3, #24 + 800b1f0: 4618 mov r0, r3 + 800b1f2: f7ff fcef bl 800abd4 + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + list. */ + prvAddTaskToReadyList( pxTCB ); + 800b1f6: 68bb ldr r3, [r7, #8] + 800b1f8: 6adb ldr r3, [r3, #44] ; 0x2c + 800b1fa: 2201 movs r2, #1 + 800b1fc: 409a lsls r2, r3 + 800b1fe: 4b24 ldr r3, [pc, #144] ; (800b290 ) + 800b200: 681b ldr r3, [r3, #0] + 800b202: 4313 orrs r3, r2 + 800b204: 4a22 ldr r2, [pc, #136] ; (800b290 ) + 800b206: 6013 str r3, [r2, #0] + 800b208: 68bb ldr r3, [r7, #8] + 800b20a: 6ada ldr r2, [r3, #44] ; 0x2c + 800b20c: 4613 mov r3, r2 + 800b20e: 009b lsls r3, r3, #2 + 800b210: 4413 add r3, r2 + 800b212: 009b lsls r3, r3, #2 + 800b214: 4a1f ldr r2, [pc, #124] ; (800b294 ) + 800b216: 441a add r2, r3 + 800b218: 68bb ldr r3, [r7, #8] + 800b21a: 3304 adds r3, #4 + 800b21c: 4619 mov r1, r3 + 800b21e: 4610 mov r0, r2 + 800b220: f7ff fc7b bl 800ab1a + { + /* Preemption is on, but a context switch should + only be performed if the unblocked task has a + priority that is equal to or higher than the + currently executing task. */ + if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) + 800b224: 68bb ldr r3, [r7, #8] + 800b226: 6ada ldr r2, [r3, #44] ; 0x2c + 800b228: 4b1b ldr r3, [pc, #108] ; (800b298 ) + 800b22a: 681b ldr r3, [r3, #0] + 800b22c: 6adb ldr r3, [r3, #44] ; 0x2c + 800b22e: 429a cmp r2, r3 + 800b230: d3b9 bcc.n 800b1a6 + { + xSwitchRequired = pdTRUE; + 800b232: 2301 movs r3, #1 + 800b234: 617b str r3, [r7, #20] + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800b236: e7b6 b.n 800b1a6 + /* Tasks of equal priority to the currently running task will share + processing time (time slice) if preemption is on, and the application + writer has not explicitly turned time slicing off. */ + #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) + { + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) + 800b238: 4b17 ldr r3, [pc, #92] ; (800b298 ) + 800b23a: 681b ldr r3, [r3, #0] + 800b23c: 6ada ldr r2, [r3, #44] ; 0x2c + 800b23e: 4915 ldr r1, [pc, #84] ; (800b294 ) + 800b240: 4613 mov r3, r2 + 800b242: 009b lsls r3, r3, #2 + 800b244: 4413 add r3, r2 + 800b246: 009b lsls r3, r3, #2 + 800b248: 440b add r3, r1 + 800b24a: 681b ldr r3, [r3, #0] + 800b24c: 2b01 cmp r3, #1 + 800b24e: d907 bls.n 800b260 + { + xSwitchRequired = pdTRUE; + 800b250: 2301 movs r3, #1 + 800b252: 617b str r3, [r7, #20] + 800b254: e004 b.n 800b260 + } + #endif /* configUSE_TICK_HOOK */ + } + else + { + ++uxPendedTicks; + 800b256: 4b11 ldr r3, [pc, #68] ; (800b29c ) + 800b258: 681b ldr r3, [r3, #0] + 800b25a: 3301 adds r3, #1 + 800b25c: 4a0f ldr r2, [pc, #60] ; (800b29c ) + 800b25e: 6013 str r3, [r2, #0] + #endif + } + + #if ( configUSE_PREEMPTION == 1 ) + { + if( xYieldPending != pdFALSE ) + 800b260: 4b0f ldr r3, [pc, #60] ; (800b2a0 ) + 800b262: 681b ldr r3, [r3, #0] + 800b264: 2b00 cmp r3, #0 + 800b266: d001 beq.n 800b26c + { + xSwitchRequired = pdTRUE; + 800b268: 2301 movs r3, #1 + 800b26a: 617b str r3, [r7, #20] + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + + return xSwitchRequired; + 800b26c: 697b ldr r3, [r7, #20] +} + 800b26e: 4618 mov r0, r3 + 800b270: 3718 adds r7, #24 + 800b272: 46bd mov sp, r7 + 800b274: bd80 pop {r7, pc} + 800b276: bf00 nop + 800b278: 20000414 .word 0x20000414 + 800b27c: 200003f4 .word 0x200003f4 + 800b280: 200003ac .word 0x200003ac + 800b284: 200003b0 .word 0x200003b0 + 800b288: 20000408 .word 0x20000408 + 800b28c: 20000410 .word 0x20000410 + 800b290: 200003f8 .word 0x200003f8 + 800b294: 200002f8 .word 0x200002f8 + 800b298: 200002f4 .word 0x200002f4 + 800b29c: 20000400 .word 0x20000400 + 800b2a0: 20000404 .word 0x20000404 + +0800b2a4 : + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext( void ) +{ + 800b2a4: b580 push {r7, lr} + 800b2a6: b088 sub sp, #32 + 800b2a8: af00 add r7, sp, #0 + if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) + 800b2aa: 4b3a ldr r3, [pc, #232] ; (800b394 ) + 800b2ac: 681b ldr r3, [r3, #0] + 800b2ae: 2b00 cmp r3, #0 + 800b2b0: d003 beq.n 800b2ba + { + /* The scheduler is currently suspended - do not allow a context + switch. */ + xYieldPending = pdTRUE; + 800b2b2: 4b39 ldr r3, [pc, #228] ; (800b398 ) + 800b2b4: 2201 movs r2, #1 + 800b2b6: 601a str r2, [r3, #0] + structure specific to this task. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } + #endif /* configUSE_NEWLIB_REENTRANT */ + } +} + 800b2b8: e067 b.n 800b38a + xYieldPending = pdFALSE; + 800b2ba: 4b37 ldr r3, [pc, #220] ; (800b398 ) + 800b2bc: 2200 movs r2, #0 + 800b2be: 601a str r2, [r3, #0] + taskCHECK_FOR_STACK_OVERFLOW(); + 800b2c0: 4b36 ldr r3, [pc, #216] ; (800b39c ) + 800b2c2: 681b ldr r3, [r3, #0] + 800b2c4: 6b1b ldr r3, [r3, #48] ; 0x30 + 800b2c6: 61fb str r3, [r7, #28] + 800b2c8: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5 + 800b2cc: 61bb str r3, [r7, #24] + 800b2ce: 69fb ldr r3, [r7, #28] + 800b2d0: 681b ldr r3, [r3, #0] + 800b2d2: 69ba ldr r2, [r7, #24] + 800b2d4: 429a cmp r2, r3 + 800b2d6: d111 bne.n 800b2fc + 800b2d8: 69fb ldr r3, [r7, #28] + 800b2da: 3304 adds r3, #4 + 800b2dc: 681b ldr r3, [r3, #0] + 800b2de: 69ba ldr r2, [r7, #24] + 800b2e0: 429a cmp r2, r3 + 800b2e2: d10b bne.n 800b2fc + 800b2e4: 69fb ldr r3, [r7, #28] + 800b2e6: 3308 adds r3, #8 + 800b2e8: 681b ldr r3, [r3, #0] + 800b2ea: 69ba ldr r2, [r7, #24] + 800b2ec: 429a cmp r2, r3 + 800b2ee: d105 bne.n 800b2fc + 800b2f0: 69fb ldr r3, [r7, #28] + 800b2f2: 330c adds r3, #12 + 800b2f4: 681b ldr r3, [r3, #0] + 800b2f6: 69ba ldr r2, [r7, #24] + 800b2f8: 429a cmp r2, r3 + 800b2fa: d008 beq.n 800b30e + 800b2fc: 4b27 ldr r3, [pc, #156] ; (800b39c ) + 800b2fe: 681a ldr r2, [r3, #0] + 800b300: 4b26 ldr r3, [pc, #152] ; (800b39c ) + 800b302: 681b ldr r3, [r3, #0] + 800b304: 3334 adds r3, #52 ; 0x34 + 800b306: 4619 mov r1, r3 + 800b308: 4610 mov r0, r2 + 800b30a: f7f5 f951 bl 80005b0 + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800b30e: 4b24 ldr r3, [pc, #144] ; (800b3a0 ) + 800b310: 681b ldr r3, [r3, #0] + 800b312: 60fb str r3, [r7, #12] + __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); + 800b314: 68fb ldr r3, [r7, #12] + 800b316: fab3 f383 clz r3, r3 + 800b31a: 72fb strb r3, [r7, #11] + return ucReturn; + 800b31c: 7afb ldrb r3, [r7, #11] + 800b31e: f1c3 031f rsb r3, r3, #31 + 800b322: 617b str r3, [r7, #20] + 800b324: 491f ldr r1, [pc, #124] ; (800b3a4 ) + 800b326: 697a ldr r2, [r7, #20] + 800b328: 4613 mov r3, r2 + 800b32a: 009b lsls r3, r3, #2 + 800b32c: 4413 add r3, r2 + 800b32e: 009b lsls r3, r3, #2 + 800b330: 440b add r3, r1 + 800b332: 681b ldr r3, [r3, #0] + 800b334: 2b00 cmp r3, #0 + 800b336: d10b bne.n 800b350 + __asm volatile + 800b338: f04f 0350 mov.w r3, #80 ; 0x50 + 800b33c: b672 cpsid i + 800b33e: f383 8811 msr BASEPRI, r3 + 800b342: f3bf 8f6f isb sy + 800b346: f3bf 8f4f dsb sy + 800b34a: b662 cpsie i + 800b34c: 607b str r3, [r7, #4] + 800b34e: e7fe b.n 800b34e + 800b350: 697a ldr r2, [r7, #20] + 800b352: 4613 mov r3, r2 + 800b354: 009b lsls r3, r3, #2 + 800b356: 4413 add r3, r2 + 800b358: 009b lsls r3, r3, #2 + 800b35a: 4a12 ldr r2, [pc, #72] ; (800b3a4 ) + 800b35c: 4413 add r3, r2 + 800b35e: 613b str r3, [r7, #16] + 800b360: 693b ldr r3, [r7, #16] + 800b362: 685b ldr r3, [r3, #4] + 800b364: 685a ldr r2, [r3, #4] + 800b366: 693b ldr r3, [r7, #16] + 800b368: 605a str r2, [r3, #4] + 800b36a: 693b ldr r3, [r7, #16] + 800b36c: 685a ldr r2, [r3, #4] + 800b36e: 693b ldr r3, [r7, #16] + 800b370: 3308 adds r3, #8 + 800b372: 429a cmp r2, r3 + 800b374: d104 bne.n 800b380 + 800b376: 693b ldr r3, [r7, #16] + 800b378: 685b ldr r3, [r3, #4] + 800b37a: 685a ldr r2, [r3, #4] + 800b37c: 693b ldr r3, [r7, #16] + 800b37e: 605a str r2, [r3, #4] + 800b380: 693b ldr r3, [r7, #16] + 800b382: 685b ldr r3, [r3, #4] + 800b384: 68db ldr r3, [r3, #12] + 800b386: 4a05 ldr r2, [pc, #20] ; (800b39c ) + 800b388: 6013 str r3, [r2, #0] +} + 800b38a: bf00 nop + 800b38c: 3720 adds r7, #32 + 800b38e: 46bd mov sp, r7 + 800b390: bd80 pop {r7, pc} + 800b392: bf00 nop + 800b394: 20000414 .word 0x20000414 + 800b398: 20000404 .word 0x20000404 + 800b39c: 200002f4 .word 0x200002f4 + 800b3a0: 200003f8 .word 0x200003f8 + 800b3a4: 200002f8 .word 0x200002f8 + +0800b3a8 : + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists( void ) +{ + 800b3a8: b580 push {r7, lr} + 800b3aa: b082 sub sp, #8 + 800b3ac: af00 add r7, sp, #0 +UBaseType_t uxPriority; + + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 800b3ae: 2300 movs r3, #0 + 800b3b0: 607b str r3, [r7, #4] + 800b3b2: e00c b.n 800b3ce + { + vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); + 800b3b4: 687a ldr r2, [r7, #4] + 800b3b6: 4613 mov r3, r2 + 800b3b8: 009b lsls r3, r3, #2 + 800b3ba: 4413 add r3, r2 + 800b3bc: 009b lsls r3, r3, #2 + 800b3be: 4a12 ldr r2, [pc, #72] ; (800b408 ) + 800b3c0: 4413 add r3, r2 + 800b3c2: 4618 mov r0, r3 + 800b3c4: f7ff fb7c bl 800aac0 + for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) + 800b3c8: 687b ldr r3, [r7, #4] + 800b3ca: 3301 adds r3, #1 + 800b3cc: 607b str r3, [r7, #4] + 800b3ce: 687b ldr r3, [r7, #4] + 800b3d0: 2b06 cmp r3, #6 + 800b3d2: d9ef bls.n 800b3b4 + } + + vListInitialise( &xDelayedTaskList1 ); + 800b3d4: 480d ldr r0, [pc, #52] ; (800b40c ) + 800b3d6: f7ff fb73 bl 800aac0 + vListInitialise( &xDelayedTaskList2 ); + 800b3da: 480d ldr r0, [pc, #52] ; (800b410 ) + 800b3dc: f7ff fb70 bl 800aac0 + vListInitialise( &xPendingReadyList ); + 800b3e0: 480c ldr r0, [pc, #48] ; (800b414 ) + 800b3e2: f7ff fb6d bl 800aac0 + + #if ( INCLUDE_vTaskDelete == 1 ) + { + vListInitialise( &xTasksWaitingTermination ); + 800b3e6: 480c ldr r0, [pc, #48] ; (800b418 ) + 800b3e8: f7ff fb6a bl 800aac0 + } + #endif /* INCLUDE_vTaskDelete */ + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + vListInitialise( &xSuspendedTaskList ); + 800b3ec: 480b ldr r0, [pc, #44] ; (800b41c ) + 800b3ee: f7ff fb67 bl 800aac0 + } + #endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + 800b3f2: 4b0b ldr r3, [pc, #44] ; (800b420 ) + 800b3f4: 4a05 ldr r2, [pc, #20] ; (800b40c ) + 800b3f6: 601a str r2, [r3, #0] + pxOverflowDelayedTaskList = &xDelayedTaskList2; + 800b3f8: 4b0a ldr r3, [pc, #40] ; (800b424 ) + 800b3fa: 4a05 ldr r2, [pc, #20] ; (800b410 ) + 800b3fc: 601a str r2, [r3, #0] +} + 800b3fe: bf00 nop + 800b400: 3708 adds r7, #8 + 800b402: 46bd mov sp, r7 + 800b404: bd80 pop {r7, pc} + 800b406: bf00 nop + 800b408: 200002f8 .word 0x200002f8 + 800b40c: 20000384 .word 0x20000384 + 800b410: 20000398 .word 0x20000398 + 800b414: 200003b4 .word 0x200003b4 + 800b418: 200003c8 .word 0x200003c8 + 800b41c: 200003dc .word 0x200003dc + 800b420: 200003ac .word 0x200003ac + 800b424: 200003b0 .word 0x200003b0 + +0800b428 : + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime( void ) +{ + 800b428: b480 push {r7} + 800b42a: b083 sub sp, #12 + 800b42c: af00 add r7, sp, #0 +TCB_t *pxTCB; + + if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) + 800b42e: 4b0c ldr r3, [pc, #48] ; (800b460 ) + 800b430: 681b ldr r3, [r3, #0] + 800b432: 681b ldr r3, [r3, #0] + 800b434: 2b00 cmp r3, #0 + 800b436: d104 bne.n 800b442 + { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + the maximum possible value so it is extremely unlikely that the + if( xTickCount >= xNextTaskUnblockTime ) test will pass until + there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + 800b438: 4b0a ldr r3, [pc, #40] ; (800b464 ) + 800b43a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800b43e: 601a str r2, [r3, #0] + which the task at the head of the delayed list should be removed + from the Blocked state. */ + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + } +} + 800b440: e008 b.n 800b454 + ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + 800b442: 4b07 ldr r3, [pc, #28] ; (800b460 ) + 800b444: 681b ldr r3, [r3, #0] + 800b446: 68db ldr r3, [r3, #12] + 800b448: 68db ldr r3, [r3, #12] + 800b44a: 607b str r3, [r7, #4] + xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); + 800b44c: 687b ldr r3, [r7, #4] + 800b44e: 685b ldr r3, [r3, #4] + 800b450: 4a04 ldr r2, [pc, #16] ; (800b464 ) + 800b452: 6013 str r3, [r2, #0] +} + 800b454: bf00 nop + 800b456: 370c adds r7, #12 + 800b458: 46bd mov sp, r7 + 800b45a: f85d 7b04 ldr.w r7, [sp], #4 + 800b45e: 4770 bx lr + 800b460: 200003ac .word 0x200003ac + 800b464: 20000410 .word 0x20000410 + +0800b468 : + } +#endif +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) +{ + 800b468: b580 push {r7, lr} + 800b46a: b084 sub sp, #16 + 800b46c: af00 add r7, sp, #0 + 800b46e: 6078 str r0, [r7, #4] + 800b470: 6039 str r1, [r7, #0] +TickType_t xTimeToWake; +const TickType_t xConstTickCount = xTickCount; + 800b472: 4b29 ldr r3, [pc, #164] ; (800b518 ) + 800b474: 681b ldr r3, [r3, #0] + 800b476: 60fb str r3, [r7, #12] + } + #endif + + /* Remove the task from the ready list before adding it to the blocked list + as the same list item is used for both lists. */ + if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) + 800b478: 4b28 ldr r3, [pc, #160] ; (800b51c ) + 800b47a: 681b ldr r3, [r3, #0] + 800b47c: 3304 adds r3, #4 + 800b47e: 4618 mov r0, r3 + 800b480: f7ff fba8 bl 800abd4 + 800b484: 4603 mov r3, r0 + 800b486: 2b00 cmp r3, #0 + 800b488: d10b bne.n 800b4a2 + { + /* The current task must be in a ready list, so there is no need to + check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + 800b48a: 4b24 ldr r3, [pc, #144] ; (800b51c ) + 800b48c: 681b ldr r3, [r3, #0] + 800b48e: 6adb ldr r3, [r3, #44] ; 0x2c + 800b490: 2201 movs r2, #1 + 800b492: fa02 f303 lsl.w r3, r2, r3 + 800b496: 43da mvns r2, r3 + 800b498: 4b21 ldr r3, [pc, #132] ; (800b520 ) + 800b49a: 681b ldr r3, [r3, #0] + 800b49c: 4013 ands r3, r2 + 800b49e: 4a20 ldr r2, [pc, #128] ; (800b520 ) + 800b4a0: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) + 800b4a2: 687b ldr r3, [r7, #4] + 800b4a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b4a8: d10a bne.n 800b4c0 + 800b4aa: 683b ldr r3, [r7, #0] + 800b4ac: 2b00 cmp r3, #0 + 800b4ae: d007 beq.n 800b4c0 + { + /* Add the task to the suspended task list instead of a delayed task + list to ensure it is not woken by a timing event. It will block + indefinitely. */ + vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800b4b0: 4b1a ldr r3, [pc, #104] ; (800b51c ) + 800b4b2: 681b ldr r3, [r3, #0] + 800b4b4: 3304 adds r3, #4 + 800b4b6: 4619 mov r1, r3 + 800b4b8: 481a ldr r0, [pc, #104] ; (800b524 ) + 800b4ba: f7ff fb2e bl 800ab1a + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } + #endif /* INCLUDE_vTaskSuspend */ +} + 800b4be: e026 b.n 800b50e + xTimeToWake = xConstTickCount + xTicksToWait; + 800b4c0: 68fa ldr r2, [r7, #12] + 800b4c2: 687b ldr r3, [r7, #4] + 800b4c4: 4413 add r3, r2 + 800b4c6: 60bb str r3, [r7, #8] + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + 800b4c8: 4b14 ldr r3, [pc, #80] ; (800b51c ) + 800b4ca: 681b ldr r3, [r3, #0] + 800b4cc: 68ba ldr r2, [r7, #8] + 800b4ce: 605a str r2, [r3, #4] + if( xTimeToWake < xConstTickCount ) + 800b4d0: 68ba ldr r2, [r7, #8] + 800b4d2: 68fb ldr r3, [r7, #12] + 800b4d4: 429a cmp r2, r3 + 800b4d6: d209 bcs.n 800b4ec + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800b4d8: 4b13 ldr r3, [pc, #76] ; (800b528 ) + 800b4da: 681a ldr r2, [r3, #0] + 800b4dc: 4b0f ldr r3, [pc, #60] ; (800b51c ) + 800b4de: 681b ldr r3, [r3, #0] + 800b4e0: 3304 adds r3, #4 + 800b4e2: 4619 mov r1, r3 + 800b4e4: 4610 mov r0, r2 + 800b4e6: f7ff fb3c bl 800ab62 +} + 800b4ea: e010 b.n 800b50e + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + 800b4ec: 4b0f ldr r3, [pc, #60] ; (800b52c ) + 800b4ee: 681a ldr r2, [r3, #0] + 800b4f0: 4b0a ldr r3, [pc, #40] ; (800b51c ) + 800b4f2: 681b ldr r3, [r3, #0] + 800b4f4: 3304 adds r3, #4 + 800b4f6: 4619 mov r1, r3 + 800b4f8: 4610 mov r0, r2 + 800b4fa: f7ff fb32 bl 800ab62 + if( xTimeToWake < xNextTaskUnblockTime ) + 800b4fe: 4b0c ldr r3, [pc, #48] ; (800b530 ) + 800b500: 681b ldr r3, [r3, #0] + 800b502: 68ba ldr r2, [r7, #8] + 800b504: 429a cmp r2, r3 + 800b506: d202 bcs.n 800b50e + xNextTaskUnblockTime = xTimeToWake; + 800b508: 4a09 ldr r2, [pc, #36] ; (800b530 ) + 800b50a: 68bb ldr r3, [r7, #8] + 800b50c: 6013 str r3, [r2, #0] +} + 800b50e: bf00 nop + 800b510: 3710 adds r7, #16 + 800b512: 46bd mov sp, r7 + 800b514: bd80 pop {r7, pc} + 800b516: bf00 nop + 800b518: 200003f4 .word 0x200003f4 + 800b51c: 200002f4 .word 0x200002f4 + 800b520: 200003f8 .word 0x200003f8 + 800b524: 200003dc .word 0x200003dc + 800b528: 200003b0 .word 0x200003b0 + 800b52c: 200003ac .word 0x200003ac + 800b530: 20000410 .word 0x20000410 + +0800b534 : + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + 800b534: b480 push {r7} + 800b536: b085 sub sp, #20 + 800b538: af00 add r7, sp, #0 + 800b53a: 60f8 str r0, [r7, #12] + 800b53c: 60b9 str r1, [r7, #8] + 800b53e: 607a str r2, [r7, #4] + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + 800b540: 68fb ldr r3, [r7, #12] + 800b542: 3b04 subs r3, #4 + 800b544: 60fb str r3, [r7, #12] + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + 800b546: 68fb ldr r3, [r7, #12] + 800b548: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 800b54c: 601a str r2, [r3, #0] + pxTopOfStack--; + 800b54e: 68fb ldr r3, [r7, #12] + 800b550: 3b04 subs r3, #4 + 800b552: 60fb str r3, [r7, #12] + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + 800b554: 68bb ldr r3, [r7, #8] + 800b556: f023 0201 bic.w r2, r3, #1 + 800b55a: 68fb ldr r3, [r7, #12] + 800b55c: 601a str r2, [r3, #0] + pxTopOfStack--; + 800b55e: 68fb ldr r3, [r7, #12] + 800b560: 3b04 subs r3, #4 + 800b562: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + 800b564: 4a0c ldr r2, [pc, #48] ; (800b598 ) + 800b566: 68fb ldr r3, [r7, #12] + 800b568: 601a str r2, [r3, #0] + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + 800b56a: 68fb ldr r3, [r7, #12] + 800b56c: 3b14 subs r3, #20 + 800b56e: 60fb str r3, [r7, #12] + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + 800b570: 687a ldr r2, [r7, #4] + 800b572: 68fb ldr r3, [r7, #12] + 800b574: 601a str r2, [r3, #0] + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + 800b576: 68fb ldr r3, [r7, #12] + 800b578: 3b04 subs r3, #4 + 800b57a: 60fb str r3, [r7, #12] + *pxTopOfStack = portINITIAL_EXC_RETURN; + 800b57c: 68fb ldr r3, [r7, #12] + 800b57e: f06f 0202 mvn.w r2, #2 + 800b582: 601a str r2, [r3, #0] + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + 800b584: 68fb ldr r3, [r7, #12] + 800b586: 3b20 subs r3, #32 + 800b588: 60fb str r3, [r7, #12] + + return pxTopOfStack; + 800b58a: 68fb ldr r3, [r7, #12] +} + 800b58c: 4618 mov r0, r3 + 800b58e: 3714 adds r7, #20 + 800b590: 46bd mov sp, r7 + 800b592: f85d 7b04 ldr.w r7, [sp], #4 + 800b596: 4770 bx lr + 800b598: 0800b59d .word 0x0800b59d + +0800b59c : +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + 800b59c: b480 push {r7} + 800b59e: b085 sub sp, #20 + 800b5a0: af00 add r7, sp, #0 +volatile uint32_t ulDummy = 0; + 800b5a2: 2300 movs r3, #0 + 800b5a4: 607b str r3, [r7, #4] + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + 800b5a6: 4b13 ldr r3, [pc, #76] ; (800b5f4 ) + 800b5a8: 681b ldr r3, [r3, #0] + 800b5aa: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800b5ae: d00b beq.n 800b5c8 + 800b5b0: f04f 0350 mov.w r3, #80 ; 0x50 + 800b5b4: b672 cpsid i + 800b5b6: f383 8811 msr BASEPRI, r3 + 800b5ba: f3bf 8f6f isb sy + 800b5be: f3bf 8f4f dsb sy + 800b5c2: b662 cpsie i + 800b5c4: 60fb str r3, [r7, #12] + 800b5c6: e7fe b.n 800b5c6 + 800b5c8: f04f 0350 mov.w r3, #80 ; 0x50 + 800b5cc: b672 cpsid i + 800b5ce: f383 8811 msr BASEPRI, r3 + 800b5d2: f3bf 8f6f isb sy + 800b5d6: f3bf 8f4f dsb sy + 800b5da: b662 cpsie i + 800b5dc: 60bb str r3, [r7, #8] + portDISABLE_INTERRUPTS(); + while( ulDummy == 0 ) + 800b5de: bf00 nop + 800b5e0: 687b ldr r3, [r7, #4] + 800b5e2: 2b00 cmp r3, #0 + 800b5e4: d0fc beq.n 800b5e0 + about code appearing after this function is called - making ulDummy + volatile makes the compiler think the function could return and + therefore not output an 'unreachable code' warning for code that appears + after it. */ + } +} + 800b5e6: bf00 nop + 800b5e8: 3714 adds r7, #20 + 800b5ea: 46bd mov sp, r7 + 800b5ec: f85d 7b04 ldr.w r7, [sp], #4 + 800b5f0: 4770 bx lr + 800b5f2: bf00 nop + 800b5f4: 20000048 .word 0x20000048 + ... + +0800b600 : +/*-----------------------------------------------------------*/ + +void vPortSVCHandler( void ) +{ + __asm volatile ( + 800b600: 4b07 ldr r3, [pc, #28] ; (800b620 ) + 800b602: 6819 ldr r1, [r3, #0] + 800b604: 6808 ldr r0, [r1, #0] + 800b606: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b60a: f380 8809 msr PSP, r0 + 800b60e: f3bf 8f6f isb sy + 800b612: f04f 0000 mov.w r0, #0 + 800b616: f380 8811 msr BASEPRI, r0 + 800b61a: 4770 bx lr + 800b61c: f3af 8000 nop.w + +0800b620 : + 800b620: 200002f4 .word 0x200002f4 + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} + 800b624: bf00 nop + 800b626: bf00 nop + +0800b628 : + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + 800b628: b480 push {r7} + 800b62a: b083 sub sp, #12 + 800b62c: af00 add r7, sp, #0 + 800b62e: f04f 0350 mov.w r3, #80 ; 0x50 + 800b632: b672 cpsid i + 800b634: f383 8811 msr BASEPRI, r3 + 800b638: f3bf 8f6f isb sy + 800b63c: f3bf 8f4f dsb sy + 800b640: b662 cpsie i + 800b642: 607b str r3, [r7, #4] + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + 800b644: 4b0f ldr r3, [pc, #60] ; (800b684 ) + 800b646: 681b ldr r3, [r3, #0] + 800b648: 3301 adds r3, #1 + 800b64a: 4a0e ldr r2, [pc, #56] ; (800b684 ) + 800b64c: 6013 str r3, [r2, #0] + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + 800b64e: 4b0d ldr r3, [pc, #52] ; (800b684 ) + 800b650: 681b ldr r3, [r3, #0] + 800b652: 2b01 cmp r3, #1 + 800b654: d110 bne.n 800b678 + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + 800b656: 4b0c ldr r3, [pc, #48] ; (800b688 ) + 800b658: 681b ldr r3, [r3, #0] + 800b65a: b2db uxtb r3, r3 + 800b65c: 2b00 cmp r3, #0 + 800b65e: d00b beq.n 800b678 + 800b660: f04f 0350 mov.w r3, #80 ; 0x50 + 800b664: b672 cpsid i + 800b666: f383 8811 msr BASEPRI, r3 + 800b66a: f3bf 8f6f isb sy + 800b66e: f3bf 8f4f dsb sy + 800b672: b662 cpsie i + 800b674: 603b str r3, [r7, #0] + 800b676: e7fe b.n 800b676 + } +} + 800b678: bf00 nop + 800b67a: 370c adds r7, #12 + 800b67c: 46bd mov sp, r7 + 800b67e: f85d 7b04 ldr.w r7, [sp], #4 + 800b682: 4770 bx lr + 800b684: 20000048 .word 0x20000048 + 800b688: e000ed04 .word 0xe000ed04 + +0800b68c : +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + 800b68c: b480 push {r7} + 800b68e: b083 sub sp, #12 + 800b690: af00 add r7, sp, #0 + configASSERT( uxCriticalNesting ); + 800b692: 4b12 ldr r3, [pc, #72] ; (800b6dc ) + 800b694: 681b ldr r3, [r3, #0] + 800b696: 2b00 cmp r3, #0 + 800b698: d10b bne.n 800b6b2 + 800b69a: f04f 0350 mov.w r3, #80 ; 0x50 + 800b69e: b672 cpsid i + 800b6a0: f383 8811 msr BASEPRI, r3 + 800b6a4: f3bf 8f6f isb sy + 800b6a8: f3bf 8f4f dsb sy + 800b6ac: b662 cpsie i + 800b6ae: 607b str r3, [r7, #4] + 800b6b0: e7fe b.n 800b6b0 + uxCriticalNesting--; + 800b6b2: 4b0a ldr r3, [pc, #40] ; (800b6dc ) + 800b6b4: 681b ldr r3, [r3, #0] + 800b6b6: 3b01 subs r3, #1 + 800b6b8: 4a08 ldr r2, [pc, #32] ; (800b6dc ) + 800b6ba: 6013 str r3, [r2, #0] + if( uxCriticalNesting == 0 ) + 800b6bc: 4b07 ldr r3, [pc, #28] ; (800b6dc ) + 800b6be: 681b ldr r3, [r3, #0] + 800b6c0: 2b00 cmp r3, #0 + 800b6c2: d104 bne.n 800b6ce + 800b6c4: 2300 movs r3, #0 + 800b6c6: 603b str r3, [r7, #0] +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) +{ + __asm volatile + 800b6c8: 683b ldr r3, [r7, #0] + 800b6ca: f383 8811 msr BASEPRI, r3 + { + portENABLE_INTERRUPTS(); + } +} + 800b6ce: bf00 nop + 800b6d0: 370c adds r7, #12 + 800b6d2: 46bd mov sp, r7 + 800b6d4: f85d 7b04 ldr.w r7, [sp], #4 + 800b6d8: 4770 bx lr + 800b6da: bf00 nop + 800b6dc: 20000048 .word 0x20000048 + +0800b6e0 : + +void xPortPendSVHandler( void ) +{ + /* This is a naked function. */ + + __asm volatile + 800b6e0: f3ef 8009 mrs r0, PSP + 800b6e4: f3bf 8f6f isb sy + 800b6e8: 4b15 ldr r3, [pc, #84] ; (800b740 ) + 800b6ea: 681a ldr r2, [r3, #0] + 800b6ec: f01e 0f10 tst.w lr, #16 + 800b6f0: bf08 it eq + 800b6f2: ed20 8a10 vstmdbeq r0!, {s16-s31} + 800b6f6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b6fa: 6010 str r0, [r2, #0] + 800b6fc: e92d 0009 stmdb sp!, {r0, r3} + 800b700: f04f 0050 mov.w r0, #80 ; 0x50 + 800b704: b672 cpsid i + 800b706: f380 8811 msr BASEPRI, r0 + 800b70a: f3bf 8f4f dsb sy + 800b70e: f3bf 8f6f isb sy + 800b712: b662 cpsie i + 800b714: f7ff fdc6 bl 800b2a4 + 800b718: f04f 0000 mov.w r0, #0 + 800b71c: f380 8811 msr BASEPRI, r0 + 800b720: bc09 pop {r0, r3} + 800b722: 6819 ldr r1, [r3, #0] + 800b724: 6808 ldr r0, [r1, #0] + 800b726: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800b72a: f01e 0f10 tst.w lr, #16 + 800b72e: bf08 it eq + 800b730: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 800b734: f380 8809 msr PSP, r0 + 800b738: f3bf 8f6f isb sy + 800b73c: 4770 bx lr + 800b73e: bf00 nop + +0800b740 : + 800b740: 200002f4 .word 0x200002f4 + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} + 800b744: bf00 nop + 800b746: bf00 nop + +0800b748 : +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + 800b748: b580 push {r7, lr} + 800b74a: b082 sub sp, #8 + 800b74c: af00 add r7, sp, #0 + __asm volatile + 800b74e: f04f 0350 mov.w r3, #80 ; 0x50 + 800b752: b672 cpsid i + 800b754: f383 8811 msr BASEPRI, r3 + 800b758: f3bf 8f6f isb sy + 800b75c: f3bf 8f4f dsb sy + 800b760: b662 cpsie i + 800b762: 607b str r3, [r7, #4] + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + 800b764: f7ff fce4 bl 800b130 + 800b768: 4603 mov r3, r0 + 800b76a: 2b00 cmp r3, #0 + 800b76c: d003 beq.n 800b776 + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + 800b76e: 4b06 ldr r3, [pc, #24] ; (800b788 ) + 800b770: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 800b774: 601a str r2, [r3, #0] + 800b776: 2300 movs r3, #0 + 800b778: 603b str r3, [r7, #0] + __asm volatile + 800b77a: 683b ldr r3, [r7, #0] + 800b77c: f383 8811 msr BASEPRI, r3 + } + } + portENABLE_INTERRUPTS(); +} + 800b780: bf00 nop + 800b782: 3708 adds r7, #8 + 800b784: 46bd mov sp, r7 + 800b786: bd80 pop {r7, pc} + 800b788: e000ed04 .word 0xe000ed04 + +0800b78c : +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ + 800b78c: b580 push {r7, lr} + 800b78e: b08a sub sp, #40 ; 0x28 + 800b790: af00 add r7, sp, #0 + 800b792: 6078 str r0, [r7, #4] +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + 800b794: 2300 movs r3, #0 + 800b796: 61fb str r3, [r7, #28] + + vTaskSuspendAll(); + 800b798: f7ff fc1e bl 800afd8 + { + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + 800b79c: 4b5c ldr r3, [pc, #368] ; (800b910 ) + 800b79e: 681b ldr r3, [r3, #0] + 800b7a0: 2b00 cmp r3, #0 + 800b7a2: d101 bne.n 800b7a8 + { + prvHeapInit(); + 800b7a4: f000 f91a bl 800b9dc + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + 800b7a8: 4b5a ldr r3, [pc, #360] ; (800b914 ) + 800b7aa: 681a ldr r2, [r3, #0] + 800b7ac: 687b ldr r3, [r7, #4] + 800b7ae: 4013 ands r3, r2 + 800b7b0: 2b00 cmp r3, #0 + 800b7b2: f040 8090 bne.w 800b8d6 + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + 800b7b6: 687b ldr r3, [r7, #4] + 800b7b8: 2b00 cmp r3, #0 + 800b7ba: d01e beq.n 800b7fa + { + xWantedSize += xHeapStructSize; + 800b7bc: 2208 movs r2, #8 + 800b7be: 687b ldr r3, [r7, #4] + 800b7c0: 4413 add r3, r2 + 800b7c2: 607b str r3, [r7, #4] + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + 800b7c4: 687b ldr r3, [r7, #4] + 800b7c6: f003 0307 and.w r3, r3, #7 + 800b7ca: 2b00 cmp r3, #0 + 800b7cc: d015 beq.n 800b7fa + { + /* Byte alignment required. */ + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + 800b7ce: 687b ldr r3, [r7, #4] + 800b7d0: f023 0307 bic.w r3, r3, #7 + 800b7d4: 3308 adds r3, #8 + 800b7d6: 607b str r3, [r7, #4] + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + 800b7d8: 687b ldr r3, [r7, #4] + 800b7da: f003 0307 and.w r3, r3, #7 + 800b7de: 2b00 cmp r3, #0 + 800b7e0: d00b beq.n 800b7fa + __asm volatile + 800b7e2: f04f 0350 mov.w r3, #80 ; 0x50 + 800b7e6: b672 cpsid i + 800b7e8: f383 8811 msr BASEPRI, r3 + 800b7ec: f3bf 8f6f isb sy + 800b7f0: f3bf 8f4f dsb sy + 800b7f4: b662 cpsie i + 800b7f6: 617b str r3, [r7, #20] + 800b7f8: e7fe b.n 800b7f8 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + 800b7fa: 687b ldr r3, [r7, #4] + 800b7fc: 2b00 cmp r3, #0 + 800b7fe: d06a beq.n 800b8d6 + 800b800: 4b45 ldr r3, [pc, #276] ; (800b918 ) + 800b802: 681b ldr r3, [r3, #0] + 800b804: 687a ldr r2, [r7, #4] + 800b806: 429a cmp r2, r3 + 800b808: d865 bhi.n 800b8d6 + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + 800b80a: 4b44 ldr r3, [pc, #272] ; (800b91c ) + 800b80c: 623b str r3, [r7, #32] + pxBlock = xStart.pxNextFreeBlock; + 800b80e: 4b43 ldr r3, [pc, #268] ; (800b91c ) + 800b810: 681b ldr r3, [r3, #0] + 800b812: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 800b814: e004 b.n 800b820 + { + pxPreviousBlock = pxBlock; + 800b816: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b818: 623b str r3, [r7, #32] + pxBlock = pxBlock->pxNextFreeBlock; + 800b81a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b81c: 681b ldr r3, [r3, #0] + 800b81e: 627b str r3, [r7, #36] ; 0x24 + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + 800b820: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b822: 685b ldr r3, [r3, #4] + 800b824: 687a ldr r2, [r7, #4] + 800b826: 429a cmp r2, r3 + 800b828: d903 bls.n 800b832 + 800b82a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b82c: 681b ldr r3, [r3, #0] + 800b82e: 2b00 cmp r3, #0 + 800b830: d1f1 bne.n 800b816 + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if( pxBlock != pxEnd ) + 800b832: 4b37 ldr r3, [pc, #220] ; (800b910 ) + 800b834: 681b ldr r3, [r3, #0] + 800b836: 6a7a ldr r2, [r7, #36] ; 0x24 + 800b838: 429a cmp r2, r3 + 800b83a: d04c beq.n 800b8d6 + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + 800b83c: 6a3b ldr r3, [r7, #32] + 800b83e: 681b ldr r3, [r3, #0] + 800b840: 2208 movs r2, #8 + 800b842: 4413 add r3, r2 + 800b844: 61fb str r3, [r7, #28] + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + 800b846: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b848: 681a ldr r2, [r3, #0] + 800b84a: 6a3b ldr r3, [r7, #32] + 800b84c: 601a str r2, [r3, #0] + + /* If the block is larger than required it can be split into + two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + 800b84e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b850: 685a ldr r2, [r3, #4] + 800b852: 687b ldr r3, [r7, #4] + 800b854: 1ad2 subs r2, r2, r3 + 800b856: 2308 movs r3, #8 + 800b858: 005b lsls r3, r3, #1 + 800b85a: 429a cmp r2, r3 + 800b85c: d920 bls.n 800b8a0 + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + 800b85e: 6a7a ldr r2, [r7, #36] ; 0x24 + 800b860: 687b ldr r3, [r7, #4] + 800b862: 4413 add r3, r2 + 800b864: 61bb str r3, [r7, #24] + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + 800b866: 69bb ldr r3, [r7, #24] + 800b868: f003 0307 and.w r3, r3, #7 + 800b86c: 2b00 cmp r3, #0 + 800b86e: d00b beq.n 800b888 + 800b870: f04f 0350 mov.w r3, #80 ; 0x50 + 800b874: b672 cpsid i + 800b876: f383 8811 msr BASEPRI, r3 + 800b87a: f3bf 8f6f isb sy + 800b87e: f3bf 8f4f dsb sy + 800b882: b662 cpsie i + 800b884: 613b str r3, [r7, #16] + 800b886: e7fe b.n 800b886 + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + 800b888: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b88a: 685a ldr r2, [r3, #4] + 800b88c: 687b ldr r3, [r7, #4] + 800b88e: 1ad2 subs r2, r2, r3 + 800b890: 69bb ldr r3, [r7, #24] + 800b892: 605a str r2, [r3, #4] + pxBlock->xBlockSize = xWantedSize; + 800b894: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b896: 687a ldr r2, [r7, #4] + 800b898: 605a str r2, [r3, #4] + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + 800b89a: 69b8 ldr r0, [r7, #24] + 800b89c: f000 f900 bl 800baa0 + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + 800b8a0: 4b1d ldr r3, [pc, #116] ; (800b918 ) + 800b8a2: 681a ldr r2, [r3, #0] + 800b8a4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b8a6: 685b ldr r3, [r3, #4] + 800b8a8: 1ad3 subs r3, r2, r3 + 800b8aa: 4a1b ldr r2, [pc, #108] ; (800b918 ) + 800b8ac: 6013 str r3, [r2, #0] + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + 800b8ae: 4b1a ldr r3, [pc, #104] ; (800b918 ) + 800b8b0: 681a ldr r2, [r3, #0] + 800b8b2: 4b1b ldr r3, [pc, #108] ; (800b920 ) + 800b8b4: 681b ldr r3, [r3, #0] + 800b8b6: 429a cmp r2, r3 + 800b8b8: d203 bcs.n 800b8c2 + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + 800b8ba: 4b17 ldr r3, [pc, #92] ; (800b918 ) + 800b8bc: 681b ldr r3, [r3, #0] + 800b8be: 4a18 ldr r2, [pc, #96] ; (800b920 ) + 800b8c0: 6013 str r3, [r2, #0] + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + 800b8c2: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b8c4: 685a ldr r2, [r3, #4] + 800b8c6: 4b13 ldr r3, [pc, #76] ; (800b914 ) + 800b8c8: 681b ldr r3, [r3, #0] + 800b8ca: 431a orrs r2, r3 + 800b8cc: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b8ce: 605a str r2, [r3, #4] + pxBlock->pxNextFreeBlock = NULL; + 800b8d0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800b8d2: 2200 movs r2, #0 + 800b8d4: 601a str r2, [r3, #0] + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + 800b8d6: f7ff fb8d bl 800aff4 + + #if( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + 800b8da: 69fb ldr r3, [r7, #28] + 800b8dc: 2b00 cmp r3, #0 + 800b8de: d101 bne.n 800b8e4 + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + 800b8e0: f7f4 fe71 bl 80005c6 + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + 800b8e4: 69fb ldr r3, [r7, #28] + 800b8e6: f003 0307 and.w r3, r3, #7 + 800b8ea: 2b00 cmp r3, #0 + 800b8ec: d00b beq.n 800b906 + 800b8ee: f04f 0350 mov.w r3, #80 ; 0x50 + 800b8f2: b672 cpsid i + 800b8f4: f383 8811 msr BASEPRI, r3 + 800b8f8: f3bf 8f6f isb sy + 800b8fc: f3bf 8f4f dsb sy + 800b900: b662 cpsie i + 800b902: 60fb str r3, [r7, #12] + 800b904: e7fe b.n 800b904 + return pvReturn; + 800b906: 69fb ldr r3, [r7, #28] +} + 800b908: 4618 mov r0, r3 + 800b90a: 3728 adds r7, #40 ; 0x28 + 800b90c: 46bd mov sp, r7 + 800b90e: bd80 pop {r7, pc} + 800b910: 20008420 .word 0x20008420 + 800b914: 2000842c .word 0x2000842c + 800b918: 20008424 .word 0x20008424 + 800b91c: 20008418 .word 0x20008418 + 800b920: 20008428 .word 0x20008428 + +0800b924 : +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ + 800b924: b580 push {r7, lr} + 800b926: b086 sub sp, #24 + 800b928: af00 add r7, sp, #0 + 800b92a: 6078 str r0, [r7, #4] +uint8_t *puc = ( uint8_t * ) pv; + 800b92c: 687b ldr r3, [r7, #4] + 800b92e: 617b str r3, [r7, #20] +BlockLink_t *pxLink; + + if( pv != NULL ) + 800b930: 687b ldr r3, [r7, #4] + 800b932: 2b00 cmp r3, #0 + 800b934: d04a beq.n 800b9cc + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + 800b936: 2308 movs r3, #8 + 800b938: 425b negs r3, r3 + 800b93a: 697a ldr r2, [r7, #20] + 800b93c: 4413 add r3, r2 + 800b93e: 617b str r3, [r7, #20] + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + 800b940: 697b ldr r3, [r7, #20] + 800b942: 613b str r3, [r7, #16] + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + 800b944: 693b ldr r3, [r7, #16] + 800b946: 685a ldr r2, [r3, #4] + 800b948: 4b22 ldr r3, [pc, #136] ; (800b9d4 ) + 800b94a: 681b ldr r3, [r3, #0] + 800b94c: 4013 ands r3, r2 + 800b94e: 2b00 cmp r3, #0 + 800b950: d10b bne.n 800b96a + 800b952: f04f 0350 mov.w r3, #80 ; 0x50 + 800b956: b672 cpsid i + 800b958: f383 8811 msr BASEPRI, r3 + 800b95c: f3bf 8f6f isb sy + 800b960: f3bf 8f4f dsb sy + 800b964: b662 cpsie i + 800b966: 60fb str r3, [r7, #12] + 800b968: e7fe b.n 800b968 + configASSERT( pxLink->pxNextFreeBlock == NULL ); + 800b96a: 693b ldr r3, [r7, #16] + 800b96c: 681b ldr r3, [r3, #0] + 800b96e: 2b00 cmp r3, #0 + 800b970: d00b beq.n 800b98a + 800b972: f04f 0350 mov.w r3, #80 ; 0x50 + 800b976: b672 cpsid i + 800b978: f383 8811 msr BASEPRI, r3 + 800b97c: f3bf 8f6f isb sy + 800b980: f3bf 8f4f dsb sy + 800b984: b662 cpsie i + 800b986: 60bb str r3, [r7, #8] + 800b988: e7fe b.n 800b988 + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + 800b98a: 693b ldr r3, [r7, #16] + 800b98c: 685a ldr r2, [r3, #4] + 800b98e: 4b11 ldr r3, [pc, #68] ; (800b9d4 ) + 800b990: 681b ldr r3, [r3, #0] + 800b992: 4013 ands r3, r2 + 800b994: 2b00 cmp r3, #0 + 800b996: d019 beq.n 800b9cc + { + if( pxLink->pxNextFreeBlock == NULL ) + 800b998: 693b ldr r3, [r7, #16] + 800b99a: 681b ldr r3, [r3, #0] + 800b99c: 2b00 cmp r3, #0 + 800b99e: d115 bne.n 800b9cc + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + 800b9a0: 693b ldr r3, [r7, #16] + 800b9a2: 685a ldr r2, [r3, #4] + 800b9a4: 4b0b ldr r3, [pc, #44] ; (800b9d4 ) + 800b9a6: 681b ldr r3, [r3, #0] + 800b9a8: 43db mvns r3, r3 + 800b9aa: 401a ands r2, r3 + 800b9ac: 693b ldr r3, [r7, #16] + 800b9ae: 605a str r2, [r3, #4] + + vTaskSuspendAll(); + 800b9b0: f7ff fb12 bl 800afd8 + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + 800b9b4: 693b ldr r3, [r7, #16] + 800b9b6: 685a ldr r2, [r3, #4] + 800b9b8: 4b07 ldr r3, [pc, #28] ; (800b9d8 ) + 800b9ba: 681b ldr r3, [r3, #0] + 800b9bc: 4413 add r3, r2 + 800b9be: 4a06 ldr r2, [pc, #24] ; (800b9d8 ) + 800b9c0: 6013 str r3, [r2, #0] + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + 800b9c2: 6938 ldr r0, [r7, #16] + 800b9c4: f000 f86c bl 800baa0 + } + ( void ) xTaskResumeAll(); + 800b9c8: f7ff fb14 bl 800aff4 + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} + 800b9cc: bf00 nop + 800b9ce: 3718 adds r7, #24 + 800b9d0: 46bd mov sp, r7 + 800b9d2: bd80 pop {r7, pc} + 800b9d4: 2000842c .word 0x2000842c + 800b9d8: 20008424 .word 0x20008424 + +0800b9dc : + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ + 800b9dc: b480 push {r7} + 800b9de: b085 sub sp, #20 + 800b9e0: af00 add r7, sp, #0 +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + 800b9e2: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800b9e6: 60bb str r3, [r7, #8] + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + 800b9e8: 4b27 ldr r3, [pc, #156] ; (800ba88 ) + 800b9ea: 60fb str r3, [r7, #12] + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + 800b9ec: 68fb ldr r3, [r7, #12] + 800b9ee: f003 0307 and.w r3, r3, #7 + 800b9f2: 2b00 cmp r3, #0 + 800b9f4: d00c beq.n 800ba10 + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + 800b9f6: 68fb ldr r3, [r7, #12] + 800b9f8: 3307 adds r3, #7 + 800b9fa: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 800b9fc: 68fb ldr r3, [r7, #12] + 800b9fe: f023 0307 bic.w r3, r3, #7 + 800ba02: 60fb str r3, [r7, #12] + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + 800ba04: 68ba ldr r2, [r7, #8] + 800ba06: 68fb ldr r3, [r7, #12] + 800ba08: 1ad3 subs r3, r2, r3 + 800ba0a: 4a1f ldr r2, [pc, #124] ; (800ba88 ) + 800ba0c: 4413 add r3, r2 + 800ba0e: 60bb str r3, [r7, #8] + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + 800ba10: 68fb ldr r3, [r7, #12] + 800ba12: 607b str r3, [r7, #4] + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + 800ba14: 4a1d ldr r2, [pc, #116] ; (800ba8c ) + 800ba16: 687b ldr r3, [r7, #4] + 800ba18: 6013 str r3, [r2, #0] + xStart.xBlockSize = ( size_t ) 0; + 800ba1a: 4b1c ldr r3, [pc, #112] ; (800ba8c ) + 800ba1c: 2200 movs r2, #0 + 800ba1e: 605a str r2, [r3, #4] + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + 800ba20: 687b ldr r3, [r7, #4] + 800ba22: 68ba ldr r2, [r7, #8] + 800ba24: 4413 add r3, r2 + 800ba26: 60fb str r3, [r7, #12] + uxAddress -= xHeapStructSize; + 800ba28: 2208 movs r2, #8 + 800ba2a: 68fb ldr r3, [r7, #12] + 800ba2c: 1a9b subs r3, r3, r2 + 800ba2e: 60fb str r3, [r7, #12] + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + 800ba30: 68fb ldr r3, [r7, #12] + 800ba32: f023 0307 bic.w r3, r3, #7 + 800ba36: 60fb str r3, [r7, #12] + pxEnd = ( void * ) uxAddress; + 800ba38: 68fb ldr r3, [r7, #12] + 800ba3a: 4a15 ldr r2, [pc, #84] ; (800ba90 ) + 800ba3c: 6013 str r3, [r2, #0] + pxEnd->xBlockSize = 0; + 800ba3e: 4b14 ldr r3, [pc, #80] ; (800ba90 ) + 800ba40: 681b ldr r3, [r3, #0] + 800ba42: 2200 movs r2, #0 + 800ba44: 605a str r2, [r3, #4] + pxEnd->pxNextFreeBlock = NULL; + 800ba46: 4b12 ldr r3, [pc, #72] ; (800ba90 ) + 800ba48: 681b ldr r3, [r3, #0] + 800ba4a: 2200 movs r2, #0 + 800ba4c: 601a str r2, [r3, #0] + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + 800ba4e: 687b ldr r3, [r7, #4] + 800ba50: 603b str r3, [r7, #0] + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + 800ba52: 683b ldr r3, [r7, #0] + 800ba54: 68fa ldr r2, [r7, #12] + 800ba56: 1ad2 subs r2, r2, r3 + 800ba58: 683b ldr r3, [r7, #0] + 800ba5a: 605a str r2, [r3, #4] + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + 800ba5c: 4b0c ldr r3, [pc, #48] ; (800ba90 ) + 800ba5e: 681a ldr r2, [r3, #0] + 800ba60: 683b ldr r3, [r7, #0] + 800ba62: 601a str r2, [r3, #0] + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800ba64: 683b ldr r3, [r7, #0] + 800ba66: 685b ldr r3, [r3, #4] + 800ba68: 4a0a ldr r2, [pc, #40] ; (800ba94 ) + 800ba6a: 6013 str r3, [r2, #0] + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + 800ba6c: 683b ldr r3, [r7, #0] + 800ba6e: 685b ldr r3, [r3, #4] + 800ba70: 4a09 ldr r2, [pc, #36] ; (800ba98 ) + 800ba72: 6013 str r3, [r2, #0] + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); + 800ba74: 4b09 ldr r3, [pc, #36] ; (800ba9c ) + 800ba76: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 800ba7a: 601a str r2, [r3, #0] +} + 800ba7c: bf00 nop + 800ba7e: 3714 adds r7, #20 + 800ba80: 46bd mov sp, r7 + 800ba82: f85d 7b04 ldr.w r7, [sp], #4 + 800ba86: 4770 bx lr + 800ba88: 20000418 .word 0x20000418 + 800ba8c: 20008418 .word 0x20008418 + 800ba90: 20008420 .word 0x20008420 + 800ba94: 20008428 .word 0x20008428 + 800ba98: 20008424 .word 0x20008424 + 800ba9c: 2000842c .word 0x2000842c + +0800baa0 : +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ + 800baa0: b480 push {r7} + 800baa2: b085 sub sp, #20 + 800baa4: af00 add r7, sp, #0 + 800baa6: 6078 str r0, [r7, #4] +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + 800baa8: 4b28 ldr r3, [pc, #160] ; (800bb4c ) + 800baaa: 60fb str r3, [r7, #12] + 800baac: e002 b.n 800bab4 + 800baae: 68fb ldr r3, [r7, #12] + 800bab0: 681b ldr r3, [r3, #0] + 800bab2: 60fb str r3, [r7, #12] + 800bab4: 68fb ldr r3, [r7, #12] + 800bab6: 681b ldr r3, [r3, #0] + 800bab8: 687a ldr r2, [r7, #4] + 800baba: 429a cmp r2, r3 + 800babc: d8f7 bhi.n 800baae + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + 800babe: 68fb ldr r3, [r7, #12] + 800bac0: 60bb str r3, [r7, #8] + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + 800bac2: 68fb ldr r3, [r7, #12] + 800bac4: 685b ldr r3, [r3, #4] + 800bac6: 68ba ldr r2, [r7, #8] + 800bac8: 4413 add r3, r2 + 800baca: 687a ldr r2, [r7, #4] + 800bacc: 429a cmp r2, r3 + 800bace: d108 bne.n 800bae2 + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + 800bad0: 68fb ldr r3, [r7, #12] + 800bad2: 685a ldr r2, [r3, #4] + 800bad4: 687b ldr r3, [r7, #4] + 800bad6: 685b ldr r3, [r3, #4] + 800bad8: 441a add r2, r3 + 800bada: 68fb ldr r3, [r7, #12] + 800badc: 605a str r2, [r3, #4] + pxBlockToInsert = pxIterator; + 800bade: 68fb ldr r3, [r7, #12] + 800bae0: 607b str r3, [r7, #4] + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + 800bae2: 687b ldr r3, [r7, #4] + 800bae4: 60bb str r3, [r7, #8] + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + 800bae6: 687b ldr r3, [r7, #4] + 800bae8: 685b ldr r3, [r3, #4] + 800baea: 68ba ldr r2, [r7, #8] + 800baec: 441a add r2, r3 + 800baee: 68fb ldr r3, [r7, #12] + 800baf0: 681b ldr r3, [r3, #0] + 800baf2: 429a cmp r2, r3 + 800baf4: d118 bne.n 800bb28 + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + 800baf6: 68fb ldr r3, [r7, #12] + 800baf8: 681a ldr r2, [r3, #0] + 800bafa: 4b15 ldr r3, [pc, #84] ; (800bb50 ) + 800bafc: 681b ldr r3, [r3, #0] + 800bafe: 429a cmp r2, r3 + 800bb00: d00d beq.n 800bb1e + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + 800bb02: 687b ldr r3, [r7, #4] + 800bb04: 685a ldr r2, [r3, #4] + 800bb06: 68fb ldr r3, [r7, #12] + 800bb08: 681b ldr r3, [r3, #0] + 800bb0a: 685b ldr r3, [r3, #4] + 800bb0c: 441a add r2, r3 + 800bb0e: 687b ldr r3, [r7, #4] + 800bb10: 605a str r2, [r3, #4] + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + 800bb12: 68fb ldr r3, [r7, #12] + 800bb14: 681b ldr r3, [r3, #0] + 800bb16: 681a ldr r2, [r3, #0] + 800bb18: 687b ldr r3, [r7, #4] + 800bb1a: 601a str r2, [r3, #0] + 800bb1c: e008 b.n 800bb30 + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + 800bb1e: 4b0c ldr r3, [pc, #48] ; (800bb50 ) + 800bb20: 681a ldr r2, [r3, #0] + 800bb22: 687b ldr r3, [r7, #4] + 800bb24: 601a str r2, [r3, #0] + 800bb26: e003 b.n 800bb30 + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + 800bb28: 68fb ldr r3, [r7, #12] + 800bb2a: 681a ldr r2, [r3, #0] + 800bb2c: 687b ldr r3, [r7, #4] + 800bb2e: 601a str r2, [r3, #0] + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if( pxIterator != pxBlockToInsert ) + 800bb30: 68fa ldr r2, [r7, #12] + 800bb32: 687b ldr r3, [r7, #4] + 800bb34: 429a cmp r2, r3 + 800bb36: d002 beq.n 800bb3e + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + 800bb38: 68fb ldr r3, [r7, #12] + 800bb3a: 687a ldr r2, [r7, #4] + 800bb3c: 601a str r2, [r3, #0] + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} + 800bb3e: bf00 nop + 800bb40: 3714 adds r7, #20 + 800bb42: 46bd mov sp, r7 + 800bb44: f85d 7b04 ldr.w r7, [sp], #4 + 800bb48: 4770 bx lr + 800bb4a: bf00 nop + 800bb4c: 20008418 .word 0x20008418 + 800bb50: 20008420 .word 0x20008420 + +0800bb54 <__errno>: + 800bb54: 4b01 ldr r3, [pc, #4] ; (800bb5c <__errno+0x8>) + 800bb56: 6818 ldr r0, [r3, #0] + 800bb58: 4770 bx lr + 800bb5a: bf00 nop + 800bb5c: 2000004c .word 0x2000004c + +0800bb60 <__libc_init_array>: + 800bb60: b570 push {r4, r5, r6, lr} + 800bb62: 4e0d ldr r6, [pc, #52] ; (800bb98 <__libc_init_array+0x38>) + 800bb64: 4c0d ldr r4, [pc, #52] ; (800bb9c <__libc_init_array+0x3c>) + 800bb66: 1ba4 subs r4, r4, r6 + 800bb68: 10a4 asrs r4, r4, #2 + 800bb6a: 2500 movs r5, #0 + 800bb6c: 42a5 cmp r5, r4 + 800bb6e: d109 bne.n 800bb84 <__libc_init_array+0x24> + 800bb70: 4e0b ldr r6, [pc, #44] ; (800bba0 <__libc_init_array+0x40>) + 800bb72: 4c0c ldr r4, [pc, #48] ; (800bba4 <__libc_init_array+0x44>) + 800bb74: f000 fc28 bl 800c3c8 <_init> + 800bb78: 1ba4 subs r4, r4, r6 + 800bb7a: 10a4 asrs r4, r4, #2 + 800bb7c: 2500 movs r5, #0 + 800bb7e: 42a5 cmp r5, r4 + 800bb80: d105 bne.n 800bb8e <__libc_init_array+0x2e> + 800bb82: bd70 pop {r4, r5, r6, pc} + 800bb84: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800bb88: 4798 blx r3 + 800bb8a: 3501 adds r5, #1 + 800bb8c: e7ee b.n 800bb6c <__libc_init_array+0xc> + 800bb8e: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 800bb92: 4798 blx r3 + 800bb94: 3501 adds r5, #1 + 800bb96: e7f2 b.n 800bb7e <__libc_init_array+0x1e> + 800bb98: 0800e3cc .word 0x0800e3cc + 800bb9c: 0800e3cc .word 0x0800e3cc + 800bba0: 0800e3cc .word 0x0800e3cc + 800bba4: 0800e3d0 .word 0x0800e3d0 + +0800bba8 : + 800bba8: b510 push {r4, lr} + 800bbaa: 1e43 subs r3, r0, #1 + 800bbac: 440a add r2, r1 + 800bbae: 4291 cmp r1, r2 + 800bbb0: d100 bne.n 800bbb4 + 800bbb2: bd10 pop {r4, pc} + 800bbb4: f811 4b01 ldrb.w r4, [r1], #1 + 800bbb8: f803 4f01 strb.w r4, [r3, #1]! + 800bbbc: e7f7 b.n 800bbae + +0800bbbe : + 800bbbe: 4402 add r2, r0 + 800bbc0: 4603 mov r3, r0 + 800bbc2: 4293 cmp r3, r2 + 800bbc4: d100 bne.n 800bbc8 + 800bbc6: 4770 bx lr + 800bbc8: f803 1b01 strb.w r1, [r3], #1 + 800bbcc: e7f9 b.n 800bbc2 + ... + +0800bbd0 : + 800bbd0: b40e push {r1, r2, r3} + 800bbd2: b500 push {lr} + 800bbd4: b09c sub sp, #112 ; 0x70 + 800bbd6: ab1d add r3, sp, #116 ; 0x74 + 800bbd8: 9002 str r0, [sp, #8] + 800bbda: 9006 str r0, [sp, #24] + 800bbdc: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000 + 800bbe0: 4809 ldr r0, [pc, #36] ; (800bc08 ) + 800bbe2: 9107 str r1, [sp, #28] + 800bbe4: 9104 str r1, [sp, #16] + 800bbe6: 4909 ldr r1, [pc, #36] ; (800bc0c ) + 800bbe8: f853 2b04 ldr.w r2, [r3], #4 + 800bbec: 9105 str r1, [sp, #20] + 800bbee: 6800 ldr r0, [r0, #0] + 800bbf0: 9301 str r3, [sp, #4] + 800bbf2: a902 add r1, sp, #8 + 800bbf4: f000 f866 bl 800bcc4 <_svfiprintf_r> + 800bbf8: 9b02 ldr r3, [sp, #8] + 800bbfa: 2200 movs r2, #0 + 800bbfc: 701a strb r2, [r3, #0] + 800bbfe: b01c add sp, #112 ; 0x70 + 800bc00: f85d eb04 ldr.w lr, [sp], #4 + 800bc04: b003 add sp, #12 + 800bc06: 4770 bx lr + 800bc08: 2000004c .word 0x2000004c + 800bc0c: ffff0208 .word 0xffff0208 + +0800bc10 <__ssputs_r>: + 800bc10: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800bc14: 688e ldr r6, [r1, #8] + 800bc16: 429e cmp r6, r3 + 800bc18: 4682 mov sl, r0 + 800bc1a: 460c mov r4, r1 + 800bc1c: 4690 mov r8, r2 + 800bc1e: 4699 mov r9, r3 + 800bc20: d837 bhi.n 800bc92 <__ssputs_r+0x82> + 800bc22: 898a ldrh r2, [r1, #12] + 800bc24: f412 6f90 tst.w r2, #1152 ; 0x480 + 800bc28: d031 beq.n 800bc8e <__ssputs_r+0x7e> + 800bc2a: 6825 ldr r5, [r4, #0] + 800bc2c: 6909 ldr r1, [r1, #16] + 800bc2e: 1a6f subs r7, r5, r1 + 800bc30: 6965 ldr r5, [r4, #20] + 800bc32: 2302 movs r3, #2 + 800bc34: eb05 0545 add.w r5, r5, r5, lsl #1 + 800bc38: fb95 f5f3 sdiv r5, r5, r3 + 800bc3c: f109 0301 add.w r3, r9, #1 + 800bc40: 443b add r3, r7 + 800bc42: 429d cmp r5, r3 + 800bc44: bf38 it cc + 800bc46: 461d movcc r5, r3 + 800bc48: 0553 lsls r3, r2, #21 + 800bc4a: d530 bpl.n 800bcae <__ssputs_r+0x9e> + 800bc4c: 4629 mov r1, r5 + 800bc4e: f000 fb21 bl 800c294 <_malloc_r> + 800bc52: 4606 mov r6, r0 + 800bc54: b950 cbnz r0, 800bc6c <__ssputs_r+0x5c> + 800bc56: 230c movs r3, #12 + 800bc58: f8ca 3000 str.w r3, [sl] + 800bc5c: 89a3 ldrh r3, [r4, #12] + 800bc5e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800bc62: 81a3 strh r3, [r4, #12] + 800bc64: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800bc68: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800bc6c: 463a mov r2, r7 + 800bc6e: 6921 ldr r1, [r4, #16] + 800bc70: f7ff ff9a bl 800bba8 + 800bc74: 89a3 ldrh r3, [r4, #12] + 800bc76: f423 6390 bic.w r3, r3, #1152 ; 0x480 + 800bc7a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800bc7e: 81a3 strh r3, [r4, #12] + 800bc80: 6126 str r6, [r4, #16] + 800bc82: 6165 str r5, [r4, #20] + 800bc84: 443e add r6, r7 + 800bc86: 1bed subs r5, r5, r7 + 800bc88: 6026 str r6, [r4, #0] + 800bc8a: 60a5 str r5, [r4, #8] + 800bc8c: 464e mov r6, r9 + 800bc8e: 454e cmp r6, r9 + 800bc90: d900 bls.n 800bc94 <__ssputs_r+0x84> + 800bc92: 464e mov r6, r9 + 800bc94: 4632 mov r2, r6 + 800bc96: 4641 mov r1, r8 + 800bc98: 6820 ldr r0, [r4, #0] + 800bc9a: f000 fa93 bl 800c1c4 + 800bc9e: 68a3 ldr r3, [r4, #8] + 800bca0: 1b9b subs r3, r3, r6 + 800bca2: 60a3 str r3, [r4, #8] + 800bca4: 6823 ldr r3, [r4, #0] + 800bca6: 441e add r6, r3 + 800bca8: 6026 str r6, [r4, #0] + 800bcaa: 2000 movs r0, #0 + 800bcac: e7dc b.n 800bc68 <__ssputs_r+0x58> + 800bcae: 462a mov r2, r5 + 800bcb0: f000 fb4a bl 800c348 <_realloc_r> + 800bcb4: 4606 mov r6, r0 + 800bcb6: 2800 cmp r0, #0 + 800bcb8: d1e2 bne.n 800bc80 <__ssputs_r+0x70> + 800bcba: 6921 ldr r1, [r4, #16] + 800bcbc: 4650 mov r0, sl + 800bcbe: f000 fa9b bl 800c1f8 <_free_r> + 800bcc2: e7c8 b.n 800bc56 <__ssputs_r+0x46> + +0800bcc4 <_svfiprintf_r>: + 800bcc4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800bcc8: 461d mov r5, r3 + 800bcca: 898b ldrh r3, [r1, #12] + 800bccc: 061f lsls r7, r3, #24 + 800bcce: b09d sub sp, #116 ; 0x74 + 800bcd0: 4680 mov r8, r0 + 800bcd2: 460c mov r4, r1 + 800bcd4: 4616 mov r6, r2 + 800bcd6: d50f bpl.n 800bcf8 <_svfiprintf_r+0x34> + 800bcd8: 690b ldr r3, [r1, #16] + 800bcda: b96b cbnz r3, 800bcf8 <_svfiprintf_r+0x34> + 800bcdc: 2140 movs r1, #64 ; 0x40 + 800bcde: f000 fad9 bl 800c294 <_malloc_r> + 800bce2: 6020 str r0, [r4, #0] + 800bce4: 6120 str r0, [r4, #16] + 800bce6: b928 cbnz r0, 800bcf4 <_svfiprintf_r+0x30> + 800bce8: 230c movs r3, #12 + 800bcea: f8c8 3000 str.w r3, [r8] + 800bcee: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800bcf2: e0c8 b.n 800be86 <_svfiprintf_r+0x1c2> + 800bcf4: 2340 movs r3, #64 ; 0x40 + 800bcf6: 6163 str r3, [r4, #20] + 800bcf8: 2300 movs r3, #0 + 800bcfa: 9309 str r3, [sp, #36] ; 0x24 + 800bcfc: 2320 movs r3, #32 + 800bcfe: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 800bd02: 2330 movs r3, #48 ; 0x30 + 800bd04: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 800bd08: 9503 str r5, [sp, #12] + 800bd0a: f04f 0b01 mov.w fp, #1 + 800bd0e: 4637 mov r7, r6 + 800bd10: 463d mov r5, r7 + 800bd12: f815 3b01 ldrb.w r3, [r5], #1 + 800bd16: b10b cbz r3, 800bd1c <_svfiprintf_r+0x58> + 800bd18: 2b25 cmp r3, #37 ; 0x25 + 800bd1a: d13e bne.n 800bd9a <_svfiprintf_r+0xd6> + 800bd1c: ebb7 0a06 subs.w sl, r7, r6 + 800bd20: d00b beq.n 800bd3a <_svfiprintf_r+0x76> + 800bd22: 4653 mov r3, sl + 800bd24: 4632 mov r2, r6 + 800bd26: 4621 mov r1, r4 + 800bd28: 4640 mov r0, r8 + 800bd2a: f7ff ff71 bl 800bc10 <__ssputs_r> + 800bd2e: 3001 adds r0, #1 + 800bd30: f000 80a4 beq.w 800be7c <_svfiprintf_r+0x1b8> + 800bd34: 9b09 ldr r3, [sp, #36] ; 0x24 + 800bd36: 4453 add r3, sl + 800bd38: 9309 str r3, [sp, #36] ; 0x24 + 800bd3a: 783b ldrb r3, [r7, #0] + 800bd3c: 2b00 cmp r3, #0 + 800bd3e: f000 809d beq.w 800be7c <_svfiprintf_r+0x1b8> + 800bd42: 2300 movs r3, #0 + 800bd44: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 800bd48: e9cd 2305 strd r2, r3, [sp, #20] + 800bd4c: 9304 str r3, [sp, #16] + 800bd4e: 9307 str r3, [sp, #28] + 800bd50: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800bd54: 931a str r3, [sp, #104] ; 0x68 + 800bd56: 462f mov r7, r5 + 800bd58: 2205 movs r2, #5 + 800bd5a: f817 1b01 ldrb.w r1, [r7], #1 + 800bd5e: 4850 ldr r0, [pc, #320] ; (800bea0 <_svfiprintf_r+0x1dc>) + 800bd60: f7f4 fa56 bl 8000210 + 800bd64: 9b04 ldr r3, [sp, #16] + 800bd66: b9d0 cbnz r0, 800bd9e <_svfiprintf_r+0xda> + 800bd68: 06d9 lsls r1, r3, #27 + 800bd6a: bf44 itt mi + 800bd6c: 2220 movmi r2, #32 + 800bd6e: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800bd72: 071a lsls r2, r3, #28 + 800bd74: bf44 itt mi + 800bd76: 222b movmi r2, #43 ; 0x2b + 800bd78: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 + 800bd7c: 782a ldrb r2, [r5, #0] + 800bd7e: 2a2a cmp r2, #42 ; 0x2a + 800bd80: d015 beq.n 800bdae <_svfiprintf_r+0xea> + 800bd82: 9a07 ldr r2, [sp, #28] + 800bd84: 462f mov r7, r5 + 800bd86: 2000 movs r0, #0 + 800bd88: 250a movs r5, #10 + 800bd8a: 4639 mov r1, r7 + 800bd8c: f811 3b01 ldrb.w r3, [r1], #1 + 800bd90: 3b30 subs r3, #48 ; 0x30 + 800bd92: 2b09 cmp r3, #9 + 800bd94: d94d bls.n 800be32 <_svfiprintf_r+0x16e> + 800bd96: b1b8 cbz r0, 800bdc8 <_svfiprintf_r+0x104> + 800bd98: e00f b.n 800bdba <_svfiprintf_r+0xf6> + 800bd9a: 462f mov r7, r5 + 800bd9c: e7b8 b.n 800bd10 <_svfiprintf_r+0x4c> + 800bd9e: 4a40 ldr r2, [pc, #256] ; (800bea0 <_svfiprintf_r+0x1dc>) + 800bda0: 1a80 subs r0, r0, r2 + 800bda2: fa0b f000 lsl.w r0, fp, r0 + 800bda6: 4318 orrs r0, r3 + 800bda8: 9004 str r0, [sp, #16] + 800bdaa: 463d mov r5, r7 + 800bdac: e7d3 b.n 800bd56 <_svfiprintf_r+0x92> + 800bdae: 9a03 ldr r2, [sp, #12] + 800bdb0: 1d11 adds r1, r2, #4 + 800bdb2: 6812 ldr r2, [r2, #0] + 800bdb4: 9103 str r1, [sp, #12] + 800bdb6: 2a00 cmp r2, #0 + 800bdb8: db01 blt.n 800bdbe <_svfiprintf_r+0xfa> + 800bdba: 9207 str r2, [sp, #28] + 800bdbc: e004 b.n 800bdc8 <_svfiprintf_r+0x104> + 800bdbe: 4252 negs r2, r2 + 800bdc0: f043 0302 orr.w r3, r3, #2 + 800bdc4: 9207 str r2, [sp, #28] + 800bdc6: 9304 str r3, [sp, #16] + 800bdc8: 783b ldrb r3, [r7, #0] + 800bdca: 2b2e cmp r3, #46 ; 0x2e + 800bdcc: d10c bne.n 800bde8 <_svfiprintf_r+0x124> + 800bdce: 787b ldrb r3, [r7, #1] + 800bdd0: 2b2a cmp r3, #42 ; 0x2a + 800bdd2: d133 bne.n 800be3c <_svfiprintf_r+0x178> + 800bdd4: 9b03 ldr r3, [sp, #12] + 800bdd6: 1d1a adds r2, r3, #4 + 800bdd8: 681b ldr r3, [r3, #0] + 800bdda: 9203 str r2, [sp, #12] + 800bddc: 2b00 cmp r3, #0 + 800bdde: bfb8 it lt + 800bde0: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff + 800bde4: 3702 adds r7, #2 + 800bde6: 9305 str r3, [sp, #20] + 800bde8: 4d2e ldr r5, [pc, #184] ; (800bea4 <_svfiprintf_r+0x1e0>) + 800bdea: 7839 ldrb r1, [r7, #0] + 800bdec: 2203 movs r2, #3 + 800bdee: 4628 mov r0, r5 + 800bdf0: f7f4 fa0e bl 8000210 + 800bdf4: b138 cbz r0, 800be06 <_svfiprintf_r+0x142> + 800bdf6: 2340 movs r3, #64 ; 0x40 + 800bdf8: 1b40 subs r0, r0, r5 + 800bdfa: fa03 f000 lsl.w r0, r3, r0 + 800bdfe: 9b04 ldr r3, [sp, #16] + 800be00: 4303 orrs r3, r0 + 800be02: 3701 adds r7, #1 + 800be04: 9304 str r3, [sp, #16] + 800be06: 7839 ldrb r1, [r7, #0] + 800be08: 4827 ldr r0, [pc, #156] ; (800bea8 <_svfiprintf_r+0x1e4>) + 800be0a: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800be0e: 2206 movs r2, #6 + 800be10: 1c7e adds r6, r7, #1 + 800be12: f7f4 f9fd bl 8000210 + 800be16: 2800 cmp r0, #0 + 800be18: d038 beq.n 800be8c <_svfiprintf_r+0x1c8> + 800be1a: 4b24 ldr r3, [pc, #144] ; (800beac <_svfiprintf_r+0x1e8>) + 800be1c: bb13 cbnz r3, 800be64 <_svfiprintf_r+0x1a0> + 800be1e: 9b03 ldr r3, [sp, #12] + 800be20: 3307 adds r3, #7 + 800be22: f023 0307 bic.w r3, r3, #7 + 800be26: 3308 adds r3, #8 + 800be28: 9303 str r3, [sp, #12] + 800be2a: 9b09 ldr r3, [sp, #36] ; 0x24 + 800be2c: 444b add r3, r9 + 800be2e: 9309 str r3, [sp, #36] ; 0x24 + 800be30: e76d b.n 800bd0e <_svfiprintf_r+0x4a> + 800be32: fb05 3202 mla r2, r5, r2, r3 + 800be36: 2001 movs r0, #1 + 800be38: 460f mov r7, r1 + 800be3a: e7a6 b.n 800bd8a <_svfiprintf_r+0xc6> + 800be3c: 2300 movs r3, #0 + 800be3e: 3701 adds r7, #1 + 800be40: 9305 str r3, [sp, #20] + 800be42: 4619 mov r1, r3 + 800be44: 250a movs r5, #10 + 800be46: 4638 mov r0, r7 + 800be48: f810 2b01 ldrb.w r2, [r0], #1 + 800be4c: 3a30 subs r2, #48 ; 0x30 + 800be4e: 2a09 cmp r2, #9 + 800be50: d903 bls.n 800be5a <_svfiprintf_r+0x196> + 800be52: 2b00 cmp r3, #0 + 800be54: d0c8 beq.n 800bde8 <_svfiprintf_r+0x124> + 800be56: 9105 str r1, [sp, #20] + 800be58: e7c6 b.n 800bde8 <_svfiprintf_r+0x124> + 800be5a: fb05 2101 mla r1, r5, r1, r2 + 800be5e: 2301 movs r3, #1 + 800be60: 4607 mov r7, r0 + 800be62: e7f0 b.n 800be46 <_svfiprintf_r+0x182> + 800be64: ab03 add r3, sp, #12 + 800be66: 9300 str r3, [sp, #0] + 800be68: 4622 mov r2, r4 + 800be6a: 4b11 ldr r3, [pc, #68] ; (800beb0 <_svfiprintf_r+0x1ec>) + 800be6c: a904 add r1, sp, #16 + 800be6e: 4640 mov r0, r8 + 800be70: f3af 8000 nop.w + 800be74: f1b0 3fff cmp.w r0, #4294967295 ; 0xffffffff + 800be78: 4681 mov r9, r0 + 800be7a: d1d6 bne.n 800be2a <_svfiprintf_r+0x166> + 800be7c: 89a3 ldrh r3, [r4, #12] + 800be7e: 065b lsls r3, r3, #25 + 800be80: f53f af35 bmi.w 800bcee <_svfiprintf_r+0x2a> + 800be84: 9809 ldr r0, [sp, #36] ; 0x24 + 800be86: b01d add sp, #116 ; 0x74 + 800be88: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800be8c: ab03 add r3, sp, #12 + 800be8e: 9300 str r3, [sp, #0] + 800be90: 4622 mov r2, r4 + 800be92: 4b07 ldr r3, [pc, #28] ; (800beb0 <_svfiprintf_r+0x1ec>) + 800be94: a904 add r1, sp, #16 + 800be96: 4640 mov r0, r8 + 800be98: f000 f882 bl 800bfa0 <_printf_i> + 800be9c: e7ea b.n 800be74 <_svfiprintf_r+0x1b0> + 800be9e: bf00 nop + 800bea0: 0800e390 .word 0x0800e390 + 800bea4: 0800e396 .word 0x0800e396 + 800bea8: 0800e39a .word 0x0800e39a + 800beac: 00000000 .word 0x00000000 + 800beb0: 0800bc11 .word 0x0800bc11 + +0800beb4 <_printf_common>: + 800beb4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800beb8: 4691 mov r9, r2 + 800beba: 461f mov r7, r3 + 800bebc: 688a ldr r2, [r1, #8] + 800bebe: 690b ldr r3, [r1, #16] + 800bec0: f8dd 8020 ldr.w r8, [sp, #32] + 800bec4: 4293 cmp r3, r2 + 800bec6: bfb8 it lt + 800bec8: 4613 movlt r3, r2 + 800beca: f8c9 3000 str.w r3, [r9] + 800bece: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 800bed2: 4606 mov r6, r0 + 800bed4: 460c mov r4, r1 + 800bed6: b112 cbz r2, 800bede <_printf_common+0x2a> + 800bed8: 3301 adds r3, #1 + 800beda: f8c9 3000 str.w r3, [r9] + 800bede: 6823 ldr r3, [r4, #0] + 800bee0: 0699 lsls r1, r3, #26 + 800bee2: bf42 ittt mi + 800bee4: f8d9 3000 ldrmi.w r3, [r9] + 800bee8: 3302 addmi r3, #2 + 800beea: f8c9 3000 strmi.w r3, [r9] + 800beee: 6825 ldr r5, [r4, #0] + 800bef0: f015 0506 ands.w r5, r5, #6 + 800bef4: d107 bne.n 800bf06 <_printf_common+0x52> + 800bef6: f104 0a19 add.w sl, r4, #25 + 800befa: 68e3 ldr r3, [r4, #12] + 800befc: f8d9 2000 ldr.w r2, [r9] + 800bf00: 1a9b subs r3, r3, r2 + 800bf02: 42ab cmp r3, r5 + 800bf04: dc28 bgt.n 800bf58 <_printf_common+0xa4> + 800bf06: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 + 800bf0a: 6822 ldr r2, [r4, #0] + 800bf0c: 3300 adds r3, #0 + 800bf0e: bf18 it ne + 800bf10: 2301 movne r3, #1 + 800bf12: 0692 lsls r2, r2, #26 + 800bf14: d42d bmi.n 800bf72 <_printf_common+0xbe> + 800bf16: f104 0243 add.w r2, r4, #67 ; 0x43 + 800bf1a: 4639 mov r1, r7 + 800bf1c: 4630 mov r0, r6 + 800bf1e: 47c0 blx r8 + 800bf20: 3001 adds r0, #1 + 800bf22: d020 beq.n 800bf66 <_printf_common+0xb2> + 800bf24: 6823 ldr r3, [r4, #0] + 800bf26: 68e5 ldr r5, [r4, #12] + 800bf28: f8d9 2000 ldr.w r2, [r9] + 800bf2c: f003 0306 and.w r3, r3, #6 + 800bf30: 2b04 cmp r3, #4 + 800bf32: bf08 it eq + 800bf34: 1aad subeq r5, r5, r2 + 800bf36: 68a3 ldr r3, [r4, #8] + 800bf38: 6922 ldr r2, [r4, #16] + 800bf3a: bf0c ite eq + 800bf3c: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800bf40: 2500 movne r5, #0 + 800bf42: 4293 cmp r3, r2 + 800bf44: bfc4 itt gt + 800bf46: 1a9b subgt r3, r3, r2 + 800bf48: 18ed addgt r5, r5, r3 + 800bf4a: f04f 0900 mov.w r9, #0 + 800bf4e: 341a adds r4, #26 + 800bf50: 454d cmp r5, r9 + 800bf52: d11a bne.n 800bf8a <_printf_common+0xd6> + 800bf54: 2000 movs r0, #0 + 800bf56: e008 b.n 800bf6a <_printf_common+0xb6> + 800bf58: 2301 movs r3, #1 + 800bf5a: 4652 mov r2, sl + 800bf5c: 4639 mov r1, r7 + 800bf5e: 4630 mov r0, r6 + 800bf60: 47c0 blx r8 + 800bf62: 3001 adds r0, #1 + 800bf64: d103 bne.n 800bf6e <_printf_common+0xba> + 800bf66: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800bf6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800bf6e: 3501 adds r5, #1 + 800bf70: e7c3 b.n 800befa <_printf_common+0x46> + 800bf72: 18e1 adds r1, r4, r3 + 800bf74: 1c5a adds r2, r3, #1 + 800bf76: 2030 movs r0, #48 ; 0x30 + 800bf78: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 800bf7c: 4422 add r2, r4 + 800bf7e: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 800bf82: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 800bf86: 3302 adds r3, #2 + 800bf88: e7c5 b.n 800bf16 <_printf_common+0x62> + 800bf8a: 2301 movs r3, #1 + 800bf8c: 4622 mov r2, r4 + 800bf8e: 4639 mov r1, r7 + 800bf90: 4630 mov r0, r6 + 800bf92: 47c0 blx r8 + 800bf94: 3001 adds r0, #1 + 800bf96: d0e6 beq.n 800bf66 <_printf_common+0xb2> + 800bf98: f109 0901 add.w r9, r9, #1 + 800bf9c: e7d8 b.n 800bf50 <_printf_common+0x9c> + ... + +0800bfa0 <_printf_i>: + 800bfa0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 800bfa4: f101 0c43 add.w ip, r1, #67 ; 0x43 + 800bfa8: 460c mov r4, r1 + 800bfaa: 7e09 ldrb r1, [r1, #24] + 800bfac: b085 sub sp, #20 + 800bfae: 296e cmp r1, #110 ; 0x6e + 800bfb0: 4617 mov r7, r2 + 800bfb2: 4606 mov r6, r0 + 800bfb4: 4698 mov r8, r3 + 800bfb6: 9a0c ldr r2, [sp, #48] ; 0x30 + 800bfb8: f000 80b3 beq.w 800c122 <_printf_i+0x182> + 800bfbc: d822 bhi.n 800c004 <_printf_i+0x64> + 800bfbe: 2963 cmp r1, #99 ; 0x63 + 800bfc0: d036 beq.n 800c030 <_printf_i+0x90> + 800bfc2: d80a bhi.n 800bfda <_printf_i+0x3a> + 800bfc4: 2900 cmp r1, #0 + 800bfc6: f000 80b9 beq.w 800c13c <_printf_i+0x19c> + 800bfca: 2958 cmp r1, #88 ; 0x58 + 800bfcc: f000 8083 beq.w 800c0d6 <_printf_i+0x136> + 800bfd0: f104 0542 add.w r5, r4, #66 ; 0x42 + 800bfd4: f884 1042 strb.w r1, [r4, #66] ; 0x42 + 800bfd8: e032 b.n 800c040 <_printf_i+0xa0> + 800bfda: 2964 cmp r1, #100 ; 0x64 + 800bfdc: d001 beq.n 800bfe2 <_printf_i+0x42> + 800bfde: 2969 cmp r1, #105 ; 0x69 + 800bfe0: d1f6 bne.n 800bfd0 <_printf_i+0x30> + 800bfe2: 6820 ldr r0, [r4, #0] + 800bfe4: 6813 ldr r3, [r2, #0] + 800bfe6: 0605 lsls r5, r0, #24 + 800bfe8: f103 0104 add.w r1, r3, #4 + 800bfec: d52a bpl.n 800c044 <_printf_i+0xa4> + 800bfee: 681b ldr r3, [r3, #0] + 800bff0: 6011 str r1, [r2, #0] + 800bff2: 2b00 cmp r3, #0 + 800bff4: da03 bge.n 800bffe <_printf_i+0x5e> + 800bff6: 222d movs r2, #45 ; 0x2d + 800bff8: 425b negs r3, r3 + 800bffa: f884 2043 strb.w r2, [r4, #67] ; 0x43 + 800bffe: 486f ldr r0, [pc, #444] ; (800c1bc <_printf_i+0x21c>) + 800c000: 220a movs r2, #10 + 800c002: e039 b.n 800c078 <_printf_i+0xd8> + 800c004: 2973 cmp r1, #115 ; 0x73 + 800c006: f000 809d beq.w 800c144 <_printf_i+0x1a4> + 800c00a: d808 bhi.n 800c01e <_printf_i+0x7e> + 800c00c: 296f cmp r1, #111 ; 0x6f + 800c00e: d020 beq.n 800c052 <_printf_i+0xb2> + 800c010: 2970 cmp r1, #112 ; 0x70 + 800c012: d1dd bne.n 800bfd0 <_printf_i+0x30> + 800c014: 6823 ldr r3, [r4, #0] + 800c016: f043 0320 orr.w r3, r3, #32 + 800c01a: 6023 str r3, [r4, #0] + 800c01c: e003 b.n 800c026 <_printf_i+0x86> + 800c01e: 2975 cmp r1, #117 ; 0x75 + 800c020: d017 beq.n 800c052 <_printf_i+0xb2> + 800c022: 2978 cmp r1, #120 ; 0x78 + 800c024: d1d4 bne.n 800bfd0 <_printf_i+0x30> + 800c026: 2378 movs r3, #120 ; 0x78 + 800c028: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 800c02c: 4864 ldr r0, [pc, #400] ; (800c1c0 <_printf_i+0x220>) + 800c02e: e055 b.n 800c0dc <_printf_i+0x13c> + 800c030: 6813 ldr r3, [r2, #0] + 800c032: 1d19 adds r1, r3, #4 + 800c034: 681b ldr r3, [r3, #0] + 800c036: 6011 str r1, [r2, #0] + 800c038: f104 0542 add.w r5, r4, #66 ; 0x42 + 800c03c: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800c040: 2301 movs r3, #1 + 800c042: e08c b.n 800c15e <_printf_i+0x1be> + 800c044: 681b ldr r3, [r3, #0] + 800c046: 6011 str r1, [r2, #0] + 800c048: f010 0f40 tst.w r0, #64 ; 0x40 + 800c04c: bf18 it ne + 800c04e: b21b sxthne r3, r3 + 800c050: e7cf b.n 800bff2 <_printf_i+0x52> + 800c052: 6813 ldr r3, [r2, #0] + 800c054: 6825 ldr r5, [r4, #0] + 800c056: 1d18 adds r0, r3, #4 + 800c058: 6010 str r0, [r2, #0] + 800c05a: 0628 lsls r0, r5, #24 + 800c05c: d501 bpl.n 800c062 <_printf_i+0xc2> + 800c05e: 681b ldr r3, [r3, #0] + 800c060: e002 b.n 800c068 <_printf_i+0xc8> + 800c062: 0668 lsls r0, r5, #25 + 800c064: d5fb bpl.n 800c05e <_printf_i+0xbe> + 800c066: 881b ldrh r3, [r3, #0] + 800c068: 4854 ldr r0, [pc, #336] ; (800c1bc <_printf_i+0x21c>) + 800c06a: 296f cmp r1, #111 ; 0x6f + 800c06c: bf14 ite ne + 800c06e: 220a movne r2, #10 + 800c070: 2208 moveq r2, #8 + 800c072: 2100 movs r1, #0 + 800c074: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 800c078: 6865 ldr r5, [r4, #4] + 800c07a: 60a5 str r5, [r4, #8] + 800c07c: 2d00 cmp r5, #0 + 800c07e: f2c0 8095 blt.w 800c1ac <_printf_i+0x20c> + 800c082: 6821 ldr r1, [r4, #0] + 800c084: f021 0104 bic.w r1, r1, #4 + 800c088: 6021 str r1, [r4, #0] + 800c08a: 2b00 cmp r3, #0 + 800c08c: d13d bne.n 800c10a <_printf_i+0x16a> + 800c08e: 2d00 cmp r5, #0 + 800c090: f040 808e bne.w 800c1b0 <_printf_i+0x210> + 800c094: 4665 mov r5, ip + 800c096: 2a08 cmp r2, #8 + 800c098: d10b bne.n 800c0b2 <_printf_i+0x112> + 800c09a: 6823 ldr r3, [r4, #0] + 800c09c: 07db lsls r3, r3, #31 + 800c09e: d508 bpl.n 800c0b2 <_printf_i+0x112> + 800c0a0: 6923 ldr r3, [r4, #16] + 800c0a2: 6862 ldr r2, [r4, #4] + 800c0a4: 429a cmp r2, r3 + 800c0a6: bfde ittt le + 800c0a8: 2330 movle r3, #48 ; 0x30 + 800c0aa: f805 3c01 strble.w r3, [r5, #-1] + 800c0ae: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff + 800c0b2: ebac 0305 sub.w r3, ip, r5 + 800c0b6: 6123 str r3, [r4, #16] + 800c0b8: f8cd 8000 str.w r8, [sp] + 800c0bc: 463b mov r3, r7 + 800c0be: aa03 add r2, sp, #12 + 800c0c0: 4621 mov r1, r4 + 800c0c2: 4630 mov r0, r6 + 800c0c4: f7ff fef6 bl 800beb4 <_printf_common> + 800c0c8: 3001 adds r0, #1 + 800c0ca: d14d bne.n 800c168 <_printf_i+0x1c8> + 800c0cc: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 800c0d0: b005 add sp, #20 + 800c0d2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 800c0d6: 4839 ldr r0, [pc, #228] ; (800c1bc <_printf_i+0x21c>) + 800c0d8: f884 1045 strb.w r1, [r4, #69] ; 0x45 + 800c0dc: 6813 ldr r3, [r2, #0] + 800c0de: 6821 ldr r1, [r4, #0] + 800c0e0: 1d1d adds r5, r3, #4 + 800c0e2: 681b ldr r3, [r3, #0] + 800c0e4: 6015 str r5, [r2, #0] + 800c0e6: 060a lsls r2, r1, #24 + 800c0e8: d50b bpl.n 800c102 <_printf_i+0x162> + 800c0ea: 07ca lsls r2, r1, #31 + 800c0ec: bf44 itt mi + 800c0ee: f041 0120 orrmi.w r1, r1, #32 + 800c0f2: 6021 strmi r1, [r4, #0] + 800c0f4: b91b cbnz r3, 800c0fe <_printf_i+0x15e> + 800c0f6: 6822 ldr r2, [r4, #0] + 800c0f8: f022 0220 bic.w r2, r2, #32 + 800c0fc: 6022 str r2, [r4, #0] + 800c0fe: 2210 movs r2, #16 + 800c100: e7b7 b.n 800c072 <_printf_i+0xd2> + 800c102: 064d lsls r5, r1, #25 + 800c104: bf48 it mi + 800c106: b29b uxthmi r3, r3 + 800c108: e7ef b.n 800c0ea <_printf_i+0x14a> + 800c10a: 4665 mov r5, ip + 800c10c: fbb3 f1f2 udiv r1, r3, r2 + 800c110: fb02 3311 mls r3, r2, r1, r3 + 800c114: 5cc3 ldrb r3, [r0, r3] + 800c116: f805 3d01 strb.w r3, [r5, #-1]! + 800c11a: 460b mov r3, r1 + 800c11c: 2900 cmp r1, #0 + 800c11e: d1f5 bne.n 800c10c <_printf_i+0x16c> + 800c120: e7b9 b.n 800c096 <_printf_i+0xf6> + 800c122: 6813 ldr r3, [r2, #0] + 800c124: 6825 ldr r5, [r4, #0] + 800c126: 6961 ldr r1, [r4, #20] + 800c128: 1d18 adds r0, r3, #4 + 800c12a: 6010 str r0, [r2, #0] + 800c12c: 0628 lsls r0, r5, #24 + 800c12e: 681b ldr r3, [r3, #0] + 800c130: d501 bpl.n 800c136 <_printf_i+0x196> + 800c132: 6019 str r1, [r3, #0] + 800c134: e002 b.n 800c13c <_printf_i+0x19c> + 800c136: 066a lsls r2, r5, #25 + 800c138: d5fb bpl.n 800c132 <_printf_i+0x192> + 800c13a: 8019 strh r1, [r3, #0] + 800c13c: 2300 movs r3, #0 + 800c13e: 6123 str r3, [r4, #16] + 800c140: 4665 mov r5, ip + 800c142: e7b9 b.n 800c0b8 <_printf_i+0x118> + 800c144: 6813 ldr r3, [r2, #0] + 800c146: 1d19 adds r1, r3, #4 + 800c148: 6011 str r1, [r2, #0] + 800c14a: 681d ldr r5, [r3, #0] + 800c14c: 6862 ldr r2, [r4, #4] + 800c14e: 2100 movs r1, #0 + 800c150: 4628 mov r0, r5 + 800c152: f7f4 f85d bl 8000210 + 800c156: b108 cbz r0, 800c15c <_printf_i+0x1bc> + 800c158: 1b40 subs r0, r0, r5 + 800c15a: 6060 str r0, [r4, #4] + 800c15c: 6863 ldr r3, [r4, #4] + 800c15e: 6123 str r3, [r4, #16] + 800c160: 2300 movs r3, #0 + 800c162: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800c166: e7a7 b.n 800c0b8 <_printf_i+0x118> + 800c168: 6923 ldr r3, [r4, #16] + 800c16a: 462a mov r2, r5 + 800c16c: 4639 mov r1, r7 + 800c16e: 4630 mov r0, r6 + 800c170: 47c0 blx r8 + 800c172: 3001 adds r0, #1 + 800c174: d0aa beq.n 800c0cc <_printf_i+0x12c> + 800c176: 6823 ldr r3, [r4, #0] + 800c178: 079b lsls r3, r3, #30 + 800c17a: d413 bmi.n 800c1a4 <_printf_i+0x204> + 800c17c: 68e0 ldr r0, [r4, #12] + 800c17e: 9b03 ldr r3, [sp, #12] + 800c180: 4298 cmp r0, r3 + 800c182: bfb8 it lt + 800c184: 4618 movlt r0, r3 + 800c186: e7a3 b.n 800c0d0 <_printf_i+0x130> + 800c188: 2301 movs r3, #1 + 800c18a: 464a mov r2, r9 + 800c18c: 4639 mov r1, r7 + 800c18e: 4630 mov r0, r6 + 800c190: 47c0 blx r8 + 800c192: 3001 adds r0, #1 + 800c194: d09a beq.n 800c0cc <_printf_i+0x12c> + 800c196: 3501 adds r5, #1 + 800c198: 68e3 ldr r3, [r4, #12] + 800c19a: 9a03 ldr r2, [sp, #12] + 800c19c: 1a9b subs r3, r3, r2 + 800c19e: 42ab cmp r3, r5 + 800c1a0: dcf2 bgt.n 800c188 <_printf_i+0x1e8> + 800c1a2: e7eb b.n 800c17c <_printf_i+0x1dc> + 800c1a4: 2500 movs r5, #0 + 800c1a6: f104 0919 add.w r9, r4, #25 + 800c1aa: e7f5 b.n 800c198 <_printf_i+0x1f8> + 800c1ac: 2b00 cmp r3, #0 + 800c1ae: d1ac bne.n 800c10a <_printf_i+0x16a> + 800c1b0: 7803 ldrb r3, [r0, #0] + 800c1b2: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800c1b6: f104 0542 add.w r5, r4, #66 ; 0x42 + 800c1ba: e76c b.n 800c096 <_printf_i+0xf6> + 800c1bc: 0800e3a1 .word 0x0800e3a1 + 800c1c0: 0800e3b2 .word 0x0800e3b2 + +0800c1c4 : + 800c1c4: 4288 cmp r0, r1 + 800c1c6: b510 push {r4, lr} + 800c1c8: eb01 0302 add.w r3, r1, r2 + 800c1cc: d807 bhi.n 800c1de + 800c1ce: 1e42 subs r2, r0, #1 + 800c1d0: 4299 cmp r1, r3 + 800c1d2: d00a beq.n 800c1ea + 800c1d4: f811 4b01 ldrb.w r4, [r1], #1 + 800c1d8: f802 4f01 strb.w r4, [r2, #1]! + 800c1dc: e7f8 b.n 800c1d0 + 800c1de: 4283 cmp r3, r0 + 800c1e0: d9f5 bls.n 800c1ce + 800c1e2: 1881 adds r1, r0, r2 + 800c1e4: 1ad2 subs r2, r2, r3 + 800c1e6: 42d3 cmn r3, r2 + 800c1e8: d100 bne.n 800c1ec + 800c1ea: bd10 pop {r4, pc} + 800c1ec: f813 4d01 ldrb.w r4, [r3, #-1]! + 800c1f0: f801 4d01 strb.w r4, [r1, #-1]! + 800c1f4: e7f7 b.n 800c1e6 + ... + +0800c1f8 <_free_r>: + 800c1f8: b538 push {r3, r4, r5, lr} + 800c1fa: 4605 mov r5, r0 + 800c1fc: 2900 cmp r1, #0 + 800c1fe: d045 beq.n 800c28c <_free_r+0x94> + 800c200: f851 3c04 ldr.w r3, [r1, #-4] + 800c204: 1f0c subs r4, r1, #4 + 800c206: 2b00 cmp r3, #0 + 800c208: bfb8 it lt + 800c20a: 18e4 addlt r4, r4, r3 + 800c20c: f000 f8d2 bl 800c3b4 <__malloc_lock> + 800c210: 4a1f ldr r2, [pc, #124] ; (800c290 <_free_r+0x98>) + 800c212: 6813 ldr r3, [r2, #0] + 800c214: 4610 mov r0, r2 + 800c216: b933 cbnz r3, 800c226 <_free_r+0x2e> + 800c218: 6063 str r3, [r4, #4] + 800c21a: 6014 str r4, [r2, #0] + 800c21c: 4628 mov r0, r5 + 800c21e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800c222: f000 b8c8 b.w 800c3b6 <__malloc_unlock> + 800c226: 42a3 cmp r3, r4 + 800c228: d90c bls.n 800c244 <_free_r+0x4c> + 800c22a: 6821 ldr r1, [r4, #0] + 800c22c: 1862 adds r2, r4, r1 + 800c22e: 4293 cmp r3, r2 + 800c230: bf04 itt eq + 800c232: 681a ldreq r2, [r3, #0] + 800c234: 685b ldreq r3, [r3, #4] + 800c236: 6063 str r3, [r4, #4] + 800c238: bf04 itt eq + 800c23a: 1852 addeq r2, r2, r1 + 800c23c: 6022 streq r2, [r4, #0] + 800c23e: 6004 str r4, [r0, #0] + 800c240: e7ec b.n 800c21c <_free_r+0x24> + 800c242: 4613 mov r3, r2 + 800c244: 685a ldr r2, [r3, #4] + 800c246: b10a cbz r2, 800c24c <_free_r+0x54> + 800c248: 42a2 cmp r2, r4 + 800c24a: d9fa bls.n 800c242 <_free_r+0x4a> + 800c24c: 6819 ldr r1, [r3, #0] + 800c24e: 1858 adds r0, r3, r1 + 800c250: 42a0 cmp r0, r4 + 800c252: d10b bne.n 800c26c <_free_r+0x74> + 800c254: 6820 ldr r0, [r4, #0] + 800c256: 4401 add r1, r0 + 800c258: 1858 adds r0, r3, r1 + 800c25a: 4282 cmp r2, r0 + 800c25c: 6019 str r1, [r3, #0] + 800c25e: d1dd bne.n 800c21c <_free_r+0x24> + 800c260: 6810 ldr r0, [r2, #0] + 800c262: 6852 ldr r2, [r2, #4] + 800c264: 605a str r2, [r3, #4] + 800c266: 4401 add r1, r0 + 800c268: 6019 str r1, [r3, #0] + 800c26a: e7d7 b.n 800c21c <_free_r+0x24> + 800c26c: d902 bls.n 800c274 <_free_r+0x7c> + 800c26e: 230c movs r3, #12 + 800c270: 602b str r3, [r5, #0] + 800c272: e7d3 b.n 800c21c <_free_r+0x24> + 800c274: 6820 ldr r0, [r4, #0] + 800c276: 1821 adds r1, r4, r0 + 800c278: 428a cmp r2, r1 + 800c27a: bf04 itt eq + 800c27c: 6811 ldreq r1, [r2, #0] + 800c27e: 6852 ldreq r2, [r2, #4] + 800c280: 6062 str r2, [r4, #4] + 800c282: bf04 itt eq + 800c284: 1809 addeq r1, r1, r0 + 800c286: 6021 streq r1, [r4, #0] + 800c288: 605c str r4, [r3, #4] + 800c28a: e7c7 b.n 800c21c <_free_r+0x24> + 800c28c: bd38 pop {r3, r4, r5, pc} + 800c28e: bf00 nop + 800c290: 20008430 .word 0x20008430 + +0800c294 <_malloc_r>: + 800c294: b570 push {r4, r5, r6, lr} + 800c296: 1ccd adds r5, r1, #3 + 800c298: f025 0503 bic.w r5, r5, #3 + 800c29c: 3508 adds r5, #8 + 800c29e: 2d0c cmp r5, #12 + 800c2a0: bf38 it cc + 800c2a2: 250c movcc r5, #12 + 800c2a4: 2d00 cmp r5, #0 + 800c2a6: 4606 mov r6, r0 + 800c2a8: db01 blt.n 800c2ae <_malloc_r+0x1a> + 800c2aa: 42a9 cmp r1, r5 + 800c2ac: d903 bls.n 800c2b6 <_malloc_r+0x22> + 800c2ae: 230c movs r3, #12 + 800c2b0: 6033 str r3, [r6, #0] + 800c2b2: 2000 movs r0, #0 + 800c2b4: bd70 pop {r4, r5, r6, pc} + 800c2b6: f000 f87d bl 800c3b4 <__malloc_lock> + 800c2ba: 4a21 ldr r2, [pc, #132] ; (800c340 <_malloc_r+0xac>) + 800c2bc: 6814 ldr r4, [r2, #0] + 800c2be: 4621 mov r1, r4 + 800c2c0: b991 cbnz r1, 800c2e8 <_malloc_r+0x54> + 800c2c2: 4c20 ldr r4, [pc, #128] ; (800c344 <_malloc_r+0xb0>) + 800c2c4: 6823 ldr r3, [r4, #0] + 800c2c6: b91b cbnz r3, 800c2d0 <_malloc_r+0x3c> + 800c2c8: 4630 mov r0, r6 + 800c2ca: f000 f863 bl 800c394 <_sbrk_r> + 800c2ce: 6020 str r0, [r4, #0] + 800c2d0: 4629 mov r1, r5 + 800c2d2: 4630 mov r0, r6 + 800c2d4: f000 f85e bl 800c394 <_sbrk_r> + 800c2d8: 1c43 adds r3, r0, #1 + 800c2da: d124 bne.n 800c326 <_malloc_r+0x92> + 800c2dc: 230c movs r3, #12 + 800c2de: 6033 str r3, [r6, #0] + 800c2e0: 4630 mov r0, r6 + 800c2e2: f000 f868 bl 800c3b6 <__malloc_unlock> + 800c2e6: e7e4 b.n 800c2b2 <_malloc_r+0x1e> + 800c2e8: 680b ldr r3, [r1, #0] + 800c2ea: 1b5b subs r3, r3, r5 + 800c2ec: d418 bmi.n 800c320 <_malloc_r+0x8c> + 800c2ee: 2b0b cmp r3, #11 + 800c2f0: d90f bls.n 800c312 <_malloc_r+0x7e> + 800c2f2: 600b str r3, [r1, #0] + 800c2f4: 50cd str r5, [r1, r3] + 800c2f6: 18cc adds r4, r1, r3 + 800c2f8: 4630 mov r0, r6 + 800c2fa: f000 f85c bl 800c3b6 <__malloc_unlock> + 800c2fe: f104 000b add.w r0, r4, #11 + 800c302: 1d23 adds r3, r4, #4 + 800c304: f020 0007 bic.w r0, r0, #7 + 800c308: 1ac3 subs r3, r0, r3 + 800c30a: d0d3 beq.n 800c2b4 <_malloc_r+0x20> + 800c30c: 425a negs r2, r3 + 800c30e: 50e2 str r2, [r4, r3] + 800c310: e7d0 b.n 800c2b4 <_malloc_r+0x20> + 800c312: 428c cmp r4, r1 + 800c314: 684b ldr r3, [r1, #4] + 800c316: bf16 itet ne + 800c318: 6063 strne r3, [r4, #4] + 800c31a: 6013 streq r3, [r2, #0] + 800c31c: 460c movne r4, r1 + 800c31e: e7eb b.n 800c2f8 <_malloc_r+0x64> + 800c320: 460c mov r4, r1 + 800c322: 6849 ldr r1, [r1, #4] + 800c324: e7cc b.n 800c2c0 <_malloc_r+0x2c> + 800c326: 1cc4 adds r4, r0, #3 + 800c328: f024 0403 bic.w r4, r4, #3 + 800c32c: 42a0 cmp r0, r4 + 800c32e: d005 beq.n 800c33c <_malloc_r+0xa8> + 800c330: 1a21 subs r1, r4, r0 + 800c332: 4630 mov r0, r6 + 800c334: f000 f82e bl 800c394 <_sbrk_r> + 800c338: 3001 adds r0, #1 + 800c33a: d0cf beq.n 800c2dc <_malloc_r+0x48> + 800c33c: 6025 str r5, [r4, #0] + 800c33e: e7db b.n 800c2f8 <_malloc_r+0x64> + 800c340: 20008430 .word 0x20008430 + 800c344: 20008434 .word 0x20008434 + +0800c348 <_realloc_r>: + 800c348: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c34a: 4607 mov r7, r0 + 800c34c: 4614 mov r4, r2 + 800c34e: 460e mov r6, r1 + 800c350: b921 cbnz r1, 800c35c <_realloc_r+0x14> + 800c352: 4611 mov r1, r2 + 800c354: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} + 800c358: f7ff bf9c b.w 800c294 <_malloc_r> + 800c35c: b922 cbnz r2, 800c368 <_realloc_r+0x20> + 800c35e: f7ff ff4b bl 800c1f8 <_free_r> + 800c362: 4625 mov r5, r4 + 800c364: 4628 mov r0, r5 + 800c366: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800c368: f000 f826 bl 800c3b8 <_malloc_usable_size_r> + 800c36c: 42a0 cmp r0, r4 + 800c36e: d20f bcs.n 800c390 <_realloc_r+0x48> + 800c370: 4621 mov r1, r4 + 800c372: 4638 mov r0, r7 + 800c374: f7ff ff8e bl 800c294 <_malloc_r> + 800c378: 4605 mov r5, r0 + 800c37a: 2800 cmp r0, #0 + 800c37c: d0f2 beq.n 800c364 <_realloc_r+0x1c> + 800c37e: 4631 mov r1, r6 + 800c380: 4622 mov r2, r4 + 800c382: f7ff fc11 bl 800bba8 + 800c386: 4631 mov r1, r6 + 800c388: 4638 mov r0, r7 + 800c38a: f7ff ff35 bl 800c1f8 <_free_r> + 800c38e: e7e9 b.n 800c364 <_realloc_r+0x1c> + 800c390: 4635 mov r5, r6 + 800c392: e7e7 b.n 800c364 <_realloc_r+0x1c> + +0800c394 <_sbrk_r>: + 800c394: b538 push {r3, r4, r5, lr} + 800c396: 4c06 ldr r4, [pc, #24] ; (800c3b0 <_sbrk_r+0x1c>) + 800c398: 2300 movs r3, #0 + 800c39a: 4605 mov r5, r0 + 800c39c: 4608 mov r0, r1 + 800c39e: 6023 str r3, [r4, #0] + 800c3a0: f7f8 f810 bl 80043c4 <_sbrk> + 800c3a4: 1c43 adds r3, r0, #1 + 800c3a6: d102 bne.n 800c3ae <_sbrk_r+0x1a> + 800c3a8: 6823 ldr r3, [r4, #0] + 800c3aa: b103 cbz r3, 800c3ae <_sbrk_r+0x1a> + 800c3ac: 602b str r3, [r5, #0] + 800c3ae: bd38 pop {r3, r4, r5, pc} + 800c3b0: 20008af8 .word 0x20008af8 + +0800c3b4 <__malloc_lock>: + 800c3b4: 4770 bx lr + +0800c3b6 <__malloc_unlock>: + 800c3b6: 4770 bx lr + +0800c3b8 <_malloc_usable_size_r>: + 800c3b8: f851 3c04 ldr.w r3, [r1, #-4] + 800c3bc: 1f18 subs r0, r3, #4 + 800c3be: 2b00 cmp r3, #0 + 800c3c0: bfbc itt lt + 800c3c2: 580b ldrlt r3, [r1, r0] + 800c3c4: 18c0 addlt r0, r0, r3 + 800c3c6: 4770 bx lr + +0800c3c8 <_init>: + 800c3c8: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c3ca: bf00 nop + 800c3cc: bcf8 pop {r3, r4, r5, r6, r7} + 800c3ce: bc08 pop {r3} + 800c3d0: 469e mov lr, r3 + 800c3d2: 4770 bx lr + +0800c3d4 <_fini>: + 800c3d4: b5f8 push {r3, r4, r5, r6, r7, lr} + 800c3d6: bf00 nop + 800c3d8: bcf8 pop {r3, r4, r5, r6, r7} + 800c3da: bc08 pop {r3} + 800c3dc: 469e mov lr, r3 + 800c3de: 4770 bx lr diff --git a/Debug/prog_demo_2021.map b/Debug/prog_demo_2021.map new file mode 100644 index 0000000..b60cb31 --- /dev/null +++ b/Debug/prog_demo_2021.map @@ -0,0 +1,10116 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + Core/Src/syscalls.o (__errno) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (exit) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (__libc_init_array) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + Middlewares/Third_Party/FreeRTOS/Source/queue.o (memcpy) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (memset) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + Core/Src/main.o (sprintf) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) (_svfprintf_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (_printf_i) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memchr.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (memchr) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (memmove) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (_free_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (_malloc_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) (_realloc_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) (__malloc_lock) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) (_malloc_usable_size_r) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) (errno) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o (__aeabi_uldivmod) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) +/opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_dvmd_tls.o) + /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0) + +Allocating common symbols +Common symbol size file + +sdramHandle 0x34 Core/Src/stm32746g_discovery_sdram.o +defaultTaskHandle 0x4 Core/Src/main.o +hi2c3 0x4c Core/Src/main.o +hspi2 0x64 Core/Src/main.o +huart7 0x80 Core/Src/main.o +htim8 0x40 Core/Src/main.o +errno 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) +hi2c1 0x4c Core/Src/main.o +hLtdcHandler 0xa8 Core/Src/stm32746g_discovery_lcd.o +uwTick 0x4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o +xQueueRegistry 0x40 Middlewares/Third_Party/FreeRTOS/Source/queue.o +pFlash 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o +htim5 0x40 Core/Src/main.o +htim3 0x40 Core/Src/main.o +hltdc 0xa8 Core/Src/main.o +hadc1 0x48 Core/Src/main.o +hadc3 0x48 Core/Src/main.o +huart1 0x80 Core/Src/main.o +hdac 0x14 Core/Src/main.o +hrtc 0x20 Core/Src/main.o +htim6 0x40 Core/Src/stm32f7xx_hal_timebase_tim.o +htim1 0x40 Core/Src/main.o +huart6 0x80 Core/Src/main.o +hdma2d 0x40 Core/Src/main.o +htim2 0x40 Core/Src/main.o +hsdram1 0x34 Core/Src/main.o + +Discarded input sections + + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .data 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + .text 0x0000000000000000 0x74 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .ARM.exidx 0x0000000000000000 0x8 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .ARM.attributes + 0x0000000000000000 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/freertos.o + .text 0x0000000000000000 0x0 Core/Src/freertos.o + .data 0x0000000000000000 0x0 Core/Src/freertos.o + .bss 0x0000000000000000 0x0 Core/Src/freertos.o + .text.vApplicationIdleHook + 0x0000000000000000 0xe Core/Src/freertos.o + .bss.xIdleTaskTCBBuffer + 0x0000000000000000 0x58 Core/Src/freertos.o + .bss.xIdleStack + 0x0000000000000000 0x200 Core/Src/freertos.o + .text.vApplicationGetIdleTaskMemory + 0x0000000000000000 0x34 Core/Src/freertos.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/ft5336.o + .text 0x0000000000000000 0x0 Core/Src/ft5336.o + .data 0x0000000000000000 0x0 Core/Src/ft5336.o + .bss 0x0000000000000000 0x0 Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0x22 Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0x8e Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0x51 Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0xef Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0x6a Core/Src/ft5336.o + .debug_macro 0x0000000000000000 0x1df Core/Src/ft5336.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .text 0x0000000000000000 0x0 Core/Src/main.o + .data 0x0000000000000000 0x0 Core/Src/main.o + .bss 0x0000000000000000 0x0 Core/Src/main.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/main.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/main.o + .debug_macro 0x0000000000000000 0x2e Core/Src/main.o + .debug_macro 0x0000000000000000 0x3b Core/Src/main.o + .debug_macro 0x0000000000000000 0x22 Core/Src/main.o + .debug_macro 0x0000000000000000 0x8e Core/Src/main.o + .debug_macro 0x0000000000000000 0x51 Core/Src/main.o + .debug_macro 0x0000000000000000 0xef Core/Src/main.o + .debug_macro 0x0000000000000000 0x6a Core/Src/main.o + .debug_macro 0x0000000000000000 0x1df Core/Src/main.o + .debug_macro 0x0000000000000000 0x1c Core/Src/main.o + .debug_macro 0x0000000000000000 0x22 Core/Src/main.o + .debug_macro 0x0000000000000000 0xdf Core/Src/main.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/main.o + .debug_macro 0x0000000000000000 0x11f Core/Src/main.o + .debug_macro 0x0000000000000000 0x19 Core/Src/main.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/main.o + .debug_macro 0x0000000000000000 0x43 Core/Src/main.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/main.o + .debug_macro 0x0000000000000000 0x174 Core/Src/main.o + .debug_macro 0x0000000000000000 0x61 Core/Src/main.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/main.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/main.o + .debug_macro 0x0000000000000000 0x185 Core/Src/main.o + .debug_macro 0x0000000000000000 0x117 Core/Src/main.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/main.o + .debug_macro 0x0000000000000000 0x27 Core/Src/main.o + .debug_macro 0x0000000000000000 0x24f Core/Src/main.o + .debug_macro 0x0000000000000000 0x41 Core/Src/main.o + .debug_macro 0x0000000000000000 0x58 Core/Src/main.o + .debug_macro 0x0000000000000000 0x236 Core/Src/main.o + .debug_macro 0x0000000000000000 0x416 Core/Src/main.o + .debug_macro 0x0000000000000000 0x153 Core/Src/main.o + .debug_macro 0x0000000000000000 0x107 Core/Src/main.o + .debug_macro 0x0000000000000000 0x20f Core/Src/main.o + .debug_macro 0x0000000000000000 0xea Core/Src/main.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/main.o + .debug_macro 0x0000000000000000 0x3c Core/Src/main.o + .debug_macro 0x0000000000000000 0x14f Core/Src/main.o + .debug_macro 0x0000000000000000 0x25b Core/Src/main.o + .debug_macro 0x0000000000000000 0x12 Core/Src/main.o + .debug_macro 0x0000000000000000 0x514 Core/Src/main.o + .debug_macro 0x0000000000000000 0x22c Core/Src/main.o + .debug_macro 0x0000000000000000 0x5a Core/Src/main.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/main.o + .debug_macro 0x0000000000000000 0x198 Core/Src/main.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/main.o + .debug_macro 0x0000000000000000 0x12f Core/Src/main.o + .debug_macro 0x0000000000000000 0x108 Core/Src/main.o + .debug_macro 0x0000000000000000 0x35 Core/Src/main.o + .debug_macro 0x0000000000000000 0x313 Core/Src/main.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/main.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/main.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/main.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/main.o + .debug_macro 0x0000000000000000 0x59 Core/Src/main.o + .debug_macro 0x0000000000000000 0x53c Core/Src/main.o + .debug_macro 0x0000000000000000 0x44 Core/Src/main.o + .debug_macro 0x0000000000000000 0x14e Core/Src/main.o + .debug_macro 0x0000000000000000 0x3f9 Core/Src/main.o + .debug_macro 0x0000000000000000 0x15a Core/Src/main.o + .debug_macro 0x0000000000000000 0xde Core/Src/main.o + .debug_macro 0x0000000000000000 0x1c Core/Src/main.o + .debug_macro 0x0000000000000000 0x26 Core/Src/main.o + .debug_macro 0x0000000000000000 0x4c5 Core/Src/main.o + .debug_macro 0x0000000000000000 0xb5 Core/Src/main.o + .debug_macro 0x0000000000000000 0xaa Core/Src/main.o + .debug_macro 0x0000000000000000 0x10 Core/Src/main.o + .debug_macro 0x0000000000000000 0x39f Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .text 0x0000000000000000 0x0 Core/Src/stm32746g_discovery.o + .data 0x0000000000000000 0x0 Core/Src/stm32746g_discovery.o + .bss 0x0000000000000000 0x0 Core/Src/stm32746g_discovery.o + .rodata.GPIO_PIN + 0x0000000000000000 0x4 Core/Src/stm32746g_discovery.o + .data.BUTTON_PORT + 0x0000000000000000 0xc Core/Src/stm32746g_discovery.o + .rodata.BUTTON_PIN + 0x0000000000000000 0x6 Core/Src/stm32746g_discovery.o + .rodata.BUTTON_IRQn + 0x0000000000000000 0x6 Core/Src/stm32746g_discovery.o + .data.COM_USART + 0x0000000000000000 0x4 Core/Src/stm32746g_discovery.o + .data.COM_TX_PORT + 0x0000000000000000 0x4 Core/Src/stm32746g_discovery.o + .data.COM_RX_PORT + 0x0000000000000000 0x4 Core/Src/stm32746g_discovery.o + .rodata.COM_TX_PIN + 0x0000000000000000 0x2 Core/Src/stm32746g_discovery.o + .rodata.COM_RX_PIN + 0x0000000000000000 0x2 Core/Src/stm32746g_discovery.o + .rodata.COM_TX_AF + 0x0000000000000000 0x2 Core/Src/stm32746g_discovery.o + .rodata.COM_RX_AF + 0x0000000000000000 0x2 Core/Src/stm32746g_discovery.o + .bss.hI2cExtHandler + 0x0000000000000000 0x4c Core/Src/stm32746g_discovery.o + .text.BSP_GetVersion + 0x0000000000000000 0x12 Core/Src/stm32746g_discovery.o + .text.BSP_LED_Init + 0x0000000000000000 0x68 Core/Src/stm32746g_discovery.o + .text.BSP_LED_DeInit + 0x0000000000000000 0x3c Core/Src/stm32746g_discovery.o + .text.BSP_LED_On + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery.o + .text.BSP_LED_Off + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery.o + .text.BSP_LED_Toggle + 0x0000000000000000 0x2c Core/Src/stm32746g_discovery.o + .text.BSP_PB_Init + 0x0000000000000000 0x118 Core/Src/stm32746g_discovery.o + .text.BSP_PB_DeInit + 0x0000000000000000 0x4c Core/Src/stm32746g_discovery.o + .text.BSP_PB_GetState + 0x0000000000000000 0x34 Core/Src/stm32746g_discovery.o + .text.BSP_COM_Init + 0x0000000000000000 0xdc Core/Src/stm32746g_discovery.o + .text.BSP_COM_DeInit + 0x0000000000000000 0x40 Core/Src/stm32746g_discovery.o + .text.I2Cx_IsDeviceReady + 0x0000000000000000 0x26 Core/Src/stm32746g_discovery.o + .text.AUDIO_IO_Init + 0x0000000000000000 0x14 Core/Src/stm32746g_discovery.o + .text.AUDIO_IO_DeInit + 0x0000000000000000 0xe Core/Src/stm32746g_discovery.o + .text.AUDIO_IO_Write + 0x0000000000000000 0x54 Core/Src/stm32746g_discovery.o + .text.AUDIO_IO_Read + 0x0000000000000000 0x58 Core/Src/stm32746g_discovery.o + .text.AUDIO_IO_Delay + 0x0000000000000000 0x16 Core/Src/stm32746g_discovery.o + .text.CAMERA_IO_Init + 0x0000000000000000 0x14 Core/Src/stm32746g_discovery.o + .text.CAMERA_IO_Write + 0x0000000000000000 0x34 Core/Src/stm32746g_discovery.o + .text.CAMERA_IO_Read + 0x0000000000000000 0x3c Core/Src/stm32746g_discovery.o + .text.CAMERA_Delay + 0x0000000000000000 0x16 Core/Src/stm32746g_discovery.o + .text.EEPROM_IO_Init + 0x0000000000000000 0x14 Core/Src/stm32746g_discovery.o + .text.EEPROM_IO_WriteData + 0x0000000000000000 0x38 Core/Src/stm32746g_discovery.o + .text.EEPROM_IO_ReadData + 0x0000000000000000 0x38 Core/Src/stm32746g_discovery.o + .text.EEPROM_IO_IsDeviceReady + 0x0000000000000000 0x28 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32746g_discovery.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32746g_discovery.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_lcd.o + .text 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_lcd.o + .data 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_lcd.o + .bss 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_lcd.o + .rodata.Font20_Table + 0x0000000000000000 0xed8 Core/Src/stm32746g_discovery_lcd.o + .data.Font20 0x0000000000000000 0x8 Core/Src/stm32746g_discovery_lcd.o + .rodata.Font16_Table + 0x0000000000000000 0xbe0 Core/Src/stm32746g_discovery_lcd.o + .data.Font16 0x0000000000000000 0x8 Core/Src/stm32746g_discovery_lcd.o + .rodata.Font8_Table + 0x0000000000000000 0x2f8 Core/Src/stm32746g_discovery_lcd.o + .data.Font8 0x0000000000000000 0x8 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DeInit + 0x0000000000000000 0x38 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetXSize + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetYSize + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_LayerRgb565Init + 0x0000000000000000 0xc0 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerVisible + 0x0000000000000000 0x7c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerVisible_NoReload + 0x0000000000000000 0x6c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetTransparency + 0x0000000000000000 0x24 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetTransparency_NoReload + 0x0000000000000000 0x24 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerAddress + 0x0000000000000000 0x20 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerAddress_NoReload + 0x0000000000000000 0x20 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerWindow + 0x0000000000000000 0x44 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetLayerWindow_NoReload + 0x0000000000000000 0x44 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetColorKeying + 0x0000000000000000 0x28 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_SetColorKeying_NoReload + 0x0000000000000000 0x28 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_ResetColorKeying + 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_ResetColorKeying_NoReload + 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_Reload + 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_GetTextColor + 0x0000000000000000 0x28 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_GetBackColor + 0x0000000000000000 0x2c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_ReadPixel + 0x0000000000000000 0x14c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_ClearStringLine + 0x0000000000000000 0xc8 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawVLine + 0x0000000000000000 0xc4 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawLine + 0x0000000000000000 0x198 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawRect + 0x0000000000000000 0x62 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawPolygon + 0x0000000000000000 0x9a Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawEllipse + 0x0000000000000000 0x1f0 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DrawBitmap + 0x0000000000000000 0x160 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_FillRect + 0x0000000000000000 0xf4 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_FillPolygon + 0x0000000000000000 0x1c8 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_FillEllipse + 0x0000000000000000 0x172 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_DisplayOff + 0x0000000000000000 0x3c Core/Src/stm32746g_discovery_lcd.o + .text.BSP_LCD_MspDeInit + 0x0000000000000000 0x94 Core/Src/stm32746g_discovery_lcd.o + .text.FillTriangle + 0x0000000000000000 0x17e Core/Src/stm32746g_discovery_lcd.o + .text.LL_ConvertLineToARGB8888 + 0x0000000000000000 0x88 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x40 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x268 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x10 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000000000 0x12a Core/Src/stm32746g_discovery_lcd.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_sdram.o + .text 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_sdram.o + .data 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_sdram.o + .bss 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_DeInit + 0x0000000000000000 0x40 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_ReadData + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_ReadData_DMA + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_WriteData + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_WriteData_DMA + 0x0000000000000000 0x30 Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_Sendcmd + 0x0000000000000000 0x2c Core/Src/stm32746g_discovery_sdram.o + .text.BSP_SDRAM_MspDeInit + 0x0000000000000000 0x2c Core/Src/stm32746g_discovery_sdram.o + .data.sdramstatus.9796 + 0x0000000000000000 0x1 Core/Src/stm32746g_discovery_sdram.o + .bss.dma_handle.9842 + 0x0000000000000000 0x60 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x0000000000000000 0x9a Core/Src/stm32746g_discovery_sdram.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32746g_discovery_ts.o + .text 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_ts.o + .data 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_ts.o + .bss 0x0000000000000000 0x0 Core/Src/stm32746g_discovery_ts.o + .text.BSP_TS_DeInit + 0x0000000000000000 0x10 Core/Src/stm32746g_discovery_ts.o + .text.BSP_TS_ITConfig + 0x0000000000000000 0x5c Core/Src/stm32746g_discovery_ts.o + .text.BSP_TS_ITGetStatus + 0x0000000000000000 0x24 Core/Src/stm32746g_discovery_ts.o + .text.BSP_TS_ITClear + 0x0000000000000000 0x20 Core/Src/stm32746g_discovery_ts.o + .text.BSP_TS_ResetTouchData + 0x0000000000000000 0x80 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x262 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x10 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x39f Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32746g_discovery_ts.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_msp.o + .text 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_msp.o + .data 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_msp.o + .bss 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_ADC_MspDeInit + 0x0000000000000000 0x64 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_DAC_MspDeInit + 0x0000000000000000 0x40 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_DMA2D_MspDeInit + 0x0000000000000000 0x34 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_LTDC_MspDeInit + 0x0000000000000000 0x78 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_RTC_MspDeInit + 0x0000000000000000 0x34 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_SPI_MspDeInit + 0x0000000000000000 0x48 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0xa0 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_UART_MspDeInit + 0x0000000000000000 0x98 Core/Src/stm32f7xx_hal_msp.o + .bss.FMC_DeInitialized + 0x0000000000000000 0x4 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_FMC_MspDeInit + 0x0000000000000000 0x7c Core/Src/stm32f7xx_hal_msp.o + .text.HAL_SDRAM_MspDeInit + 0x0000000000000000 0x14 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3f9 Core/Src/stm32f7xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_hal_timebase_tim.o + .text 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_timebase_tim.o + .data 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_timebase_tim.o + .bss 0x0000000000000000 0x0 Core/Src/stm32f7xx_hal_timebase_tim.o + .text.HAL_SuspendTick + 0x0000000000000000 0x24 Core/Src/stm32f7xx_hal_timebase_tim.o + .text.HAL_ResumeTick + 0x0000000000000000 0x24 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32f7xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f7xx_it.o + .text 0x0000000000000000 0x0 Core/Src/stm32f7xx_it.o + .data 0x0000000000000000 0x0 Core/Src/stm32f7xx_it.o + .bss 0x0000000000000000 0x0 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x3b Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x19 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x61 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x185 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x24f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x41 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x153 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x107 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x20f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xea Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x14f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x25b Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x12 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x514 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x198 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x12f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x108 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x35 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x313 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x59 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x53c Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x44 Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x14e Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000000000 0x3f9 Core/Src/stm32f7xx_it.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .text 0x0000000000000000 0x0 Core/Src/syscalls.o + .data 0x0000000000000000 0x0 Core/Src/syscalls.o + .bss 0x0000000000000000 0x0 Core/Src/syscalls.o + .bss.__env 0x0000000000000000 0x4 Core/Src/syscalls.o + .data.environ 0x0000000000000000 0x4 Core/Src/syscalls.o + .text.initialise_monitor_handles + 0x0000000000000000 0xe Core/Src/syscalls.o + .text._getpid 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._kill 0x0000000000000000 0x20 Core/Src/syscalls.o + .text._exit 0x0000000000000000 0x14 Core/Src/syscalls.o + .text._read 0x0000000000000000 0x3a Core/Src/syscalls.o + .text._write 0x0000000000000000 0x38 Core/Src/syscalls.o + .text._close 0x0000000000000000 0x18 Core/Src/syscalls.o + .text._fstat 0x0000000000000000 0x20 Core/Src/syscalls.o + .text._isatty 0x0000000000000000 0x16 Core/Src/syscalls.o + .text._lseek 0x0000000000000000 0x1a Core/Src/syscalls.o + .text._open 0x0000000000000000 0x1c Core/Src/syscalls.o + .text._wait 0x0000000000000000 0x1e Core/Src/syscalls.o + .text._unlink 0x0000000000000000 0x1e Core/Src/syscalls.o + .text._times 0x0000000000000000 0x18 Core/Src/syscalls.o + .text._stat 0x0000000000000000 0x20 Core/Src/syscalls.o + .text._link 0x0000000000000000 0x20 Core/Src/syscalls.o + .text._fork 0x0000000000000000 0x16 Core/Src/syscalls.o + .text._execve 0x0000000000000000 0x22 Core/Src/syscalls.o + .debug_info 0x0000000000000000 0xebd Core/Src/syscalls.o + .debug_abbrev 0x0000000000000000 0x261 Core/Src/syscalls.o + .debug_aranges + 0x0000000000000000 0xa8 Core/Src/syscalls.o + .debug_ranges 0x0000000000000000 0x98 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x243 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x22 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x40 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x18 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x94 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x34 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x57 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x174 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x330 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x52 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1f Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x43 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x20 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1a3 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x6a Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x52 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x40 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x40 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xd7 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3d Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x122 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x29 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x241 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x145 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x189 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x88 Core/Src/syscalls.o + .debug_line 0x0000000000000000 0x711 Core/Src/syscalls.o + .debug_str 0x0000000000000000 0x889b Core/Src/syscalls.o + .comment 0x0000000000000000 0x7c Core/Src/syscalls.o + .debug_frame 0x0000000000000000 0x2ac Core/Src/syscalls.o + .ARM.attributes + 0x0000000000000000 0x39 Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .text 0x0000000000000000 0x0 Core/Src/sysmem.o + .data 0x0000000000000000 0x0 Core/Src/sysmem.o + .bss 0x0000000000000000 0x0 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x10 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x22 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x40 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x18 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x94 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x3c Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x34 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x174 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x57 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x52 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1f Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x43 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x20 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1a3 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xef Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x6a Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1df Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f7xx.o + .text 0x0000000000000000 0x0 Core/Src/system_stm32f7xx.o + .data 0x0000000000000000 0x0 Core/Src/system_stm32f7xx.o + .bss 0x0000000000000000 0x0 Core/Src/system_stm32f7xx.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0xf4 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x2e Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x3b Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x8e Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x51 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xef Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x6a Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x1df Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x1c Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xdf Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x12cd Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x11f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x19 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x190f0 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x43 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x2bd Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x36b4 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x174 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x61 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x18ad Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x6c4 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x185 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x117 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x1fe Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x27 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x24f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x41 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x58 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x236 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x416 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x153 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x107 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x20f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xea Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xa0 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x3c Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x14f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x25b Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x12 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x514 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x22c Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x5a Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x198 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x12f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x108 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x35 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x313 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x4ca Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xd6 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x2fe Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0xa2f Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x59 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x53c Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x44 Core/Src/system_stm32f7xx.o + .debug_macro 0x0000000000000000 0x14e Core/Src/system_stm32f7xx.o + .text 0x0000000000000000 0x14 Core/Startup/startup_stm32f746nghx.o + .data 0x0000000000000000 0x0 Core/Startup/startup_stm32f746nghx.o + .bss 0x0000000000000000 0x0 Core/Startup/startup_stm32f746nghx.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DeInit + 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_MspInit + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_MspDeInit + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_InitTick + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetTickPrio + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_SetTickFreq + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetTickFreq + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_SuspendTick + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_ResumeTick + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetHalVersion + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetREVID + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetDEVID + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGSleepMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_EnableCompensationCell + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DisableCompensationCell + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_EnableFMCMemorySwapping + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .text.HAL_DisableFMCMemorySwapping + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_DeInit + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_Stop + 0x0000000000000000 0x68 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_PollForEvent + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_Start_IT + 0x0000000000000000 0x194 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_Stop_IT + 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_IRQHandler + 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_Start_DMA + 0x0000000000000000 0x1dc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_Stop_DMA + 0x0000000000000000 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_ConvCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_ConvHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_LevelOutOfWindowCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_ErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_AnalogWDGConfig + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_GetState + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.HAL_ADC_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.ADC_DMAConvCplt + 0x0000000000000000 0xba Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.ADC_DMAHalfConvCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.ADC_DMAError + 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStart + 0x0000000000000000 0x178 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStart_IT + 0x0000000000000000 0x188 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStop + 0x0000000000000000 0x98 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedPollForConversion + 0x0000000000000000 0xe6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStop_IT + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedGetValue + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeStart_DMA + 0x0000000000000000 0x178 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeStop_DMA + 0x0000000000000000 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeGetValue + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedConvCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedConfigChannel + 0x0000000000000000 0x31c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeConfigChannel + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAConvCplt + 0x0000000000000000 0xa6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAHalfConvCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAError + 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_info 0x0000000000000000 0xaf9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_abbrev 0x0000000000000000 0x21c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_aranges + 0x0000000000000000 0x90 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_ranges 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_line 0x0000000000000000 0xafa Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_str 0x0000000000000000 0xfa63d Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .debug_frame 0x0000000000000000 0x250 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_GetPendingIRQ + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_SetPendingIRQ + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_ClearPendingIRQ + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_GetActive + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_GetPriority + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.NVIC_DecodePriority + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_SystemReset + 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.SysTick_Config + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x0000000000000000 0x8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_Config + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_MPU_Disable + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_MPU_Enable + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_MPU_ConfigRegion + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPriorityGrouping + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x0000000000000000 0x1e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetActive + 0x0000000000000000 0x1e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_DeInit + 0x0000000000000000 0x3a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_Start + 0x0000000000000000 0xcc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_Stop + 0x0000000000000000 0x36 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_Start_DMA + 0x0000000000000000 0x15c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_Stop_DMA + 0x0000000000000000 0x82 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_GetValue + 0x0000000000000000 0x2a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_ConvCpltCallbackCh1 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_ConvHalfCpltCallbackCh1 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_ErrorCallbackCh1 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_SetValue + 0x0000000000000000 0x4a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_GetState + 0x0000000000000000 0x1a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.HAL_DAC_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.DAC_DMAConvCpltCh1 + 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.DAC_DMAHalfConvCpltCh1 + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .text.DAC_DMAErrorCh1 + 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_DualGetValue + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_TriangleWaveGenerate + 0x0000000000000000 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_NoiseWaveGenerate + 0x0000000000000000 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_DualSetValue + 0x0000000000000000 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_ConvCpltCallbackCh2 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_ConvHalfCpltCallbackCh2 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.HAL_DACEx_ErrorCallbackCh2 + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.DAC_DMAConvCpltCh2 + 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.DAC_DMAHalfConvCpltCh2 + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .text.DAC_DMAErrorCh2 + 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_Start + 0x0000000000000000 0x76 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_Abort + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x0000000000000000 0x1be Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x0000000000000000 0x314 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0xd4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.DMA_SetConfig + 0x0000000000000000 0x5c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_DeInit + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_Start_IT + 0x0000000000000000 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_BlendingStart + 0x0000000000000000 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_BlendingStart_IT + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_Abort + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_Suspend + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_Resume + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_EnableCLUT + 0x0000000000000000 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoad + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoad_IT + 0x0000000000000000 0xd0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoading_Abort + 0x0000000000000000 0x9e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoading_Suspend + 0x0000000000000000 0xf2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoading_Resume + 0x0000000000000000 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_IRQHandler + 0x0000000000000000 0x1f8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_LineEventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_CLUTLoadingCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_ConfigCLUT + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_ProgramLineEvent + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_EnableDeadTime + 0x0000000000000000 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_DisableDeadTime + 0x0000000000000000 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_ConfigDeadTime + 0x0000000000000000 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_DMA2D_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart + 0x0000000000000000 0x96 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart_IT + 0x0000000000000000 0x126c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_ChangeMemory + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .text.DMA_MultiBufferSetConfig + 0x0000000000000000 0x4c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_info 0x0000000000000000 0x5d3 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_abbrev 0x0000000000000000 0x1b0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_aranges + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_ranges 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_line 0x0000000000000000 0x1394 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_str 0x0000000000000000 0xfa277 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .debug_frame 0x0000000000000000 0xac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_info 0x0000000000000000 0x169 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_abbrev 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_aranges + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_line 0x0000000000000000 0x802 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .debug_str 0x0000000000000000 0xf9ef2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_SetConfigLine + 0x0000000000000000 0x150 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetConfigLine + 0x0000000000000000 0x104 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_ClearConfigLine + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_RegisterCallback + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetHandle + 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_IRQHandler + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetPending + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_ClearPending + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GenerateSWI + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_info 0x0000000000000000 0x5e9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_abbrev 0x0000000000000000 0x1bc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_aranges + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_ranges 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_line 0x0000000000000000 0x904 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_str 0x0000000000000000 0xfa10f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .debug_frame 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Program + 0x0000000000000000 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x0000000000000000 0x15c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_Program_DoubleWord + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_Program_Word + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_Program_HalfWord + 0x0000000000000000 0x4c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_Program_Byte + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x0000000000000000 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_info 0x0000000000000000 0x646 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_abbrev 0x0000000000000000 0x248 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_aranges + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_ranges 0x0000000000000000 0x90 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_line 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_str 0x0000000000000000 0xfa275 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .debug_frame 0x0000000000000000 0x274 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + COMMON 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x0000000000000000 0xd8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x0000000000000000 0x9c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x0000000000000000 0x120 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_MassErase + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_Erase_Sector + 0x0000000000000000 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetWRP + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_UserConfig + 0x0000000000000000 0x6c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetUser + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_EnableWRP + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_DisableWRP + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_BOR_LevelConfig + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_BootAddressConfig + 0x0000000000000000 0x5c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetRDP + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetBOR + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetBootAddress + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_info 0x0000000000000000 0x78c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_abbrev 0x0000000000000000 0x21d Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_aranges + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_ranges 0x0000000000000000 0x90 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0xa1e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0xfa31c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .debug_frame 0x0000000000000000 0x284 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_TogglePin + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x0000000000000000 0x16 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x0000000000000000 0x1e8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x0000000000000000 0x1ec Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x0000000000000000 0x212 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x0000000000000000 0x1e0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x0000000000000000 0x1e0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x0000000000000000 0x16c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x0000000000000000 0x16c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x0000000000000000 0x128 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x0000000000000000 0x12c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x0000000000000000 0x1ec Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x0000000000000000 0x1f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x0000000000000000 0x210 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_IT + 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_DMA + 0x0000000000000000 0x208 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_IT + 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_DMA + 0x0000000000000000 0x208 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_IT + 0x0000000000000000 0x144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_DMA + 0x0000000000000000 0x26c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_IT + 0x0000000000000000 0x144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_DMA + 0x0000000000000000 0x26c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x0000000000000000 0xc2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x0000000000000000 0x252 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x0000000000000000 0x206 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x0000000000000000 0x1e6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x0000000000000000 0x190 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITAddrCplt + 0x0000000000000000 0x104 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITMasterSeqCplt + 0x0000000000000000 0x7a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITSlaveSeqCplt + 0x0000000000000000 0x7a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x0000000000000000 0x138 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x0000000000000000 0x1ac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ITError + 0x0000000000000000 0x180 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x0000000000000000 0x96 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x0000000000000000 0x96 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x0000000000000000 0x46 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMAError + 0x0000000000000000 0x74 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_DMAAbort + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x0000000000000000 0xd8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x0000000000000000 0xca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_ConvertOtherXferOptions + 0x0000000000000000 0x36 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DeInit + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_ConfigColorKeying + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_ConfigCLUT + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_EnableColorKeying + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DisableColorKeying + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_EnableCLUT + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DisableCLUT + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_EnableDither + 0x0000000000000000 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DisableDither + 0x0000000000000000 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetWindowSize + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetWindowPosition + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetPixelFormat + 0x0000000000000000 0x6c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetAlpha + 0x0000000000000000 0x6c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetAddress + 0x0000000000000000 0x6c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetPitch + 0x0000000000000000 0x10c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_ProgramLineEvent + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_Reload + 0x0000000000000000 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_ConfigLayer_NoReload + 0x0000000000000000 0x74 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetWindowSize_NoReload + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetWindowPosition_NoReload + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetPixelFormat_NoReload + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetAlpha_NoReload + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetAddress_NoReload + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_SetPitch_NoReload + 0x0000000000000000 0xf0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_ConfigColorKeying_NoReload + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_EnableColorKeying_NoReload + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DisableColorKeying_NoReload + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_EnableCLUT_NoReload + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_DisableCLUT_NoReload + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_LTDC_GetError + 0x0000000000000000 0x1a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_info 0x0000000000000000 0x169 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_abbrev 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_aranges + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_line 0x0000000000000000 0x806 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .debug_str 0x0000000000000000 0xf9ef6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_ConfigPVD + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnablePVD + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisablePVD + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_PVD_IRQHandler + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_PVDCallback + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableBkUpReg + 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableBkUpReg + 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableFlashPowerDown + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableFlashPowerDown + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableMainRegulatorLowVoltage + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableMainRegulatorLowVoltage + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableLowRegulatorLowVoltage + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableLowRegulatorLowVoltage + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableOverDrive + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnterUnderDriveSTOPMode + 0x0000000000000000 0xc8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_GetVoltageRange + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_ControlVoltageScaling + 0x0000000000000000 0xf4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0x1c0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x0000000000000000 0xc8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_DisableCSS + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x0000000000000000 0x128 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x0000000000000000 0xe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x0000000000000000 0x218 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x0000000000000000 0x268 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnablePLLI2S + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisablePLLI2S + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnablePLLSAI + 0x0000000000000000 0xa4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisablePLLSAI + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_DeInit + 0x0000000000000000 0x158 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_GetTime + 0x0000000000000000 0xbc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_GetDate + 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_SetAlarm_IT + 0x0000000000000000 0x270 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_DeactivateAlarm + 0x0000000000000000 0x11a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_GetAlarm + 0x0000000000000000 0x11e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_AlarmIRQHandler + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_AlarmAEventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_PollForAlarmAEvent + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.HAL_RTC_GetState + 0x0000000000000000 0x1a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .text.RTC_Bcd2ToByte + 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetTimeStamp_IT + 0x0000000000000000 0xe8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateTimeStamp + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetInternalTimeStamp + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateInternalTimeStamp + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_GetTimeStamp + 0x0000000000000000 0x140 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetTamper + 0x0000000000000000 0x168 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetTamper_IT + 0x0000000000000000 0x1d8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateTamper + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_TamperTimeStampIRQHandler + 0x0000000000000000 0x104 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_TimeStampEventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_Tamper1EventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_Tamper2EventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_Tamper3EventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForTimeStampEvent + 0x0000000000000000 0x86 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForTamper1Event + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForTamper2Event + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForTamper3Event + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetWakeUpTimer + 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetWakeUpTimer_IT + 0x0000000000000000 0x190 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateWakeUpTimer + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_GetWakeUpTimer + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_WakeUpTimerIRQHandler + 0x0000000000000000 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_WakeUpTimerEventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForWakeUpTimerEvent + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_BKUPWrite + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_BKUPRead + 0x0000000000000000 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetSmoothCalib + 0x0000000000000000 0xb6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetSynchroShift + 0x0000000000000000 0xf8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetCalibrationOutPut + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateCalibrationOutPut + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_SetRefClock + 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DeactivateRefClock + 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_EnableBypassShadow + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_DisableBypassShadow + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_AlarmBEventCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .text.HAL_RTCEx_PollForAlarmBEvent + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_DeInit + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_IRQHandler + 0x0000000000000000 0x34 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_RefreshErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_DMA_XferCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_DMA_XferErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Read_8b + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Write_8b + 0x0000000000000000 0x86 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Read_16b + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Write_16b + 0x0000000000000000 0x86 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Read_32b + 0x0000000000000000 0x7e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Write_32b + 0x0000000000000000 0x86 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Read_DMA + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_Write_DMA + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_WriteProtection_Enable + 0x0000000000000000 0x42 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_WriteProtection_Disable + 0x0000000000000000 0x42 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_SetAutoRefreshNumber + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_GetModeStatus + 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .text.HAL_SDRAM_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_DeInit + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Transmit + 0x0000000000000000 0x2cc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Receive + 0x0000000000000000 0x250 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TransmitReceive + 0x0000000000000000 0x426 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Transmit_IT + 0x0000000000000000 0x10c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Receive_IT + 0x0000000000000000 0x150 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TransmitReceive_IT + 0x0000000000000000 0x160 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Transmit_DMA + 0x0000000000000000 0x1d8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Receive_DMA + 0x0000000000000000 0x238 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TransmitReceive_DMA + 0x0000000000000000 0x318 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Abort + 0x0000000000000000 0x240 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_Abort_IT + 0x0000000000000000 0x1f4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_DMAPause + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_DMAResume + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_DMAStop + 0x0000000000000000 0x7e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_IRQHandler + 0x0000000000000000 0x200 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_RxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TxRxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TxHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_RxHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_TxRxHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_ErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_AbortCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.HAL_SPI_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMATransmitCplt + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAReceiveCplt + 0x0000000000000000 0x86 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMATransmitReceiveCplt + 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAHalfTransmitCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAHalfReceiveCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAHalfTransmitReceiveCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAError + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMAAbortOnError + 0x0000000000000000 0x2a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMATxAbortCallback + 0x0000000000000000 0xde Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_DMARxAbortCallback + 0x0000000000000000 0xe2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_2linesRxISR_8BIT + 0x0000000000000000 0xbe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_2linesTxISR_8BIT + 0x0000000000000000 0x92 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_2linesRxISR_16BIT + 0x0000000000000000 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_2linesTxISR_16BIT + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_RxISR_8BIT + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_RxISR_16BIT + 0x0000000000000000 0x4c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_TxISR_8BIT + 0x0000000000000000 0x46 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_TxISR_16BIT + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_WaitFlagStateUntilTimeout + 0x0000000000000000 0xd4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_WaitFifoStateUntilTimeout + 0x0000000000000000 0xda Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_EndRxTransaction + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_EndRxTxTransaction + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_CloseRxTx_ISR + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_CloseRx_ISR + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_CloseTx_ISR + 0x0000000000000000 0x7e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_AbortRx_ISR + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .text.SPI_AbortTx_ISR + 0x0000000000000000 0x144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .text.HAL_SPIEx_FlushRxFifo + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_info 0x0000000000000000 0x6dc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_abbrev 0x0000000000000000 0x162 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_aranges + 0x0000000000000000 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_ranges 0x0000000000000000 0x10 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x288 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_line 0x0000000000000000 0x823 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_str 0x0000000000000000 0xfa3be Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .debug_frame 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Start + 0x0000000000000000 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Stop + 0x0000000000000000 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Stop_IT + 0x0000000000000000 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Start_DMA + 0x0000000000000000 0xcc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Stop_DMA + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Init + 0x0000000000000000 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start_IT + 0x0000000000000000 0x114 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop_IT + 0x0000000000000000 0x134 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start_DMA + 0x0000000000000000 0x230 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop_DMA + 0x0000000000000000 0x164 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Start + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Stop + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Start_IT + 0x0000000000000000 0x114 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_IT + 0x0000000000000000 0x134 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Start_DMA + 0x0000000000000000 0x230 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_DMA + 0x0000000000000000 0x164 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Init + 0x0000000000000000 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop + 0x0000000000000000 0x52 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start_IT + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop_IT + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start_DMA + 0x0000000000000000 0x1f8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop_DMA + 0x0000000000000000 0x110 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Init + 0x0000000000000000 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start + 0x0000000000000000 0x68 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop + 0x0000000000000000 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start_IT + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop_IT + 0x0000000000000000 0xd8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Init + 0x0000000000000000 0x124 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start + 0x0000000000000000 0x6e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop + 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_IT + 0x0000000000000000 0xae Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_IT + 0x0000000000000000 0xd4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_DMA + 0x0000000000000000 0x1f4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_DMA + 0x0000000000000000 0xfc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_ConfigChannel + 0x0000000000000000 0xfc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_ConfigChannel + 0x0000000000000000 0x138 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_ConfigChannel + 0x0000000000000000 0x184 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStart + 0x0000000000000000 0x284 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStop + 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStart + 0x0000000000000000 0x284 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStop + 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_GenerateEvent + 0x0000000000000000 0x4e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_ConfigOCrefClear + 0x0000000000000000 0x204 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_ConfigTI1Input + 0x0000000000000000 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchro_IT + 0x0000000000000000 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_ReadCapturedValue + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_CaptureHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_TriggerHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_ErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMAError + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMADelayPulseCplt + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMADelayPulseHalfCplt + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMACaptureCplt + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMACaptureHalfCplt + 0x0000000000000000 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMAPeriodElapsedCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMAPeriodElapsedHalfCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMATriggerCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_DMATriggerHalfCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI1_SetConfig + 0x0000000000000000 0xe8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI2_SetConfig + 0x0000000000000000 0x7a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI3_SetConfig + 0x0000000000000000 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI4_SetConfig + 0x0000000000000000 0x7a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_CCxChannelCmd + 0x0000000000000000 0x4a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Init + 0x0000000000000000 0x130 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_DeInit + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_IT + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_IT + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_DMA + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_DMA + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop + 0x0000000000000000 0x82 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_IT + 0x0000000000000000 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_IT + 0x0000000000000000 0xec Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_DMA + 0x0000000000000000 0x18c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_DMA + 0x0000000000000000 0xee Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop + 0x0000000000000000 0x82 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_IT + 0x0000000000000000 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_IT + 0x0000000000000000 0xec Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_DMA + 0x0000000000000000 0x18c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_DMA + 0x0000000000000000 0xee Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start + 0x0000000000000000 0x32 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop + 0x0000000000000000 0x82 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start_IT + 0x0000000000000000 0x52 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop_IT + 0x0000000000000000 0xa2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent_IT + 0x0000000000000000 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent_DMA + 0x0000000000000000 0xe4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_RemapConfig + 0x0000000000000000 0x46 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_GroupChannel5 + 0x0000000000000000 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_CommutHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_GetState + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.TIMEx_DMACommutationCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.TIMEx_DMACommutationHalfCplt + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .text.TIM_CCxNChannelCmd + 0x0000000000000000 0x4a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_Init + 0x0000000000000000 0xac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_LIN_Init + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_Init + 0x0000000000000000 0xd4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_DeInit + 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_MspInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_MspDeInit + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit + 0x0000000000000000 0x122 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive + 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit_IT + 0x0000000000000000 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive_IT + 0x0000000000000000 0x144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit_DMA + 0x0000000000000000 0xf8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive_DMA + 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAPause + 0x0000000000000000 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAResume + 0x0000000000000000 0x8c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAStop + 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Abort + 0x0000000000000000 0x11c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmit + 0x0000000000000000 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceive + 0x0000000000000000 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_Abort_IT + 0x0000000000000000 0x16c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmit_IT + 0x0000000000000000 0xac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceive_IT + 0x0000000000000000 0xdc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_IRQHandler + 0x0000000000000000 0x264 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_TxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_TxHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_RxCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_RxHalfCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_ErrorCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmitCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceiveCpltCallback + 0x0000000000000000 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_ReceiverTimeout_Config + 0x0000000000000000 0x2a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_EnableReceiverTimeout + 0x0000000000000000 0x5c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_DisableReceiverTimeout + 0x0000000000000000 0x5c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_EnableMuteMode + 0x0000000000000000 0x4a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_DisableMuteMode + 0x0000000000000000 0x4a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_EnterMuteMode + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_EnableTransmitter + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_EnableReceiver + 0x0000000000000000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_LIN_SendBreak + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_GetState + 0x0000000000000000 0x26 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.HAL_UART_GetError + 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_EndTxTransfer + 0x0000000000000000 0x2a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_EndRxTransfer + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMATransmitCplt + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMAReceiveCplt + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMARxHalfCplt + 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMAError + 0x0000000000000000 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMAAbortOnError + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMATxAbortCallback + 0x0000000000000000 0x62 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMARxAbortCallback + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMATxOnlyAbortCallback + 0x0000000000000000 0x2a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_DMARxOnlyAbortCallback + 0x0000000000000000 0x42 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_TxISR_8BIT + 0x0000000000000000 0x72 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_TxISR_16BIT + 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_EndTransmit_IT + 0x0000000000000000 0x32 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_RxISR_8BIT + 0x0000000000000000 0xa6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .text.UART_RxISR_16BIT + 0x0000000000000000 0xa6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .text.HAL_RS485Ex_Init + 0x0000000000000000 0xd0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .text.HAL_MultiProcessorEx_AddressLength_Set + 0x0000000000000000 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_info 0x0000000000000000 0x773 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_abbrev 0x0000000000000000 0x17c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_aranges + 0x0000000000000000 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_ranges 0x0000000000000000 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_line 0x0000000000000000 0x845 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_str 0x0000000000000000 0xfa3e2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .debug_frame 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .data 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_Init + 0x0000000000000000 0xe0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_DeInit + 0x0000000000000000 0x68 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_Timing_Init + 0x0000000000000000 0xa6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_Extended_Timing_Init + 0x0000000000000000 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_WriteOperation_Enable + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NORSRAM_WriteOperation_Disable + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_Init + 0x0000000000000000 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_CommonSpace_Timing_Init + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_AttributeSpace_Timing_Init + 0x0000000000000000 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_DeInit + 0x0000000000000000 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_ECC_Enable + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_ECC_Disable + 0x0000000000000000 0x24 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_NAND_GetECC + 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_SDRAM_DeInit + 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_SDRAM_WriteProtection_Enable + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_SDRAM_WriteProtection_Disable + 0x0000000000000000 0x2c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_SDRAM_SetAutoRefreshNumber + 0x0000000000000000 0x26 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .text.FMC_SDRAM_GetModeStatus + 0x0000000000000000 0x3a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x2bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x12cd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x19 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x190f0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x36b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x61 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x18ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x6c4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x185 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x1fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x24f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x41 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x153 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x107 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x20f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xea Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x14f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x25b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x12 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x514 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x12f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x35 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x313 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x4ca Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xd6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x2fe Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x59 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x53c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x0000000000000000 0x14e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.makeCmsisPriority + 0x0000000000000000 0x2c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.inHandlerMode + 0x0000000000000000 0x24 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osKernelStart + 0x0000000000000000 0xe Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osKernelRunning + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osKernelSysTick + 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadGetId + 0x0000000000000000 0xe Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadTerminate + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadYield + 0x0000000000000000 0x24 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadSetPriority + 0x0000000000000000 0x2a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadGetPriority + 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osTimerCreate + 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osTimerStart + 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osTimerStop + 0x0000000000000000 0x1e Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osTimerDelete + 0x0000000000000000 0x1e Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSignalSet + 0x0000000000000000 0x80 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSignalWait + 0x0000000000000000 0x98 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMutexCreate + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMutexWait + 0x0000000000000000 0x9c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMutexRelease + 0x0000000000000000 0x6c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMutexDelete + 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSemaphoreCreate + 0x0000000000000000 0x80 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSemaphoreWait + 0x0000000000000000 0x9c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSemaphoreRelease + 0x0000000000000000 0x6c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSemaphoreDelete + 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osPoolCreate + 0x0000000000000000 0xba Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osPoolAlloc + 0x0000000000000000 0xc8 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osPoolCAlloc + 0x0000000000000000 0x2a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osPoolFree + 0x0000000000000000 0x82 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessageCreate + 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessagePut + 0x0000000000000000 0x80 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessageGet + 0x0000000000000000 0xe8 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailCreate + 0x0000000000000000 0xb0 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailAlloc + 0x0000000000000000 0x2a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailCAlloc + 0x0000000000000000 0x46 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailPut + 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailGet + 0x0000000000000000 0xe8 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMailFree + 0x0000000000000000 0x2a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSystickHandler + 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadSuspend + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadResume + 0x0000000000000000 0x44 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadSuspendAll + 0x0000000000000000 0xe Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadResumeAll + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osDelayUntil + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osAbortDelay + 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadList + 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessagePeek + 0x0000000000000000 0x96 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessageWaiting + 0x0000000000000000 0x2c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessageAvailableSpace + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osMessageDelete + 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osRecursiveMutexCreate + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osRecursiveMutexRelease + 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osRecursiveMutexWait + 0x0000000000000000 0x58 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osSemaphoreGetCount + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x174 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x35 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x91 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x9a Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0x19 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x0000000000000000 0xf2 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_info 0x0000000000000000 0x97 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_abbrev 0x0000000000000000 0x47 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_aranges + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xe3 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x174 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x8e Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x51 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_line 0x0000000000000000 0x49e Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .debug_str 0x0000000000000000 0x826e Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .comment 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .ARM.attributes + 0x0000000000000000 0x39 Middlewares/Third_Party/FreeRTOS/Source/croutine.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupCreateStatic + 0x0000000000000000 0x72 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupCreate + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupSync + 0x0000000000000000 0x164 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupWaitBits + 0x0000000000000000 0x1a4 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupClearBits + 0x0000000000000000 0x74 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupGetBitsFromISR + 0x0000000000000000 0x4a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.xEventGroupSetBits + 0x0000000000000000 0x11a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupDelete + 0x0000000000000000 0x6c Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupSetBitsCallback + 0x0000000000000000 0x1a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.vEventGroupClearBitsCallback + 0x0000000000000000 0x1a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .text.prvTestWaitCondition + 0x0000000000000000 0x44 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_info 0x0000000000000000 0x123e Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_abbrev 0x0000000000000000 0x2da Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_aranges + 0x0000000000000000 0x70 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_ranges 0x0000000000000000 0x60 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1d3 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x91 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_macro 0x0000000000000000 0x19 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_line 0x0000000000000000 0x8a5 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_str 0x0000000000000000 0xbbe3 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .comment 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .debug_frame 0x0000000000000000 0x1a4 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .ARM.attributes + 0x0000000000000000 0x39 Middlewares/Third_Party/FreeRTOS/Source/event_groups.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/list.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/list.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/list.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/list.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericReset + 0x0000000000000000 0xd4 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericCreateStatic + 0x0000000000000000 0xfa Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericCreate + 0x0000000000000000 0x82 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvInitialiseNewQueue + 0x0000000000000000 0x3e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvInitialiseMutex + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateMutex + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateMutexStatic + 0x0000000000000000 0x36 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGiveMutexRecursive + 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueTakeMutexRecursive + 0x0000000000000000 0x6e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateCountingSemaphoreStatic + 0x0000000000000000 0x72 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueCreateCountingSemaphore + 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericSend + 0x0000000000000000 0x204 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGenericSendFromISR + 0x0000000000000000 0x138 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueGiveFromISR + 0x0000000000000000 0x122 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueReceive + 0x0000000000000000 0x1c4 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueSemaphoreTake + 0x0000000000000000 0x220 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueuePeek + 0x0000000000000000 0x1c8 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueReceiveFromISR + 0x0000000000000000 0x106 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueuePeekFromISR + 0x0000000000000000 0xda Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueMessagesWaiting + 0x0000000000000000 0x3e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueSpacesAvailable + 0x0000000000000000 0x48 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.uxQueueMessagesWaitingFromISR + 0x0000000000000000 0x3e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueDelete + 0x0000000000000000 0x48 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvGetDisinheritPriorityAfterTimeout + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvCopyDataToQueue + 0x0000000000000000 0xd4 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvCopyDataFromQueue + 0x0000000000000000 0x4c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvUnlockQueue + 0x0000000000000000 0xa4 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvIsQueueEmpty + 0x0000000000000000 0x2c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueIsQueueEmptyFromISR + 0x0000000000000000 0x4a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.prvIsQueueFull + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.xQueueIsQueueFullFromISR + 0x0000000000000000 0x4e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueAddToRegistry + 0x0000000000000000 0x50 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.pcQueueGetName + 0x0000000000000000 0x4c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .text.vQueueUnregisterQueue + 0x0000000000000000 0x54 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_info 0x0000000000000000 0x21ea Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_abbrev 0x0000000000000000 0x336 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_aranges + 0x0000000000000000 0x128 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_ranges 0x0000000000000000 0x118 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x209 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x35 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_macro 0x0000000000000000 0x87 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_line 0x0000000000000000 0x102d Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_str 0x0000000000000000 0xbff9 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .comment 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/queue.o + .debug_frame 0x0000000000000000 0x504 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .ARM.attributes + 0x0000000000000000 0x39 Middlewares/Third_Party/FreeRTOS/Source/queue.o + COMMON 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/queue.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferGenericCreate + 0x0000000000000000 0xbc Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferGenericCreateStatic + 0x0000000000000000 0x10c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.vStreamBufferDelete + 0x0000000000000000 0x50 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReset + 0x0000000000000000 0x6e Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSetTriggerLevel + 0x0000000000000000 0x5e Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSpacesAvailable + 0x0000000000000000 0x68 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferBytesAvailable + 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSend + 0x0000000000000000 0x172 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSendFromISR + 0x0000000000000000 0xe8 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvWriteMessageToBuffer + 0x0000000000000000 0x7a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceive + 0x0000000000000000 0x130 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferNextMessageLengthBytes + 0x0000000000000000 0x96 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceiveFromISR + 0x0000000000000000 0xe4 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvReadMessageFromBuffer + 0x0000000000000000 0x64 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferIsEmpty + 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferIsFull + 0x0000000000000000 0x62 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferSendCompletedFromISR + 0x0000000000000000 0x8a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.xStreamBufferReceiveCompletedFromISR + 0x0000000000000000 0x8a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvWriteBytesToBuffer + 0x0000000000000000 0xea Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvReadBytesFromBuffer + 0x0000000000000000 0xfa Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvBytesInBuffer + 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .text.prvInitialiseNewStreamBuffer + 0x0000000000000000 0x68 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_info 0x0000000000000000 0x1b2c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_abbrev 0x0000000000000000 0x32b Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_aranges + 0x0000000000000000 0xc8 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_ranges 0x0000000000000000 0xb8 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1d3 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x8e Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x51 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x46 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x174 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x10 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x35 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_line 0x0000000000000000 0xbf8 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_str 0x0000000000000000 0xbb16 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .comment 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .debug_frame 0x0000000000000000 0x358 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .ARM.attributes + 0x0000000000000000 0x39 Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxDeletedTasksWaitingCleanUp + 0x0000000000000000 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xIdleTaskHandle + 0x0000000000000000 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelete + 0x0000000000000000 0x120 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskPriorityGet + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskPriorityGetFromISR + 0x0000000000000000 0x5c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPrioritySet + 0x0000000000000000 0x154 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSuspend + 0x0000000000000000 0x128 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvTaskIsTaskSuspended + 0x0000000000000000 0x64 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskResume + 0x0000000000000000 0xbc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskResumeFromISR + 0x0000000000000000 0xe8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .rodata 0x0000000000000000 0x5 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskStartScheduler + 0x0000000000000000 0xc4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskEndScheduler + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetTickCount + 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetTickCountFromISR + 0x0000000000000000 0x24 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskGetNumberOfTasks + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.pcTaskGetName + 0x0000000000000000 0x4c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSetApplicationTaskTag + 0x0000000000000000 0x38 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetApplicationTaskTag + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetApplicationTaskTagFromISR + 0x0000000000000000 0x5c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskCallApplicationTaskHook + 0x0000000000000000 0x44 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPlaceOnEventList + 0x0000000000000000 0x4c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPlaceOnUnorderedEventList + 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskRemoveFromEventList + 0x0000000000000000 0xc8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskRemoveFromUnorderedEventList + 0x0000000000000000 0xc8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskSetTimeOutState + 0x0000000000000000 0x50 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskInternalSetTimeOutState + 0x0000000000000000 0x2c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskCheckForTimeOut + 0x0000000000000000 0xc8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskMissedYield + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvIdleTask + 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvCheckTasksWaitingTermination + 0x0000000000000000 0x58 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvDeleteTCB + 0x0000000000000000 0x60 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetCurrentTaskHandle + 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGetSchedulerState + 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskPriorityInherit + 0x0000000000000000 0x100 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskPriorityDisinherit + 0x0000000000000000 0x110 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskPriorityDisinheritAfterTimeout + 0x0000000000000000 0x138 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.uxTaskResetEventItemValue + 0x0000000000000000 0x30 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.pvTaskIncrementMutexHeldCount + 0x0000000000000000 0x28 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.ulTaskNotifyTake + 0x0000000000000000 0x90 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskNotifyWait + 0x0000000000000000 0xb4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGenericNotify + 0x0000000000000000 0x170 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskGenericNotifyFromISR + 0x0000000000000000 0x1c0 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskNotifyGiveFromISR + 0x0000000000000000 0x128 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.xTaskNotifyStateClear + 0x0000000000000000 0x4c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x35 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x0000000000000000 0x91 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/timers.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_info 0x0000000000000000 0x8ad Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_abbrev 0x0000000000000000 0x158 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_aranges + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1b1 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x87 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_macro 0x0000000000000000 0x97 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_line 0x0000000000000000 0x5e2 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .debug_str 0x0000000000000000 0xbc8c Middlewares/Third_Party/FreeRTOS/Source/timers.o + .comment 0x0000000000000000 0x7c Middlewares/Third_Party/FreeRTOS/Source/timers.o + .ARM.attributes + 0x0000000000000000 0x39 Middlewares/Third_Party/FreeRTOS/Source/timers.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .bss.ucMaxSysCallPriority + 0x0000000000000000 0x1 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .bss.ulMaxPRIGROUPValue + 0x0000000000000000 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .rodata.pcInterruptPriorityRegisters + 0x0000000000000000 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.prvPortStartFirstTask + 0x0000000000000000 0x28 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.xPortStartScheduler + 0x0000000000000000 0xf8 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.vPortEndScheduler + 0x0000000000000000 0x38 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.vPortSetupTimerInterrupt + 0x0000000000000000 0x48 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.vPortEnableVFP + 0x0000000000000000 0x14 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .text.vPortValidateInterruptPriority + 0x0000000000000000 0x84 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x174 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x8e Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x51 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .group 0x0000000000000000 0xc Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .data 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss 0x0000000000000000 0x0 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .rodata.xHeapStructSize + 0x0000000000000000 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.xPortGetFreeHeapSize + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.xPortGetMinimumEverFreeHeapSize + 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.vPortInitialiseBlocks + 0x0000000000000000 0xe Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xa5a Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x18 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x22 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x40 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x94 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x3c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x34 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x10e Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x8d Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x57 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x52 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1f Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x43 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x20 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1a3 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x330 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x16 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x29 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xef Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x6a Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1df Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x109 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x15a Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xde Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x1c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x26 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0x4c5 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xb5 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_macro 0x0000000000000000 0xaa Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x28 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .ARM.attributes + 0x0000000000000000 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + .rodata._global_impure_ptr + 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .text._sprintf_r + 0x0000000000000000 0x38 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .text.__ssprint_r + 0x0000000000000000 0xf0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memchr.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memchr.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .text.cleanup_glue + 0x0000000000000000 0x1a /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .text._reclaim_reent + 0x0000000000000000 0xb8 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_dvmd_tls.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .eh_frame 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .ARM.attributes + 0x0000000000000000 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x0000000020000000 0x0000000000050000 xrw +FLASH 0x0000000008000000 0x0000000000100000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o +LOAD Core/Src/freertos.o +LOAD Core/Src/ft5336.o +LOAD Core/Src/main.o +LOAD Core/Src/stm32746g_discovery.o +LOAD Core/Src/stm32746g_discovery_lcd.o +LOAD Core/Src/stm32746g_discovery_sdram.o +LOAD Core/Src/stm32746g_discovery_ts.o +LOAD Core/Src/stm32f7xx_hal_msp.o +LOAD Core/Src/stm32f7xx_hal_timebase_tim.o +LOAD Core/Src/stm32f7xx_it.o +LOAD Core/Src/syscalls.o +LOAD Core/Src/sysmem.o +LOAD Core/Src/system_stm32f7xx.o +LOAD Core/Startup/startup_stm32f746nghx.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.o +LOAD Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/croutine.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/event_groups.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/list.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/queue.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/tasks.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/timers.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o +LOAD Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o +START GROUP +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o +LOAD /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + 0x0000000020050000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0x1c8 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0x1c8 Core/Startup/startup_stm32f746nghx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080001c8 . = ALIGN (0x4) + +.text 0x00000000080001d0 0xc210 + 0x00000000080001d0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080001d0 0x40 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + .text 0x0000000008000210 0xa0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memchr.o) + 0x0000000008000210 memchr + .text 0x00000000080002b0 0x30 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x00000000080002b0 __aeabi_uldivmod + .text 0x00000000080002e0 0x2cc /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + 0x00000000080002e0 __udivmoddi4 + .text 0x00000000080005ac 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_dvmd_tls.o) + 0x00000000080005ac __aeabi_ldiv0 + 0x00000000080005ac __aeabi_idiv0 + *(.text*) + .text.vApplicationStackOverflowHook + 0x00000000080005b0 0x16 Core/Src/freertos.o + 0x00000000080005b0 vApplicationStackOverflowHook + .text.vApplicationMallocFailedHook + 0x00000000080005c6 0xe Core/Src/freertos.o + 0x00000000080005c6 vApplicationMallocFailedHook + .text.ft5336_Init + 0x00000000080005d4 0x1c Core/Src/ft5336.o + 0x00000000080005d4 ft5336_Init + .text.ft5336_Reset + 0x00000000080005f0 0x16 Core/Src/ft5336.o + 0x00000000080005f0 ft5336_Reset + .text.ft5336_ReadID + 0x0000000008000606 0x5c Core/Src/ft5336.o + 0x0000000008000606 ft5336_ReadID + .text.ft5336_TS_Start + 0x0000000008000662 0x22 Core/Src/ft5336.o + 0x0000000008000662 ft5336_TS_Start + .text.ft5336_TS_DetectTouch + 0x0000000008000684 0x54 Core/Src/ft5336.o + 0x0000000008000684 ft5336_TS_DetectTouch + .text.ft5336_TS_GetXY + 0x00000000080006d8 0x1e0 Core/Src/ft5336.o + 0x00000000080006d8 ft5336_TS_GetXY + .text.ft5336_TS_EnableIT + 0x00000000080008b8 0x28 Core/Src/ft5336.o + 0x00000000080008b8 ft5336_TS_EnableIT + .text.ft5336_TS_DisableIT + 0x00000000080008e0 0x28 Core/Src/ft5336.o + 0x00000000080008e0 ft5336_TS_DisableIT + .text.ft5336_TS_ITStatus + 0x0000000008000908 0x18 Core/Src/ft5336.o + 0x0000000008000908 ft5336_TS_ITStatus + .text.ft5336_TS_ClearIT + 0x0000000008000920 0x16 Core/Src/ft5336.o + 0x0000000008000920 ft5336_TS_ClearIT + .text.ft5336_TS_GetGestureID + 0x0000000008000936 0x32 Core/Src/ft5336.o + 0x0000000008000936 ft5336_TS_GetGestureID + .text.ft5336_TS_GetTouchInfo + 0x0000000008000968 0x15c Core/Src/ft5336.o + 0x0000000008000968 ft5336_TS_GetTouchInfo + .text.ft5336_Get_I2C_InitializedStatus + 0x0000000008000ac4 0x18 Core/Src/ft5336.o + .text.ft5336_I2C_InitializeIfRequired + 0x0000000008000adc 0x20 Core/Src/ft5336.o + .text.ft5336_TS_Configure + 0x0000000008000afc 0x1c Core/Src/ft5336.o + .text.main 0x0000000008000b18 0x27c Core/Src/main.o + 0x0000000008000b18 main + .text.SystemClock_Config + 0x0000000008000d94 0x160 Core/Src/main.o + 0x0000000008000d94 SystemClock_Config + .text.MX_ADC1_Init + 0x0000000008000ef4 0xa4 Core/Src/main.o + .text.MX_ADC3_Init + 0x0000000008000f98 0xa4 Core/Src/main.o + .text.MX_DAC_Init + 0x000000000800103c 0x54 Core/Src/main.o + .text.MX_DMA2D_Init + 0x0000000008001090 0x64 Core/Src/main.o + .text.MX_I2C1_Init + 0x00000000080010f4 0x80 Core/Src/main.o + .text.MX_I2C3_Init + 0x0000000008001174 0x80 Core/Src/main.o + .text.MX_LTDC_Init + 0x00000000080011f4 0x104 Core/Src/main.o + .text.MX_RTC_Init + 0x00000000080012f8 0x14c Core/Src/main.o + .text.MX_SPI2_Init + 0x0000000008001444 0x7c Core/Src/main.o + .text.MX_TIM1_Init + 0x00000000080014c0 0xa8 Core/Src/main.o + .text.MX_TIM2_Init + 0x0000000008001568 0x9c Core/Src/main.o + .text.MX_TIM3_Init + 0x0000000008001604 0x11c Core/Src/main.o + .text.MX_TIM5_Init + 0x0000000008001720 0x9c Core/Src/main.o + .text.MX_TIM8_Init + 0x00000000080017bc 0x154 Core/Src/main.o + .text.MX_UART7_Init + 0x0000000008001910 0x60 Core/Src/main.o + .text.MX_USART1_UART_Init + 0x0000000008001970 0x60 Core/Src/main.o + .text.MX_USART6_UART_Init + 0x00000000080019d0 0x60 Core/Src/main.o + .text.MX_FMC_Init + 0x0000000008001a30 0x9c Core/Src/main.o + .text.MX_GPIO_Init + 0x0000000008001acc 0x3d8 Core/Src/main.o + .text.StartDefaultTask + 0x0000000008001ea4 0x10 Core/Src/main.o + 0x0000000008001ea4 StartDefaultTask + .text.HAL_TIM_PeriodElapsedCallback + 0x0000000008001eb4 0x24 Core/Src/main.o + 0x0000000008001eb4 HAL_TIM_PeriodElapsedCallback + .text.Error_Handler + 0x0000000008001ed8 0x8 Core/Src/main.o + 0x0000000008001ed8 Error_Handler + .text.I2Cx_MspInit + 0x0000000008001ee0 0x160 Core/Src/stm32746g_discovery.o + .text.I2Cx_Init + 0x0000000008002040 0x78 Core/Src/stm32746g_discovery.o + .text.I2Cx_ReadMultiple + 0x00000000080020b8 0x5a Core/Src/stm32746g_discovery.o + .text.I2Cx_WriteMultiple + 0x0000000008002112 0x5a Core/Src/stm32746g_discovery.o + .text.I2Cx_Error + 0x000000000800216c 0x20 Core/Src/stm32746g_discovery.o + .text.TS_IO_Init + 0x000000000800218c 0x14 Core/Src/stm32746g_discovery.o + 0x000000000800218c TS_IO_Init + .text.TS_IO_Write + 0x00000000080021a0 0x34 Core/Src/stm32746g_discovery.o + 0x00000000080021a0 TS_IO_Write + .text.TS_IO_Read + 0x00000000080021d4 0x3c Core/Src/stm32746g_discovery.o + 0x00000000080021d4 TS_IO_Read + .text.TS_IO_Delay + 0x0000000008002210 0x16 Core/Src/stm32746g_discovery.o + 0x0000000008002210 TS_IO_Delay + *fill* 0x0000000008002226 0x2 + .text.BSP_LCD_Init + 0x0000000008002228 0xe0 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002228 BSP_LCD_Init + .text.BSP_LCD_GetXSize + 0x0000000008002308 0x28 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002308 BSP_LCD_GetXSize + .text.BSP_LCD_GetYSize + 0x0000000008002330 0x28 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002330 BSP_LCD_GetYSize + .text.BSP_LCD_LayerDefaultInit + 0x0000000008002358 0xc0 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002358 BSP_LCD_LayerDefaultInit + .text.BSP_LCD_SelectLayer + 0x0000000008002418 0x20 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002418 BSP_LCD_SelectLayer + .text.BSP_LCD_SetTextColor + 0x0000000008002438 0x30 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002438 BSP_LCD_SetTextColor + .text.BSP_LCD_SetBackColor + 0x0000000008002468 0x34 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002468 BSP_LCD_SetBackColor + .text.BSP_LCD_SetFont + 0x000000000800249c 0x34 Core/Src/stm32746g_discovery_lcd.o + 0x000000000800249c BSP_LCD_SetFont + .text.BSP_LCD_GetFont + 0x00000000080024d0 0x2c Core/Src/stm32746g_discovery_lcd.o + 0x00000000080024d0 BSP_LCD_GetFont + .text.BSP_LCD_Clear + 0x00000000080024fc 0x50 Core/Src/stm32746g_discovery_lcd.o + 0x00000000080024fc BSP_LCD_Clear + .text.BSP_LCD_DisplayChar + 0x000000000800254c 0x88 Core/Src/stm32746g_discovery_lcd.o + 0x000000000800254c BSP_LCD_DisplayChar + .text.BSP_LCD_DisplayStringAt + 0x00000000080025d4 0x188 Core/Src/stm32746g_discovery_lcd.o + 0x00000000080025d4 BSP_LCD_DisplayStringAt + .text.BSP_LCD_DisplayStringAtLine + 0x000000000800275c 0x2e Core/Src/stm32746g_discovery_lcd.o + 0x000000000800275c BSP_LCD_DisplayStringAtLine + *fill* 0x000000000800278a 0x2 + .text.BSP_LCD_DrawHLine + 0x000000000800278c 0xbc Core/Src/stm32746g_discovery_lcd.o + 0x000000000800278c BSP_LCD_DrawHLine + .text.BSP_LCD_DrawCircle + 0x0000000008002848 0x1e0 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002848 BSP_LCD_DrawCircle + .text.BSP_LCD_DrawPixel + 0x0000000008002a28 0x90 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002a28 BSP_LCD_DrawPixel + .text.BSP_LCD_FillCircle + 0x0000000008002ab8 0x140 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002ab8 BSP_LCD_FillCircle + .text.BSP_LCD_DisplayOn + 0x0000000008002bf8 0x3c Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002bf8 BSP_LCD_DisplayOn + .text.BSP_LCD_MspInit + 0x0000000008002c34 0x1b4 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002c34 BSP_LCD_MspInit + .text.BSP_LCD_ClockConfig + 0x0000000008002de8 0x38 Core/Src/stm32746g_discovery_lcd.o + 0x0000000008002de8 BSP_LCD_ClockConfig + .text.DrawChar + 0x0000000008002e20 0x170 Core/Src/stm32746g_discovery_lcd.o + .text.LL_FillBuffer + 0x0000000008002f90 0x98 Core/Src/stm32746g_discovery_lcd.o + .text.BSP_SDRAM_Init + 0x0000000008003028 0xbc Core/Src/stm32746g_discovery_sdram.o + 0x0000000008003028 BSP_SDRAM_Init + .text.BSP_SDRAM_Initialization_sequence + 0x00000000080030e4 0xc0 Core/Src/stm32746g_discovery_sdram.o + 0x00000000080030e4 BSP_SDRAM_Initialization_sequence + .text.BSP_SDRAM_MspInit + 0x00000000080031a4 0x1f0 Core/Src/stm32746g_discovery_sdram.o + 0x00000000080031a4 BSP_SDRAM_MspInit + .text.BSP_TS_Init + 0x0000000008003394 0x80 Core/Src/stm32746g_discovery_ts.o + 0x0000000008003394 BSP_TS_Init + .text.BSP_TS_GetState + 0x0000000008003414 0x3ac Core/Src/stm32746g_discovery_ts.o + 0x0000000008003414 BSP_TS_GetState + .text.BSP_TS_Get_GestureId + 0x00000000080037c0 0x94 Core/Src/stm32746g_discovery_ts.o + 0x00000000080037c0 BSP_TS_Get_GestureId + .text.HAL_MspInit + 0x0000000008003854 0x50 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003854 HAL_MspInit + .text.HAL_ADC_MspInit + 0x00000000080038a4 0xdc Core/Src/stm32f7xx_hal_msp.o + 0x00000000080038a4 HAL_ADC_MspInit + .text.HAL_DAC_MspInit + 0x0000000008003980 0x90 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003980 HAL_DAC_MspInit + .text.HAL_DMA2D_MspInit + 0x0000000008003a10 0x40 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003a10 HAL_DMA2D_MspInit + .text.HAL_I2C_MspInit + 0x0000000008003a50 0xf0 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003a50 HAL_I2C_MspInit + .text.HAL_I2C_MspDeInit + 0x0000000008003b40 0x78 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003b40 HAL_I2C_MspDeInit + .text.HAL_LTDC_MspInit + 0x0000000008003bb8 0x190 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003bb8 HAL_LTDC_MspInit + .text.HAL_RTC_MspInit + 0x0000000008003d48 0x34 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003d48 HAL_RTC_MspInit + .text.HAL_SPI_MspInit + 0x0000000008003d7c 0xe4 Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003d7c HAL_SPI_MspInit + .text.HAL_TIM_Base_MspInit + 0x0000000008003e60 0xdc Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003e60 HAL_TIM_Base_MspInit + .text.HAL_TIM_MspPostInit + 0x0000000008003f3c 0xbc Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003f3c HAL_TIM_MspPostInit + .text.HAL_UART_MspInit + 0x0000000008003ff8 0x18c Core/Src/stm32f7xx_hal_msp.o + 0x0000000008003ff8 HAL_UART_MspInit + .text.HAL_FMC_MspInit + 0x0000000008004184 0x120 Core/Src/stm32f7xx_hal_msp.o + .text.HAL_SDRAM_MspInit + 0x00000000080042a4 0x14 Core/Src/stm32f7xx_hal_msp.o + 0x00000000080042a4 HAL_SDRAM_MspInit + .text.HAL_InitTick + 0x00000000080042b8 0xb0 Core/Src/stm32f7xx_hal_timebase_tim.o + 0x00000000080042b8 HAL_InitTick + .text.NMI_Handler + 0x0000000008004368 0x6 Core/Src/stm32f7xx_it.o + 0x0000000008004368 NMI_Handler + .text.HardFault_Handler + 0x000000000800436e 0x6 Core/Src/stm32f7xx_it.o + 0x000000000800436e HardFault_Handler + .text.MemManage_Handler + 0x0000000008004374 0x6 Core/Src/stm32f7xx_it.o + 0x0000000008004374 MemManage_Handler + .text.BusFault_Handler + 0x000000000800437a 0x6 Core/Src/stm32f7xx_it.o + 0x000000000800437a BusFault_Handler + .text.UsageFault_Handler + 0x0000000008004380 0x6 Core/Src/stm32f7xx_it.o + 0x0000000008004380 UsageFault_Handler + .text.DebugMon_Handler + 0x0000000008004386 0xe Core/Src/stm32f7xx_it.o + 0x0000000008004386 DebugMon_Handler + .text.TIM6_DAC_IRQHandler + 0x0000000008004394 0x1c Core/Src/stm32f7xx_it.o + 0x0000000008004394 TIM6_DAC_IRQHandler + .text.LTDC_IRQHandler + 0x00000000080043b0 0x14 Core/Src/stm32f7xx_it.o + 0x00000000080043b0 LTDC_IRQHandler + .text._sbrk 0x00000000080043c4 0x6c Core/Src/sysmem.o + 0x00000000080043c4 _sbrk + .text.SystemInit + 0x0000000008004430 0x2c Core/Src/system_stm32f7xx.o + 0x0000000008004430 SystemInit + .text.Reset_Handler + 0x000000000800445c 0x50 Core/Startup/startup_stm32f746nghx.o + 0x000000000800445c Reset_Handler + .text.Default_Handler + 0x00000000080044ac 0x2 Core/Startup/startup_stm32f746nghx.o + 0x00000000080044ac RTC_Alarm_IRQHandler + 0x00000000080044ac EXTI2_IRQHandler + 0x00000000080044ac TIM8_CC_IRQHandler + 0x00000000080044ac UART8_IRQHandler + 0x00000000080044ac SPI4_IRQHandler + 0x00000000080044ac TIM1_CC_IRQHandler + 0x00000000080044ac DMA2_Stream5_IRQHandler + 0x00000000080044ac DMA1_Stream5_IRQHandler + 0x00000000080044ac PVD_IRQHandler + 0x00000000080044ac TAMP_STAMP_IRQHandler + 0x00000000080044ac CAN2_RX1_IRQHandler + 0x00000000080044ac EXTI3_IRQHandler + 0x00000000080044ac TIM8_TRG_COM_TIM14_IRQHandler + 0x00000000080044ac TIM1_UP_TIM10_IRQHandler + 0x00000000080044ac TIM8_UP_TIM13_IRQHandler + 0x00000000080044ac I2C3_ER_IRQHandler + 0x00000000080044ac EXTI0_IRQHandler + 0x00000000080044ac I2C2_EV_IRQHandler + 0x00000000080044ac DMA1_Stream2_IRQHandler + 0x00000000080044ac CAN1_RX0_IRQHandler + 0x00000000080044ac FPU_IRQHandler + 0x00000000080044ac OTG_HS_WKUP_IRQHandler + 0x00000000080044ac LTDC_ER_IRQHandler + 0x00000000080044ac CAN2_SCE_IRQHandler + 0x00000000080044ac DMA2_Stream2_IRQHandler + 0x00000000080044ac SPI1_IRQHandler + 0x00000000080044ac TIM1_BRK_TIM9_IRQHandler + 0x00000000080044ac DCMI_IRQHandler + 0x00000000080044ac CAN2_RX0_IRQHandler + 0x00000000080044ac DMA2_Stream3_IRQHandler + 0x00000000080044ac SAI2_IRQHandler + 0x00000000080044ac USART6_IRQHandler + 0x00000000080044ac USART3_IRQHandler + 0x00000000080044ac CAN1_RX1_IRQHandler + 0x00000000080044ac UART5_IRQHandler + 0x00000000080044ac DMA2_Stream0_IRQHandler + 0x00000000080044ac TIM4_IRQHandler + 0x00000000080044ac QUADSPI_IRQHandler + 0x00000000080044ac I2C1_EV_IRQHandler + 0x00000000080044ac DMA1_Stream6_IRQHandler + 0x00000000080044ac DMA1_Stream1_IRQHandler + 0x00000000080044ac UART4_IRQHandler + 0x00000000080044ac TIM3_IRQHandler + 0x00000000080044ac RCC_IRQHandler + 0x00000000080044ac TIM8_BRK_TIM12_IRQHandler + 0x00000000080044ac Default_Handler + 0x00000000080044ac CEC_IRQHandler + 0x00000000080044ac EXTI15_10_IRQHandler + 0x00000000080044ac ADC_IRQHandler + 0x00000000080044ac DMA1_Stream7_IRQHandler + 0x00000000080044ac SPI5_IRQHandler + 0x00000000080044ac TIM7_IRQHandler + 0x00000000080044ac SDMMC1_IRQHandler + 0x00000000080044ac CAN2_TX_IRQHandler + 0x00000000080044ac TIM5_IRQHandler + 0x00000000080044ac DMA2_Stream7_IRQHandler + 0x00000000080044ac I2C3_EV_IRQHandler + 0x00000000080044ac EXTI9_5_IRQHandler + 0x00000000080044ac RTC_WKUP_IRQHandler + 0x00000000080044ac ETH_WKUP_IRQHandler + 0x00000000080044ac SPDIF_RX_IRQHandler + 0x00000000080044ac SPI2_IRQHandler + 0x00000000080044ac OTG_HS_EP1_IN_IRQHandler + 0x00000000080044ac DMA1_Stream0_IRQHandler + 0x00000000080044ac CAN1_TX_IRQHandler + 0x00000000080044ac EXTI4_IRQHandler + 0x00000000080044ac RNG_IRQHandler + 0x00000000080044ac ETH_IRQHandler + 0x00000000080044ac OTG_HS_EP1_OUT_IRQHandler + 0x00000000080044ac WWDG_IRQHandler + 0x00000000080044ac SPI6_IRQHandler + 0x00000000080044ac I2C4_EV_IRQHandler + 0x00000000080044ac TIM2_IRQHandler + 0x00000000080044ac OTG_FS_WKUP_IRQHandler + 0x00000000080044ac TIM1_TRG_COM_TIM11_IRQHandler + 0x00000000080044ac OTG_HS_IRQHandler + 0x00000000080044ac DMA2D_IRQHandler + 0x00000000080044ac EXTI1_IRQHandler + 0x00000000080044ac UART7_IRQHandler + 0x00000000080044ac USART2_IRQHandler + 0x00000000080044ac I2C2_ER_IRQHandler + 0x00000000080044ac DMA2_Stream1_IRQHandler + 0x00000000080044ac CAN1_SCE_IRQHandler + 0x00000000080044ac FLASH_IRQHandler + 0x00000000080044ac DMA2_Stream4_IRQHandler + 0x00000000080044ac USART1_IRQHandler + 0x00000000080044ac OTG_FS_IRQHandler + 0x00000000080044ac SPI3_IRQHandler + 0x00000000080044ac DMA1_Stream4_IRQHandler + 0x00000000080044ac I2C1_ER_IRQHandler + 0x00000000080044ac FMC_IRQHandler + 0x00000000080044ac LPTIM1_IRQHandler + 0x00000000080044ac I2C4_ER_IRQHandler + 0x00000000080044ac DMA2_Stream6_IRQHandler + 0x00000000080044ac SAI1_IRQHandler + 0x00000000080044ac DMA1_Stream3_IRQHandler + .text.HAL_Init + 0x00000000080044ae 0x1a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x00000000080044ae HAL_Init + .text.HAL_IncTick + 0x00000000080044c8 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x00000000080044c8 HAL_IncTick + .text.HAL_GetTick + 0x00000000080044f0 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x00000000080044f0 HAL_GetTick + .text.HAL_Delay + 0x0000000008004508 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x0000000008004508 HAL_Delay + .text.HAL_ADC_Init + 0x000000000800454c 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0x000000000800454c HAL_ADC_Init + .text.HAL_ADC_Start + 0x00000000080045d4 0x180 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0x00000000080045d4 HAL_ADC_Start + .text.HAL_ADC_PollForConversion + 0x0000000008004754 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0x0000000008004754 HAL_ADC_PollForConversion + .text.HAL_ADC_GetValue + 0x000000000800485c 0x1a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0x000000000800485c HAL_ADC_GetValue + *fill* 0x0000000008004876 0x2 + .text.HAL_ADC_ConfigChannel + 0x0000000008004878 0x294 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0x0000000008004878 HAL_ADC_ConfigChannel + .text.ADC_Init + 0x0000000008004b0c 0x1f4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .text.__NVIC_SetPriorityGrouping + 0x0000000008004d00 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x0000000008004d48 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x0000000008004d64 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x0000000008004da0 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x0000000008004df4 0x66 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x0000000008004e5a 0x16 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + 0x0000000008004e5a HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x0000000008004e70 0x38 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + 0x0000000008004e70 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x0000000008004ea8 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + 0x0000000008004ea8 HAL_NVIC_EnableIRQ + .text.HAL_DAC_Init + 0x0000000008004ec4 0x44 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + 0x0000000008004ec4 HAL_DAC_Init + .text.HAL_DAC_IRQHandler + 0x0000000008004f08 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + 0x0000000008004f08 HAL_DAC_IRQHandler + .text.HAL_DAC_DMAUnderrunCallbackCh1 + 0x0000000008004f9c 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + 0x0000000008004f9c HAL_DAC_DMAUnderrunCallbackCh1 + .text.HAL_DAC_ConfigChannel + 0x0000000008004fb0 0x9a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + 0x0000000008004fb0 HAL_DAC_ConfigChannel + .text.HAL_DACEx_DMAUnderrunCallbackCh2 + 0x000000000800504a 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + 0x000000000800504a HAL_DACEx_DMAUnderrunCallbackCh2 + *fill* 0x000000000800505e 0x2 + .text.HAL_DMA_Init + 0x0000000008005060 0x15c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + 0x0000000008005060 HAL_DMA_Init + .text.HAL_DMA_DeInit + 0x00000000080051bc 0xbc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + 0x00000000080051bc HAL_DMA_DeInit + .text.DMA_CalcBaseAndBitshift + 0x0000000008005278 0x6c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.DMA_CheckFifoParam + 0x00000000080052e4 0xf4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .text.HAL_DMA2D_Init + 0x00000000080053d8 0x94 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + 0x00000000080053d8 HAL_DMA2D_Init + .text.HAL_DMA2D_Start + 0x000000000800546c 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + 0x000000000800546c HAL_DMA2D_Start + .text.HAL_DMA2D_PollForTransfer + 0x00000000080054c2 0x1d2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + 0x00000000080054c2 HAL_DMA2D_PollForTransfer + .text.HAL_DMA2D_ConfigLayer + 0x0000000008005694 0x124 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + 0x0000000008005694 HAL_DMA2D_ConfigLayer + .text.DMA2D_SetConfig + 0x00000000080057b8 0x138 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .text.HAL_GPIO_Init + 0x00000000080058f0 0x354 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + 0x00000000080058f0 HAL_GPIO_Init + .text.HAL_GPIO_DeInit + 0x0000000008005c44 0x214 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + 0x0000000008005c44 HAL_GPIO_DeInit + .text.HAL_GPIO_ReadPin + 0x0000000008005e58 0x30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + 0x0000000008005e58 HAL_GPIO_ReadPin + .text.HAL_GPIO_WritePin + 0x0000000008005e88 0x32 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + 0x0000000008005e88 HAL_GPIO_WritePin + *fill* 0x0000000008005eba 0x2 + .text.HAL_I2C_Init + 0x0000000008005ebc 0x120 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0x0000000008005ebc HAL_I2C_Init + .text.HAL_I2C_DeInit + 0x0000000008005fdc 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0x0000000008005fdc HAL_I2C_DeInit + *fill* 0x000000000800603a 0x2 + .text.HAL_I2C_Mem_Write + 0x000000000800603c 0x228 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0x000000000800603c HAL_I2C_Mem_Write + .text.HAL_I2C_Mem_Read + 0x0000000008006264 0x234 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0x0000000008006264 HAL_I2C_Mem_Read + .text.HAL_I2C_GetState + 0x0000000008006498 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0x0000000008006498 HAL_I2C_GetState + .text.I2C_RequestMemoryWrite + 0x00000000080064b4 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x000000000800655c 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x0000000008006604 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x000000000800664c 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x00000000080066cc 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x000000000800674c 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x00000000080067c4 0xcc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.I2C_TransferConfig + 0x0000000008006890 0x5c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x00000000080068ec 0x96 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + 0x00000000080068ec HAL_I2CEx_ConfigAnalogFilter + .text.HAL_I2CEx_ConfigDigitalFilter + 0x0000000008006982 0x98 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + 0x0000000008006982 HAL_I2CEx_ConfigDigitalFilter + *fill* 0x0000000008006a1a 0x2 + .text.HAL_LTDC_Init + 0x0000000008006a1c 0x1a0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006a1c HAL_LTDC_Init + .text.HAL_LTDC_IRQHandler + 0x0000000008006bbc 0x148 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006bbc HAL_LTDC_IRQHandler + .text.HAL_LTDC_ErrorCallback + 0x0000000008006d04 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006d04 HAL_LTDC_ErrorCallback + .text.HAL_LTDC_LineEventCallback + 0x0000000008006d18 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006d18 HAL_LTDC_LineEventCallback + .text.HAL_LTDC_ReloadEventCallback + 0x0000000008006d2c 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006d2c HAL_LTDC_ReloadEventCallback + .text.HAL_LTDC_ConfigLayer + 0x0000000008006d40 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006d40 HAL_LTDC_ConfigLayer + .text.HAL_LTDC_GetState + 0x0000000008006dbc 0x1c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0x0000000008006dbc HAL_LTDC_GetState + .text.LTDC_SetConfig + 0x0000000008006dd8 0x334 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .text.HAL_PWR_EnableBkUpAccess + 0x000000000800710c 0x20 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + 0x000000000800710c HAL_PWR_EnableBkUpAccess + .text.HAL_PWREx_EnableOverDrive + 0x000000000800712c 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + 0x000000000800712c HAL_PWREx_EnableOverDrive + .text.HAL_RCC_OscConfig + 0x00000000080071cc 0x548 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x00000000080071cc HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x0000000008007714 0x1d8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x0000000008007714 HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x00000000080078ec 0x164 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x00000000080078ec HAL_RCC_GetSysClockFreq + .text.HAL_RCC_GetHCLKFreq + 0x0000000008007a50 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x0000000008007a50 HAL_RCC_GetHCLKFreq + .text.HAL_RCC_GetPCLK1Freq + 0x0000000008007a68 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x0000000008007a68 HAL_RCC_GetPCLK1Freq + .text.HAL_RCC_GetPCLK2Freq + 0x0000000008007a90 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x0000000008007a90 HAL_RCC_GetPCLK2Freq + .text.HAL_RCC_GetClockConfig + 0x0000000008007ab8 0x64 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0x0000000008007ab8 HAL_RCC_GetClockConfig + .text.HAL_RCCEx_PeriphCLKConfig + 0x0000000008007b1c 0x7dc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + 0x0000000008007b1c HAL_RCCEx_PeriphCLKConfig + .text.HAL_RTC_Init + 0x00000000080082f8 0xf8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x00000000080082f8 HAL_RTC_Init + .text.HAL_RTC_SetTime + 0x00000000080083f0 0x17c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x00000000080083f0 HAL_RTC_SetTime + .text.HAL_RTC_SetDate + 0x000000000800856c 0x150 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x000000000800856c HAL_RTC_SetDate + .text.HAL_RTC_SetAlarm + 0x00000000080086bc 0x230 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x00000000080086bc HAL_RTC_SetAlarm + .text.HAL_RTC_WaitForSynchro + 0x00000000080088ec 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x00000000080088ec HAL_RTC_WaitForSynchro + .text.RTC_EnterInitMode + 0x000000000800893c 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x000000000800893c RTC_EnterInitMode + .text.RTC_ByteToBcd2 + 0x0000000008008994 0x3c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0x0000000008008994 RTC_ByteToBcd2 + .text.HAL_RTCEx_SetTimeStamp + 0x00000000080089d0 0xac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + 0x00000000080089d0 HAL_RTCEx_SetTimeStamp + .text.HAL_SDRAM_Init + 0x0000000008008a7c 0x68 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + 0x0000000008008a7c HAL_SDRAM_Init + .text.HAL_SDRAM_SendCommand + 0x0000000008008ae4 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + 0x0000000008008ae4 HAL_SDRAM_SendCommand + .text.HAL_SDRAM_ProgramRefreshRate + 0x0000000008008b3a 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + 0x0000000008008b3a HAL_SDRAM_ProgramRefreshRate + .text.HAL_SPI_Init + 0x0000000008008b7a 0x124 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + 0x0000000008008b7a HAL_SPI_Init + .text.HAL_TIM_Base_Init + 0x0000000008008c9e 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008c9e HAL_TIM_Base_Init + .text.HAL_TIM_Base_Start_IT + 0x0000000008008cf4 0x54 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008cf4 HAL_TIM_Base_Start_IT + .text.HAL_TIM_PWM_Init + 0x0000000008008d48 0x56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008d48 HAL_TIM_PWM_Init + .text.HAL_TIM_PWM_MspInit + 0x0000000008008d9e 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008d9e HAL_TIM_PWM_MspInit + .text.HAL_TIM_IRQHandler + 0x0000000008008db2 0x23e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008db2 HAL_TIM_IRQHandler + .text.HAL_TIM_PWM_ConfigChannel + 0x0000000008008ff0 0x230 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008008ff0 HAL_TIM_PWM_ConfigChannel + .text.HAL_TIM_ConfigClockSource + 0x0000000008009220 0x174 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009220 HAL_TIM_ConfigClockSource + .text.HAL_TIM_SlaveConfigSynchro + 0x0000000008009394 0x84 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009394 HAL_TIM_SlaveConfigSynchro + .text.HAL_TIM_OC_DelayElapsedCallback + 0x0000000008009418 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009418 HAL_TIM_OC_DelayElapsedCallback + .text.HAL_TIM_IC_CaptureCallback + 0x000000000800942c 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x000000000800942c HAL_TIM_IC_CaptureCallback + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0000000008009440 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009440 HAL_TIM_PWM_PulseFinishedCallback + .text.HAL_TIM_TriggerCallback + 0x0000000008009454 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009454 HAL_TIM_TriggerCallback + .text.TIM_Base_SetConfig + 0x0000000008009468 0x140 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009468 TIM_Base_SetConfig + .text.TIM_OC1_SetConfig + 0x00000000080095a8 0xe4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_OC2_SetConfig + 0x000000000800968c 0xf0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x000000000800968c TIM_OC2_SetConfig + .text.TIM_OC3_SetConfig + 0x000000000800977c 0xec Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x0000000008009868 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_OC5_SetConfig + 0x0000000008009918 0xa4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_OC6_SetConfig + 0x00000000080099bc 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_SlaveTimer_SetConfig + 0x0000000008009a64 0x110 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI1_ConfigInputStage + 0x0000000008009b74 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_TI2_ConfigInputStage + 0x0000000008009bd2 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_ITRx_SetConfig + 0x0000000008009c32 0x36 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .text.TIM_ETR_SetConfig + 0x0000000008009c68 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0x0000000008009c68 TIM_ETR_SetConfig + .text.HAL_TIMEx_MasterConfigSynchronization + 0x0000000008009ca8 0x11c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0x0000000008009ca8 HAL_TIMEx_MasterConfigSynchronization + .text.HAL_TIMEx_ConfigBreakDeadTime + 0x0000000008009dc4 0xfc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0x0000000008009dc4 HAL_TIMEx_ConfigBreakDeadTime + .text.HAL_TIMEx_CommutCallback + 0x0000000008009ec0 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0x0000000008009ec0 HAL_TIMEx_CommutCallback + .text.HAL_TIMEx_BreakCallback + 0x0000000008009ed4 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0x0000000008009ed4 HAL_TIMEx_BreakCallback + .text.HAL_TIMEx_Break2Callback + 0x0000000008009ee8 0x14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0x0000000008009ee8 HAL_TIMEx_Break2Callback + .text.HAL_UART_Init + 0x0000000008009efc 0x9c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0x0000000008009efc HAL_UART_Init + .text.UART_SetConfig + 0x0000000008009f98 0x554 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0x0000000008009f98 UART_SetConfig + .text.UART_AdvFeatureConfig + 0x000000000800a4ec 0x144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0x000000000800a4ec UART_AdvFeatureConfig + .text.UART_CheckIdleState + 0x000000000800a630 0x5e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0x000000000800a630 UART_CheckIdleState + .text.UART_WaitOnFlagUntilTimeout + 0x000000000800a68e 0xf6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0x000000000800a68e UART_WaitOnFlagUntilTimeout + .text.FMC_SDRAM_Init + 0x000000000800a784 0xe4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + 0x000000000800a784 FMC_SDRAM_Init + .text.FMC_SDRAM_Timing_Init + 0x000000000800a868 0x100 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + 0x000000000800a868 FMC_SDRAM_Timing_Init + .text.FMC_SDRAM_SendCommand + 0x000000000800a968 0x42 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + 0x000000000800a968 FMC_SDRAM_SendCommand + .text.FMC_SDRAM_ProgramRefreshRate + 0x000000000800a9aa 0x26 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + 0x000000000800a9aa FMC_SDRAM_ProgramRefreshRate + .text.makeFreeRtosPriority + 0x000000000800a9d0 0x30 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .text.osThreadCreate + 0x000000000800aa00 0x98 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + 0x000000000800aa00 osThreadCreate + .text.osDelay 0x000000000800aa98 0x28 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + 0x000000000800aa98 osDelay + .text.vListInitialise + 0x000000000800aac0 0x40 Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800aac0 vListInitialise + .text.vListInitialiseItem + 0x000000000800ab00 0x1a Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800ab00 vListInitialiseItem + .text.vListInsertEnd + 0x000000000800ab1a 0x48 Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800ab1a vListInsertEnd + .text.vListInsert + 0x000000000800ab62 0x72 Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800ab62 vListInsert + .text.uxListRemove + 0x000000000800abd4 0x54 Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x000000000800abd4 uxListRemove + .text.xTaskCreateStatic + 0x000000000800ac28 0xc0 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800ac28 xTaskCreateStatic + .text.xTaskCreate + 0x000000000800ace8 0x8a Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800ace8 xTaskCreate + .text.prvInitialiseNewTask + 0x000000000800ad72 0x126 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvAddNewTaskToReadyList + 0x000000000800ae98 0xd4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.vTaskDelay + 0x000000000800af6c 0x6c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800af6c vTaskDelay + .text.vTaskSuspendAll + 0x000000000800afd8 0x1c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800afd8 vTaskSuspendAll + .text.xTaskResumeAll + 0x000000000800aff4 0x13c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800aff4 xTaskResumeAll + .text.xTaskIncrementTick + 0x000000000800b130 0x174 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800b130 xTaskIncrementTick + .text.vTaskSwitchContext + 0x000000000800b2a4 0x104 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000800b2a4 vTaskSwitchContext + .text.prvInitialiseTaskLists + 0x000000000800b3a8 0x80 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvResetNextTaskUnblockTime + 0x000000000800b428 0x40 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.prvAddCurrentTaskToDelayedList + 0x000000000800b468 0xcc Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .text.pxPortInitialiseStack + 0x000000000800b534 0x68 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b534 pxPortInitialiseStack + .text.prvTaskExitError + 0x000000000800b59c 0x5c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + *fill* 0x000000000800b5f8 0x8 + .text.SVC_Handler + 0x000000000800b600 0x28 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b600 SVC_Handler + .text.vPortEnterCritical + 0x000000000800b628 0x64 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b628 vPortEnterCritical + .text.vPortExitCritical + 0x000000000800b68c 0x54 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b68c vPortExitCritical + .text.PendSV_Handler + 0x000000000800b6e0 0x68 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b6e0 PendSV_Handler + .text.SysTick_Handler + 0x000000000800b748 0x44 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x000000000800b748 SysTick_Handler + .text.pvPortMalloc + 0x000000000800b78c 0x198 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x000000000800b78c pvPortMalloc + .text.vPortFree + 0x000000000800b924 0xb8 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x000000000800b924 vPortFree + .text.prvHeapInit + 0x000000000800b9dc 0xc4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.prvInsertBlockIntoFreeList + 0x000000000800baa0 0xb4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .text.__errno 0x000000000800bb54 0xc /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + 0x000000000800bb54 __errno + .text.__libc_init_array + 0x000000000800bb60 0x48 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + 0x000000000800bb60 __libc_init_array + .text.memcpy 0x000000000800bba8 0x16 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + 0x000000000800bba8 memcpy + .text.memset 0x000000000800bbbe 0x10 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + 0x000000000800bbbe memset + *fill* 0x000000000800bbce 0x2 + .text.sprintf 0x000000000800bbd0 0x40 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + 0x000000000800bbd0 sprintf + 0x000000000800bbd0 siprintf + .text.__ssputs_r + 0x000000000800bc10 0xb4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + 0x000000000800bc10 __ssputs_r + .text._svfprintf_r + 0x000000000800bcc4 0x1f0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + 0x000000000800bcc4 _svfprintf_r + 0x000000000800bcc4 _svfiprintf_r + .text._printf_common + 0x000000000800beb4 0xea /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000800beb4 _printf_common + *fill* 0x000000000800bf9e 0x2 + .text._printf_i + 0x000000000800bfa0 0x224 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000800bfa0 _printf_i + .text.memmove 0x000000000800c1c4 0x32 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + 0x000000000800c1c4 memmove + *fill* 0x000000000800c1f6 0x2 + .text._free_r 0x000000000800c1f8 0x9c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + 0x000000000800c1f8 _free_r + .text._malloc_r + 0x000000000800c294 0xb4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x000000000800c294 _malloc_r + .text._realloc_r + 0x000000000800c348 0x4c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + 0x000000000800c348 _realloc_r + .text._sbrk_r 0x000000000800c394 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + 0x000000000800c394 _sbrk_r + .text.__malloc_lock + 0x000000000800c3b4 0x2 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + 0x000000000800c3b4 __malloc_lock + .text.__malloc_unlock + 0x000000000800c3b6 0x2 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + 0x000000000800c3b6 __malloc_unlock + .text._malloc_usable_size_r + 0x000000000800c3b8 0x10 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + 0x000000000800c3b8 _malloc_usable_size_r + *(.glue_7) + .glue_7 0x000000000800c3c8 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x000000000800c3c8 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x000000000800c3c8 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + *(.init) + .init 0x000000000800c3c8 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + 0x000000000800c3c8 _init + .init 0x000000000800c3cc 0x8 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + *(.fini) + .fini 0x000000000800c3d4 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + 0x000000000800c3d4 _fini + .fini 0x000000000800c3d8 0x8 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + 0x000000000800c3e0 . = ALIGN (0x4) + 0x000000000800c3e0 _etext = . + +.vfp11_veneer 0x000000000800c3e0 0x0 + .vfp11_veneer 0x000000000800c3e0 0x0 linker stubs + +.v4_bx 0x000000000800c3e0 0x0 + .v4_bx 0x000000000800c3e0 0x0 linker stubs + +.iplt 0x000000000800c3e0 0x0 + .iplt 0x000000000800c3e0 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + +.rodata 0x000000000800c3e0 0x1fe4 + 0x000000000800c3e0 . = ALIGN (0x4) + *(.rodata) + .rodata 0x000000000800c3e0 0x64 Core/Src/main.o + *(.rodata*) + .rodata.Font24_Table + 0x000000000800c444 0x1ab8 Core/Src/stm32746g_discovery_lcd.o + 0x000000000800c444 Font24_Table + .rodata.Font12_Table + 0x000000000800defc 0x474 Core/Src/stm32746g_discovery_lcd.o + 0x000000000800defc Font12_Table + .rodata.AHBPrescTable + 0x000000000800e370 0x10 Core/Src/system_stm32f7xx.o + 0x000000000800e370 AHBPrescTable + .rodata.APBPrescTable + 0x000000000800e380 0x8 Core/Src/system_stm32f7xx.o + 0x000000000800e380 APBPrescTable + .rodata.flagBitshiftOffset.9876 + 0x000000000800e388 0x8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .rodata._svfprintf_r.str1.1 + 0x000000000800e390 0x11 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .rodata._printf_i.str1.1 + 0x000000000800e3a1 0x22 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000800e3c4 . = ALIGN (0x4) + *fill* 0x000000000800e3c3 0x1 + +.ARM.extab 0x000000000800e3c4 0x0 + 0x000000000800e3c4 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x000000000800e3c4 . = ALIGN (0x4) + +.ARM 0x000000000800e3c4 0x8 + 0x000000000800e3c4 . = ALIGN (0x4) + 0x000000000800e3c4 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x000000000800e3c4 0x8 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + 0x000000000800e3cc __exidx_end = . + 0x000000000800e3cc . = ALIGN (0x4) + +.rel.dyn 0x000000000800e3cc 0x0 + .rel.iplt 0x000000000800e3cc 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + +.preinit_array 0x000000000800e3cc 0x0 + 0x000000000800e3cc . = ALIGN (0x4) + 0x000000000800e3cc PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x000000000800e3cc PROVIDE (__preinit_array_end = .) + 0x000000000800e3cc . = ALIGN (0x4) + +.init_array 0x000000000800e3cc 0x4 + 0x000000000800e3cc . = ALIGN (0x4) + 0x000000000800e3cc PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x000000000800e3cc 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + 0x000000000800e3d0 PROVIDE (__init_array_end = .) + 0x000000000800e3d0 . = ALIGN (0x4) + +.fini_array 0x000000000800e3d0 0x4 + 0x000000000800e3d0 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x000000000800e3d0 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x000000000800e3d4 . = ALIGN (0x4) + 0x000000000800e3d4 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0xb0 load address 0x000000000800e3d4 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.ft5336_ts_drv + 0x0000000020000000 0x28 Core/Src/ft5336.o + 0x0000000020000000 ft5336_ts_drv + .data.Font24 0x0000000020000028 0x8 Core/Src/stm32746g_discovery_lcd.o + 0x0000000020000028 Font24 + .data.Font12 0x0000000020000030 0x8 Core/Src/stm32746g_discovery_lcd.o + 0x0000000020000030 Font12 + .data.sdramstatus.9792 + 0x0000000020000038 0x1 Core/Src/stm32746g_discovery_sdram.o + *fill* 0x0000000020000039 0x3 + .data.SystemCoreClock + 0x000000002000003c 0x4 Core/Src/system_stm32f7xx.o + 0x000000002000003c SystemCoreClock + .data.uwTickPrio + 0x0000000020000040 0x4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x0000000020000040 uwTickPrio + .data.uwTickFreq + 0x0000000020000044 0x1 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x0000000020000044 uwTickFreq + *fill* 0x0000000020000045 0x3 + .data.uxCriticalNesting + 0x0000000020000048 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .data._impure_ptr + 0x000000002000004c 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + 0x000000002000004c _impure_ptr + .data.impure_data + 0x0000000020000050 0x60 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + *(.RamFunc) + *(.RamFunc*) + 0x00000000200000b0 . = ALIGN (0x4) + 0x00000000200000b0 _edata = . + +.igot.plt 0x00000000200000b0 0x0 load address 0x000000000800e484 + .igot.plt 0x00000000200000b0 0x0 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + 0x00000000200000b0 . = ALIGN (0x4) + +.bss 0x00000000200000b0 0x8a4c load address 0x000000000800e484 + 0x00000000200000b0 _sbss = . + 0x00000000200000b0 __bss_start__ = _sbss + *(.bss) + .bss 0x00000000200000b0 0x1c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + *(.bss*) + .bss.ft5336_handle + 0x00000000200000cc 0x3 Core/Src/ft5336.o + *fill* 0x00000000200000cf 0x1 + .bss.coord.5529 + 0x00000000200000d0 0x2 Core/Src/ft5336.o + *fill* 0x00000000200000d2 0x2 + .bss.TS_State.12025 + 0x00000000200000d4 0x2c Core/Src/main.o + .bss.hI2cAudioHandler + 0x0000000020000100 0x4c Core/Src/stm32746g_discovery.o + .bss.hDma2dHandler + 0x000000002000014c 0x40 Core/Src/stm32746g_discovery_lcd.o + .bss.ActiveLayer + 0x000000002000018c 0x4 Core/Src/stm32746g_discovery_lcd.o + .bss.DrawProp 0x0000000020000190 0x18 Core/Src/stm32746g_discovery_lcd.o + .bss.periph_clk_init_struct.10379 + 0x00000000200001a8 0x84 Core/Src/stm32746g_discovery_lcd.o + .bss.Timing 0x000000002000022c 0x1c Core/Src/stm32746g_discovery_sdram.o + .bss.Command 0x0000000020000248 0x10 Core/Src/stm32746g_discovery_sdram.o + .bss.dma_handle.9828 + 0x0000000020000258 0x60 Core/Src/stm32746g_discovery_sdram.o + .bss.tsDriver 0x00000000200002b8 0x4 Core/Src/stm32746g_discovery_ts.o + .bss.tsXBoundary + 0x00000000200002bc 0x2 Core/Src/stm32746g_discovery_ts.o + .bss.tsYBoundary + 0x00000000200002be 0x2 Core/Src/stm32746g_discovery_ts.o + .bss.tsOrientation + 0x00000000200002c0 0x1 Core/Src/stm32746g_discovery_ts.o + .bss.I2cAddress + 0x00000000200002c1 0x1 Core/Src/stm32746g_discovery_ts.o + *fill* 0x00000000200002c2 0x2 + .bss._x.9944 0x00000000200002c4 0x14 Core/Src/stm32746g_discovery_ts.o + .bss._y.9945 0x00000000200002d8 0x14 Core/Src/stm32746g_discovery_ts.o + .bss.FMC_Initialized + 0x00000000200002ec 0x4 Core/Src/stm32f7xx_hal_msp.o + .bss.__sbrk_heap_end + 0x00000000200002f0 0x4 Core/Src/sysmem.o + .bss.pxCurrentTCB + 0x00000000200002f4 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x00000000200002f4 pxCurrentTCB + .bss.pxReadyTasksLists + 0x00000000200002f8 0x8c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xDelayedTaskList1 + 0x0000000020000384 0x14 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xDelayedTaskList2 + 0x0000000020000398 0x14 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.pxDelayedTaskList + 0x00000000200003ac 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.pxOverflowDelayedTaskList + 0x00000000200003b0 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xPendingReadyList + 0x00000000200003b4 0x14 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xTasksWaitingTermination + 0x00000000200003c8 0x14 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xSuspendedTaskList + 0x00000000200003dc 0x14 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxCurrentNumberOfTasks + 0x00000000200003f0 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xTickCount + 0x00000000200003f4 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxTopReadyPriority + 0x00000000200003f8 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xSchedulerRunning + 0x00000000200003fc 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxPendedTicks + 0x0000000020000400 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xYieldPending + 0x0000000020000404 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xNumOfOverflows + 0x0000000020000408 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxTaskNumber + 0x000000002000040c 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.xNextTaskUnblockTime + 0x0000000020000410 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.uxSchedulerSuspended + 0x0000000020000414 0x4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .bss.ucHeap 0x0000000020000418 0x8000 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xStart 0x0000000020008418 0x8 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.pxEnd 0x0000000020008420 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xFreeBytesRemaining + 0x0000000020008424 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xMinimumEverFreeBytesRemaining + 0x0000000020008428 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.xBlockAllocatedBit + 0x000000002000842c 0x4 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.__malloc_free_list + 0x0000000020008430 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x0000000020008430 __malloc_free_list + .bss.__malloc_sbrk_start + 0x0000000020008434 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + 0x0000000020008434 __malloc_sbrk_start + *(COMMON) + COMMON 0x0000000020008438 0x5a0 Core/Src/main.o + 0x0000000020008438 defaultTaskHandle + 0x000000002000843c hi2c3 + 0x0000000020008488 hspi2 + 0x00000000200084ec huart7 + 0x000000002000856c htim8 + 0x00000000200085ac hi2c1 + 0x00000000200085f8 htim5 + 0x0000000020008638 htim3 + 0x0000000020008678 hltdc + 0x0000000020008720 hadc1 + 0x0000000020008768 hadc3 + 0x00000000200087b0 huart1 + 0x0000000020008830 hdac + 0x0000000020008844 hrtc + 0x0000000020008864 htim1 + 0x00000000200088a4 huart6 + 0x0000000020008924 hdma2d + 0x0000000020008964 htim2 + 0x00000000200089a4 hsdram1 + COMMON 0x00000000200089d8 0xa8 Core/Src/stm32746g_discovery_lcd.o + 0x00000000200089d8 hLtdcHandler + COMMON 0x0000000020008a80 0x34 Core/Src/stm32746g_discovery_sdram.o + 0x0000000020008a80 sdramHandle + COMMON 0x0000000020008ab4 0x40 Core/Src/stm32f7xx_hal_timebase_tim.o + 0x0000000020008ab4 htim6 + COMMON 0x0000000020008af4 0x4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0x0000000020008af4 uwTick + COMMON 0x0000000020008af8 0x4 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + 0x0000000020008af8 errno + 0x0000000020008afc . = ALIGN (0x4) + 0x0000000020008afc _ebss = . + 0x0000000020008afc __bss_end__ = _ebss + +._user_heap_stack + 0x0000000020008afc 0x604 load address 0x000000000800e484 + 0x0000000020008b00 . = ALIGN (0x8) + *fill* 0x0000000020008afc 0x4 + [!provide] PROVIDE (end = .) + 0x0000000020008b00 PROVIDE (_end = .) + 0x0000000020008d00 . = (. + _Min_Heap_Size) + *fill* 0x0000000020008b00 0x200 + 0x0000000020009100 . = (. + _Min_Stack_Size) + *fill* 0x0000000020008d00 0x400 + 0x0000000020009100 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x22 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .ARM.attributes + 0x0000000000000022 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + .ARM.attributes + 0x0000000000000056 0x39 Core/Src/freertos.o + .ARM.attributes + 0x000000000000008f 0x39 Core/Src/ft5336.o + .ARM.attributes + 0x00000000000000c8 0x39 Core/Src/main.o + .ARM.attributes + 0x0000000000000101 0x39 Core/Src/stm32746g_discovery.o + .ARM.attributes + 0x000000000000013a 0x39 Core/Src/stm32746g_discovery_lcd.o + .ARM.attributes + 0x0000000000000173 0x39 Core/Src/stm32746g_discovery_sdram.o + .ARM.attributes + 0x00000000000001ac 0x39 Core/Src/stm32746g_discovery_ts.o + .ARM.attributes + 0x00000000000001e5 0x39 Core/Src/stm32f7xx_hal_msp.o + .ARM.attributes + 0x000000000000021e 0x39 Core/Src/stm32f7xx_hal_timebase_tim.o + .ARM.attributes + 0x0000000000000257 0x39 Core/Src/stm32f7xx_it.o + .ARM.attributes + 0x0000000000000290 0x39 Core/Src/sysmem.o + .ARM.attributes + 0x00000000000002c9 0x39 Core/Src/system_stm32f7xx.o + .ARM.attributes + 0x0000000000000302 0x21 Core/Startup/startup_stm32f746nghx.o + .ARM.attributes + 0x0000000000000323 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .ARM.attributes + 0x000000000000035c 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .ARM.attributes + 0x0000000000000395 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .ARM.attributes + 0x00000000000003ce 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .ARM.attributes + 0x0000000000000407 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .ARM.attributes + 0x0000000000000440 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .ARM.attributes + 0x0000000000000479 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .ARM.attributes + 0x00000000000004b2 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .ARM.attributes + 0x00000000000004eb 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .ARM.attributes + 0x0000000000000524 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .ARM.attributes + 0x000000000000055d 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .ARM.attributes + 0x0000000000000596 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .ARM.attributes + 0x00000000000005cf 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000608 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .ARM.attributes + 0x0000000000000641 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .ARM.attributes + 0x000000000000067a 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .ARM.attributes + 0x00000000000006b3 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .ARM.attributes + 0x00000000000006ec 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .ARM.attributes + 0x0000000000000725 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .ARM.attributes + 0x000000000000075e 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .ARM.attributes + 0x0000000000000797 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .ARM.attributes + 0x00000000000007d0 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .ARM.attributes + 0x0000000000000809 0x39 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .ARM.attributes + 0x0000000000000842 0x39 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .ARM.attributes + 0x000000000000087b 0x39 Middlewares/Third_Party/FreeRTOS/Source/list.o + .ARM.attributes + 0x00000000000008b4 0x39 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .ARM.attributes + 0x00000000000008ed 0x39 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .ARM.attributes + 0x0000000000000926 0x39 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .ARM.attributes + 0x000000000000095f 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + .ARM.attributes + 0x0000000000000993 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x00000000000009c7 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x00000000000009fb 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + .ARM.attributes + 0x0000000000000a2f 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000a63 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .ARM.attributes + 0x0000000000000a97 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .ARM.attributes + 0x0000000000000acb 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + .ARM.attributes + 0x0000000000000aff 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memchr.o) + .ARM.attributes + 0x0000000000000b1f 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + .ARM.attributes + 0x0000000000000b53 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + .ARM.attributes + 0x0000000000000b87 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .ARM.attributes + 0x0000000000000bbb 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + .ARM.attributes + 0x0000000000000bef 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + .ARM.attributes + 0x0000000000000c23 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + .ARM.attributes + 0x0000000000000c57 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + .ARM.attributes + 0x0000000000000c8b 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .ARM.attributes + 0x0000000000000cbf 0x22 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000000000000ce1 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000000d15 0x22 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000d37 0x22 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o +OUTPUT(prog_demo_2021.elf elf32-littlearm) + +.debug_info 0x0000000000000000 0x29de5 + .debug_info 0x0000000000000000 0x3c1 Core/Src/freertos.o + .debug_info 0x00000000000003c1 0x591 Core/Src/ft5336.o + .debug_info 0x0000000000000952 0x3b6b Core/Src/main.o + .debug_info 0x00000000000044bd 0x19bb Core/Src/stm32746g_discovery.o + .debug_info 0x0000000000005e78 0x2264 Core/Src/stm32746g_discovery_lcd.o + .debug_info 0x00000000000080dc 0xf1e Core/Src/stm32746g_discovery_sdram.o + .debug_info 0x0000000000008ffa 0x9dd Core/Src/stm32746g_discovery_ts.o + .debug_info 0x00000000000099d7 0x2ae9 Core/Src/stm32f7xx_hal_msp.o + .debug_info 0x000000000000c4c0 0xbe7 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_info 0x000000000000d0a7 0xbdf Core/Src/stm32f7xx_it.o + .debug_info 0x000000000000dc86 0x985 Core/Src/sysmem.o + .debug_info 0x000000000000e60b 0x73d Core/Src/system_stm32f7xx.o + .debug_info 0x000000000000ed48 0x22 Core/Startup/startup_stm32f746nghx.o + .debug_info 0x000000000000ed6a 0x9d3 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_info 0x000000000000f73d 0xc9d Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_info 0x00000000000103da 0x104a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_info 0x0000000000011424 0xa3a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_info 0x0000000000011e5e 0x7c0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_info 0x000000000001261e 0x968 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_info 0x0000000000012f86 0xee9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_info 0x0000000000013e6f 0x7dc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_info 0x000000000001464b 0x1fb9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_info 0x0000000000016604 0x738 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_info 0x0000000000016d3c 0x1104 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_info 0x0000000000017e40 0x9b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_info 0x00000000000187f4 0x96b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_info 0x000000000001915f 0x935 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_info 0x0000000000019a94 0x7ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_info 0x000000000001a241 0xc56 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_info 0x000000000001ae97 0xff7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_info 0x000000000001be8e 0xca1 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_info 0x000000000001cb2f 0x166a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_info 0x000000000001e199 0x25a2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_info 0x000000000002073b 0x121c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_info 0x0000000000021957 0x16d1 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_info 0x0000000000023028 0xccd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_info 0x0000000000023cf5 0x1ea9 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_info 0x0000000000025b9e 0xacb Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_info 0x0000000000026669 0x2699 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_info 0x0000000000028d02 0x4e4 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_info 0x00000000000291e6 0xbff Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_abbrev 0x0000000000000000 0x51ee + .debug_abbrev 0x0000000000000000 0x12a Core/Src/freertos.o + .debug_abbrev 0x000000000000012a 0x1ea Core/Src/ft5336.o + .debug_abbrev 0x0000000000000314 0x2cd Core/Src/main.o + .debug_abbrev 0x00000000000005e1 0x287 Core/Src/stm32746g_discovery.o + .debug_abbrev 0x0000000000000868 0x298 Core/Src/stm32746g_discovery_lcd.o + .debug_abbrev 0x0000000000000b00 0x218 Core/Src/stm32746g_discovery_sdram.o + .debug_abbrev 0x0000000000000d18 0x22b Core/Src/stm32746g_discovery_ts.o + .debug_abbrev 0x0000000000000f43 0x24d Core/Src/stm32f7xx_hal_msp.o + .debug_abbrev 0x0000000000001190 0x19d Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_abbrev 0x000000000000132d 0x169 Core/Src/stm32f7xx_it.o + .debug_abbrev 0x0000000000001496 0x19b Core/Src/sysmem.o + .debug_abbrev 0x0000000000001631 0x147 Core/Src/system_stm32f7xx.o + .debug_abbrev 0x0000000000001778 0x12 Core/Startup/startup_stm32f746nghx.o + .debug_abbrev 0x000000000000178a 0x1c7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_abbrev 0x0000000000001951 0x205 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_abbrev 0x0000000000001b56 0x2fa Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_abbrev 0x0000000000001e50 0x1e4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_abbrev 0x0000000000002034 0x1e8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_abbrev 0x000000000000221c 0x229 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_abbrev 0x0000000000002445 0x211 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_abbrev 0x0000000000002656 0x1c9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_abbrev 0x000000000000281f 0x22a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_abbrev 0x0000000000002a49 0x178 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_abbrev 0x0000000000002bc1 0x209 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_abbrev 0x0000000000002dca 0x1b6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_abbrev 0x0000000000002f80 0x1b8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_abbrev 0x0000000000003138 0x21a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_abbrev 0x0000000000003352 0x1ad Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_abbrev 0x00000000000034ff 0x1be Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_abbrev 0x00000000000036bd 0x1e9 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_abbrev 0x00000000000038a6 0x1f7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_abbrev 0x0000000000003a9d 0x228 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_abbrev 0x0000000000003cc5 0x230 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_abbrev 0x0000000000003ef5 0x21e Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_abbrev 0x0000000000004113 0x205 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_abbrev 0x0000000000004318 0x170 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_abbrev 0x0000000000004488 0x379 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_abbrev 0x0000000000004801 0x1cf Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_abbrev 0x00000000000049d0 0x349 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_abbrev 0x0000000000004d19 0x21b Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_abbrev 0x0000000000004f34 0x2ba Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_aranges 0x0000000000000000 0x2490 + .debug_aranges + 0x0000000000000000 0x38 Core/Src/freertos.o + .debug_aranges + 0x0000000000000038 0x90 Core/Src/ft5336.o + .debug_aranges + 0x00000000000000c8 0xd8 Core/Src/main.o + .debug_aranges + 0x00000000000001a0 0x128 Core/Src/stm32746g_discovery.o + .debug_aranges + 0x00000000000002c8 0x1d8 Core/Src/stm32746g_discovery_lcd.o + .debug_aranges + 0x00000000000004a0 0x68 Core/Src/stm32746g_discovery_sdram.o + .debug_aranges + 0x0000000000000508 0x58 Core/Src/stm32746g_discovery_ts.o + .debug_aranges + 0x0000000000000560 0xd8 Core/Src/stm32f7xx_hal_msp.o + .debug_aranges + 0x0000000000000638 0x30 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_aranges + 0x0000000000000668 0x58 Core/Src/stm32f7xx_it.o + .debug_aranges + 0x00000000000006c0 0x20 Core/Src/sysmem.o + .debug_aranges + 0x00000000000006e0 0x28 Core/Src/system_stm32f7xx.o + .debug_aranges + 0x0000000000000708 0x28 Core/Startup/startup_stm32f746nghx.o + .debug_aranges + 0x0000000000000730 0x100 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_aranges + 0x0000000000000830 0xe8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_aranges + 0x0000000000000918 0x118 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_aranges + 0x0000000000000a30 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_aranges + 0x0000000000000af0 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_aranges + 0x0000000000000b60 0x90 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_aranges + 0x0000000000000bf0 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_aranges + 0x0000000000000cf8 0x58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_aranges + 0x0000000000000d50 0x288 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_aranges + 0x0000000000000fd8 0x28 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_aranges + 0x0000000000001000 0x158 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_aranges + 0x0000000000001158 0xa0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_aranges + 0x00000000000011f8 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_aranges + 0x0000000000001278 0x88 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_aranges + 0x0000000000001300 0x50 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_aranges + 0x0000000000001350 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_aranges + 0x0000000000001408 0x140 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_aranges + 0x0000000000001548 0xd0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_aranges + 0x0000000000001618 0x1d8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_aranges + 0x00000000000017f0 0x3b8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_aranges + 0x0000000000001ba8 0x160 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_aranges + 0x0000000000001d08 0x210 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_aranges + 0x0000000000001f18 0xc8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_aranges + 0x0000000000001fe0 0x1d8 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_aranges + 0x00000000000021b8 0x40 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_aranges + 0x00000000000021f8 0x1c8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_aranges + 0x00000000000023c0 0x80 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_aranges + 0x0000000000002440 0x50 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_ranges 0x0000000000000000 0x2208 + .debug_ranges 0x0000000000000000 0x28 Core/Src/freertos.o + .debug_ranges 0x0000000000000028 0x80 Core/Src/ft5336.o + .debug_ranges 0x00000000000000a8 0xc8 Core/Src/main.o + .debug_ranges 0x0000000000000170 0x118 Core/Src/stm32746g_discovery.o + .debug_ranges 0x0000000000000288 0x1c8 Core/Src/stm32746g_discovery_lcd.o + .debug_ranges 0x0000000000000450 0x58 Core/Src/stm32746g_discovery_sdram.o + .debug_ranges 0x00000000000004a8 0x48 Core/Src/stm32746g_discovery_ts.o + .debug_ranges 0x00000000000004f0 0xc8 Core/Src/stm32f7xx_hal_msp.o + .debug_ranges 0x00000000000005b8 0x20 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_ranges 0x00000000000005d8 0x48 Core/Src/stm32f7xx_it.o + .debug_ranges 0x0000000000000620 0x10 Core/Src/sysmem.o + .debug_ranges 0x0000000000000630 0x18 Core/Src/system_stm32f7xx.o + .debug_ranges 0x0000000000000648 0x20 Core/Startup/startup_stm32f746nghx.o + .debug_ranges 0x0000000000000668 0xf0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_ranges 0x0000000000000758 0xd8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_ranges 0x0000000000000830 0x108 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_ranges 0x0000000000000938 0xb0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_ranges 0x00000000000009e8 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_ranges 0x0000000000000a48 0x80 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_ranges 0x0000000000000ac8 0xf8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_ranges 0x0000000000000bc0 0x48 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_ranges 0x0000000000000c08 0x278 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_ranges 0x0000000000000e80 0x18 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_ranges 0x0000000000000e98 0x148 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_ranges 0x0000000000000fe0 0x90 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_ranges 0x0000000000001070 0x70 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_ranges 0x00000000000010e0 0x78 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_ranges 0x0000000000001158 0x40 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_ranges 0x0000000000001198 0xa8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_ranges 0x0000000000001240 0x130 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_ranges 0x0000000000001370 0xc0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_ranges 0x0000000000001430 0x1c8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_ranges 0x00000000000015f8 0x3a8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_ranges 0x00000000000019a0 0x150 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_ranges 0x0000000000001af0 0x200 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_ranges 0x0000000000001cf0 0xb8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_ranges 0x0000000000001da8 0x1c8 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_ranges 0x0000000000001f70 0x30 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_ranges 0x0000000000001fa0 0x1b8 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_ranges 0x0000000000002158 0x70 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_ranges 0x00000000000021c8 0x40 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_macro 0x0000000000000000 0x2df43 + .debug_macro 0x0000000000000000 0x2f9 Core/Src/freertos.o + .debug_macro 0x00000000000002f9 0xa5a Core/Src/freertos.o + .debug_macro 0x0000000000000d53 0x174 Core/Src/freertos.o + .debug_macro 0x0000000000000ec7 0x22 Core/Src/freertos.o + .debug_macro 0x0000000000000ee9 0x8e Core/Src/freertos.o + .debug_macro 0x0000000000000f77 0x51 Core/Src/freertos.o + .debug_macro 0x0000000000000fc8 0xef Core/Src/freertos.o + .debug_macro 0x00000000000010b7 0x6a Core/Src/freertos.o + .debug_macro 0x0000000000001121 0x1df Core/Src/freertos.o + .debug_macro 0x0000000000001300 0x109 Core/Src/freertos.o + .debug_macro 0x0000000000001409 0x15a Core/Src/freertos.o + .debug_macro 0x0000000000001563 0xde Core/Src/freertos.o + .debug_macro 0x0000000000001641 0x1c Core/Src/freertos.o + .debug_macro 0x000000000000165d 0x26 Core/Src/freertos.o + .debug_macro 0x0000000000001683 0x4c5 Core/Src/freertos.o + .debug_macro 0x0000000000001b48 0xb5 Core/Src/freertos.o + .debug_macro 0x0000000000001bfd 0xaa Core/Src/freertos.o + .debug_macro 0x0000000000001ca7 0x2bd Core/Src/freertos.o + .debug_macro 0x0000000000001f64 0x2e Core/Src/freertos.o + .debug_macro 0x0000000000001f92 0x3b Core/Src/freertos.o + .debug_macro 0x0000000000001fcd 0x1c Core/Src/freertos.o + .debug_macro 0x0000000000001fe9 0x22 Core/Src/freertos.o + .debug_macro 0x000000000000200b 0xdf Core/Src/freertos.o + .debug_macro 0x00000000000020ea 0x12cd Core/Src/freertos.o + .debug_macro 0x00000000000033b7 0x11f Core/Src/freertos.o + .debug_macro 0x00000000000034d6 0x19 Core/Src/freertos.o + .debug_macro 0x00000000000034ef 0x190f0 Core/Src/freertos.o + .debug_macro 0x000000000001c5df 0x43 Core/Src/freertos.o + .debug_macro 0x000000000001c622 0x36b4 Core/Src/freertos.o + .debug_macro 0x000000000001fcd6 0x61 Core/Src/freertos.o + .debug_macro 0x000000000001fd37 0x18ad Core/Src/freertos.o + .debug_macro 0x00000000000215e4 0x6c4 Core/Src/freertos.o + .debug_macro 0x0000000000021ca8 0x185 Core/Src/freertos.o + .debug_macro 0x0000000000021e2d 0x117 Core/Src/freertos.o + .debug_macro 0x0000000000021f44 0x1fe Core/Src/freertos.o + .debug_macro 0x0000000000022142 0x27 Core/Src/freertos.o + .debug_macro 0x0000000000022169 0x24f Core/Src/freertos.o + .debug_macro 0x00000000000223b8 0x41 Core/Src/freertos.o + .debug_macro 0x00000000000223f9 0x58 Core/Src/freertos.o + .debug_macro 0x0000000000022451 0x236 Core/Src/freertos.o + .debug_macro 0x0000000000022687 0x416 Core/Src/freertos.o + .debug_macro 0x0000000000022a9d 0x153 Core/Src/freertos.o + .debug_macro 0x0000000000022bf0 0x107 Core/Src/freertos.o + .debug_macro 0x0000000000022cf7 0x20f Core/Src/freertos.o + .debug_macro 0x0000000000022f06 0xea Core/Src/freertos.o + .debug_macro 0x0000000000022ff0 0xa0 Core/Src/freertos.o + .debug_macro 0x0000000000023090 0x3c Core/Src/freertos.o + .debug_macro 0x00000000000230cc 0x14f Core/Src/freertos.o + .debug_macro 0x000000000002321b 0x25b Core/Src/freertos.o + .debug_macro 0x0000000000023476 0x12 Core/Src/freertos.o + .debug_macro 0x0000000000023488 0x514 Core/Src/freertos.o + .debug_macro 0x000000000002399c 0x22c Core/Src/freertos.o + .debug_macro 0x0000000000023bc8 0x5a Core/Src/freertos.o + .debug_macro 0x0000000000023c22 0xa5 Core/Src/freertos.o + .debug_macro 0x0000000000023cc7 0x198 Core/Src/freertos.o + .debug_macro 0x0000000000023e5f 0xd6 Core/Src/freertos.o + .debug_macro 0x0000000000023f35 0x12f Core/Src/freertos.o + .debug_macro 0x0000000000024064 0x108 Core/Src/freertos.o + .debug_macro 0x000000000002416c 0x35 Core/Src/freertos.o + .debug_macro 0x00000000000241a1 0x313 Core/Src/freertos.o + .debug_macro 0x00000000000244b4 0x4ca Core/Src/freertos.o + .debug_macro 0x000000000002497e 0xd6 Core/Src/freertos.o + .debug_macro 0x0000000000024a54 0x2fe Core/Src/freertos.o + .debug_macro 0x0000000000024d52 0xa2f Core/Src/freertos.o + .debug_macro 0x0000000000025781 0x59 Core/Src/freertos.o + .debug_macro 0x00000000000257da 0x53c Core/Src/freertos.o + .debug_macro 0x0000000000025d16 0x44 Core/Src/freertos.o + .debug_macro 0x0000000000025d5a 0x14e Core/Src/freertos.o + .debug_macro 0x0000000000025ea8 0x3f9 Core/Src/freertos.o + .debug_macro 0x00000000000262a1 0x7b Core/Src/ft5336.o + .debug_macro 0x000000000002631c 0x10 Core/Src/ft5336.o + .debug_macro 0x000000000002632c 0x39f Core/Src/ft5336.o + .debug_macro 0x00000000000266cb 0x4f4 Core/Src/main.o + .debug_macro 0x0000000000026bbf 0x109 Core/Src/main.o + .debug_macro 0x0000000000026cc8 0x91 Core/Src/main.o + .debug_macro 0x0000000000026d59 0x8d Core/Src/main.o + .debug_macro 0x0000000000026de6 0x9a Core/Src/main.o + .debug_macro 0x0000000000026e80 0x19 Core/Src/main.o + .debug_macro 0x0000000000026e99 0xf2 Core/Src/main.o + .debug_macro 0x0000000000026f8b 0x40 Core/Src/main.o + .debug_macro 0x0000000000026fcb 0xa0 Core/Src/main.o + .debug_macro 0x000000000002706b 0x268 Core/Src/main.o + .debug_macro 0x00000000000272d3 0x10 Core/Src/main.o + .debug_macro 0x00000000000272e3 0x12a Core/Src/main.o + .debug_macro 0x000000000002740d 0x2e Core/Src/main.o + .debug_macro 0x000000000002743b 0x46 Core/Src/main.o + .debug_macro 0x0000000000027481 0x18 Core/Src/main.o + .debug_macro 0x0000000000027499 0x3c Core/Src/main.o + .debug_macro 0x00000000000274d5 0x34 Core/Src/main.o + .debug_macro 0x0000000000027509 0x16 Core/Src/main.o + .debug_macro 0x000000000002751f 0x35 Core/Src/main.o + .debug_macro 0x0000000000027554 0x32a Core/Src/main.o + .debug_macro 0x000000000002787e 0x10 Core/Src/main.o + .debug_macro 0x000000000002788e 0x52 Core/Src/main.o + .debug_macro 0x00000000000278e0 0x1f Core/Src/main.o + .debug_macro 0x00000000000278ff 0x43 Core/Src/main.o + .debug_macro 0x0000000000027942 0x20 Core/Src/main.o + .debug_macro 0x0000000000027962 0x1a3 Core/Src/main.o + .debug_macro 0x0000000000027b05 0x10 Core/Src/main.o + .debug_macro 0x0000000000027b15 0x1c Core/Src/main.o + .debug_macro 0x0000000000027b31 0x52 Core/Src/main.o + .debug_macro 0x0000000000027b83 0x40 Core/Src/main.o + .debug_macro 0x0000000000027bc3 0x10 Core/Src/main.o + .debug_macro 0x0000000000027bd3 0x40 Core/Src/main.o + .debug_macro 0x0000000000027c13 0xd7 Core/Src/main.o + .debug_macro 0x0000000000027cea 0x1c Core/Src/main.o + .debug_macro 0x0000000000027d06 0x3d Core/Src/main.o + .debug_macro 0x0000000000027d43 0x16 Core/Src/main.o + .debug_macro 0x0000000000027d59 0x145 Core/Src/main.o + .debug_macro 0x0000000000027e9e 0x2af Core/Src/stm32746g_discovery.o + .debug_macro 0x000000000002814d 0x262 Core/Src/stm32746g_discovery.o + .debug_macro 0x00000000000283af 0x2e9 Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000028698 0x9a Core/Src/stm32746g_discovery_lcd.o + .debug_macro 0x0000000000028732 0x291 Core/Src/stm32746g_discovery_sdram.o + .debug_macro 0x00000000000289c3 0x2b8 Core/Src/stm32746g_discovery_ts.o + .debug_macro 0x0000000000028c7b 0x291 Core/Src/stm32f7xx_hal_msp.o + .debug_macro 0x0000000000028f0c 0x282 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_macro 0x000000000002918e 0x29b Core/Src/stm32f7xx_it.o + .debug_macro 0x0000000000029429 0xee Core/Src/sysmem.o + .debug_macro 0x0000000000029517 0x23b Core/Src/sysmem.o + .debug_macro 0x0000000000029752 0x288 Core/Src/system_stm32f7xx.o + .debug_macro 0x00000000000299da 0x2a6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_macro 0x0000000000029c80 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_macro 0x0000000000029f03 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_macro 0x000000000002a185 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_macro 0x000000000002a408 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_macro 0x000000000002a68a 0x288 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_macro 0x000000000002a912 0x291 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_macro 0x000000000002aba3 0x2b8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_macro 0x000000000002ae5b 0x347 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_macro 0x000000000002b1a2 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_macro 0x000000000002b424 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_macro 0x000000000002b6a7 0x2a0 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_macro 0x000000000002b947 0x29a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_macro 0x000000000002bbe1 0x2a6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_macro 0x000000000002be87 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_macro 0x000000000002c109 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_macro 0x000000000002c38c 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_macro 0x000000000002c60e 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_macro 0x000000000002c890 0x28a Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_macro 0x000000000002cb1a 0x283 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_macro 0x000000000002cd9d 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_macro 0x000000000002d01f 0x29f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_macro 0x000000000002d2be 0x282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_macro 0x000000000002d540 0x1f1 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x000000000002d731 0x10 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x000000000002d741 0x20 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x000000000002d761 0xc7 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_macro 0x000000000002d828 0x17a Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_macro 0x000000000002d9a2 0x26c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x000000000002dc0e 0x10 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_macro 0x000000000002dc1e 0x184 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_macro 0x000000000002dda2 0x1a1 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_line 0x0000000000000000 0x1dc92 + .debug_line 0x0000000000000000 0x93d Core/Src/freertos.o + .debug_line 0x000000000000093d 0x525 Core/Src/ft5336.o + .debug_line 0x0000000000000e62 0x1015 Core/Src/main.o + .debug_line 0x0000000000001e77 0xb16 Core/Src/stm32746g_discovery.o + .debug_line 0x000000000000298d 0xf7e Core/Src/stm32746g_discovery_lcd.o + .debug_line 0x000000000000390b 0x92d Core/Src/stm32746g_discovery_sdram.o + .debug_line 0x0000000000004238 0x98d Core/Src/stm32746g_discovery_ts.o + .debug_line 0x0000000000004bc5 0xb0c Core/Src/stm32f7xx_hal_msp.o + .debug_line 0x00000000000056d1 0x83b Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_line 0x0000000000005f0c 0x8a0 Core/Src/stm32f7xx_it.o + .debug_line 0x00000000000067ac 0x49a Core/Src/sysmem.o + .debug_line 0x0000000000006c46 0x820 Core/Src/system_stm32f7xx.o + .debug_line 0x0000000000007466 0x85 Core/Startup/startup_stm32f746nghx.o + .debug_line 0x00000000000074eb 0xa2f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_line 0x0000000000007f1a 0xc58 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_line 0x0000000000008b72 0xb30 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_line 0x00000000000096a2 0xa60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_line 0x000000000000a102 0x923 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_line 0x000000000000aa25 0xadb Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_line 0x000000000000b500 0xd68 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_line 0x000000000000c268 0xa14 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_line 0x000000000000cc7c 0x1b8b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_line 0x000000000000e807 0x89f Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_line 0x000000000000f0a6 0x10de Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_line 0x0000000000010184 0x974 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_line 0x0000000000010af8 0x950 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_line 0x0000000000011448 0xaa5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_line 0x0000000000011eed 0xa17 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_line 0x0000000000012904 0xb97 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_line 0x000000000001349b 0xf47 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_line 0x00000000000143e2 0xb63 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_line 0x0000000000014f45 0x1282 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_line 0x00000000000161c7 0x1b4c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_line 0x0000000000017d13 0xeb7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_line 0x0000000000018bca 0x13b6 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_line 0x0000000000019f80 0xab7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_line 0x000000000001aa37 0xca3 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_line 0x000000000001b6da 0x643 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_line 0x000000000001bd1d 0x11f1 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_line 0x000000000001cf0e 0x659 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_line 0x000000000001d567 0x72b Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_str 0x0000000000000000 0x114119 + .debug_str 0x0000000000000000 0xfe52f Core/Src/freertos.o + 0xfec4a (size before relaxing) + .debug_str 0x00000000000fe52f 0x1695 Core/Src/ft5336.o + 0x5304 (size before relaxing) + .debug_str 0x00000000000ffbc4 0xa3a8 Core/Src/main.o + 0x10a6a6 (size before relaxing) + .debug_str 0x0000000000109f6c 0xa61 Core/Src/stm32746g_discovery.o + 0xfc3e2 (size before relaxing) + .debug_str 0x000000000010a9cd 0x858 Core/Src/stm32746g_discovery_lcd.o + 0xfcf08 (size before relaxing) + .debug_str 0x000000000010b225 0x1a9 Core/Src/stm32746g_discovery_sdram.o + 0xfb0b4 (size before relaxing) + .debug_str 0x000000000010b3ce 0x160 Core/Src/stm32746g_discovery_ts.o + 0xfced5 (size before relaxing) + .debug_str 0x000000000010b52e 0x207 Core/Src/stm32f7xx_hal_msp.o + 0xfcb64 (size before relaxing) + .debug_str 0x000000000010b735 0x98 Core/Src/stm32f7xx_hal_timebase_tim.o + 0xfab04 (size before relaxing) + .debug_str 0x000000000010b7cd 0xa6 Core/Src/stm32f7xx_it.o + 0xfb5c5 (size before relaxing) + .debug_str 0x000000000010b873 0x369 Core/Src/sysmem.o + 0x5f69 (size before relaxing) + .debug_str 0x000000000010bbdc 0x188 Core/Src/system_stm32f7xx.o + 0xfa160 (size before relaxing) + .debug_str 0x000000000010bd64 0x36 Core/Startup/startup_stm32f746nghx.o + 0x76 (size before relaxing) + .debug_str 0x000000000010bd9a 0x341 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + 0xfaa12 (size before relaxing) + .debug_str 0x000000000010c0db 0x281 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + 0xfa603 (size before relaxing) + .debug_str 0x000000000010c35c 0x375 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + 0xfaab9 (size before relaxing) + .debug_str 0x000000000010c6d1 0x1bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + 0xfa49e (size before relaxing) + .debug_str 0x000000000010c88e 0x164 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + 0xfa3ce (size before relaxing) + .debug_str 0x000000000010c9f2 0x323 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + 0xfa49a (size before relaxing) + .debug_str 0x000000000010cd15 0x360 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + 0xfa64b (size before relaxing) + .debug_str 0x000000000010d075 0x244 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + 0xfa336 (size before relaxing) + .debug_str 0x000000000010d2b9 0xcd4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + 0xfb24e (size before relaxing) + .debug_str 0x000000000010df8d 0x3b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + 0xfa48a (size before relaxing) + .debug_str 0x000000000010dfc8 0x406 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + 0xfa6ce (size before relaxing) + .debug_str 0x000000000010e3ce 0x2c5 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + 0xfa418 (size before relaxing) + .debug_str 0x000000000010e693 0x1bd Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + 0xfa3da (size before relaxing) + .debug_str 0x000000000010e850 0x263 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + 0xfa47b (size before relaxing) + .debug_str 0x000000000010eab3 0x159 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + 0xfa405 (size before relaxing) + .debug_str 0x000000000010ec0c 0x1ac Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + 0xfa474 (size before relaxing) + .debug_str 0x000000000010edb8 0x5b2 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + 0xfa801 (size before relaxing) + .debug_str 0x000000000010f36a 0x254 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + 0xfa66e (size before relaxing) + .debug_str 0x000000000010f5be 0x557 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + 0xfa91a (size before relaxing) + .debug_str 0x000000000010fb15 0xc4b Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + 0xfb1ec (size before relaxing) + .debug_str 0x0000000000110760 0x448 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + 0xfaa3f (size before relaxing) + .debug_str 0x0000000000110ba8 0x7c7 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + 0xfacbf (size before relaxing) + .debug_str 0x000000000011136f 0x477 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + 0xfa5be (size before relaxing) + .debug_str 0x00000000001117e6 0x92b Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + 0xe2cd (size before relaxing) + .debug_str 0x0000000000112111 0x219 Middlewares/Third_Party/FreeRTOS/Source/list.o + 0xa770 (size before relaxing) + .debug_str 0x000000000011232a 0x1413 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0xcbef (size before relaxing) + .debug_str 0x000000000011373d 0x782 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + 0x84b8 (size before relaxing) + .debug_str 0x0000000000113ebf 0x25a Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0xaf80 (size before relaxing) + +.comment 0x0000000000000000 0x7b + .comment 0x0000000000000000 0x7b Core/Src/freertos.o + 0x7c (size before relaxing) + .comment 0x000000000000007b 0x7c Core/Src/ft5336.o + .comment 0x000000000000007b 0x7c Core/Src/main.o + .comment 0x000000000000007b 0x7c Core/Src/stm32746g_discovery.o + .comment 0x000000000000007b 0x7c Core/Src/stm32746g_discovery_lcd.o + .comment 0x000000000000007b 0x7c Core/Src/stm32746g_discovery_sdram.o + .comment 0x000000000000007b 0x7c Core/Src/stm32746g_discovery_ts.o + .comment 0x000000000000007b 0x7c Core/Src/stm32f7xx_hal_msp.o + .comment 0x000000000000007b 0x7c Core/Src/stm32f7xx_hal_timebase_tim.o + .comment 0x000000000000007b 0x7c Core/Src/stm32f7xx_it.o + .comment 0x000000000000007b 0x7c Core/Src/sysmem.o + .comment 0x000000000000007b 0x7c Core/Src/system_stm32f7xx.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .comment 0x000000000000007b 0x7c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .comment 0x000000000000007b 0x7c Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .comment 0x000000000000007b 0x7c Middlewares/Third_Party/FreeRTOS/Source/list.o + .comment 0x000000000000007b 0x7c Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .comment 0x000000000000007b 0x7c Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .comment 0x000000000000007b 0x7c Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + +.debug_frame 0x0000000000000000 0x9d9c + .debug_frame 0x0000000000000000 0xa0 Core/Src/freertos.o + .debug_frame 0x00000000000000a0 0x230 Core/Src/ft5336.o + .debug_frame 0x00000000000002d0 0x330 Core/Src/main.o + .debug_frame 0x0000000000000600 0x4b0 Core/Src/stm32746g_discovery.o + .debug_frame 0x0000000000000ab0 0x840 Core/Src/stm32746g_discovery_lcd.o + .debug_frame 0x00000000000012f0 0x168 Core/Src/stm32746g_discovery_sdram.o + .debug_frame 0x0000000000001458 0x124 Core/Src/stm32746g_discovery_ts.o + .debug_frame 0x000000000000157c 0x380 Core/Src/stm32f7xx_hal_msp.o + .debug_frame 0x00000000000018fc 0x74 Core/Src/stm32f7xx_hal_timebase_tim.o + .debug_frame 0x0000000000001970 0xe0 Core/Src/stm32f7xx_it.o + .debug_frame 0x0000000000001a50 0x34 Core/Src/sysmem.o + .debug_frame 0x0000000000001a84 0x58 Core/Src/system_stm32f7xx.o + .debug_frame 0x0000000000001adc 0x3b4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o + .debug_frame 0x0000000000001e90 0x3fc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.o + .debug_frame 0x000000000000228c 0x498 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o + .debug_frame 0x0000000000002724 0x338 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.o + .debug_frame 0x0000000000002a5c 0x1bc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.o + .debug_frame 0x0000000000002c18 0x250 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o + .debug_frame 0x0000000000002e68 0x490 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.o + .debug_frame 0x00000000000032f8 0x14c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.o + .debug_frame 0x0000000000003444 0xbbc Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.o + .debug_frame 0x0000000000004000 0x60 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.o + .debug_frame 0x0000000000004060 0x61c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.o + .debug_frame 0x000000000000467c 0x254 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.o + .debug_frame 0x00000000000048d0 0x1c8 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.o + .debug_frame 0x0000000000004a98 0x1f4 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.o + .debug_frame 0x0000000000004c8c 0x118 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.o + .debug_frame 0x0000000000004da4 0x308 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.o + .debug_frame 0x00000000000050ac 0x59c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.o + .debug_frame 0x0000000000005648 0x37c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.o + .debug_frame 0x00000000000059c4 0x860 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.o + .debug_frame 0x0000000000006224 0x1144 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.o + .debug_frame 0x0000000000007368 0x610 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.o + .debug_frame 0x0000000000007978 0x96c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.o + .debug_frame 0x00000000000082e4 0x37c Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.o + .debug_frame 0x0000000000008660 0x800 Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.o + .debug_frame 0x0000000000008e60 0xd8 Middlewares/Third_Party/FreeRTOS/Source/list.o + .debug_frame 0x0000000000008f38 0x7c4 Middlewares/Third_Party/FreeRTOS/Source/tasks.o + .debug_frame 0x00000000000096fc 0x1a8 Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.o + .debug_frame 0x00000000000098a4 0x108 Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .debug_frame 0x00000000000099ac 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-errno.o) + .debug_frame 0x00000000000099cc 0x2c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-init.o) + .debug_frame 0x00000000000099f8 0x28 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memcpy-stub.o) + .debug_frame 0x0000000000009a20 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000009a40 0x6c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sprintf.o) + .debug_frame 0x0000000000009aac 0x90 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-svfprintf.o) + .debug_frame 0x0000000000009b3c 0x60 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-vfprintf_i.o) + .debug_frame 0x0000000000009b9c 0x28 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-memmove.o) + .debug_frame 0x0000000000009bc4 0x38 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-freer.o) + .debug_frame 0x0000000000009bfc 0x2c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-mallocr.o) + .debug_frame 0x0000000000009c28 0x3c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-reallocr.o) + .debug_frame 0x0000000000009c64 0x2c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-sbrkr.o) + .debug_frame 0x0000000000009c90 0x30 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-mlock.o) + .debug_frame 0x0000000000009cc0 0x20 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-nano-msizer.o) + .debug_frame 0x0000000000009ce0 0x5c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/libc_nano.a(lib_a-reent.o) + .debug_frame 0x0000000000009d3c 0x2c /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x0000000000009d68 0x34 /opt/st/stm32cubeide_1.5.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/libgcc.a(_udivmoddi4.o) diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..abaec4a --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,29 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := +OBJCOPY_BIN := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32F7xx_HAL_Driver/Src \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \ +Middlewares/Third_Party/FreeRTOS/Source \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1 \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang \ + diff --git a/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h new file mode 100644 index 0000000..2c47d3f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h @@ -0,0 +1,17860 @@ +/** + ****************************************************************************** + * @file stm32f746xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f746xx + * @{ + */ + +#ifndef __STM32F746xx_H +#define __STM32F746xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32F7xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ + + +#include "system_stm32f7xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved7; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20010000UL /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2004C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) +#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) +#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x0000UL +#define USB_OTG_DEVICE_BASE 0x0800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_EP_REG_SIZE 0x0020UL +#define USB_OTG_HOST_BASE 0x0400UL +#define USB_OTG_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx + * @{ + */ + +#ifndef __STM32F7xx_H +#define __STM32F7xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F7) +#define STM32F7 +#endif /* STM32F7 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ +#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F765xx) && \ + !defined (STM32F767xx) && !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && \ + !defined (STM32F722xx) && !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && \ + !defined (STM32F730xx) && !defined (STM32F750xx) + + /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, + STM32F756NG Devices */ + /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG, + STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */ + /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */ + /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG, + STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */ + /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI, + STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */ + /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II, + STM32F769NG, STM32F769NI, STM32F768AI Devices */ + /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */ + /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */ + /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC, + STM32F722VC, STM32F722RC Devices */ + /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */ + /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */ + /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */ + /* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */ + /* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.2.5 + */ +#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F7_CMSIS_VERSION_RC)) +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32F722xx) + #include "stm32f722xx.h" +#elif defined(STM32F723xx) + #include "stm32f723xx.h" +#elif defined(STM32F732xx) + #include "stm32f732xx.h" +#elif defined(STM32F733xx) + #include "stm32f733xx.h" +#elif defined(STM32F756xx) + #include "stm32f756xx.h" +#elif defined(STM32F746xx) + #include "stm32f746xx.h" +#elif defined(STM32F745xx) + #include "stm32f745xx.h" +#elif defined(STM32F765xx) + #include "stm32f765xx.h" +#elif defined(STM32F767xx) + #include "stm32f767xx.h" +#elif defined(STM32F769xx) + #include "stm32f769xx.h" +#elif defined(STM32F777xx) + #include "stm32f777xx.h" +#elif defined(STM32F779xx) + #include "stm32f779xx.h" +#elif defined(STM32F730xx) + #include "stm32f730xx.h" +#elif defined(STM32F750xx) + #include "stm32f750xx.h" +#else + #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0U, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +#ifdef USE_HAL_DRIVER + #include "stm32f7xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F7xx_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h new file mode 100644 index 0000000..126ac71 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h @@ -0,0 +1,123 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F7XX_H +#define __SYSTEM_STM32F7XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F7xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F7xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F7XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..7d751fb --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..d8031b0 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..79a2cac --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..1bd41a4 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..3c90a2c --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..ae3f2e3 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..ec76ab2 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1918 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..2d0f106 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2927 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..6f82227 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..b9377e8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..fd1c407 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,976 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 23. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..8202a8d --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1993 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 22. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..b0dfbd3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..02f82e2 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3002 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 06. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..308b868 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..ada6c2a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..9086c64 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..665822d --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..7d4b600 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..99ee9f9 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..2d265fb --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,3776 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h new file mode 100644 index 0000000..bc029ab --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h @@ -0,0 +1,276 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_H +#define __STM32F7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_conf.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + + +/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) + + +/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ + }while(0); +/** + * @brief Return the memory boot mapping as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_MEM_BOOT_ADD0 + * @arg @ref SYSCFG_MEM_BOOT_ADD1 + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + + /* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_EnableFMCMemorySwapping(void); +void HAL_DisableFMCMemorySwapping(void); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h new file mode 100644 index 0000000..cd9973f --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h @@ -0,0 +1,959 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_ADC_H +#define STM32F7xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. + * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for + all the ADCs. + This parameter can be a value of @ref ADC_ClockPrescaler */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_Align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. + Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. + Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) + or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. + Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). + If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ + uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge by default. + This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +}ADC_InitTypeDef; + + + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 + This parameter can be a value of @ref ADC_regular_rank */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ +}ADC_ChannelConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_analog_watchdog_selection */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel + This parameter can be a value of @ref ADC_channels */ + FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured + is interrupt mode or in polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +}ADC_HandleTypeDef; + + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler + * @{ + */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) +#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) +#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) +/** + * @} + */ + +/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) +#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) +#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) +#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular + * @{ + */ +/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ +/* compatibility with other STM32 devices. */ + + +#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) +#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) +#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) +#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3) +#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) +#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) + +#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) +#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) + +/** + * @} + */ + +/** @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_regular_rank ADC group regular sequencer rank + * @{ + */ +#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ +#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ +#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ +#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ +#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ +#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ +#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ +#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ +#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ +#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ +#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ +#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ +#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ +#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ +#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ +#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_channels ADC Common Channels + * @{ + */ +#define ADC_CHANNEL_0 ((uint32_t)0x00000000U) +#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) +#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) +#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) +#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) +#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) +#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) + +#define ADC_INTERNAL_NONE 0x80000000U +#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) +#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U)) +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC Sampling Times + * @{ + */ +#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) +#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) +#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) +#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) +#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) +#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) +/** + * @} + */ + + /** @defgroup ADC_EOCSelection ADC EOC Selection + * @{ + */ +#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) +#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event Type + * @{ + */ +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC Interrupts Definition + * @{ + */ +#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) +#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) +#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) +#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC Flags Definition + * @{ + */ +#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) +#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) +#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) +#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) +#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) +#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) +/** + * @} + */ + +/** @defgroup ADC_channels_type ADC Channels Type + * @{ + */ +#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) +#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */ +#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @brief Reset ADC handle state + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif + +/** + * @brief Enable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) + +/** + * @brief Disable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the ADC's pending flags. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f7xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ +/* Delay for ADC stabilization time. */ +/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ +/* Unit: us */ +#define ADC_STAB_DELAY_US ((uint32_t) 3U) +/* Delay for temperature sensor stabilization time. */ +/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in + code of final user */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_INTERNAL_NONE)) +#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) +#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES)) +#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_6B)) +#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START)) +#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ + ((__ALIGN__) == ADC_DATAALIGN_LEFT)) + + +#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) +#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \ + ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \ + ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT)) +#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE)) +#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) + +#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_2 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_3 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_4 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_5 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_6 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_7 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_8 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_9 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_10) || \ + ((__RANK__) == ADC_REGULAR_RANK_11) || \ + ((__RANK__) == ADC_REGULAR_RANK_12) || \ + ((__RANK__) == ADC_REGULAR_RANK_13) || \ + ((__RANK__) == ADC_REGULAR_RANK_14) || \ + ((__RANK__) == ADC_REGULAR_RANK_15) || \ + ((__RANK__) == ADC_REGULAR_RANK_16)) + +#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ + ((__SCAN_MODE__) == ADC_SCAN_ENABLE)) + +#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) +#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))) + +/** + * @brief Set ADC Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. + * @retval None + */ +#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 16. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. + * @retval None + */ +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos) + +/** + * @brief Enable ADC scan mode. + * @param _SCANCONV_MODE_ Scan conversion mode. + * @retval None + */ +#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) + +/** + * @brief Enable the ADC end of conversion selection. + * @param _EOCSelection_MODE_ End of conversion selection mode. + * @retval None + */ +#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMAContReq_MODE_ DMA continuous request mode. + * @retval None + */ +#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) + +/** + * @brief Return resolution bits in CR1 register. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_ADC_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h new file mode 100644 index 0000000..4bc259d --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_ADC_EX_H +#define STM32F7xx_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. + * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. + If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ +}ADC_InjectionConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. + This parameter can be a value of @ref ADCEx_Common_mode */ + uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. + This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ +}ADC_MultiModeTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADCEx_Common_mode ADC Common Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) +#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +/** + * @} + */ + +/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */ +#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) +#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2) +#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) + +#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3) +#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1) +/** + * @} + */ + +/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank + * @{ + */ +#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) +#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) +#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) +#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) +/** + * @} + */ + +/** @defgroup ADCEx_channels ADC Specific Channels + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Macros ADC Private Macros + * @{ + */ + +#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INTERL) || \ + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ + ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_INTERL) || \ + ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG)) +#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ + ((__MODE__) == ADC_DMAACCESSMODE_1) || \ + ((__MODE__) == ADC_DMAACCESSMODE_2) || \ + ((__MODE__) == ADC_DMAACCESSMODE_3)) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) +#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \ + ((__RANK__) == ADC_INJECTED_RANK_2) || \ + ((__RANK__) == ADC_INJECTED_RANK_3) || \ + ((__RANK__) == ADC_INJECTED_RANK_4)) +#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) + +/** + * @brief Set the selected injected Channel rank. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. + * @retval None + */ +#define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_ADC_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h new file mode 100644 index 0000000..f600c5b --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h @@ -0,0 +1,406 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CORTEX_H +#define __STM32F7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h new file mode 100644 index 0000000..f08177b --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dac.h + * @author MCD Application Team + * @brief Header file of DAC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DAC_H +#define __STM32F7xx_HAL_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ +}HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +typedef struct __DAC_HandleTypeDef +#else +typedef struct +#endif +{ + DAC_TypeDef *Instance; /*!< Register base address */ + + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ + + HAL_LockTypeDef Lock; /*!< DAC locking object */ + + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac); + + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +}DAC_HandleTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_ChannelConfTypeDef; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DAC Callback ID enumeration definition + */ +typedef enum +{ + HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ + HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ + HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ + HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ + HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ + HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ + HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ +}HAL_DAC_CallbackIDTypeDef; + +/** + * @brief HAL DAC Callback pointer definition + */ +typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code + * @{ + */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DAC_trigger_selection DAC Trigger Selection + * @{ + */ + +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ + +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_output_buffer DAC Output Buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) +#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel Selection + * @{ + */ +#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) +/** + * @} + */ + +/** @defgroup DAC_data_alignment DAC Data Alignment + * @{ + */ +#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) +#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) +#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup DAC_flags_definition DAC Flags Definition + * @{ + */ +#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +/** + * @} + */ + +/** @defgroup DAC_IT_definition DAC IT Definition + * @{ + */ +#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @brief Reset DAC handle state + * @param __HANDLE__: specifies the DAC handle. + * @retval None + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** @brief Enable the DAC channel + * @param __HANDLE__: specifies the DAC handle. + * @param __DAC_CHANNEL__: specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \ +((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__))) + +/** @brief Disable the DAC channel + * @param __HANDLE__: specifies the DAC handle + * @param __DAC_CHANNEL__: specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \ +((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__))) + + +/** @brief Enable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) + +/** @brief Disable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified DAC interrupt source is enabled or disabled. + * @param __HANDLE__: DAC handle + * @param __INTERRUPT__: DAC interrupt source to check + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag + * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag + * @retval None + */ +#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the DAC's flag. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag + * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) +/** + * @} + */ + +/* Include DAC HAL Extension module */ +#include "stm32f7xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_Private_Constants DAC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +/** @brief Set DHR12R1 alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) + +/** @brief Set DHR12R2 alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) + +/** @brief Set DHR12RD alignment + * @param __ALIGNMENT__: specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F7xx_HAL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h new file mode 100644 index 0000000..289cb5f --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dac.h + * @author MCD Application Team + * @brief Header file of DAC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DAC_EX_H +#define __STM32F7xx_HAL_DAC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DACEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DACEx_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 + * @{ + */ +/* Extension features functions ***********************************************/ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); + +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Constants DAC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DACEx_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Functions DAC Private Functions + * @{ + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F7xx_HAL_DAC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h new file mode 100644 index 0000000..b8c3a86 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DEF +#define __STM32F7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || defined ( __GNUC__ ) +/* ARM & GNUCompiler + ---------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F7xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h new file mode 100644 index 0000000..63f752a --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h @@ -0,0 +1,749 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_H +#define __STM32F7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMAEx_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ +#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 +#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 +#define DMA_MBURST_INC16 DMA_SxCR_MBURST +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 +#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 +#define DMA_PBURST_INC16 DMA_SxCR_PBURST +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC DMA_SxCR_TCIE +#define DMA_IT_HT DMA_SxCR_HTIE +#define DMA_IT_TE DMA_SxCR_TEIE +#define DMA_IT_DME DMA_SxCR_DMEIE +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h new file mode 100644 index 0000000..adb5cb2 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma2d.h + * @author MCD Application Team + * @brief Header file of DMA2D HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_DMA2D_H +#define STM32F7xx_HAL_DMA2D_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined (DMA2D) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA2D DMA2D + * @brief DMA2D HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Types DMA2D Exported Types + * @{ + */ +#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ + +/** + * @brief DMA2D CLUT Structure definition + */ +typedef struct +{ + uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ + + uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. + This parameter can be one value of @ref DMA2D_CLUT_CM. */ + + uint32_t Size; /*!< Configures the DMA2D CLUT size. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ +} DMA2D_CLUTCfgTypeDef; + +/** + * @brief DMA2D Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the DMA2D transfer mode. + This parameter can be one value of @ref DMA2D_Mode. */ + + uint32_t ColorMode; /*!< Configures the color format of the output image. + This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ + + uint32_t OutputOffset; /*!< Specifies the Offset value. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ + + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) + for the output pixel format converter. + This parameter can be one value of @ref DMA2D_RB_Swap. */ + +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + + +} DMA2D_InitTypeDef; + + +/** + * @brief DMA2D Layer structure definition + */ +typedef struct +{ + uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + + uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. + This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ + + uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. + This parameter can be one value of @ref DMA2D_Alpha_Mode. */ + + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. + @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where + - InputAlpha[24:31] is the alpha value ALPHA[0:7] + - InputAlpha[16:23] is the red value RED[0:7] + - InputAlpha[8:15] is the green value GREEN[0:7] + - InputAlpha[0:7] is the blue value BLUE[0:7]. */ +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. + This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ + + uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). + This parameter can be one value of @ref DMA2D_RB_Swap. */ +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + +} DMA2D_LayerCfgTypeDef; + +/** + * @brief HAL DMA2D State structures definition + */ +typedef enum +{ + HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ + HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ + HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ +}HAL_DMA2D_StateTypeDef; + +/** + * @brief DMA2D handle Structure definition + */ +typedef struct __DMA2D_HandleTypeDef +{ + DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ + + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ + + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ + + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ + + void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ + + void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ + + void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ + +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ + + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ +} DMA2D_HandleTypeDef; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D Callback pointer definition + */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants + * @{ + */ + +/** @defgroup DMA2D_Error_Code DMA2D Error Code + * @{ + */ +#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ +#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ +#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DMA2D_Mode DMA2D Mode + * @{ + */ +#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ +#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode + * @{ + */ +#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ +#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ +#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode + * @{ + */ +#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ +#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ +#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ +#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ +#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ +#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ +#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ +#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ +#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ +#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ +#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode + * @{ + */ +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ +#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value + with original alpha channel value */ +/** + * @} + */ + +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion + * @{ + */ +#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ +/** + * @} + */ + +/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap + * @{ + */ +#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ +#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ +/** + * @} + */ +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + + + +/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode + * @{ + */ +#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ +#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ +/** + * @} + */ + +/** @defgroup DMA2D_Interrupts DMA2D Interrupts + * @{ + */ +#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_Flags DMA2D Flags + * @{ + */ +#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +/** + * @} + */ + +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ +/** + * @} + */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DMA2D common Callback ID enumeration definition + */ +typedef enum +{ + HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ + HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ + HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ + HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ + HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ + HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ +}HAL_DMA2D_CallbackIDTypeDef; +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + +/** + * @} + */ +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros + * @{ + */ + +/** @brief Reset DMA2D handle state + * @param __HANDLE__ specifies the DMA2D handle. + * @retval None + */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + +/** + * @brief Enable the DMA2D. + * @param __HANDLE__ DMA2D handle + * @retval None. + */ +#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) + + +/* Interrupt & Flag management */ +/** + * @brief Get the DMA2D pending flags. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval The state of FLAG. + */ +#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA2D pending flags. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval None + */ +#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA2D interrupts. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA2D interrupts. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA2D interrupt source is enabled or not. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval The state of INTERRUPT source. + */ +#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark + * @{ + */ +#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ +/** + * @} + */ + +/** @defgroup DMA2D_Color_Value DMA2D Color Value + * @{ + */ +#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ +/** + * @} + */ + +/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers + * @{ + */ +#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ +/** + * @} + */ + +/** @defgroup DMA2D_Layers DMA2D Layers + * @{ + */ +#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ +#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ +/** + * @} + */ + +/** @defgroup DMA2D_Offset DMA2D Offset + * @{ + */ +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ +/** + * @} + */ + +/** @defgroup DMA2D_Size DMA2D Size + * @{ + */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ +/** + * @} + */ + +/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size + * @{ + */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Macros DMA2D Private Macros + * @{ + */ +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) + +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) + +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) + +#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) +#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) +#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) +#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) + +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4)) + +#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ + ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ + ((AlphaMode) == DMA2D_COMBINE_ALPHA)) + +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) +#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ + ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) + +#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ + ((RB_Swap) == DMA2D_RB_SWAP)) +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + + +#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) +#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) +#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) +#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) +#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_DMA2D_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h new file mode 100644 index 0000000..e657a89 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_EX_H +#define __STM32F7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMAEx_Channel_selection DMA Channel selection + * @brief DMAEx channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10) || \ + ((CHANNEL) == DMA_CHANNEL_11) || \ + ((CHANNEL) == DMA_CHANNEL_12) || \ + ((CHANNEL) == DMA_CHANNEL_13) || \ + ((CHANNEL) == DMA_CHANNEL_14) || \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h new file mode 100644 index 0000000..aa2dfde --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h @@ -0,0 +1,1337 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dsi.h + * @author MCD Application Team + * @brief Header file of DSI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_DSI_H +#define STM32F7xx_HAL_DSI_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DSI) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DSI DSI + * @brief DSI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** + * @brief DSI Init Structure definition + */ +typedef struct +{ + uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control + This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ + + uint32_t TXEscapeCkdiv; /*!< TX Escape clock division + The values 0 and 1 stop the TX_ESC clock generation */ + + uint32_t NumberOfLanes; /*!< Number of lanes + This parameter can be any value of @ref DSI_Number_Of_Lanes */ + +} DSI_InitTypeDef; + +/** + * @brief DSI PLL Clock structure definition + */ +typedef struct +{ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ + + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ + + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ + +} DSI_PLLInitTypeDef; + +/** + * @brief DSI Video mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using + 18-bit configuration). + This parameter can be any value of @ref DSI_LooselyPacked */ + + uint32_t Mode; /*!< Video mode type + This parameter can be any value of @ref DSI_Video_Mode_Type */ + + uint32_t PacketSize; /*!< Video packet size */ + + uint32_t NumberOfChunks; /*!< Number of chunks */ + + uint32_t NullPacketSize; /*!< Null packet size */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ + + uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ + + uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ + + uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ + + uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ + + uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ + + uint32_t VerticalActive; /*!< Vertical active duration */ + + uint32_t LPCommandEnable; /*!< Low-power command enable + This parameter can be any value of @ref DSI_LP_Command */ + + uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VSA, VBP and VFP regions */ + + uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that + can fit in a line during VACT region */ + + uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable + This parameter can be any value of @ref DSI_LP_HFP */ + + uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable + This parameter can be any value of @ref DSI_LP_HBP */ + + uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable + This parameter can be any value of @ref DSI_LP_VACT */ + + uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable + This parameter can be any value of @ref DSI_LP_VFP */ + + uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable + This parameter can be any value of @ref DSI_LP_VBP */ + + uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable + This parameter can be any value of @ref DSI_LP_VSYNC */ + + uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable + This parameter can be any value of @ref DSI_FBTA_acknowledge */ + +} DSI_VidCfgTypeDef; + +/** + * @brief DSI Adapted command mode configuration + */ +typedef struct +{ + uint32_t VirtualChannelID; /*!< Virtual channel ID */ + + uint32_t ColorCoding; /*!< Color coding for LTDC interface + This parameter can be any value of @ref DSI_Color_Coding */ + + uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in + pixels. This parameter can be any value between 0x00 and 0xFFFFU */ + + uint32_t TearingEffectSource; /*!< Tearing effect source + This parameter can be any value of @ref DSI_TearingEffectSource */ + + uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity + This parameter can be any value of @ref DSI_TearingEffectPolarity */ + + uint32_t HSPolarity; /*!< HSYNC pin polarity + This parameter can be any value of @ref DSI_HSYNC_Polarity */ + + uint32_t VSPolarity; /*!< VSYNC pin polarity + This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ + + uint32_t DEPolarity; /*!< Data Enable pin polarity + This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ + + uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted + This parameter can be any value of @ref DSI_Vsync_Polarity */ + + uint32_t AutomaticRefresh; /*!< Automatic refresh mode + This parameter can be any value of @ref DSI_AutomaticRefresh */ + + uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable + This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ + +} DSI_CmdCfgTypeDef; + +/** + * @brief DSI command transmission mode configuration + */ +typedef struct +{ + uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ + + uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ + + uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ + + uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ + + uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ + + uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission + This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ + + uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ + + uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ + + uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ + + uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission + This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ + + uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission + This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ + + uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission + This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ + + uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable + This parameter can be any value of @ref DSI_AcknowledgeRequest */ + +} DSI_LPCmdTypeDef; + +/** + * @brief DSI PHY Timings definition + */ +typedef struct +{ + uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed + to low-power transmission */ + + uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed + to low-power transmission */ + + uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power + to high-speed transmission */ + + uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ + + uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the + Stop state */ + +} DSI_PHY_TimerTypeDef; + +/** + * @brief DSI HOST Timeouts definition + */ +typedef struct +{ + uint32_t TimeoutCkdiv; /*!< Time-out clock division */ + + uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ + + uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ + + uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ + + uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ + + uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ + + uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode + This parameter can be any value of @ref DSI_HS_PrespMode */ + + uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ + + uint32_t BTATimeout; /*!< BTA time-out */ + +} DSI_HOST_TimeoutTypeDef; + +/** + * @brief DSI States Structure definition + */ +typedef enum +{ + HAL_DSI_STATE_RESET = 0x00U, + HAL_DSI_STATE_READY = 0x01U, + HAL_DSI_STATE_ERROR = 0x02U, + HAL_DSI_STATE_BUSY = 0x03U, + HAL_DSI_STATE_TIMEOUT = 0x04U +} HAL_DSI_StateTypeDef; + +/** + * @brief DSI Handle Structure definition + */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +typedef struct __DSI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +{ + DSI_TypeDef *Instance; /*!< Register base address */ + DSI_InitTypeDef Init; /*!< DSI required parameters */ + HAL_LockTypeDef Lock; /*!< DSI peripheral status */ + __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ + __IO uint32_t ErrorCode; /*!< DSI Error code */ + uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ + void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ + void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ + + void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ + void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +} DSI_HandleTypeDef; + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DSI Callback ID enumeration definition + */ +typedef enum +{ + HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ + HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ + + HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ + HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ + HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ + +} HAL_DSI_CallbackIDTypeDef; + +/** + * @brief HAL DSI Callback pointer definition + */ +typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ + +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_DCS_Command DSI DCS Command + * @{ + */ +#define DSI_ENTER_IDLE_MODE 0x39U +#define DSI_ENTER_INVERT_MODE 0x21U +#define DSI_ENTER_NORMAL_MODE 0x13U +#define DSI_ENTER_PARTIAL_MODE 0x12U +#define DSI_ENTER_SLEEP_MODE 0x10U +#define DSI_EXIT_IDLE_MODE 0x38U +#define DSI_EXIT_INVERT_MODE 0x20U +#define DSI_EXIT_SLEEP_MODE 0x11U +#define DSI_GET_3D_CONTROL 0x3FU +#define DSI_GET_ADDRESS_MODE 0x0BU +#define DSI_GET_BLUE_CHANNEL 0x08U +#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU +#define DSI_GET_DISPLAY_MODE 0x0DU +#define DSI_GET_GREEN_CHANNEL 0x07U +#define DSI_GET_PIXEL_FORMAT 0x0CU +#define DSI_GET_POWER_MODE 0x0AU +#define DSI_GET_RED_CHANNEL 0x06U +#define DSI_GET_SCANLINE 0x45U +#define DSI_GET_SIGNAL_MODE 0x0EU +#define DSI_NOP 0x00U +#define DSI_READ_DDB_CONTINUE 0xA8U +#define DSI_READ_DDB_START 0xA1U +#define DSI_READ_MEMORY_CONTINUE 0x3EU +#define DSI_READ_MEMORY_START 0x2EU +#define DSI_SET_3D_CONTROL 0x3DU +#define DSI_SET_ADDRESS_MODE 0x36U +#define DSI_SET_COLUMN_ADDRESS 0x2AU +#define DSI_SET_DISPLAY_OFF 0x28U +#define DSI_SET_DISPLAY_ON 0x29U +#define DSI_SET_GAMMA_CURVE 0x26U +#define DSI_SET_PAGE_ADDRESS 0x2BU +#define DSI_SET_PARTIAL_COLUMNS 0x31U +#define DSI_SET_PARTIAL_ROWS 0x30U +#define DSI_SET_PIXEL_FORMAT 0x3AU +#define DSI_SET_SCROLL_AREA 0x33U +#define DSI_SET_SCROLL_START 0x37U +#define DSI_SET_TEAR_OFF 0x34U +#define DSI_SET_TEAR_ON 0x35U +#define DSI_SET_TEAR_SCANLINE 0x44U +#define DSI_SET_VSYNC_TIMING 0x40U +#define DSI_SOFT_RESET 0x01U +#define DSI_WRITE_LUT 0x2DU +#define DSI_WRITE_MEMORY_CONTINUE 0x3CU +#define DSI_WRITE_MEMORY_START 0x2CU +/** + * @} + */ + +/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type + * @{ + */ +#define DSI_VID_MODE_NB_PULSES 0U +#define DSI_VID_MODE_NB_EVENTS 1U +#define DSI_VID_MODE_BURST 2U +/** + * @} + */ + +/** @defgroup DSI_Color_Mode DSI Color Mode + * @{ + */ +#define DSI_COLOR_MODE_FULL 0x00000000U +#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM +/** + * @} + */ + +/** @defgroup DSI_ShutDown DSI ShutDown + * @{ + */ +#define DSI_DISPLAY_ON 0x00000000U +#define DSI_DISPLAY_OFF DSI_WCR_SHTDN +/** + * @} + */ + +/** @defgroup DSI_LP_Command DSI LP Command + * @{ + */ +#define DSI_LP_COMMAND_DISABLE 0x00000000U +#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE +/** + * @} + */ + +/** @defgroup DSI_LP_HFP DSI LP HFP + * @{ + */ +#define DSI_LP_HFP_DISABLE 0x00000000U +#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE +/** + * @} + */ + +/** @defgroup DSI_LP_HBP DSI LP HBP + * @{ + */ +#define DSI_LP_HBP_DISABLE 0x00000000U +#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VACT DSI LP VACT + * @{ + */ +#define DSI_LP_VACT_DISABLE 0x00000000U +#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE +/** + * @} + */ + +/** @defgroup DSI_LP_VFP DSI LP VFP + * @{ + */ +#define DSI_LP_VFP_DISABLE 0x00000000U +#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE +/** + * @} + */ + +/** @defgroup DSI_LP_VBP DSI LP VBP + * @{ + */ +#define DSI_LP_VBP_DISABLE 0x00000000U +#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE +/** + * @} + */ + +/** @defgroup DSI_LP_VSYNC DSI LP VSYNC + * @{ + */ +#define DSI_LP_VSYNC_DISABLE 0x00000000U +#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE +/** + * @} + */ + +/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge + * @{ + */ +#define DSI_FBTAA_DISABLE 0x00000000U +#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE +/** + * @} + */ + +/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source + * @{ + */ +#define DSI_TE_DSILINK 0x00000000U +#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC +/** + * @} + */ + +/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity + * @{ + */ +#define DSI_TE_RISING_EDGE 0x00000000U +#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL +/** + * @} + */ + +/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity + * @{ + */ +#define DSI_VSYNC_FALLING 0x00000000U +#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL +/** + * @} + */ + +/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh + * @{ + */ +#define DSI_AR_DISABLE 0x00000000U +#define DSI_AR_ENABLE DSI_WCFGR_AR +/** + * @} + */ + +/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request + * @{ + */ +#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE +/** + * @} + */ + +/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request + * @{ + */ +#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U +#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP + * @{ + */ +#define DSI_LP_GSW0P_DISABLE 0x00000000U +#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP + * @{ + */ +#define DSI_LP_GSW1P_DISABLE 0x00000000U +#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP + * @{ + */ +#define DSI_LP_GSW2P_DISABLE 0x00000000U +#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP + * @{ + */ +#define DSI_LP_GSR0P_DISABLE 0x00000000U +#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP + * @{ + */ +#define DSI_LP_GSR1P_DISABLE 0x00000000U +#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP + * @{ + */ +#define DSI_LP_GSR2P_DISABLE 0x00000000U +#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite + * @{ + */ +#define DSI_LP_GLW_DISABLE 0x00000000U +#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP + * @{ + */ +#define DSI_LP_DSW0P_DISABLE 0x00000000U +#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP + * @{ + */ +#define DSI_LP_DSW1P_DISABLE 0x00000000U +#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP + * @{ + */ +#define DSI_LP_DSR0P_DISABLE 0x00000000U +#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX +/** + * @} + */ + +/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write + * @{ + */ +#define DSI_LP_DLW_DISABLE 0x00000000U +#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX +/** + * @} + */ + +/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet + * @{ + */ +#define DSI_LP_MRDP_DISABLE 0x00000000U +#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS +/** + * @} + */ + +/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode + * @{ + */ +#define DSI_HS_PM_DISABLE 0x00000000U +#define DSI_HS_PM_ENABLE DSI_TCCR3_PM +/** + * @} + */ + + +/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control + * @{ + */ +#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U +#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR +/** + * @} + */ + +/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes + * @{ + */ +#define DSI_ONE_DATA_LANE 0U +#define DSI_TWO_DATA_LANES 1U +/** + * @} + */ + +/** @defgroup DSI_FlowControl DSI Flow Control + * @{ + */ +#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE +#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE +#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE +#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE +#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ + DSI_FLOW_CONTROL_EOTP_TX) +/** + * @} + */ + +/** @defgroup DSI_Color_Coding DSI Color Coding + * @{ + */ +#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ +#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ +#define DSI_RGB888 0x00000005U +/** + * @} + */ + +/** @defgroup DSI_LooselyPacked DSI Loosely Packed + * @{ + */ +#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE +#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity + * @{ + */ +#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP +/** + * @} + */ + +/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity + * @{ + */ +#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U +#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP +/** + * @} + */ + +/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity + * @{ + */ +#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U +#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP +/** + * @} + */ + +/** @defgroup DSI_PLL_IDF DSI PLL IDF + * @{ + */ +#define DSI_PLL_IN_DIV1 0x00000001U +#define DSI_PLL_IN_DIV2 0x00000002U +#define DSI_PLL_IN_DIV3 0x00000003U +#define DSI_PLL_IN_DIV4 0x00000004U +#define DSI_PLL_IN_DIV5 0x00000005U +#define DSI_PLL_IN_DIV6 0x00000006U +#define DSI_PLL_IN_DIV7 0x00000007U +/** + * @} + */ + +/** @defgroup DSI_PLL_ODF DSI PLL ODF + * @{ + */ +#define DSI_PLL_OUT_DIV1 0x00000000U +#define DSI_PLL_OUT_DIV2 0x00000001U +#define DSI_PLL_OUT_DIV4 0x00000002U +#define DSI_PLL_OUT_DIV8 0x00000003U +/** + * @} + */ + +/** @defgroup DSI_Flags DSI Flags + * @{ + */ +#define DSI_FLAG_TE DSI_WISR_TEIF +#define DSI_FLAG_ER DSI_WISR_ERIF +#define DSI_FLAG_BUSY DSI_WISR_BUSY +#define DSI_FLAG_PLLLS DSI_WISR_PLLLS +#define DSI_FLAG_PLLL DSI_WISR_PLLLIF +#define DSI_FLAG_PLLU DSI_WISR_PLLUIF +#define DSI_FLAG_RRS DSI_WISR_RRS +#define DSI_FLAG_RR DSI_WISR_RRIF +/** + * @} + */ + +/** @defgroup DSI_Interrupts DSI Interrupts + * @{ + */ +#define DSI_IT_TE DSI_WIER_TEIE +#define DSI_IT_ER DSI_WIER_ERIE +#define DSI_IT_PLLL DSI_WIER_PLLLIE +#define DSI_IT_PLLU DSI_WIER_PLLUIE +#define DSI_IT_RR DSI_WIER_RRIE +/** + * @} + */ + +/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ +#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ +#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ +#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type + * @{ + */ +#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ +#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ +/** + * @} + */ + +/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type + * @{ + */ +#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ +#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ +#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ +#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ +/** + * @} + */ + +/** @defgroup DSI_Error_Data_Type DSI Error Data Type + * @{ + */ +#define HAL_DSI_ERROR_NONE 0U +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Lane_Group DSI Lane Group + * @{ + */ +#define DSI_CLOCK_LANE 0x00000000U +#define DSI_DATA_LANES 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Communication_Delay DSI Communication Delay + * @{ + */ +#define DSI_SLEW_RATE_HSTX 0x00000000U +#define DSI_SLEW_RATE_LPTX 0x00000001U +#define DSI_HS_DELAY 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_CustomLane DSI CustomLane + * @{ + */ +#define DSI_SWAP_LANE_PINS 0x00000000U +#define DSI_INVERT_HS_SIGNAL 0x00000001U +/** + * @} + */ + +/** @defgroup DSI_Lane_Select DSI Lane Select + * @{ + */ +#define DSI_CLK_LANE 0x00000000U +#define DSI_DATA_LANE0 0x00000001U +#define DSI_DATA_LANE1 0x00000002U +/** + * @} + */ + +/** @defgroup DSI_PHY_Timing DSI PHY Timing + * @{ + */ +#define DSI_TCLK_POST 0x00000000U +#define DSI_TLPX_CLK 0x00000001U +#define DSI_THS_EXIT 0x00000002U +#define DSI_TLPX_DATA 0x00000003U +#define DSI_THS_ZERO 0x00000004U +#define DSI_THS_TRAIL 0x00000005U +#define DSI_THS_PREPARE 0x00000006U +#define DSI_TCLK_ZERO 0x00000007U +#define DSI_TCLK_PREPARE 0x00000008U +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** + * @brief Reset DSI handle state. + * @param __HANDLE__: DSI handle + * @retval None + */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) +#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ + +/** + * @brief Enables the DSI host. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disables the DSI host. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Enables the DSI wrapper. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disable the DSI wrapper. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Enables the DSI PLL. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disables the DSI PLL. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Enables the DSI regulator. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Disables the DSI regulator. + * @param __HANDLE__ DSI handle + * @retval None. + */ +#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ + } while(0U) + +/** + * @brief Get the DSI pending flags. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_BUSY : Busy Flag + * @arg DSI_FLAG_PLLLS: PLL Lock Status + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RRS : Regulator Ready Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) + +/** + * @brief Clears the DSI pending flags. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag + * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag + * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag + * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag + * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag + * @retval None + */ +#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) + +/** + * @brief Enables the specified DSI interrupts. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified DSI interrupts. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval None + */ +#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DSI interrupt source is enabled or not. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. + * This parameter can be one of the following values: + * @arg DSI_IT_TE : Tearing Effect Interrupt + * @arg DSI_IT_ER : End of Refresh Interrupt + * @arg DSI_IT_PLLL: PLL Lock Interrupt + * @arg DSI_IT_PLLU: PLL Unlock Interrupt + * @arg DSI_IT_RR : Regulator Ready Interrupt + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Functions DSI Exported Functions + * @{ + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); +void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); + +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t *ParametersTable); +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t *Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t *ParametersTable); +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); + +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, + uint32_t Value); +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, + uint32_t Value); +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); + +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DSI_Private_Types DSI Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DSI_Private_Defines DSI Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Variables DSI Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Constants DSI Private Constants + * @{ + */ +#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DSI_Private_Macros DSI Private Macros + * @{ + */ +#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) +#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ + ((IDF) == DSI_PLL_IN_DIV2) || \ + ((IDF) == DSI_PLL_IN_DIV3) || \ + ((IDF) == DSI_PLL_IN_DIV4) || \ + ((IDF) == DSI_PLL_IN_DIV5) || \ + ((IDF) == DSI_PLL_IN_DIV6) || \ + ((IDF) == DSI_PLL_IN_DIV7)) +#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ + ((ODF) == DSI_PLL_OUT_DIV2) || \ + ((ODF) == DSI_PLL_OUT_DIV4) || \ + ((ODF) == DSI_PLL_OUT_DIV8)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) +#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ + ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ + ((VideoModeType) == DSI_VID_MODE_BURST)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) +#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) +#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) +#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ + ((MODE) == DSI_GEN_LONG_PKT_WRITE)) +#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ + ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ + ((Timing) == DSI_TLPX_CLK ) || \ + ((Timing) == DSI_THS_EXIT ) || \ + ((Timing) == DSI_TLPX_DATA ) || \ + ((Timing) == DSI_THS_ZERO ) || \ + ((Timing) == DSI_THS_TRAIL ) || \ + ((Timing) == DSI_THS_PREPARE ) || \ + ((Timing) == DSI_TCLK_ZERO ) || \ + ((Timing) == DSI_TCLK_PREPARE)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_DSI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h new file mode 100644 index 0000000..c9f137c --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_EXTI_H +#define STM32F7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#if defined(ETH) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* ETH */ +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ +#if defined(EXTI_IMR_IM24) +#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ +#endif /* EXTI_IMR_IM24 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000006u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOI 0x00000008u +#define EXTI_GPIOJ 0x00000009u +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM24) +#define EXTI_LINE_NB 25u +#else +#define EXTI_LINE_NB 24u +#endif /* EXTI_IMR_IM24 */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ + ((__LINE__) == EXTI_TRIGGER_RISING) || \ + ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOK) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ)) +#endif /* GPIOK */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h new file mode 100644 index 0000000..66a901e --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_H +#define __STM32F7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /* Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + +#if defined (FLASH_OPTCR2_PCROP) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) +#else +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) +#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 2) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#elif (FLASH_SECTOR_TOTAL == 4) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#else +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#endif /* FLASH_SECTOR_TOTAL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH Adaptive Real-Time memory accelerator. + * @note The ART accelerator is available only for flash access on ITCM interface. + * @retval none + */ +#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Disable the FLASH Adaptive Real-Time memory accelerator. + * @retval none + */ +#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Resets the FLASH Adaptive Real-Time memory accelerator. + * @note This function must be used only when the Adaptive Real-Time memory accelerator + * is disabled. + * @retval None + */ +#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h new file mode 100644 index 0000000..d417503 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -0,0 +1,700 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_EX_H +#define __STM32F7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + +#if defined (FLASH_OPTCR_nDBANK) + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ +#endif /* FLASH_OPTCR_nDBANK */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. + nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ + + uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + + uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + +#if defined (FLASH_OPTCR2_PCROP) + uint32_t PCROPSector; /*!< Set the PCROP sector. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ + + uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ +#endif /* FLASH_OPTCR2_PCROP */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ +#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ +#if defined (FLASH_OPTCR2_PCROP) +#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ +#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog + * @{ + */ +#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ +#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBOOT) +/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT + * @{ + */ +#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash + (Dual bank Boot mode), or RAM if Boot address option in RAM */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank + * @{ + */ +#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ +#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#if (SRAM2_BASE == 0x2003C000U) +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ +#else +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ +#endif /* SRAM2_BASE == 0x2003C000U */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ +#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ +#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit + * @{ + */ +#if defined (FLASH_OPTCR_nDBANK) +#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ +#else +#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ +#endif /* FLASH_OPTCR_nDBANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ +/** + * @} + */ + +#if (FLASH_SECTOR_TOTAL == 24) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. + * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). + * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. + * @{ + */ +/* Single Bank Sectors */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ +#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ +#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ +#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ + +/* Dual Bank Sectors */ +#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ +#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ +#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ +#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ +#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ +#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ +#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ +#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ +#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ +#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ +#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ +#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ +#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ +#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ +#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ +#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ +#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ +#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ +#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ +#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ +#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ +#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ +#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR2_PCROP) +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ +#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ +#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ +#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit + * @{ + */ +#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ +#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ +/** + * @} + */ +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Adress + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) + +#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ + OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) +#else +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) +#endif /* FLASH_OPTCR2_PCROP */ + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if (FLASH_SECTOR_TOTAL == 8) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 24) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ + ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ + ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ + ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ + ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ + ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ + ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ + ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ + ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 4) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR_nDBANK) +#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ + ((VALUE) == OB_NDBANK_DUAL_BANK)) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR_nDBOOT) +#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ + ((VALUE) == OB_DUAL_BOOT_ENABLE)) +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) +#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ + ((VALUE) == OB_PCROP_RDP_ENABLE)) +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h new file mode 100644 index 0000000..08e0acb --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_H +#define __STM32F7xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ +/** + * @} + */ + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h new file mode 100644 index 0000000..cd1413c --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -0,0 +1,658 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_EX_H +#define __STM32F7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ +/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ +#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) + /** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/** + * @} + */ + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F745xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#elif defined(STM32F767xx) || defined(STM32F777xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F769xx) || defined(STM32F779xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) +#elif defined(STM32F765xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \ + ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h new file mode 100644 index 0000000..f09e057 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h @@ -0,0 +1,782 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_H +#define STM32F7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization + section in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h new file mode 100644 index 0000000..8303789 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_EX_H +#define STM32F7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#else +#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */ +#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C_PB8_FMP) +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#else +#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ +#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C1_FMP) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C2_FMP) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif +#if defined(SYSCFG_PMC_I2C4_FMP) +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#else +#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +#endif + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#if (defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) +#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(SYSCFG_PMC_I2C1_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) +#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ + + + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h new file mode 100644 index 0000000..da2f091 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h @@ -0,0 +1,689 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_LTDC_H +#define STM32F7xx_HAL_LTDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (LTDC) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +} HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +typedef struct __LTDC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + +} LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +} HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32f7xx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_LTDC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h new file mode 100644 index 0000000..515b220 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h @@ -0,0 +1,85 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_LTDC_EX_H +#define STM32F7xx_HAL_LTDC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (LTDC) && defined (DSI) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" +#include "stm32f7xx_hal_dsi.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_LTDC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h new file mode 100644 index 0000000..e9ca922 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h @@ -0,0 +1,404 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_H +#define __STM32F7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR1_WUIF +#define PWR_FLAG_SB PWR_CSR1_SBF +#define PWR_FLAG_PVDO PWR_CSR1_PVDO +#define PWR_FLAG_BRR PWR_CSR1_BRR +#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)). + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h new file mode 100644 index 0000000..e35d3bb --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_EX_H +#define __STM32F7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) +#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) +#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) +#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) +#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) +#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) + +/** + * @} + */ + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags + * @{ + */ +#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 +#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 +#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 +#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 +#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 +#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ +/** @brief Macros to enable or disable the Over drive mode. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) +#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) + +/** @brief Macros to enable or disable the Over drive switching. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) + +/** @brief Check Wake Up flag is set or not. + * @param __WUFLAG__ specifies the Wake Up flag to check. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) + +/** @brief Clear the WakeUp pins flags. + * @param __WUFLAG__ specifies the Wake Up pin flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); + +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); + +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \ + ((__PIN__) == PWR_WAKEUP_PIN2) || \ + ((__PIN__) == PWR_WAKEUP_PIN3) || \ + ((__PIN__) == PWR_WAKEUP_PIN4) || \ + ((__PIN__) == PWR_WAKEUP_PIN5) || \ + ((__PIN__) == PWR_WAKEUP_PIN6) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h new file mode 100644 index 0000000..dfeb31b --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h @@ -0,0 +1,1310 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_H +#define __STM32F7xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f7xx_hal_rcc_ex.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config RCC HSE Config + * @{ + */ +#define RCC_HSE_OFF ((uint32_t)0x00000000U) +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config RCC LSE Config + * @{ + */ +#define RCC_LSE_OFF ((uint32_t)0x00000000U) +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config RCC HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint32_t)0x00000000U) +#define RCC_HSI_ON RCC_CR_HSION + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config RCC LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint32_t)0x00000000U) +#define RCC_LSI_ON RCC_CSR_LSION +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint32_t)0x00000000U) +#define RCC_PLL_OFF ((uint32_t)0x00000001U) +#define RCC_PLL_ON ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type RCC System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source RCC System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +/** + * @} + */ + + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) +/** + * @} + */ + + + +/** @defgroup RCC_MCO_Index RCC MCO Index + * @{ + */ +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 ((uint32_t)0x00000000U) +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt RCC Interrupt + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01U) +#define RCC_IT_LSERDY ((uint8_t)0x02U) +#define RCC_IT_HSIRDY ((uint8_t)0x04U) +#define RCC_IT_HSERDY ((uint8_t)0x08U) +#define RCC_IT_PLLRDY ((uint8_t)0x10U) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) +#define RCC_IT_CSS ((uint8_t)0x80U) +/** + * @} + */ + +/** @defgroup RCC_Flag RCC Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41U) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) +#define RCC_FLAG_BORRST ((uint8_t)0x79U) +#define RCC_FLAG_PINRST ((uint8_t)0x7AU) +#define RCC_FLAG_PORRST ((uint8_t)0x7BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations + * @{ + */ +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief EGet the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) +#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) +#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) +#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ + } while (0) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) +#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration + * @{ + */ + +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ + RCC->CFGR |= (__SOURCE__); \ + }while(0) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) +#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ + (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ + /** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ +#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ + +/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias + * @brief RCC registers bit address alias + * @{ + */ +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) + +#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ + ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) + + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) + + +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((DRIVE) == RCC_LSEDRIVE_HIGH)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h new file mode 100644 index 0000000..f92f9d6 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -0,0 +1,3524 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_EX_H +#define __STM32F7xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider + This parameter will be used only when PLLSAI is disabled */ +}RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t Usart6ClockSelection; /*!< USART6 clock source + This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ + + uint32_t Uart7ClockSelection; /*!< UART7 clock source + This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ + + uint32_t Uart8ClockSelection; /*!< UART8 clock source + This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t I2c4ClockSelection; /*!< I2C4 clock source + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t CecClockSelection; /*!< CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source + This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +}RCC_PeriphCLKInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider + * @{ + */ +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider + * @{ + */ +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR + * @{ + */ +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 +#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 +#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC + +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) +#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 +#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 +#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 +#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 +#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source + * @{ + */ +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 +#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 +#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source + * @{ + */ +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 +#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 +#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source + * @{ + */ +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 +#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 +#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 + +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL + +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source + * @{ + */ +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) +#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL +/** + * @} + */ + +/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) +#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +/** + * @} + */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + UNUSED(tmpreg); \ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + } while(0) + +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases AHB/APB peripheral reset. + * @{ + */ + +/** @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) + +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) + +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB2 peripheral reset. + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB3 peripheral reset + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) + +/** @brief Force or release APB1 peripheral reset. + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable + * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) + +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) + +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) + +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__ specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*---------------------------------------------------------------------------------------------*/ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ + RCC->DCKCFGR1 |= (__PRESC__); \ + }while(0) + +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) +#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#else +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Macro to configure SAI1 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) + + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) + + +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source + */ +#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) + +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) + + /** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) + + /** @brief Macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) + + /** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) + + /** @brief Macro to configure the UART7 clock (UART7CLK). + * + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) + +/** @brief Macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) + +/** @brief Macro to configure the CEC clock (CECCLK). + * + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) + +/** @brief Macro to configure the CLK48 source (CLK48CLK). + * + * @param __CLK48_SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source + */ +#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) + +/** @brief macro to get the CLK48 source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source + */ +#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) + +/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). + * + * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock + */ +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + +/** @brief macro to get the SDMMC1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock + */ +#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32F745xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) + +#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#define IS_RCC_USART1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) +#define IS_RCC_USART3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) +#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) +#define IS_RCC_LPTIM1CLK(SOURCE) \ + (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) +#define IS_RCC_CLK48SOURCE(SOURCE) \ + (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ + ((SOURCE) == RCC_CLK48SOURCE_PLL)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ + defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h new file mode 100644 index 0000000..1157def --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h @@ -0,0 +1,857 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RTC_H +#define __STM32F7xx_HAL_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +}HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ +}RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. + This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + + uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit + in CR register to store the operation. + This parameter can be a value of @ref RTC_StoreOperation_Definitions */ +}RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ + +}RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm . + This parameter can be a value of @ref RTC_Alarms_Definitions */ +}RTC_AlarmTypeDef; + +/** + * @brief RTC Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Register base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ + + void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ + + void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ + + void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ + + void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ + + void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ + + void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */ + + void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ + + void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +}RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ +}HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 0x00000000U +#define RTC_HOURFORMAT_12 0x00000040U +/** + * @} + */ + + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U +#define RTC_OUTPUT_POLARITY_LOW 0x00100000U +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE /* 0x00000008 */ +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U) +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U +#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_NONE 0x00000000U +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET 0x00000000U +#define RTC_STOREOPERATION_SET 0x00040000U +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions + * @{ + */ +#define RTC_FORMAT_BIN 0x00000000U +#define RTC_FORMAT_BCD 0x00000001U +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE 0x00000000U +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL 0x80808080U +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match + to activate alarm. */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS RTC_CR_TSIE +#define RTC_IT_WUT RTC_CR_WUTIE +#define RTC_IT_ALRA RTC_CR_ALRAIE +#define RTC_IT_ALRB RTC_CR_ALRBIE +#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /* Used only to Enable the Tamper Interrupt */ +#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE +#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE +#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_ITSF RTC_ISR_ITSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0u) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) & 0x0000FFFFU) != RESET)? SET : RESET) + +/** + * @brief Get the selected RTC Alarm's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to check. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRBF + * @arg RTC_FLAG_ALRAWF + * @arg RTC_FLAG_ALRBWF + * @retval None + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) + +/** + * @brief Clear the RTC Alarm's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_FLAG_ALRAF + * @arg RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Clear the RTC Alarm associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) +/** + * @} + */ + +/* Include RTC HAL Extension module */ +#include "stm32f7xx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @{ + */ +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK 0x007F7F7FU +#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK 0xFFFFFF5FU + +#define RTC_TIMEOUT_VALUE 1000U + +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \ + ((__FORMAT__) == RTC_HOURFORMAT_24)) +#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((__POL__) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL)) +#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FU) +#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= 0x7FFFU) +#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) +#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || ((__PM__) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE)) +#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \ + ((__OPERATION__) == RTC_STOREOPERATION_SET)) +#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD)) +#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) +#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) +#define IS_RTC_DATE(__DATE__) (((__DATE__) >= 1U) && ((__DATE__) <= 31U)) +#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >0U) && ((__DATE__) <= 31U)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) +#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & 0x7F7F7F7FU) == (uint32_t)RESET) +#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B)) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= 0x00007FFFU) +#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h new file mode 100644 index 0000000..cbadbc4 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h @@ -0,0 +1,1017 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RTC_EX_H +#define __STM32F7xx_HAL_RTC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** + * @brief RTC Tamper structure definition + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + + uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. + This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ + + uint32_t Filter; /*!< Specifies the RTC Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ +}RTC_TamperTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output selection Definitions + * @{ + */ +#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000U) +#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000U) +#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000U) +#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000U) +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions + * @{ + */ +#define RTC_BKP_DR0 ((uint32_t)0x00000000U) +#define RTC_BKP_DR1 ((uint32_t)0x00000001U) +#define RTC_BKP_DR2 ((uint32_t)0x00000002U) +#define RTC_BKP_DR3 ((uint32_t)0x00000003U) +#define RTC_BKP_DR4 ((uint32_t)0x00000004U) +#define RTC_BKP_DR5 ((uint32_t)0x00000005U) +#define RTC_BKP_DR6 ((uint32_t)0x00000006U) +#define RTC_BKP_DR7 ((uint32_t)0x00000007U) +#define RTC_BKP_DR8 ((uint32_t)0x00000008U) +#define RTC_BKP_DR9 ((uint32_t)0x00000009U) +#define RTC_BKP_DR10 ((uint32_t)0x0000000AU) +#define RTC_BKP_DR11 ((uint32_t)0x0000000BU) +#define RTC_BKP_DR12 ((uint32_t)0x0000000CU) +#define RTC_BKP_DR13 ((uint32_t)0x0000000DU) +#define RTC_BKP_DR14 ((uint32_t)0x0000000EU) +#define RTC_BKP_DR15 ((uint32_t)0x0000000FU) +#define RTC_BKP_DR16 ((uint32_t)0x00000010U) +#define RTC_BKP_DR17 ((uint32_t)0x00000011U) +#define RTC_BKP_DR18 ((uint32_t)0x00000012U) +#define RTC_BKP_DR19 ((uint32_t)0x00000013U) +#define RTC_BKP_DR20 ((uint32_t)0x00000014U) +#define RTC_BKP_DR21 ((uint32_t)0x00000015U) +#define RTC_BKP_DR22 ((uint32_t)0x00000016U) +#define RTC_BKP_DR23 ((uint32_t)0x00000017U) +#define RTC_BKP_DR24 ((uint32_t)0x00000018U) +#define RTC_BKP_DR25 ((uint32_t)0x00000019U) +#define RTC_BKP_DR26 ((uint32_t)0x0000001AU) +#define RTC_BKP_DR27 ((uint32_t)0x0000001BU) +#define RTC_BKP_DR28 ((uint32_t)0x0000001CU) +#define RTC_BKP_DR29 ((uint32_t)0x0000001DU) +#define RTC_BKP_DR30 ((uint32_t)0x0000001EU) +#define RTC_BKP_DR31 ((uint32_t)0x0000001FU) +/** + * @} + */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definitions + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E +#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E +#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions + * @{ + */ +#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE +#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE +#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE +#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE +/** + * @} + */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000U) +#define RTC_TIMESTAMPPIN_POS1 ((uint32_t)0x00000002U) +#define RTC_TIMESTAMPPIN_POS2 ((uint32_t)0x00000004U) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definitions + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000U) +#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002U) +#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE +#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE +/** + * @} + */ + + /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions +* @{ +*/ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000U) +#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000U) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions + * @{ + */ +#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000U) +#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000U) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */ + +#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800U) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000U) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800U) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700U) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000U) /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000U) /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000U) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStampOnTamperDetection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003U) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004U) +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibration + period is 8s, else 2exp18 RTCCLK seconds */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000U) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000U) +#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000U) +/** + * @} + */ + + /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000U) +#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Get the selected RTC WakeUpTimer's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTWF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Enable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) + +/** + * @brief Disable the RTC Tamper1 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) + +/** + * @brief Enable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) + +/** + * @brief Disable the RTC Tamper2 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) + +/** + * @brief Enable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) + +/** + * @brief Disable the RTC Tamper3 input detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) + +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ + ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP: All tampers interrupts + * @arg RTC_IT_TAMP1: Tamper1 interrupt + * @arg RTC_IT_TAMP2: Tamper2 interrupt + * @arg RTC_IT_TAMP3: Tamper3 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Get the selected RTC Tamper's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag sources to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP1F: Tamper1 flag + * @arg RTC_FLAG_TAMP2F: Tamper2 flag + * @arg RTC_FLAG_TAMP3F: Tamper3 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to check. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TS: TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) + +/** + * @brief Get the selected RTC TimeStamp's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Clear the RTC Time Stamp's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg RTC_FLAG_TSF + * @arg RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Enable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) + +/** + * @brief Disable the RTC internal TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) + +/** + * @brief Get the selected RTC Internal Time Stamp's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Clear the RTC Internal Time Stamp's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. + * This parameter can be: + * @arg RTC_FLAG_ITSF + * @retval None + */ +#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Get the selected RTC shift operation's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_SHPF + * @retval None + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) + +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC WakeUp Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @{ + */ + +/* RTC TimeStamp and Tamper functions *****************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); + +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @{ + */ +/* RTC Wake-up functions ******************************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @{ + */ +/* Extension Control functions ************************************************/ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @{ + */ +/* Extension RTC features functions *******************************************/ +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) +#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#define IS_RTC_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \ + ((__OUTPUT__) == RTC_OUTPUT_ALARMA) || \ + ((__OUTPUT__) == RTC_OUTPUT_ALARMB) || \ + ((__OUTPUT__) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_BKP(__BKP__) ((__BKP__) < (uint32_t) RTC_BKP_NUMBER) +#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \ + ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXE))) == 0x00U) && ((__TAMPER__) != (uint32_t)RESET)) + +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)(0xFFFFFFFFU ^ RTC_TAMPCR_TAMPXIE)) == 0x00U) && ((__INTERRUPT__) != (uint32_t)RESET)) + +#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \ + ((__PIN__) == RTC_TIMESTAMPPIN_POS1) || \ + ((__PIN__) == RTC_TIMESTAMPPIN_POS2)) +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) +#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFFF) +#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC)) +#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) +#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x000001FF) +#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \ + ((__SEL__) == RTC_SHIFTADD1S_SET)) +#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= 0x00007FFF) +#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \ + ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RTC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h new file mode 100644 index 0000000..dff8833 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_sdram.h + * @author MCD Application Team + * @brief Header file of SDRAM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_SDRAM_H +#define __STM32F7xx_HAL_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_fmc.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Types SDRAM Exported Types + * @{ + */ + +/** + * @brief HAL SDRAM State structure definition + */ +typedef enum +{ + HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ + HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ + HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ + HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ + HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ + HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ + +}HAL_SDRAM_StateTypeDef; + +/** + * @brief SDRAM handle Structure definition + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +typedef struct __SDRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +{ + FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ + + __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ + + HAL_LockTypeDef Lock; /*!< SDRAM locking object */ + + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */ +#endif +} SDRAM_HandleTypeDef; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SDRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ + HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ + HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ + HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ + HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ +}HAL_SDRAM_CallbackIDTypeDef; + +/** + * @brief HAL SDRAM Callback pointer definition + */ +typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); +typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros + * @{ + */ + +/** @brief Reset SDRAM handle state + * @param __HANDLE__ specifies the SDRAM handle. + * @retval None + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @addtogroup SDRAM_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); + +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/* SDRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback); +#endif + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group3 + * @{ + */ +/* SDRAM Control functions *****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group4 + * @{ + */ +/* SDRAM State functions ********************************************************/ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_SDRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h new file mode 100644 index 0000000..a1d7c50 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h @@ -0,0 +1,846 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_SPI_H +#define STM32F7xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + CPOL setting is ignored).. */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000300U) +#define SPI_DATASIZE_5BIT (0x00000400U) +#define SPI_DATASIZE_6BIT (0x00000500U) +#define SPI_DATASIZE_7BIT (0x00000600U) +#define SPI_DATASIZE_8BIT (0x00000700U) +#define SPI_DATASIZE_9BIT (0x00000800U) +#define SPI_DATASIZE_10BIT (0x00000900U) +#define SPI_DATASIZE_11BIT (0x00000A00U) +#define SPI_DATASIZE_12BIT (0x00000B00U) +#define SPI_DATASIZE_13BIT (0x00000C00U) +#define SPI_DATASIZE_14BIT (0x00000D00U) +#define SPI_DATASIZE_15BIT (0x00000E00U) +#define SPI_DATASIZE_16BIT (0x00000F00U) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + * This parameter can be one of the following values: + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_8BIT : CRC 8bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) +#define SPI_CRC_LENGTH_8BIT (0x00000001U) +#define SPI_CRC_LENGTH_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold + * @{ + * This parameter can be one of the following values: + * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : + * RXNE event is generated if the FIFO + * level is greater or equal to 1/4(8-bits). + * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16 bits). */ +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +/** + * @} + */ + +/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level + * @{ + */ +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + }while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR regsiter. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 regsiter. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Include SPI HAL Extended module */ +#include "stm32f7xx_hal_spi_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h new file mode 100644 index 0000000..c5675d7 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_SPI_EX_H +#define STM32F7xx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_SPI_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h new file mode 100644 index 0000000..ab067a5 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h @@ -0,0 +1,2272 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_H +#define STM32F7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6)) +#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h new file mode 100644 index 0000000..b8d3472 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h @@ -0,0 +1,361 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_EX_H +#define STM32F7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} +TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM2_TIM8_TRGO (0x00000000U) +#define TIM_TIM2_ETH_PTP (0x00000400U) +#define TIM_TIM2_USBFS_SOF (0x00000800U) +#define TIM_TIM2_USBHS_SOF (0x00000C00U) +#define TIM_TIM5_GPIO (0x00000000U) +#define TIM_TIM5_LSI (0x00000040U) +#define TIM_TIM5_LSE (0x00000080U) +#define TIM_TIM5_RTC (0x000000C0U) +#define TIM_TIM11_GPIO (0x00000000U) +#define TIM_TIM11_SPDIFRX (0x00000001U) +#define TIM_TIM11_HSE (0x00000002U) +#define TIM_TIM11_MCO1 (0x00000003U) +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\ + ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\ + ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\ + ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\ + ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\ + ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\ + ((__TIM_REMAP__) == TIM_TIM11_MCO1)) +#if defined(TIM_BREAK_INPUT_SUPPORT) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h new file mode 100644 index 0000000..473ff95 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h @@ -0,0 +1,1532 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_H +#define STM32F7xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck is the UART input clock */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#if defined(USART_ISR_REACK) +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#endif /* USART_ISR_REACK */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#if defined(USART_CR1_UESM) +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#endif /* USART_CR1_UESM */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#if defined(USART_CR1_UESM) +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#endif /* USART_CR1_UESM */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#if defined(USART_CR1_UESM) +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* USART_CR1_UESM */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag +#if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: +#if defined(USART_ISR_REACK) + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag +#endif + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + #endif + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) + + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 27000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +#if defined(USART_CR1_UESM) +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +#endif /* USART_CR1_UESM */ +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +#if defined(USART_CR1_UESM) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* USART_CR1_UESM */ + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32f7xx_hal_uart_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h new file mode 100644 index 0000000..866a490 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_EX_H +#define STM32F7xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +#if defined(USART_CR1_UESM) +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +#if defined(USART_CR1_UESM) +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#endif /* USART_CR1_UESM */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +#if defined(USART_CR1_UESM) +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +#endif/* USART_CR1_UESM */ +#if defined(USART_CR3_UCESM) +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); + +#endif /* USART_CR3_UCESM */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART7) \ + { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ + case RCC_UART7CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART7CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART7CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART7CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART8) \ + { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ + case RCC_UART8CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART8CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART8CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART8CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h new file mode 100644 index 0000000..c326c3e --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h @@ -0,0 +1,1321 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_fmc.h + * @author MCD Application Team + * @brief Header file of FMC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_FMC_H +#define __STM32F7xx_LL_FMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FMC_LL + * @{ + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ +#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ + ((BANK) == FMC_NORSRAM_BANK2) || \ + ((BANK) == FMC_NORSRAM_BANK3) || \ + ((BANK) == FMC_NORSRAM_BANK4)) + +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) + +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) + +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) + +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) + +#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) + +#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) + +#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) + +#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ + ((STATE) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) + +#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) + +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) + +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) + +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) + +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) + +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) + +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) + +/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time + * @{ + */ +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) +/** + * @} + */ + +/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time + * @{ + */ +#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Setup_Time FMC Setup Time + * @{ + */ +#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time + * @{ + */ +#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time + * @{ + */ +#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time + * @{ + */ +#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) + +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) + +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) + +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) + +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) + +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) + +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) + +/** @defgroup FMC_Data_Latency FMC Data Latency + * @{ + */ +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +/** + * @} + */ + +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) + +#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) + + +/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time + * @{ + */ +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time + * @{ + */ +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time + * @{ + */ +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +/** + * @} + */ + +/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration + * @{ + */ +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FMC_CLK_Division FMC CLK Division + * @{ + */ +#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay + * @{ + */ +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay + * @{ + */ +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time + * @{ + */ +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay + * @{ + */ +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time + * @{ + */ +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay + * @{ + */ +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay + * @{ + */ +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number + * @{ + */ +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition + * @{ + */ +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate + * @{ + */ +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance + * @{ + */ +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance + * @{ + */ +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance + * @{ + */ +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance + * @{ + */ +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +/** + * @} + */ + +#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ + ((BANK) == FMC_SDRAM_BANK2)) + +#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) + +#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) + +#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) + + +#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) + +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) + +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types + * @{ + */ +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef + +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#define FMC_NAND_DEVICE FMC_Bank3 +#define FMC_SDRAM_DEVICE FMC_Bank5_6 + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ + +}FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +}FMC_NORSRAM_TimingTypeDef; + +/** + * @brief FMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +}FMC_NAND_InitTypeDef; + +/** + * @brief FMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +}FMC_NAND_PCC_TimingTypeDef; + +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. + This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. + This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. + This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ +}FMC_SDRAM_InitTypeDef; + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +}FMC_SDRAM_TimingTypeDef; + +/** + * @brief SDRAM command parameters structure definition + */ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ +}FMC_SDRAM_CommandTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ + +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) +#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) +#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) +#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) +#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +/** + * @} + */ + +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @{ + */ +#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) +#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) +#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) +#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller + * @{ + */ +/** @defgroup FMC_NAND_Bank FMC NAND Bank + * @{ + */ +#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_feature FMC Wait feature + * @{ + */ +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @{ + */ +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @{ + */ +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_ECC FMC ECC + * @{ + */ +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) +#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @{ + */ +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller + * @{ + */ +/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) +#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) +#define FMC_IT_LEVEL ((uint32_t)0x00000010U) +#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) +#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @{ + */ +#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) +#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) +#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) +#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE +#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY +#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @{ + */ + +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) + +/** + * @} + */ + +/** @defgroup FMC_Interrupt FMC Interrupt + * @brief macros to handle FMC interrupts + * @{ + */ + +/** + * @brief Enable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) + +/** + * @brief Disable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND Instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) + +/** + * @brief Enable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) + +/** + * @brief Disable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. + * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR + * @retval None + */ +#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** @defgroup FMC_LL_NAND NAND + * @{ + */ +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM SDRAM + * @{ + */ +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_FMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c new file mode 100644 index 0000000..48bbd53 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -0,0 +1,620 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F7xx HAL Driver version number V1.2.8 + */ +#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, and instruction cache through ART accelerator. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Instruction cache through ART accelerator */ +#if (ART_ACCLERATOR_ENABLE != 0) + __HAL_FLASH_ART_ENABLE(); +#endif /* ART_ACCLERATOR_ENABLE */ + + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Enables the FMC Memory Mapping Swapping. + * + * @note SDRAM is accessible at 0x60000000 + * and NOR/RAM is accessible at 0xC0000000 + * + * @retval None + */ +void HAL_EnableFMCMemorySwapping(void) +{ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * + * @retval None + */ +void HAL_DisableFMCMemorySwapping(void) +{ + + SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); +} + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** +* @brief Enable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} + +/** +* @brief Disable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c new file mode 100644 index 0000000..b58d9bd --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c @@ -0,0 +1,2063 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + State and errors functions + * + @verbatim + ============================================================================== + ##### ADC Peripheral features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + (#) Interrupt generation at the end of conversion, end of injected conversion, + and in case of analog watchdog or overrun events + (#) Single and continuous conversion modes. + (#) Scan mode for automatic conversion of channel 0 to channel x. + (#) Data alignment with in-built data coherency. + (#) Channel-wise programmable sampling time. + (#) External trigger option with configurable polarity for both regular and + injected conversion. + (#) Dual/Triple mode (on devices with 2 ADCs or more). + (#) Configurable DMA data storage in Dual/Triple ADC mode. + (#) Configurable delay between conversions in Dual/Triple interleaved mode. + (#) ADC conversion type (refer to the datasheets). + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + (#) ADC input range: VREF(minus) = VIN = VREF(plus). + (#) DMA request generation during regular channel conversion. + + + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + + *** Configuration of ADC, groups regular/injected, channels parameters *** + ============================================================================== + [..] + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the injected group parameters (conversion trigger, + sequencer, ..., of injected group) + and the channels for injected group parameters (channel number, + channel rank into sequencer, ..., into injected group) + using function HAL_ADCEx_InjectedConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). + + (#) Optionally, for devices with several ADC instances: configure the + multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). + + *** Execution of ADC conversions *** + ============================================================================== + [..] + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADC_Start() + (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + (+) Stop the ADC peripheral using HAL_ADC_Stop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() + + *** ADC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in ADC HAL driver. + + (+) __HAL_ADC_ENABLE : Enable the ADC peripheral + (+) __HAL_ADC_DISABLE : Disable the ADC peripheral + (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt + (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt + (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled + (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags + (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status + (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register + + *** Callback functions *** + ============================== + [..] + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + (@) You can refer to the ADC HAL driver header file for more useful macros + + *** Deinitialization of ADC *** + ============================================================================== + [..] + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). + (++) ADC clock disable using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA using function HAL_DMA_DeInit(). + (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + + *** Callback registration *** + ============================================================================== + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADC_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct and initializes the ADC MSP. + * + * @note This function is used to configure the global features of the ADC ( + * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, + * the rest of the configuration parameters are specific to the regular + * channels group (scan mode activation, continuous mode activation, + * External trigger source and edge, DMA continuous request after the + * last transfer and End of conversion selection). + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + if(hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + ADC_Init(hadc); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular channel. + (+) Stop conversion of regular channel. + (+) Start conversion of regular channel and enable interrupt. + (+) Stop conversion of regular channel and disable interrupt. + (+) Start conversion of regular channel and enable DMA transfer. + (+) Stop conversion of regular channel and disable DMA transfer. + (+) Handle ADC interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC and starts conversion of the regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC and stop conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for regular conversion complete + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function. + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. + * @arg ADC_OVR_EVENT: ADC Overrun event. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Analog watchdog (level out of window) event */ + if(EventType == ADC_AWD_EVENT) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + /* Overrun event */ + else + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* Return ADC state */ + return HAL_OK; +} + + +/** + * @brief Enables the interrupt and starts ADC conversion of regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables the interrupt and stop ADC conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles ADC interrupt request + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + + tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); + tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); + /* Check End of conversion flag for regular channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + + tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); + tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); + /* Check End of conversion flag for injected channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + } + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) + { + /* Disable ADC end of single conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + } + + tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); + tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); + /* Check Analog watchdog flag */ + if(tmp1 && tmp2) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + } + + tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); + tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); + /* Check Overrun flag */ + if(tmp1 && tmp2) + { + /* Note: On STM32F7, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } +} + +/** + * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CR2 |= ADC_CR2_DMA; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode */ + hadc->Instance->CR2 &= ~ADC_CR2_DMA; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of regular channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Return the selected ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Regular conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Regular conversion half DMA transfer callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file + */ +} + +/** + * @brief Error ADC callback. + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure regular channels. + (+) Configure injected channels. + (+) Configure multimode. + (+) Configure the analog watch dog. + +@endverbatim + * @{ + */ + + /** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfig ADC configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); + } + else + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + } + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); + } + + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 13 to 16 */ + else + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); + } + + /* if no internal channel selected */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) + { + /* Disable the VBAT & TSVREFE channel*/ + ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); + } + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) + { + /* Enable the VBAT channel*/ + ADC->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) + { + /* Enable the TSVREFE channel*/ + ADC->CCR |= ADC_CCR_TSVREFE; + + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure + * that contains the configuration information of ADC analog watchdog. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters */ + assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); +#endif /* USE_FULL_ASSERT */ + + /* Process locked */ + __HAL_LOCK(hadc); + + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); + + /* Set the analog watchdog enable mode */ + hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; + + /* Set the high threshold */ + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + + /* Set the low threshold */ + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + + /* Clear the Analog watchdog channel select bits */ + hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; + + /* Set the Analog watchdog channel */ + hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the ADC state + (+) Check the ADC Error + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL state + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct without initializing the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +static void ADC_Init(ADC_HandleTypeDef* hadc) +{ + /* Set ADC parameters */ + /* Set the ADC clock prescaler */ + ADC->CCR &= ~(ADC_CCR_ADCPRE); + ADC->CCR |= hadc->Init.ClockPrescaler; + + /* Set ADC scan mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + + /* Set ADC resolution */ + hadc->Instance->CR1 &= ~(ADC_CR1_RES); + hadc->Instance->CR1 |= hadc->Init.Resolution; + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + hadc->Instance->CR2 |= hadc->Init.DataAlign; + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + } + + /* Enable or disable ADC continuous conversion mode */ + hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + + if(hadc->Init.DiscontinuousConvMode != DISABLE) + { + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); + } + + /* Set ADC number of conversion */ + hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + + /* Enable or disable ADC DMA continuous request */ + hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + + /* Enable or disable ADC end of conversion selection */ + hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c new file mode 100644 index 0000000..3c29a79 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c @@ -0,0 +1,1039 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the ADC extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the ADC DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + (#) Configure the ADC Prescaler, conversion resolution and data alignment + using the HAL_ADC_Init() function. + + (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() + and HAL_ADC_ConfigChannel() functions. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() + (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback + (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Select the Multi mode ADC regular channels features (dual or triple mode) + and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. + (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADCEx_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of injected channel. + (+) Stop conversion of injected channel. + (+) Start multimode and enable DMA transfer. + (+) Stop multimode and disable DMA transfer. + (+) Get result of injected channel conversion. + (+) Get result of multimode conversion. + (+) Configure injected channels. + (+) Configure multimode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + uint32_t tmp1 = 0, tmp2 = 0; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables the interrupt and starts ADC conversion of injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + uint32_t tmp1 = 0, tmp2 = 0; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Poll for injected conversion complete + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; + } + } + } + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of injected channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param InjectedRank the ADC injected rank. + * This parameter can be one of the following values: + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + * @retval None + */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Return the selected ADC converted value */ + switch(InjectedRank) + { + case ADC_INJECTED_RANK_4: + { + tmp = hadc->Instance->JDR4; + } + break; + case ADC_INJECTED_RANK_3: + { + tmp = hadc->Instance->JDR3; + } + break; + case ADC_INJECTED_RANK_2: + { + tmp = hadc->Instance->JDR2; + } + break; + case ADC_INJECTED_RANK_1: + { + tmp = hadc->Instance->JDR1; + } + break; + default: + break; + } + return tmp; +} + +/** + * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral + * + * @note Caution: This function must be used only with the ADC master. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + if (hadc->Init.DMAContinuousRequests != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADC->CCR &= ~ADC_CCR_DDS; + } + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); + + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode for multimode */ + ADC->CCR &= ~ADC_CCR_DDS; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval The converted data value. + */ +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +{ + /* Return the multi mode conversion value */ + return ADC->CDR; +} + +/** + * @brief Injected conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfigInjected ADC configuration structure for injected channel. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); +#endif /* USE_FULL_ASSERT */ + + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + + /*---------------------------- ADCx JSQR Configuration -----------------*/ + hadc->Instance->JSQR &= ~(ADC_JSQR_JL); + hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + + /* Rank configuration */ + + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + } + + if (sConfigInjected->AutoInjectedConv != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 |= ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); + } + + if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 |= ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); + } + + switch(sConfigInjected->InjectedRank) + { + case 1: + /* Set injected channel 1 offset */ + hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); + hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + break; + case 2: + /* Set injected channel 2 offset */ + hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); + hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + break; + case 3: + /* Set injected channel 3 offset */ + hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); + hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + break; + default: + /* Set injected channel 4 offset */ + hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); + hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + break; + } + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) + { + /* Enable the VBAT channel*/ + ADC->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) + { + /* Enable the TSVREFE channel*/ + ADC->CCR |= ADC_CCR_TSVREFE; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the ADC multi-mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains + * the configuration information for multimode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +{ + /* Check the parameters */ + assert_param(IS_ADC_MODE(multimode->Mode)); + assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Set ADC mode */ + ADC->CCR &= ~(ADC_CCR_MULTI); + ADC->CCR |= multimode->Mode; + + /* Set the ADC DMA access mode */ + ADC->CCR &= ~(ADC_CCR_DMA); + ADC->CCR |= multimode->DMAAccessMode; + + /* Set delay between two sampling phases */ + ADC->CCR &= ~(ADC_CCR_DELAY); + ADC->CCR |= multimode->TwoSamplingDelay; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + + /** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c new file mode 100644 index 0000000..b0a816a --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c @@ -0,0 +1,505 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c new file mode 100644 index 0000000..7f79561 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c @@ -0,0 +1,1299 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dac.c + * @author MCD Application Team + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Digital to Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * + @verbatim + ============================================================================== + ##### DAC Peripheral features ##### + ============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + The device integrates two 12-bit Digital Analog Converters that can + be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9. + The used pin (GPIOx_Pin9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...) + + (#) Software using DAC_TRIGGER_SOFTWARE + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() + (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate() + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_ALIGN_8B_R + (#) 12-bit left alignment using DAC_ALIGN_12B_L + (#) 12-bit right alignment using DAC_ALIGN_12B_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + DAC_OUTx = VREF+ * DOR / 4095 + with DOR is the Data Output Register + VEF+ is the input voltage reference (refer to the device datasheet) + e.g. To set DAC_OUT1 to 0.7V, use + Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not + a software trigger) occurs if DMA1 requests are enabled using + HAL_DAC_Start_DMA() + [..] + DMA1 requests are mapped as following: + (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be + already configured + (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be + already configured + + -@- For Dual mode and specific signal (Triangle and noise) generation please + refer to Extension Features Driver description + + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using HAL_DAC_Init() + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + (+) All Callbacks + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init + and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit + or @ref HAL_DAC_Init function. + + When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup DAC_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DAC peripheral according to the specified parameters + * in the DAC_InitStruct. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if(hdac->State == HAL_DAC_STATE_RESET) + { +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the DAC Callback settings */ + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + + if(hdac->MspInitCallback == NULL) + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +{ + /* Check DAC handle */ + if(hdac == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + if(hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } + /* DeInit the low level hardware */ + hdac->MspDeInitCallback(hdac); +#else + /* DeInit the low level hardware */ + HAL_DAC_MspDeInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the DAC MSP. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + + if(Channel == DAC_CHANNEL_1) + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + } + } + else + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + { + /* Enable the selected DAC software conversion*/ + hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData: The Source memory Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if(Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + hdac->Instance->CR |= DAC_CR_DMAEN1; + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + } + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_DMAEN2; + + /* Case of use of channel 2 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } + + /* Enable the DMA Stream */ + if(Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + else /* Channel2 is used for */ + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Check if DMA Channel effectively disabled */ + if(status != HAL_OK) + { + /* Update DAC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check underrun channel 1 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else + HAL_DAC_DMAUnderrunCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + /* Check underrun channel 2 flag */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel1 DMA request */ + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Conversion complete callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig: DAC configuration structure. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << Channel; + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + /* Disable wave generation */ + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if(Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC state + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) +{ + /* Return DAC state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DAC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdac); + + if(hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} + +/** + * @brief Unregister a User DAC Callback + * DAC Callback is redirected to the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdac); + + if(hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSP_INIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSP_DEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh1(hdac); +#else + HAL_DAC_ErrorCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c new file mode 100644 index 0000000..e48624b --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dac_ex.c + * @author MCD Application Team + * @brief Extended DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of DAC extension peripheral: + * + Extended features functions + * + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DACEx DACEx + * @brief DAC driver modules + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DACEx_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +{ + uint32_t tmp = 0; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude: Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the selected wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @brief Conversion complete callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c new file mode 100644 index 0000000..6bd09e1 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c @@ -0,0 +1,1307 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Select Callbacks functions using HAL_DMA_RegisterCallback() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer flag */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c new file mode 100644 index 0000000..0941f06 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c @@ -0,0 +1,2008 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma2d.c + * @author MCD Application Team + * @brief DMA2D HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DMA2D peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Program the required configuration through the following parameters: + the transfer mode, the output color mode and the output offset using + HAL_DMA2D_Init() function. + + (#) Program the required configuration through the following parameters: + the input color mode, the input color, the input alpha value, the alpha mode, + the red/blue swap mode, the inverted alpha mode and the input offset using + HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. + + *** Polling mode IO operation *** + ================================= + [..] + (#) Configure pdata parameter (explained hereafter), destination and data length + and enable the transfer using HAL_DMA2D_Start(). + (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage + user can specify the value of timeout according to his end application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (#) Configure pdata parameter, destination and data length and enable + the transfer using HAL_DMA2D_Start_IT(). + (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. + (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback (member + of DMA2D handle structure). + (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback + XferErrorCallback. + + -@- In Register-to-Memory transfer mode, pdata parameter is the register + color, in Memory-to-memory or Memory-to-Memory with pixel format + conversion pdata is the source address. + + -@- Configure the foreground source address, the background source address, + the destination and data length then Enable the transfer using + HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() + in interrupt mode. + + -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions + are used if the memory to memory with blending transfer mode is selected. + + (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling + mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. + + (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent(). + + (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two + consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() + and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or + HAL_DMA2D_DisableDeadTime(). + + (#) The transfer can be suspended, resumed and aborted using the following + functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). + + (#) The CLUT loading can be suspended, resumed and aborted using the following + functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), + HAL_DMA2D_CLUTLoading_Abort(). + + (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). + + (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). + + *** DMA2D HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA2D HAL driver : + + (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. + (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. + (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. + (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. + (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. + (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. + + *** Callback registration *** + =================================== + [..] + (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. + + (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) XferCpltCallback : callback for transfer complete. + (+) XferErrorCallback : callback for transfer error. + (+) LineEventCallback : callback for line event. + (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. + (+) MspInitCallback : DMA2D MspInit. + (+) MspDeInitCallback : DMA2D MspDeInit. + + (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions: + examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + Exception as well for Transfer Completion and Transfer Error callbacks that are not defined + as weak (surcharged) functions. They must be defined by the user to be resorted to. + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit + or @ref HAL_DMA2D_Init function. + + When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + (@) You can refer to the DMA2D HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +#ifdef HAL_DMA2D_MODULE_ENABLED +#if defined (DMA2D) + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA2D DMA2D + * @brief DMA2D HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_TimeOut DMA2D Time Out + * @{ + */ +#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */ +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DMA2D + (+) De-initialize the DMA2D + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA2D according to the specified + * parameters in the DMA2D_InitTypeDef and create the associated handle. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the DMA2D peripheral state */ + if(hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); + assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); + assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); + assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + if(hdma2d->MspInitCallback == NULL) + { + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; + } + + /* Init the low level hardware */ + hdma2d->MspInitCallback(hdma2d); + } +#else + if(hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_DMA2D_MspInit(hdma2d); + } +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Deinitializes the DMA2D peripheral registers to their default reset + * values. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ + +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) +{ + + /* Check the DMA2D peripheral state */ + if(hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Before aborting any DMA2D transfer or CLUT loading, check + first whether or not DMA2D clock is enabled */ + if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) + { + /* Abort DMA2D transfer if any */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) + { + if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) + { + /* Issue when aborting DMA2D transfer */ + return HAL_ERROR; + } + } + else + { + /* Abort background CLUT loading if any */ + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) + { + /* Issue when aborting background CLUT loading */ + return HAL_ERROR; + } + } + else + { + /* Abort foreground CLUT loading if any */ + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) + { + /* Issue when aborting foreground CLUT loading */ + return HAL_ERROR; + } + } + } + } + } + + /* Reset DMA2D control registers*/ + hdma2d->Instance->CR = 0U; + hdma2d->Instance->IFCR = 0x3FU; + hdma2d->Instance->FGOR = 0U; + hdma2d->Instance->BGOR = 0U; + hdma2d->Instance->FGPFCCR = 0U; + hdma2d->Instance->BGPFCCR = 0U; + hdma2d->Instance->OPFCCR = 0U; + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + + if(hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } + + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); + +#else + /* Carry on with de-initialization of low level hardware */ + HAL_DMA2D_MspDeInit(hdma2d); +#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Initializes the DMA2D MSP. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the DMA2D MSP. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspDeInit can be implemented in the user file. + */ +} + +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DMA2D Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} + +/** + * @brief Unregister a DMA2D Callback + * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * @param hdma2d DMA2D handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID + * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID + * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID + * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID + * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID + * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID + * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID + * @retval status + */ +HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) +{ +HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma2d); + + if(HAL_DMA2D_STATE_READY == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; + + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; + + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; + + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; + + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + { + switch (CallbackID) + { + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; + + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; + + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + return status; +} +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer. + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer with interrupt. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer with interrupt. + (+) Abort DMA2D transfer. + (+) Suspend DMA2D transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. + (+) Configure CLUT loading then start transfer in polling mode. + (+) Configure CLUT loading then start transfer in interrupt mode. + (+) Abort DMA2D CLUT loading. + (+) Suspend DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. + (+) Poll for transfer complete. + (+) handle DMA2D interrupt request. + (+) Transfer watermark callback. + (+) CLUT Transfer Complete callback. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA2D Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the DMA2D Transfer with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata Configure the source memory Buffer address if + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1 The source memory Buffer address for the foreground layer. + * @param SrcAddress2 The source memory Buffer address for the background layer. + * @param DstAddress The destination memory Buffer address. + * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart; + + /* Abort the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue) */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively disabled */ + while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart; + + /* Suspend the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively suspended */ + while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D Transfer. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the SUSP and START bits */ + if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + { + /* Ongoing transfer is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + + /* Resume the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing 0 has no + effect on START bitvalue). */ + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + + return HAL_OK; +} + + +/** + * @brief Enable the DMA2D CLUT Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Enable the background CLUT loading */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + else + { + /* Enable the foreground CLUT loading */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + + +/** + * @brief Start DMA2D CLUT Loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Abort the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is aborted */ + while((*reg & DMA2D_BGPFCCR_START) != 0U) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart; + uint32_t loadsuspended; + const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + + /* Suspend the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == DMA2D_FOREGROUND_LAYER) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is suspended */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + while (loadsuspended == 0UL) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((*reg & DMA2D_BGPFCCR_START) != 0U) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D CLUT loading. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the SUSP and START bits for background or foreground CLUT loading */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Background CLUT loading suspension check */ + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + { + if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + } + else + { + /* Foreground CLUT loading suspension check */ + if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + { + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + } + + /* Resume the CLUT loading */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + return HAL_OK; +} + + +/** + + * @brief Polling for transfer complete or CLUT loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t layer_start; + __IO uint32_t isrflags = 0x0U; + + /* Polling for DMA2D transfer */ + if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; + layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; + if (layer_start != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + { + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + } + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} +/** + * @brief Handle DMA2D interrupt request. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); + uint32_t crflags = READ_REG(hdma2d->Instance->CR); + + /* Transfer Error Interrupt management ***************************************/ + if ((isrflags & DMA2D_FLAG_TE) != 0U) + { + if ((crflags & DMA2D_IT_TE) != 0U) + { + /* Disable the transfer Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + + /* Clear the transfer error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Configuration Error Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_CE) != 0U) + { + if ((crflags & DMA2D_IT_CE) != 0U) + { + /* Disable the Configuration Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); + + /* Clear the Configuration error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* CLUT access Error Interrupt management ***********************************/ + if ((isrflags & DMA2D_FLAG_CAE) != 0U) + { + if ((crflags & DMA2D_IT_CAE) != 0U) + { + /* Disable the CLUT access error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); + + /* Clear the CLUT access error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Transfer watermark Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_TW) != 0U) + { + if ((crflags & DMA2D_IT_TW) != 0U) + { + /* Disable the transfer watermark interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Clear the transfer watermark flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); + + /* Transfer watermark Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->LineEventCallback(hdma2d); +#else + HAL_DMA2D_LineEventCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + + } + } + /* Transfer Complete Interrupt management ************************************/ + if ((isrflags & DMA2D_FLAG_TC) != 0U) + { + if ((crflags & DMA2D_IT_TC) != 0U) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); + + /* Clear the transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferCpltCallback != NULL) + { + /* Transfer complete Callback */ + hdma2d->XferCpltCallback(hdma2d); + } + } + } + /* CLUT Transfer Complete Interrupt management ******************************/ + if ((isrflags & DMA2D_FLAG_CTC) != 0U) + { + if ((crflags & DMA2D_IT_CTC) != 0U) + { + /* Disable the CLUT transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); + + /* Clear the CLUT transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + /* CLUT Transfer complete Callback */ +#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) + hdma2d->CLUTLoadingCpltCallback(hdma2d); +#else + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); +#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ + } + } + +} + +/** + * @brief Transfer watermark callback. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_LineEventCallback can be implemented in the user file. + */ +} + +/** + * @brief CLUT Transfer Complete callback. + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the DMA2D foreground or background layer parameters. + (+) Configure the DMA2D CLUT transfer. + (+) Configure the line watermark + (+) Configure the dead time value. + (+) Enable or disable the dead time value functionality. + + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA2D Layer according to the specified + * parameters in the DMA2D_HandleTypeDef. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + DMA2D_LayerCfgTypeDef *pLayerCfg; + uint32_t regMask, regValue; + + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); + if(hdma2d->Init.Mode != DMA2D_R2M) + { + assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); + if(hdma2d->Init.Mode != DMA2D_M2M) + { + assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); + } + } +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); + assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + + /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ +#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); + regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); +#else + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); + regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; +#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ + + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + } + + /* Configure the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + } + } + /* Configure the foreground DMA2D layer */ + else + { + + + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + } + } + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure the DMA2D CLUT Transfer. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + } + + /* Set the DMA2D state to Ready*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + + +/** + * @brief Configure the line watermark. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Line Line Watermark configuration (maximum 16-bit long value expected). + * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. + * @note The transfer watermark interrupt is disabled once it has occurred. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINEWATERMARK(Line)); + + if (Line > DMA2D_LWR_LW) + { + return HAL_ERROR; + } + else + { + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Sets the Line watermark configuration */ + WRITE_REG(hdma2d->Instance->LWR, Line); + + /* Enable the Line interrupt */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; + } +} + +/** + * @brief Enable DMA2D dead time feature. + * @param hdma2d DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR EN bit */ + SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Disable DMA2D dead time feature. + * @param hdma2d DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Clear DMA2D_AMTCR EN bit */ + CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure dead time. + * @note The dead time value represents the guaranteed minimum number of cycles between + * two consecutive transactions on the AHB bus. + * @param hdma2d DMA2D handle. + * @param DeadTime dead time value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR DT field */ + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos)); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to: + (+) Get the DMA2D state + (+) Get the DMA2D error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA2D state + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL state + */ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->State; +} + +/** + * @brief Return the DMA2D error code + * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for DMA2D. + * @retval DMA2D Error Code + */ +uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ + +/** + * @brief Set the DMA2D transfer parameters. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the specified DMA2D. + * @param pdata The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param Width The width of data to be transferred from source to destination. + * @param Height The height of data to be transferred from source to destination. + * @retval HAL status + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; + uint32_t tmp4; + + /* Configure DMA2D data size */ + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + + /* Configure DMA2D destination address */ + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); + + /* Register to memory DMA2D mode selected */ + if (hdma2d->Init.Mode == DMA2D_R2M) + { + tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; + tmp2 = pdata & DMA2D_OCOLR_RED_1; + tmp3 = pdata & DMA2D_OCOLR_GREEN_1; + tmp4 = pdata & DMA2D_OCOLR_BLUE_1; + + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) + { + tmp = (tmp3 | tmp2 | tmp1| tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) + { + tmp = (tmp3 | tmp2 | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) + { + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 10U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) + { + tmp1 = (tmp1 >> 31U); + tmp2 = (tmp2 >> 19U); + tmp3 = (tmp3 >> 11U); + tmp4 = (tmp4 >> 3U ); + tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); + } + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ + { + tmp1 = (tmp1 >> 28U); + tmp2 = (tmp2 >> 20U); + tmp3 = (tmp3 >> 12U); + tmp4 = (tmp4 >> 4U ); + tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); + } + /* Write to DMA2D OCOLR register */ + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + } + else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ + { + /* Configure DMA2D source address */ + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* DMA2D */ +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c new file mode 100644 index 0000000..0873354 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c new file mode 100644 index 0000000..8793739 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c @@ -0,0 +1,2705 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_dsi.c + * @author MCD Application Team + * @brief DSI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the DSI peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required + PLL parameters, number of lanes and TX Escape clock divider. + (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + command mode. + (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host. + (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer(). + (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop(). + Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively + to write DSI short packets, long packets and to read DSI packets. + + (#) The DSI Host Offers two Low power modes : + (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData() + and @ref HAL_DSI_ExitULPMData() + + (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM() + and @ref HAL_DSI_ExitULPM() + + (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function @ref HAL_DSI_GetError() + + (#) To control DSI state you can use the following function: HAL_DSI_GetState() + + *** DSI HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DSI HAL driver. + + (+) __HAL_DSI_ENABLE: Enable the DSI Host. + (+) __HAL_DSI_DISABLE: Disable the DSI Host. + (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. + (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. + (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. + (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. + (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. + (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. + (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. + (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. + (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. + (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. + (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + + + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_DSI_RegisterCallback() to register a callback. + + Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit + or HAL_DSI_Init function. + + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DSI_MODULE_ENABLED + +#if defined(DSI) + +/** @addtogroup DSI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup DSI_Private_Constants + * @{ + */ +#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ + +#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ + DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ + DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ + DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) +#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) +#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX +#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX +#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) +#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE +#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE +#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE +#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE +#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, + uint32_t Data1); + +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); + +/* Private functions ---------------------------------------------------------*/ +/** + * @brief Generic DSI packet header configuration + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet + * This parameter can be any value of : + * @ref DSI_SHORT_WRITE_PKT_Data_Type + * or @ref DSI_LONG_WRITE_PKT_Data_Type + * or @ref DSI_SHORT_READ_PKT_Data_Type + * or DSI_MAX_RETURN_PKT_SIZE + * @param Data0 Word count LSB + * @param Data1 Word count MSB + * @retval None + */ +static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, + uint32_t ChannelID, + uint32_t DataType, + uint32_t Data0, + uint32_t Data1) +{ + /* Update the DSI packet header with new information */ + DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U)); +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2 DSC parameter or second generic parameter. + * @retval HAL status + */ +static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + uint32_t tickstart; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the packet to send a short DCS command with 0 or 1 parameter */ + /* Update the DSI packet header with new information */ + hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); + + return HAL_OK; +} + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DSI_Exported_Functions + * @{ + */ + +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DSI + (+) De-initialize the DSI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DSI according to the specified + * parameters in the DSI_InitTypeDef and create the associated handle. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains + * the PLL Clock structure definition for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) +{ + uint32_t tickstart; + uint32_t unitIntervalx4; + uint32_t tempIDF; + + /* Check the DSI handle allocation */ + if (hdsi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); + assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); + assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); + assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); + assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->State == HAL_DSI_STATE_RESET) + { + /* Reset the DSI callback to the legacy weak callbacks */ + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hdsi->MspInitCallback == NULL) + { + hdsi->MspInitCallback = HAL_DSI_MspInit; + } + /* Initialize the low level hardware */ + hdsi->MspInitCallback(hdsi); + } +#else + if (hdsi->State == HAL_DSI_STATE_RESET) + { + /* Initialize the low level hardware */ + HAL_DSI_MspInit(hdsi); + } +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /**************** Turn on the regulator and enable the DSI PLL ****************/ + + /* Enable the regulator */ + __HAL_DSI_REG_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the regulator is ready */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the PLL division factors */ + hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U)); + + /* Enable the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /*************************** Set the PHY parameters ***************************/ + + /* D-PHY clock and digital enable*/ + hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Clock lane configuration */ + hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); + hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); + + /* Configure the number of active data lanes */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; + hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; + + /************************ Set the DSI clock parameters ************************/ + + /* Set the TX escape clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; + hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; + + /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ + /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ + /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ + tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; + unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV); + + /* Set the bit period in high-speed mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; + hdsi->Instance->WPCR[0U] |= unitIntervalx4; + + /****************************** Error management *****************************/ + + /* Disable all error interrupts and reset the Error Mask */ + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + hdsi->ErrorMsk = 0U; + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initializes the DSI peripheral registers to their default reset + * values. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) +{ + /* Check the DSI handle allocation */ + if (hdsi == NULL) + { + return HAL_ERROR; + } + + /* Change DSI peripheral state */ + hdsi->State = HAL_DSI_STATE_BUSY; + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* D-PHY clock and digital disable */ + hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Disable the regulator */ + __HAL_DSI_REG_DISABLE(hdsi); + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + if (hdsi->MspDeInitCallback == NULL) + { + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; + } + /* DeInit the low level hardware */ + hdsi->MspDeInitCallback(hdsi); +#else + /* DeInit the low level hardware */ + HAL_DSI_MspDeInit(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + + /* Initialise the error code */ + hdsi->ErrorCode = HAL_DSI_ERROR_NONE; + + /* Initialize the DSI state*/ + hdsi->State = HAL_DSI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable the error monitor flags + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ActiveErrors indicates which error interrupts will be enabled. + * This parameter can be any combination of @ref DSI_Error_Data_Type. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + hdsi->Instance->IER[0U] = 0U; + hdsi->Instance->IER[1U] = 0U; + + /* Store active errors to the handle */ + hdsi->ErrorMsk = ActiveErrors; + + if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; + } + + if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) + { + /* Enable the interrupt generation on selected errors */ + hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Initializes the DSI MSP. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initializes the DSI MSP. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DSI Callback + * To be used instead of the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, + pDSI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = pCallback; + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = pCallback; + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = pCallback; + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = pCallback; + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief Unregister a DSI Callback + * DSI callabck is redirected to the weak predefined callback + * @param hdsi dsi handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdsi); + + if (hdsi->State == HAL_DSI_STATE_READY) + { + switch (CallbackID) + { + case HAL_DSI_TEARING_EFFECT_CB_ID : + hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ + break; + + case HAL_DSI_ENDOF_REFRESH_CB_ID : + hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ + break; + + case HAL_DSI_ERROR_CB_ID : + hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hdsi->State == HAL_DSI_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DSI_MSPINIT_CB_ID : + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_DSI_MSPDEINIT_CB_ID : + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdsi); + + return status; +} +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle DSI interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handles DSI interrupt request. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) +{ + uint32_t ErrorStatus0, ErrorStatus1; + + /* Tearing Effect Interrupt management ***************************************/ + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) + { + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) + { + /* Clear the Tearing Effect Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); + + /* Tearing Effect Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Tearing Effect callback */ + hdsi->TearingEffectCallback(hdsi); +#else + /*Call legacy Tearing Effect callback*/ + HAL_DSI_TearingEffectCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } + + /* End of Refresh Interrupt management ***************************************/ + if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) + { + if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) + { + /* Clear the End of Refresh Interrupt Flag */ + __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); + + /* End of Refresh Callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered End of refresh callback */ + hdsi->EndOfRefreshCallback(hdsi); +#else + /*Call Legacy End of refresh callback */ + HAL_DSI_EndOfRefreshCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } + + /* Error Interrupts management ***********************************************/ + if (hdsi->ErrorMsk != 0U) + { + ErrorStatus0 = hdsi->Instance->ISR[0U]; + ErrorStatus0 &= hdsi->Instance->IER[0U]; + ErrorStatus1 = hdsi->Instance->ISR[1U]; + ErrorStatus1 &= hdsi->Instance->IER[1U]; + + if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; + } + + if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; + } + + if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_TX; + } + + if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_RX; + } + + if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; + } + + if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; + } + + if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; + } + + if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; + } + + if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; + } + + if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) + { + hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; + } + + /* Check only selected errors */ + if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE) + { + /* DSI error interrupt callback */ +#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) + /*Call registered Error callback */ + hdsi->ErrorCallback(hdsi); +#else + /*Call Legacy Error callback */ + HAL_DSI_ErrorCallback(hdsi); +#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Tearing Effect DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_TearingEffectCallback could be implemented in the user file + */ +} + +/** + * @brief End of Refresh DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_EndOfRefreshCallback could be implemented in the user file + */ +} + +/** + * @brief Operation Error DSI callback. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval None + */ +__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdsi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DSI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the Generic interface read-back Virtual Channel ID + (+) Select video mode and configure the corresponding parameters + (+) Configure command transmission mode: High-speed or Low-power + (+) Configure the flow control + (+) Configure the DSI PHY timer + (+) Configure the DSI HOST timeout + (+) Configure the DSI HOST timeout + (+) Start/Stop the DSI module + (+) Refresh the display in command mode + (+) Controls the display color mode in Video mode + (+) Control the display shutdown in Video mode + (+) write short DCS or short Generic command + (+) write long DCS or long Generic command + (+) Read command (DCS or generic) + (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) + (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) + (+) Start/Stop test pattern generation + (+) Slew-Rate And Delay Tuning + (+) Low-Power Reception Filter Tuning + (+) Activate an additional current path on all lanes to meet the SDDTx parameter + (+) Custom lane pins configuration + (+) Set custom timing for the PHY + (+) Force the Clock/Data Lane in TX Stop Mode + (+) Force LP Receiver in Low-Power Mode + (+) Force Data Lanes in RX Mode after a BTA + (+) Enable a pull-down on the lanes to prevent from floating states when unused + (+) Switch off the contention detection on data lanes + +@endverbatim + * @{ + */ + +/** + * @brief Configure the Generic interface read-back Virtual Channel ID. + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VirtualChannelID Virtual channel ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the GVCID register */ + hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; + hdsi->Instance->GVCIDR |= VirtualChannelID; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select video mode and configure the corresponding parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); + assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); + assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); + assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); + assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); + assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); + assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); + assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); + assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); + assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); + assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); + /* Check the LooselyPacked variant only in 18-bit mode */ + if (VidCfg->ColorCoding == DSI_RGB666) + { + assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); + } + + /* Select video mode by resetting CMDM and DSIM bits */ + hdsi->Instance->MCR &= ~DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + + /* Configure the video mode transmission type */ + hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; + hdsi->Instance->VMCR |= VidCfg->Mode; + + /* Configure the video packet size */ + hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; + hdsi->Instance->VPCR |= VidCfg->PacketSize; + + /* Set the chunks number to be transmitted through the DSI link */ + hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; + hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; + + /* Set the size of the null packet */ + hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; + hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U); + + /* Enable/disable the loosely packed variant to 18-bit configuration */ + if (VidCfg->ColorCoding == DSI_RGB666) + { + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; + hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; + } + + /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ + hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; + hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; + + /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ + hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; + hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; + + /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ + hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; + hdsi->Instance->VLCR |= VidCfg->HorizontalLine; + + /* Set the Vertical Synchronization Active (VSA) */ + hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; + hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; + + /* Set the Vertical Back Porch (VBP)*/ + hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; + hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; + + /* Set the Vertical Front Porch (VFP)*/ + hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; + hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; + + /* Set the Vertical Active period*/ + hdsi->Instance->VVACR &= ~DSI_VVACR_VA; + hdsi->Instance->VVACR |= VidCfg->VerticalActive; + + /* Configure the command transmission mode */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; + hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; + + /* Low power largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; + hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U); + + /* Low power VACT largest packet size */ + hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; + hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; + + /* Enable LP transition in HFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; + + /* Enable LP transition in HBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; + hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; + + /* Enable LP transition in VACT period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; + + /* Enable LP transition in VFP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; + + /* Enable LP transition in VBP period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; + + /* Enable LP transition in vertical sync period */ + hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; + hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; + + /* Enable the request for an acknowledge response at the end of a frame */ + hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; + hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Select adapted command mode and configure the corresponding parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); + assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); + assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); + assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); + assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); + assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); + assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); + assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); + assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); + + /* Select command mode by setting CMDM and DSIM bits */ + hdsi->Instance->MCR |= DSI_MCR_CMDM; + hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; + hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; + + /* Select the virtual channel for the LTDC interface traffic */ + hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; + hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; + + /* Configure the polarity of control signals */ + hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); + hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); + + /* Select the color coding for the host */ + hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; + hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; + + /* Select the color coding for the wrapper */ + hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; + hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U); + + /* Configure the maximum allowed size for write memory command */ + hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; + hdsi->Instance->LCCR |= CmdCfg->CommandSize; + + /* Configure the tearing effect source and polarity and select the refresh mode */ + hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); + hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | + CmdCfg->VSyncPol); + + /* Configure the tearing effect acknowledge request */ + hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; + hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; + + /* Enable the Tearing Effect interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); + + /* Enable the End of Refresh interrupt */ + __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure command transmission mode: High-speed or Low-power + * and enable/disable acknowledge request after packet transmission + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains + * the DSI command transmission mode configuration parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); + assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); + assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); + assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); + assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); + assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); + assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); + assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); + assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); + assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); + assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); + assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); + assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); + + /* Select High-speed or Low-power for command transmission */ + hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \ + DSI_CMCR_GSW1TX | \ + DSI_CMCR_GSW2TX | \ + DSI_CMCR_GSR0TX | \ + DSI_CMCR_GSR1TX | \ + DSI_CMCR_GSR2TX | \ + DSI_CMCR_GLWTX | \ + DSI_CMCR_DSW0TX | \ + DSI_CMCR_DSW1TX | \ + DSI_CMCR_DSR0TX | \ + DSI_CMCR_DLWTX | \ + DSI_CMCR_MRDPS); + hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \ + LPCmd->LPGenShortWriteOneP | \ + LPCmd->LPGenShortWriteTwoP | \ + LPCmd->LPGenShortReadNoP | \ + LPCmd->LPGenShortReadOneP | \ + LPCmd->LPGenShortReadTwoP | \ + LPCmd->LPGenLongWrite | \ + LPCmd->LPDcsShortWriteNoP | \ + LPCmd->LPDcsShortWriteOneP | \ + LPCmd->LPDcsShortReadNoP | \ + LPCmd->LPDcsLongWrite | \ + LPCmd->LPMaxReadPacket); + + /* Configure the acknowledge request after each packet transmission */ + hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; + hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the flow control parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param FlowControl flow control feature(s) to be enabled. + * This parameter can be any combination of @ref DSI_FlowControl. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); + + /* Set the DSI Host Protocol Configuration Register */ + hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; + hdsi->Instance->PCR |= FlowControl; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI PHY timer parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains + * the DSI PHY timing parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) +{ + uint32_t maxTime; + /* Process locked */ + __HAL_LOCK(hdsi); + + maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime : + PhyTimers->ClockLaneHS2LPTime; + + /* Clock lane timer configuration */ + + /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two + High-Speed transmission. + To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed + to Low-Power and from Low-Power to High-Speed. + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. + + Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. + */ + hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); + hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U)); + + /* Data lane timer configuration */ + hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); + hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | (( + PhyTimers->DataLaneHS2LPTime) << 24U)); + + /* Configure the wait period to request HS transmission after a stop state */ + hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; + hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Configure the DSI HOST timeout parameters + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains + * the DSI host timeout parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Set the timeout clock division factor */ + hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; + hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U); + + /* High-speed transmission timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; + hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U); + + /* Low-power reception timeout */ + hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; + hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; + + /* High-speed read timeout */ + hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; + hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; + + /* Low-power read timeout */ + hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; + hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; + + /* High-speed write timeout */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; + + /* High-speed write presp mode */ + hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; + hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; + + /* Low-speed write timeout */ + hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; + hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; + + /* BTA timeout */ + hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; + hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start the DSI module + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Enable the DSI host */ + __HAL_DSI_ENABLE(hdsi); + + /* Enable the DSI wrapper */ + __HAL_DSI_WRAPPER_ENABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop the DSI module + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable the DSI host */ + __HAL_DSI_DISABLE(hdsi); + + /* Disable the DSI wrapper */ + __HAL_DSI_WRAPPER_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Refresh the display in command mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Update the display */ + hdsi->Instance->WCR |= DSI_WCR_LTDCEN; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Controls the display color mode in Video mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ColorMode Color mode (full or 8-colors). + * This parameter can be any value of @ref DSI_Color_Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_COLOR_MODE(ColorMode)); + + /* Update the display color mode */ + hdsi->Instance->WCR &= ~DSI_WCR_COLM; + hdsi->Instance->WCR |= ColorMode; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Control the display shutdown in Video mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Shutdown Shut-down (Display-ON or Display-OFF). + * This parameter can be any value of @ref DSI_ShutDown + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_SHUT_DOWN(Shutdown)); + + /* Update the display Shutdown */ + hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; + hdsi->Instance->WCR |= Shutdown; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief write short DCS or short Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. + * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code. + * @param Param2 DSC parameter or second generic parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); + + /* Process locked */ + __HAL_LOCK(hdsi); + + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return status; +} + +/** + * @brief write long DCS or long Generic command + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. + * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. + * This parameter can be any value of @ref DSI_DCS_Command or a + * generic command code + * @param ParametersTable Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, + uint32_t ChannelID, + uint32_t Mode, + uint32_t NbParams, + uint32_t Param1, + uint8_t *ParametersTable) +{ + uint32_t uicounter, nbBytes, count; + uint32_t tickstart; + uint32_t fifoword; + uint8_t *pparams = ParametersTable; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for Command FIFO Empty */ + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ + fifoword = Param1; + nbBytes = (NbParams < 3U) ? NbParams : 3U; + + for (count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count))); + } + hdsi->Instance->GPDR = fifoword; + + uicounter = NbParams - nbBytes; + pparams += nbBytes; + /* Set the Next parameters on the write FIFO command*/ + while (uicounter != 0U) + { + nbBytes = (uicounter < 4U) ? uicounter : 4U; + fifoword = 0U; + for (count = 0U; count < nbBytes; count++) + { + fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count)); + } + hdsi->Instance->GPDR = fifoword; + + uicounter -= nbBytes; + pparams += nbBytes; + } + + /* Configure the packet to send a long DCS command */ + DSI_ConfigPacketHeader(hdsi->Instance, + ChannelID, + Mode, + ((NbParams + 1U) & 0x00FFU), + (((NbParams + 1U) & 0xFF00U) >> 8U)); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Read command (DCS or generic) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. + * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, + uint32_t ChannelNbr, + uint8_t *Array, + uint32_t Size, + uint32_t Mode, + uint32_t DCSCmd, + uint8_t *ParametersTable) +{ + uint32_t tickstart; + uint8_t *pdata = Array; + uint32_t datasize = Size; + uint32_t fifoword; + uint32_t nbbytes; + uint32_t count; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check the parameters */ + assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); + + if (datasize > 2U) + { + /* set max return packet size */ + if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + + /* Configure the packet to read command */ + if (Mode == DSI_DCS_SHORT_PKT_READ) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); + } + else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) + { + DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* If DSI fifo is not empty, read requested bytes */ + while (((int32_t)(datasize)) > 0) + { + if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) + { + fifoword = hdsi->Instance->GPDR; + nbbytes = (datasize < 4U) ? datasize : 4U; + + for (count = 0U; count < nbbytes; count++) + { + *pdata = (uint8_t)(fifoword >> (8U * count)); + pdata++; + datasize--; + } + } + + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* ULPS Request on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_URDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the D-PHY active lanes enter into ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running + * (only data lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Exit ULPS on Data Lanes */ + hdsi->Instance->PUCR |= DSI_PUCR_UEDL; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms*/ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Clock lane configuration: no more HS request */ + hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; + + /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); + + /* ULPS Request on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn off the DSI PLL */ + __HAL_DSI_PLL_DISABLE(hdsi); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off + * (both data and clock lanes are in ULPM) + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) +{ + uint32_t tickstart; + + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Exit ULPS on Clock and Data Lanes */ + hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until all active lanes exit ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | + DSI_PSR_UANC)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* wait for 1 ms */ + HAL_Delay(1U); + + /* De-assert the ULPM requests and the ULPM exit bits */ + hdsi->Instance->PUCR = 0U; + + /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); + + /* Restore clock lane configuration to HS */ + hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Start test pattern generation + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Mode Pattern generator mode + * This parameter can be one of the following values: + * 0 : Color bars (horizontal or vertical) + * 1 : BER pattern (vertical only) + * @param Orientation Pattern generator orientation + * This parameter can be one of the following values: + * 0 : Vertical color bars + * 1 : Horizontal color bars + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Configure pattern generator mode and orientation */ + hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); + hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U)); + + /* Enable pattern generator by setting PGE bit */ + hdsi->Instance->VMCR |= DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Stop test pattern generation + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Disable pattern generator by clearing PGE bit */ + hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set Slew-Rate And Delay Tuning + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CommDelay Communication delay to be adjusted. + * This parameter can be any value of @ref DSI_Communication_Delay + * @param Lane select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param Value Custom value of the slew-rate or delay + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, + uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); + assert_param(IS_DSI_LANE_GROUP(Lane)); + + switch (CommDelay) + { + case DSI_SLEW_RATE_HSTX: + if (Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Slew Rate Control on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; + hdsi->Instance->WPCR[1U] |= Value << 16U; + } + else if (Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Slew Rate Control on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; + hdsi->Instance->WPCR[1U] |= Value << 18U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_SLEW_RATE_LPTX: + if (Lane == DSI_CLOCK_LANE) + { + /* Low-Power transmission Slew Rate Compensation on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; + hdsi->Instance->WPCR[1U] |= Value << 6U; + } + else if (Lane == DSI_DATA_LANES) + { + /* Low-Power transmission Slew Rate Compensation on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; + hdsi->Instance->WPCR[1U] |= Value << 8U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_HS_DELAY: + if (Lane == DSI_CLOCK_LANE) + { + /* High-Speed Transmission Delay on Clock Lane */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; + hdsi->Instance->WPCR[1U] |= Value; + } + else if (Lane == DSI_DATA_LANES) + { + /* High-Speed Transmission Delay on Data Lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; + hdsi->Instance->WPCR[1U] |= Value << 2U; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Low-Power Reception Filter Tuning + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Low-Power RX low-pass Filtering Tuning */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; + hdsi->Instance->WPCR[1U] |= Frequency << 25U; + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Activate an additional current path on all lanes to meet the SDDTx parameter + * defined in the MIPI D-PHY specification + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Activate/Disactivate additional current path on all lanes */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Custom lane pins configuration + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param CustomLane Function to be applyed on selected lane. + * This parameter can be any value of @ref DSI_CustomLane + * @param Lane select between clock or data lane 0 or data lane 1. + * This parameter can be any value of @ref DSI_Lane_Select + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, + FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); + assert_param(IS_DSI_LANE(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch (CustomLane) + { + case DSI_SWAP_LANE_PINS: + if (Lane == DSI_CLK_LANE) + { + /* Swap pins on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); + } + else if (Lane == DSI_DATA_LANE0) + { + /* Swap pins on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); + } + else if (Lane == DSI_DATA_LANE1) + { + /* Swap pins on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + case DSI_INVERT_HS_SIGNAL: + if (Lane == DSI_CLK_LANE) + { + /* Invert HS signal on clock lane */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); + } + else if (Lane == DSI_DATA_LANE0) + { + /* Invert HS signal on data lane 0 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); + } + else if (Lane == DSI_DATA_LANE1) + { + /* Invert HS signal on data lane 1 */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Set custom timing for the PHY + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Timing PHY timing to be adjusted. + * This parameter can be any value of @ref DSI_PHY_Timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_PHY_TIMING(Timing)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + switch (Timing) + { + case DSI_TCLK_POST: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; + hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; + } + + break; + case DSI_TLPX_CLK: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; + hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; + } + + break; + case DSI_THS_EXIT: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; + hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; + } + + break; + case DSI_TLPX_DATA: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; + hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; + } + + break; + case DSI_THS_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; + hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; + } + + break; + case DSI_THS_TRAIL: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; + hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; + } + + break; + case DSI_THS_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; + hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; + } + + break; + case DSI_TCLK_ZERO: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; + hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; + } + + break; + case DSI_TCLK_PREPARE: + /* Enable/Disable custom timing setting */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); + + if (State != DISABLE) + { + /* Set custom value */ + hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; + hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; + } + + break; + default: + break; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force the Clock/Data Lane in TX Stop Mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param Lane select between clock or data lanes. + * This parameter can be any value of @ref DSI_Lane_Group + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_DSI_LANE_GROUP(Lane)); + assert_param(IS_FUNCTIONAL_STATE(State)); + + if (Lane == DSI_CLOCK_LANE) + { + /* Force/Unforce the Clock Lane in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); + } + else if (Lane == DSI_DATA_LANES) + { + /* Force/Unforce the Data Lanes in TX Stop Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force LP Receiver in Low-Power Mode + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force/Unforce LP Receiver in Low-Power Mode */ + hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; + hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Force Data Lanes in RX Mode after a BTA + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Force Data Lanes in RX Mode */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Enable a pull-down on the lanes to prevent from floating states when unused + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Enable/Disable pull-down on lanes */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @brief Switch off the contention detection on data lanes + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @param State ENABLE or DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) +{ + /* Process locked */ + __HAL_LOCK(hdsi); + + /* Check function parameters */ + assert_param(IS_FUNCTIONAL_STATE(State)); + + /* Contention Detection on Data Lanes OFF */ + hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; + hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); + + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DSI state. + (+) Get error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DSI state + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval HAL state + */ +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +{ + return hdsi->State; +} + +/** + * @brief Return the DSI error code + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains + * the configuration information for the DSI. + * @retval DSI Error Code + */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +{ + /* Get the error code */ + return hdsi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DSI */ + +#endif /* HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c new file mode 100644 index 0000000..246f456 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file stm32F7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + /* No Trigger selected */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c new file mode 100644 index 0000000..27fa98c --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c @@ -0,0 +1,817 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) Any attempt to read the Flash memory while it is being written or erased, causes the + bus to stall. Read operations are processed correctly once the program operation has + completed. This means that code or data fetches cannot be performed while a write/erase + operation is ongoing. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp = 0; + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0) + { + temp = pFlash.Sector; + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(temp); + + /* Increment sector number */ + temp = ++pFlash.Sector; + FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called.*/ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = temp = 0xFFFFFFFFU; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(temp); + /* Sector Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + break; + } + + case FLASH_PROC_MASSERASE : + { + /* MassErase ended. Return the selected bank : in this product we don't have Banks */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + /* MAss Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + + case FLASH_PROC_PROGRAM : + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + /* Programming procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + default : + break; + } + } + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + break; + } + case FLASH_PROC_MASSERASE : + { + /* No return in case of Mass Erase */ + temp = 0; + break; + } + case FLASH_PROC_PROGRAM : + { + /*return the faulty address*/ + temp = pFlash.Address; + break; + } + default : + break; + } + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + + /*Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be: + * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag + * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If there is an error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program the double-word */ + *(__IO uint32_t*)Address = (uint32_t)Data; + *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); + +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; + } + +#if defined (FLASH_OPTCR2_PCROP) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c new file mode 100644 index 0000000..33314d4 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c @@ -0,0 +1,1122 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Dual boot mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define SECTOR_MASK 0xFFFFFF07U +#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); +static uint32_t FLASH_OB_GetUser(void); +static uint32_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetBOR(void); +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); + +#if defined (FLASH_OPTCR_nDBANK) +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); +#else +static void FLASH_MassErase(uint8_t VoltageRange); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR2_PCROP) +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); +static uint32_t FLASH_OB_GetPCROP(void); +static uint32_t FLASH_OB_GetPCROPRDP(void); +#endif /* FLASH_OPTCR2_PCROP */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFF means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { +#if defined (FLASH_OPTCR_nDBANK) + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); +#else + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); +#endif /* FLASH_OPTCR_nDBANK */ + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Boot 0 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); + } + + /* Boot 1 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); + } + +#if defined (FLASH_OPTCR2_PCROP) + /* PCROP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); + } + + /* PCROP_RDP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) + { + status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + + /*Get WRP*/ + pOBInit->WRPSector = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + + /*Get Boot Address when Boot pin = 0 */ + pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); + + /*Get Boot Address when Boot pin = 1 */ + pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); + +#if defined (FLASH_OPTCR2_PCROP) + /*Get PCROP Sectors */ + pOBInit->PCROPSector = FLASH_OB_GetPCROP(); + + /*Get PCROP_RDP Value */ + pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); +#endif /* FLASH_OPTCR2_PCROP */ +} +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + else + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @param NDBank Flash Single Bank mode enabled. + * This parameter can be one of the following values: + * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) + * @param NDBoot Flash Dual boot mode disable. + * This parameter can be one of the following values: + * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + assert_param(IS_OB_NDBANK(NDBank)); + assert_param(IS_OB_NDBOOT(NDBoot)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); +} +#else + +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); +} +#endif /* FLASH_OPTCR_nDBANK */ + +/** + * @brief Enable the write protection of the desired bank1 or bank2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM7 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_SECTOR_All + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Write protection enabled on sectors */ + FLASH->OPTCR &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_Sector_All + * + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write protection disabled on sectors */ + FLASH->OPTCR |= (WRPSector); + } + + return status; +} + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); + + return HAL_OK; + +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * @param Address specifies Boot base address + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); + } + else + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); + } + } + + return status; +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FlagStatus FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) + { + readstatus = OB_RDP_LEVEL_0; + } + else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) + { + readstatus = OB_RDP_LEVEL_2; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint32_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return ((uint32_t)(FLASH->OPTCR & 0x0C)); +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * + * @retval uint32_t Boot Base Address: + * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + */ +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) +{ + uint32_t Address = 0; + + /* Return the Boot base Address */ + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; + } + else + { + Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); + } + + return Address; +} + +#if defined (FLASH_OPTCR2_PCROP) +/** + * @brief Set the PCROP protection for sectors. + * @param PCROPSector specifies the sector(s) to be PCROP protected. + * This parameter can be one of the following values: + * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 + * @arg OB_PCROP_SECTOR_ALL + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SECTOR(PCROPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector); + } + + return status; +} + +/** + * @brief Set the PCROP_RDP value + * @param Pcrop_Rdp specifies the PCROP_RDP bit value. + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp); + } + + return status; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @retval uint32_t FLASH PCROP Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP)); +} + +/** + * @brief Return the FLASH PCROP_RDP option byte value. + * @retval uint32_t FLASH PCROP_RDP option byte value + */ +static uint32_t FLASH_OB_GetPCROPRDP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP)); +} +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c new file mode 100644 index 0000000..0afa1df --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c @@ -0,0 +1,532 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE ((uint32_t)0x00000003U) +#define EXTI_MODE ((uint32_t)0x10000000U) +#define GPIO_MODE_IT ((uint32_t)0x00010000U) +#define GPIO_MODE_EVT ((uint32_t)0x00020000U) +#define RISING_EDGE ((uint32_t)0x00100000U) +#define FALLING_EDGE ((uint32_t)0x00200000U) +#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U) + +#define GPIO_NUMBER ((uint32_t)16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + temp |= (GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + temp |= ((GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~tmp; + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != 0X00u) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKR register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c new file mode 100644 index 0000000..ef049ec --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -0,0 +1,6522 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() + or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() + or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SlaveAddr_SHIFT 7U +#define SlaveAddr_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (0x00000001U) +#define I2C_XFER_RX_IT (0x00000002U) +#define I2C_XFER_LISTEN_IT (0x00000004U) + +#define I2C_XFER_ERROR_IT (0x00000011U) +#define I2C_XFER_CPLT_IT (0x00000012U) +#define I2C_XFER_RELOAD_IT (0x00000012U) + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_ERROR; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount < MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** +* @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. +* @retval I2C Error Code +*/ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Datas have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on goind, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tmpoptions = hi2c->XferOptions; + + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + if (hi2c->hdmatx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Reset AbortCpltCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c new file mode 100644 index 0000000..1bde438 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to: + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +#endif +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c new file mode 100644 index 0000000..de8103f --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c @@ -0,0 +1,2142 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Program the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, + the pixel clock polarity, Data Enable polarity and the LTDC background color value + using HAL_LTDC_Init() function + + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_LTDC_RegisterCallback() to register a callback. + + Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit + or HAL_LTDC_Init function. + + When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +#ifdef HAL_LTDC_MODULE_ENABLED +#if defined (LTDC) +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp, tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16U); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16U); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16U); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } + /* DeInit the low level hardware */ + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callabck is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* FIFO underrun Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Line Interrupt management ************************************************/ + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ + HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Register reload Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ + HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t counter; + uint32_t *pcolorlut = pCLUT; + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for (counter = 0U; (counter < CLUTSize); counter++) + { + if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + else + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + + pcolorlut++; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval LTDC Error Code + */ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* LTDC */ +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c new file mode 100644 index 0000000..dc946af --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c @@ -0,0 +1,149 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +#if defined (LTDC) && defined (DSI) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c new file mode 100644 index 0000000..51c4468 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c @@ -0,0 +1,599 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK ((uint32_t)0x00003F00) +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There are up to 6 Wake-up pin in the STM32F7 devices family + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + -@@- The Regulator parameter is not used for the STM32F7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which sets the default polarity: + * detection on high level (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly states the enabled pin and + * the chosen polarity + * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 + * @arg PWR_WAKEUP_PIN4 + * @arg PWR_WAKEUP_PIN5 + * @arg PWR_WAKEUP_PIN6 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CSR2, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F7 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Ensure that all instructions done before entering SLEEP mode */ + __DSB(); + __ISB(); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode ---------------------------------*/ + tmpreg = PWR->CR1; + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); + + /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Ensure that all instructions done before entering STOP mode */ + __DSB(); + __ISB(); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pins if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + PWR->CR1 |= PWR_CR1_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c new file mode 100644 index 0000000..6ff3321 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c @@ -0,0 +1,554 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_BKPREG_TIMEOUT_VALUE 1000 +#define PWR_VOSRDY_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) In Run mode: the main regulator has 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) In Stop mode: the main regulator or low power regulator supplies a low power + voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Enable Backup regulator */ + PWR->CSR1 |= PWR_CSR1_BRE; + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Disable Backup regulator */ + PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + /* Enable the Flash Power Down */ + PWR->CR1 |= PWR_CR1_FPDS; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + /* Disable the Flash Power Down */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); +} + +/** + * @brief Enables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + /* Enable Main regulator low voltage */ + PWR->CR1 |= PWR_CR1_MRUDS; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + /* Disable Main regulator low voltage */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + /* Enable low power regulator */ + PWR->CR1 |= PWR_CR1_LPUDS; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + /* Disable low power regulator */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); +} + +/** + * @brief Activates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tempreg = 0; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for UnderDrive mode is ready */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Select the regulator state in STOP mode ---------------------------------*/ + tempreg = PWR->CR1; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tempreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tempreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +/** + * @brief Returns Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or + * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * typical output voltage at 1.4 V, + * system frequency up to 216 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * typical output voltage at 1.2 V, + * system frequency up to 180 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, + * typical output voltage at 1.00 V, + * system frequency up to 151 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0; + + assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c new file mode 100644 index 0000000..d63a6f4 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -0,0 +1,1242 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== +##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 216 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clock is automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M7 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + macros to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; + + /* Reset PLLI2SCFGR register to default value */ + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; + + /* Reset PLLSAICFGR register to default value */ + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + FlagStatus pwrclkchanged = RESET; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0, pllvco = 0, pllp = 0; + uint32_t sysclockfreq = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + + sysclockfreq = pllvco / pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +#if defined (RCC_PLLCFGR_PLLR) + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); +#endif +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c new file mode 100644 index 0000000..c1cbbd2 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -0,0 +1,1776 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Defines RCCEx Private Defines + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +/** + * @} + */ + + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register will be set to their reset values. + +@endverbatim + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ + defined (STM32F750xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t tmpreg1 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + plli2sused = 1; + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + pllsaiused = 1; + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; +#else + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the I2C4 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CEC clock configuration -----------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the DFSDM clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg = 0; + /* This variable is used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0; + /* This variable is used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0; + /* This variable is used to store the SAI clock source */ + uint32_t saiclocksource = 0; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI1 */ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + return frequency; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c new file mode 100644 index 0000000..5364bfb --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c @@ -0,0 +1,1850 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) peripheral: + * + Initialization and de-initialization functions + * + RTC Time and Date functions + * + RTC Alarm functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### Backup Domain Operating Condition ##### + ============================================================================== + [..] The real-time clock (RTC), the RTC backup registers, and the backup + SRAM (BKP SRAM) can be powered from the VBAT voltage when the main + VDD supply is powered off. + To retain the content of the RTC backup registers, backup SRAM, and supply + the RTC when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + [..] To allow the RTC operating even when the main digital supply (VDD) is turned + off, the VBAT pin powers the following blocks: + (#) The RTC + (#) The LSE oscillator + (#) The backup SRAM when the low power backup regulator is enabled + (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) + + [..] When the backup domain is supplied by VDD (analog switch connected to VDD), + the following pins are available: + (#) PC14 and PC15 can be used as either GPIO or LSE pins + (#) PC13 can be used as a GPIO or as the RTC_AF1 pin + (#) PI8 can be used as a GPIO or as the RTC_AF2 pin + + [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT + because VDD is not present), the following pins are available: + (#) PC14 and PC15 can be used as LSE pins only + (#) PC13 can be used as the RTC_AF1 pin + (#) PI8 can be used as the RTC_AF2 pin + (#) PC1 can be used as the RTC_AF3 pin + + ##### Backup Domain Reset ##### + ================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. The BKPSRAM is not affected by this reset. The only + way to reset the BKPSRAM is through the Flash interface by requesting + a protection level change from 1 to 0. + [..] A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + + ##### How to use this driver ##### + ================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wake-up mode), by using the RTC alarm + or the RTC wake-up events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wake-up from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() + or @ref HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + @endverbatim + + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wake-up from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + /* Check the RTC peripheral state */ + if(hrtc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); + assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + + if(hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if(hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE; + hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; + } +} + +/** + * @brief DeInitializes the RTC peripheral + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This function doesn't reset the RTC Backup Data registers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + hrtc->Instance->TR = (uint32_t)0x00000000; + hrtc->Instance->DR = (uint32_t)0x00002101; + /* Reset All CR bits except CR[2:0] */ + hrtc->Instance->CR &= (uint32_t)0x00000007; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till WUTWF flag is set and if Time out is reached exit */ + while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Reset all RTC CR register bits */ + hrtc->Instance->CR &= (uint32_t)0x00000000; + hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; + hrtc->Instance->PRER = (uint32_t)0x007F00FF; + hrtc->Instance->ALRMAR = (uint32_t)0x00000000; + hrtc->Instance->ALRMBR = (uint32_t)0x00000000; + hrtc->Instance->SHIFTR = (uint32_t)0x00000000; + hrtc->Instance->CALR = (uint32_t)0x00000000; + hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; + hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + hrtc->Instance->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + hrtc->Instance->TAMPCR = 0x00000000; + + /* Reset Option register */ + hrtc->Instance->OR = 0x00000000; + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if(hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + hrtc->State = HAL_RTC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hrtc); + + if(HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callabck is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrtc); + + if(HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the RTC MSP. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup RTC_Group2 RTC Time and Date functions + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Sets RTC current time. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTime Pointer to Time structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == RTC_FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + (((uint32_t)sTime->TimeFormat) << 16)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ + ((uint32_t)(sTime->Minutes) << 8) | \ + ((uint32_t)sTime->Seconds) | \ + ((uint32_t)(sTime->TimeFormat) << 16)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_TR register */ + hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + /* Clear the bits to be configured */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current time. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get subseconds values from the correspondent registers*/ + sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + + /* Get SecondFraction structure field from the corresponding register field*/ + sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); + + /* Get the TR register */ + tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); + sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); + + /* Check the input parameters format */ + if(Format == RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + + return HAL_OK; +} + +/** + * @brief Sets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate Pointer to date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if(Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + ((uint32_t)sDate->WeekDay << 13)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ + (((uint32_t)sDate->Month) << 8) | \ + ((uint32_t)sDate->Date) | \ + (((uint32_t)sDate->WeekDay) << 13)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + /* Set the RTC_DR register */ + hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY ; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; + } +} + +/** + * @brief Gets RTC current date. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sDate Pointer to Date structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + if(Format == RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Group3 RTC Alarm functions + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Sets the specified RTC Alarm. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tickstart = 0; + uint32_t tmpreg = 0, subsecondtmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == RTC_FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets the specified RTC Alarm with Interrupt + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm Pointer to Alarm structure + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg FORMAT_BIN: Binary data format + * @arg FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(Format == RTC_FORMAT_BIN) + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + + if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + do + { + if (count-- == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + do + { + if (count-- == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + + EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + if(Alarm == RTC_ALARM_A) + { + /* AlarmA */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + else + { + /* AlarmB */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC Alarm value and masks. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +{ + uint32_t tmpreg = 0, subsecondtmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + if(Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); + } + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + + if(Format == RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +/** + * @brief This function handles Alarm interrupt request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +{ + /* Get the AlarmA interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET) + { + /* Get the pending status of the AlarmA Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + { + /* AlarmA callback */ + #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); + #else + HAL_RTC_AlarmAEventCallback(hrtc); + #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the AlarmA interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + } + } + + /* Get the AlarmB interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET) + { + /* Get the pending status of the AlarmB Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET) + { + /* AlarmB callback */ + #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmBEventCallback(hrtc); + #else + HAL_RTCEx_AlarmBEventCallback(hrtc); + #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the AlarmB interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Alarm A callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmA Polling request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Group4 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wake-up from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTC_Group5 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) +{ + return hrtc->State; +} + +/** + * @} + */ + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +{ + uint32_t tickstart = 0; + + /* Check if the Initialization mode is set */ + if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + /* Set the Initialization mode */ + hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcdhigh = 0; + + while(Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Converts from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c new file mode 100644 index 0000000..f0cdff5 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c @@ -0,0 +1,1875 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_rtc_ex.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extension peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extension Control functions + * + Extension RTC features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer in interrupt mode + using the HAL_RTC_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() + function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Enables the RTC TimeStamp using the HAL_RTC_SetTimeStamp() function. + You can also configure the RTC TimeStamp with interrupt mode using the + HAL_RTC_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp() + function. + + *** Internal TimeStamp configuration *** + =============================== + [..] + (+) Enables the RTC internal TimeStamp using the HAL_RTC_SetInternalTimeStamp() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTC_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTC_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the RTC_TAMPCR register. + + *** Backup Data Registers configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite() + function. + (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead() + function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + + +/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg|= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; + hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets TimeStamp with Interrupt. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note This API must be called before enabling the TimeStamp feature. + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + tmpreg |= TimeStampEdge; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; + hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); + + /* Clear RTC Timestamp flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); + + /* Enable IT timestamp */ + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates TimeStamp. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + uint32_t tmpreg = 0U; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); + + /* Get the RTC_CR register and clear the bits to be configured */ + tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Configure the Time Stamp TSEDGE and Enable bits */ + hrtc->Instance->CR = (uint32_t)tmpreg; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Internal TimeStamp. + * @note This API must be called before enabling the internal TimeStamp feature. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates internal TimeStamp. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the internal Time Stamp Enable bits */ + __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets the RTC TimeStamp value. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * FORMAT_BIN: Binary data format + * FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime = 0U, tmpdate = 0U; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); + tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); + sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); + sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); + + /* Check the input parameters format */ + if(Format == RTC_FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Clear the TIMESTAMP Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + return HAL_OK; +} + +/** + * @brief Sets Tamper + * @note By calling this API we disable the tamper interrupt for all tampers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); + } + + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } + } + + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0U) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0U) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } + if((sTamper->Tamper & RTC_TAMPER_3) != 0U) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ + (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ + (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ + (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\ + (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ + (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF); + + hrtc->Instance->TAMPCR |= tmpreg; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets Tamper with interrupt. + * @note By calling this API we force the tamper interrupt for all tampers. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param sTamper Pointer to RTC Tamper. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the tamper trigger */ + if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + { + sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); + } + + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } + } + + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + sTamper->MaskFlag = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } + } + + tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ + (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ + (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ + (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE |\ + (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ + (uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF); + + hrtc->Instance->TAMPCR |= tmpreg; + + if(sTamper->Tamper == RTC_TAMPER_1) + { + /* Clear RTC Tamper 1 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + } + else if(sTamper->Tamper == RTC_TAMPER_2) + { + /* Clear RTC Tamper 2 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + else + { + /* Clear RTC Tamper 3 flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + + /* RTC Tamper Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + + EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates Tamper. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Tamper Selected tamper pin. + * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + +/* Disable the selected Tamper pin */ + hrtc->Instance->TAMPCR &= (uint32_t)~Tamper; + + if ((Tamper & RTC_TAMPER_1) != 0) + { + /* Disable the Tamper1 interrupt */ + hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1); + } + if ((Tamper & RTC_TAMPER_2) != 0) + { + /* Disable the Tamper2 interrupt */ + hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2); + } + if ((Tamper & RTC_TAMPER_3) != 0) + { + /* Disable the Tamper2 interrupt */ + hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3); + } + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief This function handles TimeStamp interrupt request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the TimeStamp interrupt source enable status */ + if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET) + { + /* Get the pending status of the TIMESTAMP Interrupt */ + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET) + { + /* TIMESTAMP callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the TIMESTAMP interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + } + } + + /* Get the Tamper1 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != (uint32_t)RESET) + { + /* Get the pending status of the Tamper1 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) + { + /* Tamper callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper1EventCallback(hrtc); +#else + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + } + } + + /* Get the Tamper2 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != (uint32_t)RESET) + { + /* Get the pending status of the Tamper2 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET) + { + /* Tamper callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper2EventCallback(hrtc); +#else + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + } + + /* Get the Tamper3 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != (uint32_t)RESET) + { + /* Get the pending status of the Tamper3 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != (uint32_t)RESET) + { + /* Tamper callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->Tamper3EventCallback(hrtc); +#else + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + } + + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 1 callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 2 callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles TimeStamp polling request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + { + /* Clear the TIMESTAMP OverRun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper1 Polling. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper2 Polling. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles Tamper3 Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RTCEx_Group2 RTC Wake-up functions + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Sets wake up timer. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + { + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Sets wake up timer with interrupt + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + __IO uint32_t count; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Check RTC WUTWF flag is reset only when wake up timer enabled */ + if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + { + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + do + { + if(count-- == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET); + } + + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + do + { + if(count-- == 0U) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET); + + /* Configure the Wake-up Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + + EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + + /* Clear RTC Wake Up timer Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates wake up timer counter. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart = 0U; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Gets wake up timer counter. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + /* Get the counter value */ + return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); +} + +/** + * @brief This function handles Wake Up Timer interrupt request. + * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper + * interrupt line (shared by timestamp and tampers) wakeup timer + * interrupt line is exclusive to the wakeup timer. + * There is no need in this case to check on the interrupt enable + * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(). + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the WAKEUPTIMER Interrupt */ + if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET) + { + /* WAKEUPTIMER callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + } + + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles Wake Up Timer Polling. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup RTCEx_Group3 Extension Peripheral Control functions + * @brief Extension Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extension Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param BackupRegister RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @brief Sets the Smooth calibration parameters. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmouthCalibMinusPulsesValue must be equal to 0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* check if a calibration is pending*/ + if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* check if a calibration is pending*/ + while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + } + + /* Configure the Smooth calibration settings */ + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed*/ + while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + + /* Check if the reference clock detection is disabled */ + if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Clear flags before config */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)CalibOutput; + + __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enables the RTC reference clock detection. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Enables the Bypass Shadow feature. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disables the Bypass Shadow feature. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Reset the BYPSHAD bit */ + hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @} + */ + + /** @defgroup RTCEx_Group4 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alram B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief This function handles AlarmB Polling request. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } + + /* Clear the Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c new file mode 100644 index 0000000..5880109 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c @@ -0,0 +1,1105 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_sdram.c + * @author MCD Application Team + * @brief SDRAM HAL module driver. + * This file provides a generic firmware to drive SDRAM memories mounted + * as external device. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. + The following sequence should be followed to configure the FMC to interface + with SDRAM memories: + + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: + SDRAM_HandleTypeDef hdsram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: + FMC_SDRAM_TimingTypeDef Timing; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() + (##) Control register configuration using the FMC SDRAM interface function + FMC_SDRAM_Init() + (##) Timing register configuration using the FMC SDRAM interface function + FMC_SDRAM_Timing_Init() + (##) Program the SDRAM external device by applying its initialization sequence + according to the device plugged in your hardware. This step is mandatory + for accessing the SDRAM device. + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the SDRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access + (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + + (#) You can continuously monitor the SDRAM device HAL state by calling the function + HAL_SDRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init + and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit + or @ref HAL_SDRAM_Init function. + + When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SDRAM SDRAM + * @brief SDRAM driver modules + * @{ + */ +#ifdef HAL_SDRAM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SDRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if(hsdram == NULL) + { + return HAL_ERROR; + } + + if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if(hsdram->MspInitCallback == NULL) + { + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + } + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); +#endif + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if(hsdram->MspDeInitCallback == NULL) + { + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdram->MspDeInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspDeInit(hsdram); +#endif + + /* Configure the SDRAM registers with their reset values */ + FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief SDRAM MSP Init. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SDRAM MSP DeInit. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function handles SDRAM refresh error interrupt request. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status +*/ +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) +{ + /* Check SDRAM interrupt Rising edge flag */ + if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + { + /* SDRAM refresh error interrupt callback */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->RefreshErrorCallback(hsdram); +#else + HAL_SDRAM_RefreshErrorCallback(hsdram); +#endif + + /* Clear SDRAM refresh error interrupt pending bit */ + __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); + } +} + +/** + * @brief SDRAM Refresh error callback. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SDRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint8_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + + +/** + * @brief Writes 8-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + + +/** + * @brief Reads 16-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint16_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes 16-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Reads 32-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint32_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes 32-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(tmp == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SDRAM Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} +/** + * @brief Unregister a User SDRAM Callback + * SDRAM Callback is redirected to the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} + +/** + * @brief Register a User SDRAM Callback for DMA transfers + * To be used instead of the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} +#endif + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + + return HAL_OK; +} + +/** + * @brief Disables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Sends Command to the SDRAM bank. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Command SDRAM command structure + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if(Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Programs the SDRAM Memory Refresh rate. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param AutoRefreshNumber The SDRAM auto Refresh number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Returns the SDRAM memory current mode. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval The SDRAM memory mode. + */ +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) +{ + /* Return the SDRAM memory current mode */ + return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SDRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SDRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SDRAM state. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL state + */ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +{ + return hsdram->State; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c new file mode 100644 index 0000000..65a9357 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c @@ -0,0 +1,4273 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); +#if (USE_SPI_CRC != 0U) + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + hspi->Instance->CR1 |= SPI_CR1_CRCL; + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | + hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; + hspi->TxXferCount--; + } + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Read CRC to Flush DR and RXNE flag */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); + } + else + { + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + uint32_t spi_cr1; + uint32_t spi_cr2; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read CRC */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); + } + else + { + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + } + } + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + /* Packing mode is enabled only if the DMA setting is HALWORD */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Check the even/odd of the data size + crc if enabled */ + if ((hspi->TxXferCount & 0x1U) == 0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + + /* The packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if ((hspi->TxXferSize & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count, resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count, resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Read 16bit CRC */ + READ_REG(hspi->Instance->DR); + } + else + { + /* Read 8bit CRC */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + } + else + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + READ_REG(hspi->Instance->DR); + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in packing mode */ + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + /* Receive data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Regsiter */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + hspi->CRCSize--; + + /* Check end of the reception */ + if (hspi->CRCSize == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in packing Bit mode */ + if (hspi->TxXferCount >= 2U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + /* Transmit data in 8 Bit mode */ + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Regsiter */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 8bit CRC to flush Data Register */ + READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + + hspi->CRCSize--; + + if (hspi->CRCSize == 0U) + { + SPI_CloseRx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Read 16bit CRC to flush Data Register */ + READ_REG(hspi->Instance->DR); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Read 8bit CRC to flush Data Register */ + READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Check TXEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } + while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c new file mode 100644 index 0000000..c4bdc97 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPIEx_Private_Constants SPIEx Private Constants + * @{ + */ +#define SPI_FIFO_SIZE 4UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) Rx data flush function: + (++) HAL_SPIEx_FlushRxFifo() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg; + uint8_t count = 0U; + while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + { + count++; + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + if (count == SPI_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c new file mode 100644 index 0000000..29de7d5 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -0,0 +1,6901 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, + uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture/compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + { + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + if (HAL_OK == status) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The ouput configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c new file mode 100644 index 0000000..f2d976a --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c @@ -0,0 +1,2154 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if (((uint32_t)pData == 0U) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } +#else + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +#endif /* DFSDM1_Channel0 */ + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = 0; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = 9; + break; + } + + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = 8; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous + * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c new file mode 100644 index 0000000..25a901f --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c @@ -0,0 +1,3618 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + +#if defined(USART_CR1_UESM) + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#endif /* USART_CR1_UESM */ + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() +#if defined(USART_CR1_UESM) + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() +#endif + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + __HAL_LOCK(huart); + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ +#if defined(USART_CR1_UESM) + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +#endif /* USART_CR1_UESM */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +#if defined(USART_CR1_UESM) +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_UESM) + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#endif /* USART_CR1_UESM */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv = 0x00000000U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + tmpreg |= huart->Init.OneBitSampling; + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + break; + case UART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#if defined(USART_ISR_REACK) + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#endif + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Handle UART Communication Timeout. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c new file mode 100644 index 0000000..fcbcf4f --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c @@ -0,0 +1,485 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +#if defined(USART_CR1_UESM) +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode + (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. +#if defined(USART_CR1_UESM) + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality +#endif + +@endverbatim + * @{ + */ + +#if defined(USART_CR3_UCESM) +/** + * @brief Keep UART Clock enabled when in Stop Mode. + * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled + * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UCESM bit */ + SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Clock when in Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UCESM bit */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR3_UCESM */ +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +#if defined(USART_CR1_UESM) +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ +#if defined(USART_CR1_UESM) + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} +#endif /* USART_CR1_UESM */ + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c new file mode 100644 index 0000000..b50df92 --- /dev/null +++ b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c @@ -0,0 +1,1082 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_fmc.c + * @author MCD Application Team + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes three memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Get the BTCR register value */ + tmpr = Device->BTCR[Init->NSBank]; + + /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, + WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ + tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ + FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ + FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \ + FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ + FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS)); + + /* Set NORSRAM device control parameters */ + tmpr |= (uint32_t)(Init->DataAddressMux |\ + Init->MemoryType |\ + Init->MemoryDataWidth |\ + Init->BurstAccessMode |\ + Init->WaitSignalPolarity |\ + Init->WaitSignalActive |\ + Init->WriteOperation |\ + Init->WaitSignal |\ + Init->ExtendedMode |\ + Init->AsynchronousWait |\ + Init->WriteBurst |\ + Init->ContinuousClock |\ + Init->PageSize |\ + Init->WriteFifo); + + if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + + Device->BTCR[Init->NSBank] = tmpr; + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); + } + if(Init->NSBank != FMC_NORSRAM_BANK1) + { + Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + } + + return HAL_OK; +} + + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if(Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DB; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2; + } + + Device->BTCR[Bank + 1] = 0x0FFFFFFF; + ExDevice->BWTR[Bank] = 0x0FFFFFFF; + + return HAL_OK; +} + + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Get the BTCR register value */ + tmpr = Device->BTCR[Bank + 1]; + + /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ + tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ + FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ + FMC_BTR1_ACCMOD)); + + /* Set FMC_NORSRAM device timing parameters */ + tmpr |= (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << 4) |\ + ((Timing->DataSetupTime) << 8) |\ + ((Timing->BusTurnAroundDuration) << 16) |\ + (((Timing->CLKDivision)-1) << 20) |\ + (((Timing->DataLatency)-2) << 24) |\ + (Timing->AccessMode) + ); + + Device->BTCR[Bank + 1] = tmpr; + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); + tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); + Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Get the BWTR register value */ + tmpr = Device->BWTR[Bank]; + + /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ + tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ + FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); + + tmpr |= (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << 4) |\ + ((Timing->DataSetupTime) << 8) |\ + ((Timing->BusTurnAroundDuration) << 16) |\ + (Timing->AccessMode)); + + Device->BWTR[Bank] = tmpr; + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFF; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PCR; + + /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ + tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ + FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)); + /* Set NAND device control parameters */ + tmpr |= (uint32_t)(Init->Waitfeature |\ + FMC_PCR_MEMORY_TYPE_NAND |\ + Init->MemoryDataWidth |\ + Init->EccComputation |\ + Init->ECCPageSize |\ + ((Init->TCLRSetupTime) << 9) |\ + ((Init->TARSetupTime) << 13)); + + /* NAND bank 3 registers configuration */ + Device->PCR = tmpr; + + return HAL_OK; + +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PMEM; + + /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ + tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \ + FMC_PMEM_MEMHIZ3)); + /* Set FMC_NAND device timing parameters */ + tmpr |= (uint32_t)(Timing->SetupTime |\ + ((Timing->WaitSetupTime) << 8) |\ + ((Timing->HoldSetupTime) << 16) |\ + ((Timing->HiZSetupTime) << 24) + ); + + /* NAND bank 3 registers configuration */ + Device->PMEM = tmpr; + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PATT; + + /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ + tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \ + FMC_PATT_ATTHIZ3)); + /* Set FMC_NAND device timing parameters */ + tmpr |= (uint32_t)(Timing->SetupTime |\ + ((Timing->WaitSetupTime) << 8) |\ + ((Timing->HoldSetupTime) << 16) |\ + ((Timing->HiZSetupTime) << 24)); + + /* NAND bank 3 registers configuration */ + Device->PATT = tmpr; + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + Device->PCR = 0x00000018U; + Device->SR = 0x00000040U; + Device->PMEM = 0xFCFCFCFCU; + Device->PATT = 0xFCFCFCFCU; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FMC_NAND_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + Device->PCR |= FMC_PCR_ECCEN; + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + Device->PCR &= ~FMC_PCR_ECCEN; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection |\ + Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay + ); + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay); + + tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection); + + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; + } + + return HAL_OK; +} + + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RPDelay)-1) << 20) |\ + (((Timing->RCDDelay)-1) << 24)); + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TRC and TRP bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); + + tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->RPDelay)-1) << 20)); + + tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RCDDelay)-1) << 24)); + + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device Pointer to SDRAM device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0; + Device->SDTR[Bank] = 0x0FFFFFFF; + Device->SDCMR = 0x00000000; + Device->SDRTR = 0x00000000; + Device->SDSR = 0x00000000; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param hsdram FMC_SDRAM handle + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + __IO uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + tmpr = (uint32_t)((Command->CommandMode) |\ + (Command->CommandTarget) |\ + (((Command->AutoRefreshNumber)-1) << 5) |\ + ((Command->ModeRegisterDefinition) << 9) + ); + + Device->SDCMR = tmpr; + + return HAL_OK; +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + Device->SDRTR |= (RefreshRate<<1); + + return HAL_OK; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. + * @retval None + */ +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + Device->SDCMR |= (AutoRefreshNumber << 5); + + return HAL_OK; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if(Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/Release_Notes.html b/Fonts/Release_Notes.html new file mode 100644 index 0000000..8c60ce7 --- /dev/null +++ b/Fonts/Release_Notes.html @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + Release Notes for STM32Cube Fonts Utilities Driver + + + + + + + + + +
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Release +Notes for STM32Cube Fonts Utilities Driver

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Copyright +2014 STMicroelectronics

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V1.0.0 / 18-February-2014

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+ + \ No newline at end of file diff --git a/Fonts/font12.c b/Fonts/font12.c new file mode 100644 index 0000000..7d428cd --- /dev/null +++ b/Fonts/font12.c @@ -0,0 +1,1464 @@ +/** + ****************************************************************************** + * @file Font12.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text Font12 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text Font12 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// + +const uint8_t Font12_Table[] = +{ + // @0 ' ' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @12 '!' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @24 '"' (7 pixels wide) + 0x00, // + 0x6C, // ## ## + 0x48, // # # + 0x48, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @36 '#' (7 pixels wide) + 0x00, // + 0x14, // # # + 0x14, // # # + 0x28, // # # + 0x7C, // ##### + 0x28, // # # + 0x7C, // ##### + 0x28, // # # + 0x50, // # # + 0x50, // # # + 0x00, // + 0x00, // + + // @48 '$' (7 pixels wide) + 0x00, // + 0x10, // # + 0x38, // ### + 0x40, // # + 0x40, // # + 0x38, // ### + 0x48, // # # + 0x70, // ### + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @60 '%' (7 pixels wide) + 0x00, // + 0x20, // # + 0x50, // # # + 0x20, // # + 0x0C, // ## + 0x70, // ### + 0x08, // # + 0x14, // # # + 0x08, // # + 0x00, // + 0x00, // + 0x00, // + + // @72 '&' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x20, // # + 0x20, // # + 0x54, // # # # + 0x48, // # # + 0x34, // ## # + 0x00, // + 0x00, // + 0x00, // + + // @84 ''' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @96 '(' (7 pixels wide) + 0x00, // + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x08, // # + 0x00, // + + // @108 ')' (7 pixels wide) + 0x00, // + 0x20, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @120 '*' (7 pixels wide) + 0x00, // + 0x10, // # + 0x7C, // ##### + 0x10, // # + 0x28, // # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @132 '+' (7 pixels wide) + 0x00, // + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0xFE, // ####### + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @144 ',' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x10, // # + 0x30, // ## + 0x20, // # + 0x00, // + + // @156 '-' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @168 '.' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @180 '/' (7 pixels wide) + 0x00, // + 0x04, // # + 0x04, // # + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + 0x00, // + + // @192 '0' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @204 '1' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @216 '2' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x04, // # + 0x08, // # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @228 '3' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x04, // # + 0x18, // ## + 0x04, // # + 0x04, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @240 '4' (7 pixels wide) + 0x00, // + 0x0C, // ## + 0x14, // # # + 0x14, // # # + 0x24, // # # + 0x44, // # # + 0x7E, // ###### + 0x04, // # + 0x0E, // ### + 0x00, // + 0x00, // + 0x00, // + + // @252 '5' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x20, // # + 0x20, // # + 0x38, // ### + 0x04, // # + 0x04, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @264 '6' (7 pixels wide) + 0x00, // + 0x1C, // ### + 0x20, // # + 0x40, // # + 0x78, // #### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @276 '7' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x44, // # # + 0x04, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @288 '8' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @300 '9' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x08, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @312 ':' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @324 ';' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x18, // ## + 0x00, // + 0x00, // + 0x18, // ## + 0x30, // ## + 0x20, // # + 0x00, // + 0x00, // + + // @336 '<' (7 pixels wide) + 0x00, // + 0x00, // + 0x0C, // ## + 0x10, // # + 0x60, // ## + 0x80, // # + 0x60, // ## + 0x10, // # + 0x0C, // ## + 0x00, // + 0x00, // + 0x00, // + + // @348 '=' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x00, // + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @360 '>' (7 pixels wide) + 0x00, // + 0x00, // + 0xC0, // ## + 0x20, // # + 0x18, // ## + 0x04, // # + 0x18, // ## + 0x20, // # + 0xC0, // ## + 0x00, // + 0x00, // + 0x00, // + + // @372 '?' (7 pixels wide) + 0x00, // + 0x00, // + 0x18, // ## + 0x24, // # # + 0x04, // # + 0x08, // # + 0x10, // # + 0x00, // + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @384 '@' (7 pixels wide) + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x4C, // # ## + 0x54, // # # # + 0x54, // # # # + 0x4C, // # ## + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @396 'A' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x28, // # # + 0x28, // # # + 0x28, // # # + 0x7C, // ##### + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @408 'B' (7 pixels wide) + 0x00, // + 0xF8, // ##### + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @420 'C' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x40, // # + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @432 'D' (7 pixels wide) + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + 0x00, // + + // @444 'E' (7 pixels wide) + 0x00, // + 0xFC, // ###### + 0x44, // # # + 0x50, // # # + 0x70, // ### + 0x50, // # # + 0x40, // # + 0x44, // # # + 0xFC, // ###### + 0x00, // + 0x00, // + 0x00, // + + // @456 'F' (7 pixels wide) + 0x00, // + 0x7E, // ###### + 0x22, // # # + 0x28, // # # + 0x38, // ### + 0x28, // # # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @468 'G' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x4E, // # ### + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @480 'H' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x7C, // ##### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @492 'I' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @504 'J' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x08, // # + 0x08, // # + 0x08, // # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @516 'K' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x48, // # # + 0x50, // # # + 0x70, // ### + 0x48, // # # + 0x44, // # # + 0xE6, // ### ## + 0x00, // + 0x00, // + 0x00, // + + // @528 'L' (7 pixels wide) + 0x00, // + 0x70, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x24, // # # + 0x24, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @540 'M' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x6C, // ## ## + 0x6C, // ## ## + 0x54, // # # # + 0x54, // # # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @552 'N' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x64, // ## # + 0x64, // ## # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x4C, // # ## + 0xEC, // ### ## + 0x00, // + 0x00, // + 0x00, // + + // @564 'O' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @576 'P' (7 pixels wide) + 0x00, // + 0x78, // #### + 0x24, // # # + 0x24, // # # + 0x24, // # # + 0x38, // ### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @588 'Q' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x1C, // ### + 0x00, // + 0x00, // + + // @600 'R' (7 pixels wide) + 0x00, // + 0xF8, // ##### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x48, // # # + 0x44, // # # + 0xE2, // ### # + 0x00, // + 0x00, // + 0x00, // + + // @612 'S' (7 pixels wide) + 0x00, // + 0x34, // ## # + 0x4C, // # ## + 0x40, // # + 0x38, // ### + 0x04, // # + 0x04, // # + 0x64, // ## # + 0x58, // # ## + 0x00, // + 0x00, // + 0x00, // + + // @624 'T' (7 pixels wide) + 0x00, // + 0xFE, // ####### + 0x92, // # # # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @636 'U' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @648 'V' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @660 'W' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + + // @672 'X' (7 pixels wide) + 0x00, // + 0xC6, // ## ## + 0x44, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x28, // # # + 0x44, // # # + 0xC6, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @684 'Y' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @696 'Z' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x44, // # # + 0x08, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @708 '[' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x38, // ### + 0x00, // + + // @720 '\' (7 pixels wide) + 0x00, // + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x00, // + 0x00, // + + // @732 ']' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x38, // ### + 0x00, // + + // @744 '^' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x28, // # # + 0x44, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @756 '_' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0xFE, // ####### + + // @768 '`' (7 pixels wide) + 0x00, // + 0x10, // # + 0x08, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @780 'a' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x3C, // #### + 0x44, // # # + 0x44, // # # + 0x3E, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @792 'b' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @804 'c' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @816 'd' (7 pixels wide) + 0x00, // + 0x0C, // ## + 0x04, // # + 0x34, // ## # + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3E, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @828 'e' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x7C, // ##### + 0x40, // # + 0x40, // # + 0x3C, // #### + 0x00, // + 0x00, // + 0x00, // + + // @840 'f' (7 pixels wide) + 0x00, // + 0x1C, // ### + 0x20, // # + 0x7C, // ##### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @852 'g' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x36, // ## ## + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x38, // ### + 0x00, // + + // @864 'h' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @876 'i' (7 pixels wide) + 0x00, // + 0x10, // # + 0x00, // + 0x70, // ### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @888 'j' (7 pixels wide) + 0x00, // + 0x10, // # + 0x00, // + 0x78, // #### + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x70, // ### + 0x00, // + + // @900 'k' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x5C, // # ### + 0x48, // # # + 0x70, // ### + 0x50, // # # + 0x48, // # # + 0xDC, // ## ### + 0x00, // + 0x00, // + 0x00, // + + // @912 'l' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @924 'm' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xE8, // ### # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0xFE, // ####### + 0x00, // + 0x00, // + 0x00, // + + // @936 'n' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @948 'o' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @960 'p' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x40, // # + 0xE0, // ### + 0x00, // + + // @972 'q' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x36, // ## ## + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x0E, // ### + 0x00, // + + // @984 'r' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x6C, // ## ## + 0x30, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @996 's' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x38, // ### + 0x04, // # + 0x44, // # # + 0x78, // #### + 0x00, // + 0x00, // + 0x00, // + + // @1008 't' (7 pixels wide) + 0x00, // + 0x00, // + 0x20, // # + 0x7C, // ##### + 0x20, // # + 0x20, // # + 0x20, // # + 0x22, // # # + 0x1C, // ### + 0x00, // + 0x00, // + 0x00, // + + // @1020 'u' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xCC, // ## ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x4C, // # ## + 0x36, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @1032 'v' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @1044 'w' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + + // @1056 'x' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xCC, // ## ## + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x48, // # # + 0xCC, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @1068 'y' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x24, // # # + 0x28, // # # + 0x18, // ## + 0x10, // # + 0x10, // # + 0x78, // #### + 0x00, // + + // @1080 'z' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x48, // # # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @1092 '{' (7 pixels wide) + 0x00, // + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x00, // + + // @1104 '|' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @1116 '}' (7 pixels wide) + 0x00, // + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x00, // + + // @1128 '~' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x24, // # # + 0x58, // # ## + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // +}; + +sFONT Font12 = { + Font12_Table, + 7, /* Width */ + 12, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/font16.c b/Fonts/font16.c new file mode 100644 index 0000000..3c0e189 --- /dev/null +++ b/Fonts/font16.c @@ -0,0 +1,1844 @@ +/** + ****************************************************************************** + * @file font16.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font16 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font16 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// + +const uint8_t Font16_Table[] = +{ + // @0 ' ' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @32 '!' (11 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @64 '"' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x1D, 0xC0, // ### ### + 0x08, 0x80, // # # + 0x08, 0x80, // # # + 0x08, 0x80, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @96 '#' (11 pixels wide) + 0x00, 0x00, // + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x3F, 0xC0, // ######## + 0x1B, 0x00, // ## ## + 0x3F, 0xC0, // ######## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @128 '$' (11 pixels wide) + 0x04, 0x00, // # + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x38, 0x00, // ### + 0x1E, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @160 '%' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x24, 0x00, // # # + 0x24, 0x00, // # # + 0x18, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x1E, 0x00, // #### + 0x31, 0x80, // ## ## + 0x02, 0x40, // # # + 0x02, 0x40, // # # + 0x01, 0x80, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @192 '&' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x1D, 0x80, // ### ## + 0x37, 0x00, // ## ### + 0x33, 0x00, // ## ## + 0x1D, 0x80, // ### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @224 ''' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @256 '(' (11 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0E, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0E, 0x00, // ### + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @288 ')' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x1C, 0x00, // ### + 0x18, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @320 '*' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x3F, 0xC0, // ######## + 0x0F, 0x00, // #### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @352 '+' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x3F, 0x80, // ####### + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @384 ',' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x0C, 0x00, // ## + 0x08, 0x00, // # + 0x08, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + + // @416 '-' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @448 '.' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @480 '/' (11 pixels wide) + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @512 '0' (11 pixels wide) + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @544 '1' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x3E, 0x00, // ##### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @576 '2' (11 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x19, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @608 '3' (11 pixels wide) + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x61, 0x80, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x61, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @640 '4' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x0F, 0x00, // #### + 0x0B, 0x00, // # ## + 0x1B, 0x00, // ## ## + 0x13, 0x00, // # ## + 0x33, 0x00, // ## ## + 0x3F, 0x80, // ####### + 0x03, 0x00, // ## + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @672 '5' (11 pixels wide) + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1F, 0x00, // ##### + 0x11, 0x80, // # ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x21, 0x80, // # ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @704 '6' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1C, 0x00, // ### + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @736 '7' (11 pixels wide) + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x43, 0x00, // # ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @768 '8' (11 pixels wide) + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @800 '9' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x07, 0x00, // ### + 0x3C, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @832 ':' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @864 ';' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x08, 0x00, // # + 0x08, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @896 '<' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0xC0, // ## + 0x03, 0x00, // ## + 0x04, 0x00, // # + 0x18, 0x00, // ## + 0x60, 0x00, // ## + 0x18, 0x00, // ## + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @928 '=' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @960 '>' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x60, 0x00, // ## + 0x18, 0x00, // ## + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0xC0, // ## + 0x03, 0x00, // ## + 0x04, 0x00, // # + 0x18, 0x00, // ## + 0x60, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @992 '?' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x01, 0x80, // ## + 0x07, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1024 '@' (11 pixels wide) + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x11, 0x00, // # # + 0x21, 0x00, // # # + 0x21, 0x00, // # # + 0x27, 0x00, // # ### + 0x29, 0x00, // # # # + 0x29, 0x00, // # # # + 0x27, 0x00, // # ### + 0x20, 0x00, // # + 0x11, 0x00, // # # + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1056 'A' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x0F, 0x00, // #### + 0x09, 0x00, // # # + 0x19, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x79, 0xE0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1088 'B' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1120 'C' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x40, // ##### # + 0x30, 0xC0, // ## ## + 0x60, 0x40, // ## # + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x60, 0x40, // ## # + 0x30, 0x80, // ## # + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1152 'D' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1184 'E' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x30, 0x80, // ## # + 0x30, 0x80, // ## # + 0x32, 0x00, // ## # + 0x3E, 0x00, // ##### + 0x32, 0x00, // ## # + 0x30, 0x80, // ## # + 0x30, 0x80, // ## # + 0x7F, 0x80, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1216 'F' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x30, 0x40, // ## # + 0x30, 0x40, // ## # + 0x32, 0x00, // ## # + 0x3E, 0x00, // ##### + 0x32, 0x00, // ## # + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1248 'G' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1E, 0x80, // #### # + 0x31, 0x80, // ## ## + 0x60, 0x80, // ## # + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x67, 0xC0, // ## ##### + 0x61, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1280 'H' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x80, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1312 'I' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1344 'J' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x63, 0x00, // ## ## + 0x63, 0x00, // ## ## + 0x63, 0x00, // ## ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1376 'K' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x33, 0x00, // ## ## + 0x36, 0x00, // ## ## + 0x3C, 0x00, // #### + 0x3E, 0x00, // ##### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x79, 0xC0, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1408 'L' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7E, 0x00, // ###### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x40, // ## # + 0x18, 0x40, // ## # + 0x18, 0x40, // ## # + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1440 'M' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0xE0, 0xE0, // ### ### + 0x60, 0xC0, // ## ## + 0x71, 0xC0, // ### ### + 0x7B, 0xC0, // #### #### + 0x6A, 0xC0, // ## # # ## + 0x6E, 0xC0, // ## ### ## + 0x64, 0xC0, // ## # ## + 0x60, 0xC0, // ## ## + 0xFB, 0xE0, // ##### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1472 'N' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x73, 0xC0, // ### #### + 0x31, 0x80, // ## ## + 0x39, 0x80, // ### ## + 0x3D, 0x80, // #### ## + 0x35, 0x80, // ## # ## + 0x37, 0x80, // ## #### + 0x33, 0x80, // ## ### + 0x31, 0x80, // ## ## + 0x79, 0x80, // #### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1504 'O' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1536 'P' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7E, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1568 'Q' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x0C, 0xC0, // ## ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1600 'R' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3E, 0x00, // ##### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7C, 0xE0, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1632 'S' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x38, 0x00, // ### + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1664 'T' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x4C, 0x80, // # ## # + 0x4C, 0x80, // # ## # + 0x4C, 0x80, // # ## # + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1696 'U' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1728 'V' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x0A, 0x00, // # # + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1760 'W' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0xFB, 0xE0, // ##### ##### + 0x60, 0xC0, // ## ## + 0x64, 0xC0, // ## # ## + 0x6E, 0xC0, // ## ### ## + 0x6E, 0xC0, // ## ### ## + 0x2A, 0x80, // # # # # + 0x3B, 0x80, // ### ### + 0x3B, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1792 'X' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1824 'Y' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x79, 0xE0, // #### #### + 0x30, 0xC0, // ## ## + 0x19, 0x80, // ## ## + 0x0F, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1856 'Z' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x21, 0x80, // # ## + 0x23, 0x00, // # ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x0C, 0x00, // ## + 0x18, 0x80, // ## # + 0x30, 0x80, // ## # + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1888 '[' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1920 '\' (11 pixels wide) + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1952 ']' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1E, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1984 '^' (11 pixels wide) + 0x04, 0x00, // # + 0x0A, 0x00, // # # + 0x0A, 0x00, // # # + 0x11, 0x00, // # # + 0x20, 0x80, // # # + 0x20, 0x80, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2016 '_' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xFF, 0xE0, // ########### + + // @2048 '`' (11 pixels wide) + 0x08, 0x00, // # + 0x04, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2080 'a' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2112 'b' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x39, 0x80, // ### ## + 0x77, 0x00, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2144 'c' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1E, 0x80, // #### # + 0x31, 0x80, // ## ## + 0x60, 0x80, // ## # + 0x60, 0x00, // ## + 0x60, 0x80, // ## # + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2176 'd' (11 pixels wide) + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1D, 0x80, // ### ## + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2208 'e' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x7F, 0xC0, // ######### + 0x60, 0x00, // ## + 0x30, 0xC0, // ## ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2240 'f' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0xE0, // ###### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x80, // ####### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2272 'g' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2304 'h' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2336 'i' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2368 'j' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2400 'k' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x80, // ## #### + 0x36, 0x00, // ## ## + 0x3C, 0x00, // #### + 0x3C, 0x00, // #### + 0x36, 0x00, // ## ## + 0x33, 0x00, // ## ## + 0x77, 0xC0, // ### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2432 'l' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2464 'm' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x76, 0xE0, // ### ## ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2496 'n' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x00, // ### ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2528 'o' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2560 'p' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x00, // ### ### + 0x39, 0x80, // ### ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x39, 0x80, // ### ## + 0x37, 0x00, // ## ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2592 'q' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2624 'r' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0x80, // #### ### + 0x1C, 0xC0, // ### ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2656 's' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x3C, 0x00, // #### + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2688 't' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x7F, 0x00, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x80, // ## # + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2720 'u' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x73, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2752 'v' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2784 'w' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xF1, 0xE0, // #### #### + 0x60, 0xC0, // ## ## + 0x64, 0xC0, // ## # ## + 0x6E, 0xC0, // ## ### ## + 0x3B, 0x80, // ### ### + 0x3B, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2816 'x' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2848 'y' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x79, 0xE0, // #### #### + 0x30, 0xC0, // ## ## + 0x19, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x0B, 0x00, // # ## + 0x0F, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2880 'z' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x21, 0x80, // # ## + 0x03, 0x00, // ## + 0x0E, 0x00, // ### + 0x18, 0x00, // ## + 0x30, 0x80, // ## # + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2912 '{' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2944 '|' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2976 '}' (11 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3008 '~' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x24, 0x80, // # # # + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // +}; + +sFONT Font16 = { + Font16_Table, + 11, /* Width */ + 16, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/font20.c b/Fonts/font20.c new file mode 100644 index 0000000..e9e6afa --- /dev/null +++ b/Fonts/font20.c @@ -0,0 +1,2223 @@ +/** + ****************************************************************************** + * @file font20.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font20 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font20 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ + +// Character bitmaps for Courier New 15pt +const uint8_t Font20_Table[] = +{ + // @0 ' ' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @40 '!' (14 pixels wide) + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @80 '"' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1C, 0xE0, // ### ### + 0x1C, 0xE0, // ### ### + 0x1C, 0xE0, // ### ### + 0x08, 0x40, // # # + 0x08, 0x40, // # # + 0x08, 0x40, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @120 '#' (14 pixels wide) + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @160 '$' (14 pixels wide) + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x07, 0xE0, // ###### + 0x0F, 0xE0, // ####### + 0x18, 0x60, // ## ## + 0x18, 0x00, // ## + 0x1F, 0x00, // ##### + 0x0F, 0xC0, // ###### + 0x00, 0xE0, // ### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xC0, // ####### + 0x1F, 0x80, // ###### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @200 '%' (14 pixels wide) + 0x00, 0x00, // + 0x1C, 0x00, // ### + 0x22, 0x00, // # # + 0x22, 0x00, // # # + 0x22, 0x00, // # # + 0x1C, 0x60, // ### ## + 0x01, 0xE0, // #### + 0x0F, 0x80, // ##### + 0x3C, 0x00, // #### + 0x31, 0xC0, // ## ### + 0x02, 0x20, // # # + 0x02, 0x20, // # # + 0x02, 0x20, // # # + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @240 '&' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0xE0, // ##### + 0x0F, 0xE0, // ####### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x0F, 0x30, // #### ## + 0x1F, 0xF0, // ######### + 0x19, 0xE0, // ## #### + 0x18, 0xC0, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @280 ''' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x01, 0x00, // # + 0x01, 0x00, // # + 0x01, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @320 '(' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @360 ')' (14 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @400 '*' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1B, 0x60, // ## ## ## + 0x1F, 0xE0, // ######## + 0x07, 0x80, // #### + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x0C, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @440 '+' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @480 ',' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @520 '-' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @560 '.' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @600 '/' (14 pixels wide) + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @640 '0' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x1F, 0xC0, // ####### + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @680 '1' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @720 '2' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @760 '3' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x3F, 0xC0, // ######## + 0x30, 0xE0, // ## ### + 0x00, 0x60, // ## + 0x00, 0xE0, // ### + 0x07, 0xC0, // ##### + 0x07, 0xC0, // ##### + 0x00, 0xE0, // ### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x60, 0xE0, // ## ### + 0x7F, 0xC0, // ######### + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @800 '4' (14 pixels wide) + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x06, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0xC0, // ## + 0x03, 0xE0, // ##### + 0x03, 0xE0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @840 '5' (14 pixels wide) + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1F, 0x80, // ###### + 0x1F, 0xC0, // ####### + 0x18, 0xE0, // ## ### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x30, 0xE0, // ## ### + 0x3F, 0xC0, // ######## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @880 '6' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xE0, // ##### + 0x0F, 0xE0, // ####### + 0x1E, 0x00, // #### + 0x18, 0x00, // ## + 0x38, 0x00, // ### + 0x37, 0x80, // ## #### + 0x3F, 0xC0, // ######## + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xC0, // ####### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @920 '7' (14 pixels wide) + 0x00, 0x00, // + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x30, 0x60, // ## ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @960 '8' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xC0, // ####### + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1000 '9' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x1F, 0xC0, // ####### + 0x38, 0xC0, // ### ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xE0, // ######## + 0x0F, 0x60, // #### ## + 0x00, 0xE0, // ### + 0x00, 0xC0, // ## + 0x03, 0xC0, // #### + 0x3F, 0x80, // ####### + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1040 ':' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1080 ';' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x01, 0xC0, // ### + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1120 '<' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x30, // ## + 0x00, 0xF0, // #### + 0x03, 0xC0, // #### + 0x07, 0x00, // ### + 0x1C, 0x00, // ### + 0x78, 0x00, // #### + 0x1C, 0x00, // ### + 0x07, 0x00, // ### + 0x03, 0xC0, // #### + 0x00, 0xF0, // #### + 0x00, 0x30, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1160 '=' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xF0, // ########### + 0x7F, 0xF0, // ########### + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xF0, // ########### + 0x7F, 0xF0, // ########### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1200 '>' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x30, 0x00, // ## + 0x3C, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x80, // ### + 0x00, 0xE0, // ### + 0x00, 0x78, // #### + 0x00, 0xE0, // ### + 0x03, 0x80, // ### + 0x0F, 0x00, // #### + 0x3C, 0x00, // #### + 0x30, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1240 '?' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x00, 0x60, // ## + 0x01, 0xC0, // ### + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1280 '@' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x0C, 0x80, // ## # + 0x08, 0x40, // # # + 0x10, 0x40, // # # + 0x10, 0x40, // # # + 0x11, 0xC0, // # ### + 0x12, 0x40, // # # # + 0x12, 0x40, // # # # + 0x12, 0x40, // # # # + 0x11, 0xC0, // # ### + 0x10, 0x00, // # + 0x08, 0x00, // # + 0x08, 0x40, // # # + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1320 'A' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x03, 0x80, // ### + 0x06, 0xC0, // ## ## + 0x06, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x30, 0x30, // ## ## + 0x78, 0x78, // #### #### + 0x78, 0x78, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1360 'B' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x3F, 0xC0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xC0, // ####### + 0x1F, 0xE0, // ######## + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1400 'C' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x0F, 0xF0, // ######## + 0x1C, 0x70, // ### ### + 0x38, 0x30, // ### ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x38, 0x30, // ### ## + 0x1C, 0x70, // ### ### + 0x0F, 0xE0, // ####### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1440 'D' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x7F, 0xC0, // ######### + 0x30, 0xE0, // ## ### + 0x30, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x70, // ## ### + 0x30, 0xE0, // ## ### + 0x7F, 0xC0, // ######### + 0x7F, 0x80, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1480 'E' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1520 'F' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1560 'G' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x31, 0xF8, // ## ###### + 0x31, 0xF8, // ## ###### + 0x30, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1600 'H' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1640 'I' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1680 'J' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0xF8, // ####### + 0x03, 0xF8, // ####### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0xE0, // ## ### + 0x3F, 0xC0, // ######## + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1720 'K' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3E, 0xF8, // ##### ##### + 0x3E, 0xF8, // ##### ##### + 0x18, 0xE0, // ## ### + 0x19, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1F, 0x00, // ##### + 0x1D, 0x80, // ### ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0x60, // ## ## + 0x3E, 0x78, // ##### #### + 0x3E, 0x38, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1760 'L' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x30, // ## ## + 0x0C, 0x30, // ## ## + 0x0C, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1800 'M' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0x78, // #### #### + 0x78, 0x78, // #### #### + 0x38, 0x70, // ### ### + 0x3C, 0xF0, // #### #### + 0x34, 0xB0, // ## # # ## + 0x37, 0xB0, // ## #### ## + 0x37, 0xB0, // ## #### ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x30, 0x30, // ## ## + 0x7C, 0xF8, // ##### ##### + 0x7C, 0xF8, // ##### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1840 'N' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x39, 0xF0, // ### ##### + 0x3D, 0xF0, // #### ##### + 0x1C, 0x60, // ### ## + 0x1E, 0x60, // #### ## + 0x1E, 0x60, // #### ## + 0x1B, 0x60, // ## ## ## + 0x1B, 0x60, // ## ## ## + 0x19, 0xE0, // ## #### + 0x19, 0xE0, // ## #### + 0x18, 0xE0, // ## ### + 0x3E, 0xE0, // ##### ### + 0x3E, 0x60, // ##### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1880 'O' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x1C, 0xE0, // ### ### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1920 'P' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x3F, 0xE0, // ######### + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xE0, // ######## + 0x1F, 0xC0, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1960 'Q' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x1C, 0xE0, // ### ### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x07, 0xB0, // #### ## + 0x0F, 0xF0, // ######## + 0x0C, 0xE0, // ## ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2000 'R' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x3F, 0xE0, // ######### + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xE0, // ######## + 0x1F, 0xC0, // ####### + 0x18, 0xE0, // ## ### + 0x18, 0x60, // ## ## + 0x18, 0x70, // ## ### + 0x3E, 0x38, // ##### ### + 0x3E, 0x18, // ##### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2040 'S' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0xB0, // ##### ## + 0x1F, 0xF0, // ######### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x38, 0x00, // ### + 0x1F, 0x80, // ###### + 0x07, 0xE0, // ###### + 0x00, 0x70, // ### + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x3F, 0xE0, // ######### + 0x37, 0xC0, // ## ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2080 'T' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0xC0, // ###### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2120 'U' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2160 'V' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2200 'W' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7C, 0x7C, // ##### ##### + 0x7C, 0x7C, // ##### ##### + 0x30, 0x18, // ## ## + 0x33, 0x98, // ## ### ## + 0x33, 0x98, // ## ### ## + 0x33, 0x98, // ## ### ## + 0x36, 0xD8, // ## ## ## ## + 0x16, 0xD0, // # ## ## # + 0x1C, 0x70, // ### ### + 0x1C, 0x70, // ### ### + 0x1C, 0x70, // ### ### + 0x18, 0x30, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2240 'X' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x0D, 0x80, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2280 'Y' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x0C, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x07, 0x80, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0xC0, // ###### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2320 'Z' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2360 '[' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2400 '\' (14 pixels wide) + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2440 ']' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0x00, // #### + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2480 '^' (14 pixels wide) + 0x00, 0x00, // + 0x02, 0x00, // # + 0x07, 0x00, // ### + 0x0D, 0x80, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x20, 0x20, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2520 '_' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xFF, 0xFC, // ############## + 0xFF, 0xFC, // ############## + + // @2560 '`' (14 pixels wide) + 0x00, 0x00, // + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0x80, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2600 'a' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0xC0, // ###### + 0x1F, 0xE0, // ######## + 0x00, 0x60, // ## + 0x0F, 0xE0, // ####### + 0x1F, 0xE0, // ######## + 0x38, 0x60, // ### ## + 0x30, 0xE0, // ## ### + 0x3F, 0xF0, // ########## + 0x1F, 0x70, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2640 'b' (14 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x80, // ## #### + 0x3F, 0xE0, // ######### + 0x38, 0x60, // ### ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x60, // ### ## + 0x7F, 0xE0, // ########## + 0x77, 0x80, // ### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2680 'c' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x38, 0x30, // ### ## + 0x1F, 0xF0, // ######### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2720 'd' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x70, // ### + 0x00, 0x70, // ### + 0x00, 0x30, // ## + 0x00, 0x30, // ## + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1F, 0xF8, // ########## + 0x07, 0xB8, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2760 'e' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x30, 0x00, // ## + 0x18, 0x30, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2800 'f' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xF0, // ###### + 0x07, 0xF0, // ####### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2840 'g' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB8, // #### ### + 0x1F, 0xF8, // ########## + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x30, // ## + 0x00, 0x70, // ### + 0x0F, 0xE0, // ####### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2880 'h' (14 pixels wide) + 0x00, 0x00, // + 0x38, 0x00, // ### + 0x38, 0x00, // ### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1B, 0xC0, // ## #### + 0x1F, 0xE0, // ######## + 0x1C, 0x60, // ### ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2920 'i' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2960 'j' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0xC0, // ### + 0x3F, 0x80, // ####### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3000 'k' (14 pixels wide) + 0x00, 0x00, // + 0x38, 0x00, // ### + 0x38, 0x00, // ### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1B, 0xE0, // ## ##### + 0x1B, 0xE0, // ## ##### + 0x1B, 0x00, // ## ## + 0x1E, 0x00, // #### + 0x1E, 0x00, // #### + 0x1B, 0x00, // ## ## + 0x19, 0x80, // ## ## + 0x39, 0xF0, // ### ##### + 0x39, 0xF0, // ### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3040 'l' (14 pixels wide) + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3080 'm' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7E, 0xE0, // ###### ### + 0x7F, 0xF0, // ########### + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x7B, 0xB8, // #### ### ### + 0x7B, 0xB8, // #### ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3120 'n' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3B, 0xC0, // ### #### + 0x3F, 0xE0, // ######### + 0x1C, 0x60, // ### ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3160 'o' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3200 'p' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x80, // ### #### + 0x7F, 0xE0, // ########## + 0x38, 0x60, // ### ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x60, // ### ## + 0x3F, 0xE0, // ######### + 0x37, 0x80, // ## #### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3240 'q' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB8, // #### ### + 0x1F, 0xF8, // ########## + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x30, // ## + 0x00, 0x30, // ## + 0x00, 0xF8, // ##### + 0x00, 0xF8, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3280 'r' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xE0, // #### ### + 0x3D, 0xF0, // #### ##### + 0x0F, 0x30, // #### ## + 0x0E, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3320 's' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xE0, // ###### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x1E, 0x00, // #### + 0x0F, 0xC0, // ###### + 0x01, 0xE0, // #### + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3360 't' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x30, // ## ## + 0x0F, 0xF0, // ######## + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3400 'u' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x38, 0xE0, // ### ### + 0x38, 0xE0, // ### ### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xF0, // ######### + 0x0F, 0x70, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3440 'v' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3480 'w' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x32, 0x60, // ## # ## + 0x32, 0x60, // ## # ## + 0x37, 0xE0, // ## ###### + 0x1D, 0xC0, // ### ### + 0x1D, 0xC0, // ### ### + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3520 'x' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x0C, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x03, 0x00, // ## + 0x07, 0x80, // #### + 0x0C, 0xC0, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3560 'y' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0F, 0x80, // ##### + 0x07, 0x00, // ### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x7F, 0x00, // ####### + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3600 'z' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0xC0, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3640 '{' (14 pixels wide) + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x03, 0xC0, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x07, 0x00, // ### + 0x0E, 0x00, // ### + 0x07, 0x00, // ### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0xC0, // #### + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3680 '|' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3720 '}' (14 pixels wide) + 0x00, 0x00, // + 0x1C, 0x00, // ### + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x07, 0x00, // ### + 0x03, 0x80, // ### + 0x07, 0x00, // ### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1E, 0x00, // #### + 0x1C, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3760 '~' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x3F, 0x30, // ###### ## + 0x33, 0xF0, // ## ###### + 0x01, 0xE0, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // +}; + + +sFONT Font20 = { + Font20_Table, + 14, /* Width */ + 20, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/font24.c b/Fonts/font24.c new file mode 100644 index 0000000..bdee2f1 --- /dev/null +++ b/Fonts/font24.c @@ -0,0 +1,2600 @@ +/** + ****************************************************************************** + * @file font24.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font24 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font24 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +const uint8_t Font24_Table [] = +{ + // @0 ' ' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @72 '!' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @144 '"' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0E, 0x70, 0x00, // ### ### + 0x0E, 0x70, 0x00, // ### ### + 0x0E, 0x70, 0x00, // ### ### + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @216 '#' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @288 '$' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x07, 0xB0, 0x00, // #### ## + 0x0F, 0xF0, 0x00, // ######## + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x70, 0x00, // ## ### + 0x1C, 0x00, 0x00, // ### + 0x0F, 0x80, 0x00, // ##### + 0x07, 0xE0, 0x00, // ###### + 0x00, 0xF0, 0x00, // #### + 0x18, 0x30, 0x00, // ## ## + 0x1C, 0x30, 0x00, // ### ## + 0x1C, 0x70, 0x00, // ### ### + 0x1F, 0xE0, 0x00, // ######## + 0x1B, 0xC0, 0x00, // ## #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @360 '%' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x80, 0x00, // #### + 0x0F, 0xC0, 0x00, // ###### + 0x1C, 0xE0, 0x00, // ### ### + 0x18, 0x60, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x1C, 0xE0, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x07, 0xE0, 0x00, // ###### + 0x1F, 0xF0, 0x00, // ######### + 0x07, 0x38, 0x00, // ### ### + 0x06, 0x18, 0x00, // ## ## + 0x06, 0x18, 0x00, // ## ## + 0x07, 0x38, 0x00, // ### ### + 0x03, 0xF0, 0x00, // ###### + 0x01, 0xE0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @432 '&' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xF0, 0x00, // ###### + 0x07, 0xF0, 0x00, // ####### + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x07, 0x00, 0x00, // ### + 0x0F, 0x9C, 0x00, // ##### ### + 0x1D, 0xFC, 0x00, // ### ####### + 0x18, 0xF0, 0x00, // ## #### + 0x18, 0x70, 0x00, // ## ### + 0x0F, 0xFC, 0x00, // ########## + 0x07, 0xDC, 0x00, // ##### ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @504 ''' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @576 '(' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0xF0, 0x00, // #### + 0x00, 0xE0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0x38, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @648 ')' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x18, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x0F, 0x00, 0x00, // #### + 0x0E, 0x00, 0x00, // ### + 0x1C, 0x00, 0x00, // ### + 0x18, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @720 '*' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1D, 0xB8, 0x00, // ### ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @792 '+' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @864 ',' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @936 '-' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1008 '.' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1080 '/' (17 pixels wide) + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x0E, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1152 '0' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x07, 0xE0, 0x00, // ###### + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1224 '1' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x80, 0x00, // # + 0x07, 0x80, 0x00, // #### + 0x1F, 0x80, 0x00, // ###### + 0x1D, 0x80, 0x00, // ### ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1296 '2' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x1F, 0xF0, 0x00, // ######### + 0x38, 0x30, 0x00, // ### ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1368 '3' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xE0, 0x00, // ####### + 0x0C, 0x70, 0x00, // ## ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x70, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1440 '4' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xE0, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x03, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x30, 0x60, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x60, 0x00, // ## + 0x03, 0xF8, 0x00, // ####### + 0x03, 0xF8, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1512 '5' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF0, 0x00, // ######### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xC0, 0x00, // ## #### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x30, 0x00, // ### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x30, 0x30, 0x00, // ## ## + 0x3F, 0xF0, 0x00, // ########## + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1584 '6' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xF8, 0x00, // ##### + 0x03, 0xF8, 0x00, // ####### + 0x07, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xC0, 0x00, // ## #### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x30, 0x00, // ### ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x38, 0x00, // ## ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1656 '7' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0xE0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1728 '8' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xE0, 0x00, // ###### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x07, 0xE0, 0x00, // ###### + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x07, 0xE0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1800 '9' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x30, 0x00, // ### ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x38, 0x00, // ## ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xD8, 0x00, // #### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x1F, 0xC0, 0x00, // ####### + 0x1F, 0x00, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1872 ':' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1944 ';' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xF0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x02, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2016 '<' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x1C, 0x00, // ### + 0x00, 0x3C, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x0F, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0xF0, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0x0F, 0x00, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0x3C, 0x00, // #### + 0x00, 0x1C, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2088 '=' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2160 '>' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x70, 0x00, 0x00, // ### + 0x78, 0x00, 0x00, // #### + 0x1E, 0x00, 0x00, // #### + 0x07, 0x80, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x00, 0x1E, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x07, 0x80, 0x00, // #### + 0x1E, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x70, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2232 '?' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x0F, 0xE0, 0x00, // ####### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x30, 0x00, // ## ## + 0x00, 0x70, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x03, 0xC0, 0x00, // #### + 0x03, 0x80, 0x00, // ### + 0x03, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2304 '@' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xE0, 0x00, // ##### + 0x07, 0xF0, 0x00, // ####### + 0x0E, 0x38, 0x00, // ### ### + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x78, 0x00, // ## #### + 0x18, 0xF8, 0x00, // ## ##### + 0x19, 0xD8, 0x00, // ## ### ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x18, 0xF8, 0x00, // ## ##### + 0x18, 0x78, 0x00, // ## #### + 0x18, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0E, 0x18, 0x00, // ### ## + 0x07, 0xF8, 0x00, // ######## + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2376 'A' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0xC0, 0x00, // ####### + 0x01, 0xC0, 0x00, // ### + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0F, 0xF8, 0x00, // ######### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0xFC, 0x7F, 0x00, // ###### ####### + 0xFC, 0x7F, 0x00, // ###### ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2448 'B' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xE0, 0x00, // ########## + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x1C, 0x00, // ## ### + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF0, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2520 'C' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2592 'D' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xC0, 0x00, // ######### + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0xF0, 0x00, // ########### + 0x7F, 0xE0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2664 'E' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF8, 0x00, // ############ + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x80, 0x00, // ## ## + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x19, 0x80, 0x00, // ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF8, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2736 'F' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0xCC, 0x00, // ## ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0F, 0xC0, 0x00, // ###### + 0x0F, 0xC0, 0x00, // ###### + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2808 'G' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0xFE, 0x00, // ## ####### + 0x30, 0xFE, 0x00, // ## ####### + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x0C, 0x00, // ### ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xFC, 0x00, // ########## + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2880 'H' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2952 'I' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3024 'J' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xFE, 0x00, // ########## + 0x07, 0xFE, 0x00, // ########## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x60, 0x00, // ## ## + 0x3F, 0xE0, 0x00, // ######### + 0x0F, 0x80, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3096 'K' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x3E, 0x00, // ####### ##### + 0x7F, 0x3E, 0x00, // ####### ##### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x18, 0xC0, 0x00, // ## ## + 0x19, 0x80, 0x00, // ## ## + 0x1B, 0x80, 0x00, // ## ### + 0x1F, 0xC0, 0x00, // ####### + 0x1C, 0xE0, 0x00, // ### ### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x1F, 0x00, // ####### ##### + 0x7F, 0x1F, 0x00, // ####### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3168 'L' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x80, 0x00, // ######## + 0x7F, 0x80, 0x00, // ######## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3240 'M' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xF0, 0x0F, 0x00, // #### #### + 0xF8, 0x1F, 0x00, // ##### ##### + 0x38, 0x1C, 0x00, // ### ### + 0x3C, 0x3C, 0x00, // #### #### + 0x3C, 0x3C, 0x00, // #### #### + 0x36, 0x6C, 0x00, // ## ## ## ## + 0x36, 0x6C, 0x00, // ## ## ## ## + 0x33, 0xCC, 0x00, // ## #### ## + 0x33, 0xCC, 0x00, // ## #### ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0xFE, 0x7F, 0x00, // ####### ####### + 0xFE, 0x7F, 0x00, // ####### ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3312 'N' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0xFE, 0x00, // #### ####### + 0x78, 0xFE, 0x00, // #### ####### + 0x1C, 0x18, 0x00, // ### ## + 0x1E, 0x18, 0x00, // #### ## + 0x1F, 0x18, 0x00, // ##### ## + 0x1B, 0x18, 0x00, // ## ## ## + 0x1B, 0x98, 0x00, // ## ### ## + 0x19, 0xD8, 0x00, // ## ### ## + 0x18, 0xD8, 0x00, // ## ## ## + 0x18, 0xF8, 0x00, // ## ##### + 0x18, 0x78, 0x00, // ## #### + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x18, 0x00, // ####### ## + 0x7F, 0x18, 0x00, // ####### ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3384 'O' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3456 'P' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF8, 0x00, // ########### + 0x0C, 0x1C, 0x00, // ## ### + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0F, 0xF8, 0x00, // ######### + 0x0F, 0xE0, 0x00, // ####### + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3528 'Q' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x07, 0xC0, 0x00, // ##### + 0x07, 0xCC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x0C, 0x38, 0x00, // ## ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3600 'R' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xE0, 0x00, // ########## + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xC0, 0x00, // ####### + 0x18, 0xE0, 0x00, // ## ### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x1E, 0x00, // ####### #### + 0x7F, 0x0E, 0x00, // ####### ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3672 'S' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xD8, 0x00, // ##### ## + 0x0F, 0xF8, 0x00, // ######### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1E, 0x00, 0x00, // #### + 0x0F, 0xC0, 0x00, // ###### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x78, 0x00, // #### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x1F, 0xF0, 0x00, // ######### + 0x1B, 0xE0, 0x00, // ## ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3744 'T' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3816 'U' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3888 'V' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x7F, 0x00, // ####### ####### + 0x7F, 0x7F, 0x00, // ####### ####### + 0x18, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x00, 0x80, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3960 'W' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xFE, 0x3F, 0x80, // ####### ####### + 0xFE, 0x3F, 0x80, // ####### ####### + 0x30, 0x06, 0x00, // ## ## + 0x30, 0x06, 0x00, // ## ## + 0x30, 0x86, 0x00, // ## # ## + 0x19, 0xCC, 0x00, // ## ### ## + 0x19, 0xCC, 0x00, // ## ### ## + 0x1B, 0x6C, 0x00, // ## ## ## ## + 0x1B, 0x6C, 0x00, // ## ## ## ## + 0x1E, 0x7C, 0x00, // #### ##### + 0x0E, 0x38, 0x00, // ### ### + 0x0E, 0x38, 0x00, // ### ### + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4032 'X' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4104 'Y' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7C, 0x7E, 0x00, // ##### ###### + 0x7C, 0x7E, 0x00, // ##### ###### + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4176 'Z' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x18, 0xC0, 0x00, // ## ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4248 '[' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0xF0, 0x00, // ##### + 0x01, 0xF0, 0x00, // ##### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xF0, 0x00, // ##### + 0x01, 0xF0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4320 '\' (17 pixels wide) + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x0E, 0x00, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4392 ']' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x80, 0x00, // ##### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x80, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4464 '^' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x80, 0x00, // # + 0x01, 0xC0, 0x00, // ### + 0x03, 0xE0, 0x00, // ##### + 0x07, 0x70, 0x00, // ### ### + 0x06, 0x30, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x10, 0x04, 0x00, // # # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4536 '_' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xFF, 0xFF, 0x00, // ################ + 0xFF, 0xFF, 0x00, // ################ + + // @4608 '`' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x03, 0x00, 0x00, // ## + 0x03, 0x80, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4680 'a' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0F, 0xC0, 0x00, // ###### + 0x1F, 0xE0, 0x00, // ######## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x07, 0xF0, 0x00, // ####### + 0x1F, 0xF0, 0x00, // ######### + 0x38, 0x30, 0x00, // ### ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x70, 0x00, // ## ### + 0x1F, 0xFC, 0x00, // ########### + 0x0F, 0xBC, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4752 'b' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xE0, 0x00, // ## ##### + 0x1F, 0xF8, 0x00, // ########## + 0x1C, 0x18, 0x00, // ### ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x18, 0x00, // ### ## + 0x7F, 0xF8, 0x00, // ############ + 0x7B, 0xE0, 0x00, // #### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4824 'c' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x38, 0x0C, 0x00, // ### ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x38, 0x0C, 0x00, // ### ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4896 'd' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x78, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x07, 0xD8, 0x00, // ##### ## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xFE, 0x00, // ############ + 0x07, 0xDE, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4968 'e' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xE0, 0x00, // ###### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x18, 0x0C, 0x00, // ## ## + 0x1F, 0xFC, 0x00, // ########### + 0x07, 0xF0, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5040 'f' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0xFC, 0x00, // ####### + 0x03, 0xFC, 0x00, // ######## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5112 'g' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xDE, 0x00, // ##### #### + 0x1F, 0xFE, 0x00, // ############ + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xD8, 0x00, // ##### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5184 'h' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xE0, 0x00, // ## ##### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5256 'i' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5328 'j' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF0, 0x00, // ######### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x1F, 0xE0, 0x00, // ######## + 0x1F, 0x80, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5400 'k' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3C, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0xF8, 0x00, // ## ##### + 0x0C, 0xF8, 0x00, // ## ##### + 0x0C, 0xC0, 0x00, // ## ## + 0x0D, 0x80, 0x00, // ## ## + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x00, 0x00, // #### + 0x0F, 0x80, 0x00, // ##### + 0x0D, 0xC0, 0x00, // ## ### + 0x0C, 0xE0, 0x00, // ## ### + 0x3C, 0x7C, 0x00, // #### ##### + 0x3C, 0x7C, 0x00, // #### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5472 'l' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5544 'm' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xF7, 0x78, 0x00, // #### ### #### + 0xFF, 0xFC, 0x00, // ############## + 0x39, 0xCC, 0x00, // ### ### ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0xFD, 0xEF, 0x00, // ###### #### #### + 0xFD, 0xEF, 0x00, // ###### #### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5616 'n' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7B, 0xE0, 0x00, // #### ##### + 0x7F, 0xF0, 0x00, // ########### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5688 'o' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5760 'p' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7B, 0xE0, 0x00, // #### ##### + 0x7F, 0xF8, 0x00, // ############ + 0x1C, 0x18, 0x00, // ### ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x18, 0x00, // ### ## + 0x1F, 0xF8, 0x00, // ########## + 0x1B, 0xE0, 0x00, // ## ##### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x7F, 0x00, 0x00, // ####### + 0x7F, 0x00, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5832 'q' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xDE, 0x00, // ##### #### + 0x1F, 0xFE, 0x00, // ############ + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xD8, 0x00, // ##### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0xFE, 0x00, // ####### + 0x00, 0xFE, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5904 'r' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3E, 0x78, 0x00, // ##### #### + 0x3E, 0xFC, 0x00, // ##### ###### + 0x07, 0xCC, 0x00, // ##### ## + 0x07, 0x00, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5976 's' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xF8, 0x00, // ######## + 0x0F, 0xF8, 0x00, // ######### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1F, 0x80, 0x00, // ###### + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0xF8, 0x00, // ##### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xE0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6048 't' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x1C, 0x00, // ## ### + 0x07, 0xFC, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6120 'u' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x78, 0x00, // #### #### + 0x78, 0x78, 0x00, // #### #### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x0F, 0xFE, 0x00, // ########### + 0x07, 0xDE, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6192 'v' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7C, 0x3E, 0x00, // ##### ##### + 0x7C, 0x3E, 0x00, // ##### ##### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6264 'w' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x3C, 0x00, // #### #### + 0x78, 0x3C, 0x00, // #### #### + 0x31, 0x18, 0x00, // ## # ## + 0x33, 0x98, 0x00, // ## ### ## + 0x33, 0x98, 0x00, // ## ### ## + 0x1A, 0xB0, 0x00, // ## # # ## + 0x1E, 0xF0, 0x00, // #### #### + 0x1E, 0xF0, 0x00, // #### #### + 0x1C, 0x60, 0x00, // ### ## + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6336 'x' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3E, 0x7C, 0x00, // ##### ##### + 0x3E, 0x7C, 0x00, // ##### ##### + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x3E, 0x7C, 0x00, // ##### ##### + 0x3E, 0x7C, 0x00, // ##### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6408 'y' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x1F, 0x00, // ###### ##### + 0x7E, 0x1F, 0x00, // ###### ##### + 0x18, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0xE0, 0x00, // ##### + 0x01, 0xC0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6480 'z' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6552 '{' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xE0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x80, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xE0, 0x00, // #### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6624 '|' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6696 '}' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x00, 0x00, // ### + 0x07, 0x80, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x07, 0x80, 0x00, // #### + 0x07, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6768 '~' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0E, 0x00, 0x00, // ### + 0x1F, 0x18, 0x00, // ##### ## + 0x3B, 0xB8, 0x00, // ### ### ### + 0x31, 0xF0, 0x00, // ## ##### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // +}; + +sFONT Font24 = { + Font24_Table, + 17, /* Width */ + 24, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/font8.c b/Fonts/font8.c new file mode 100644 index 0000000..1a3cbf9 --- /dev/null +++ b/Fonts/font8.c @@ -0,0 +1,1084 @@ +/** + ****************************************************************************** + * @file Font8.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text Font8 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "fonts.h" + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text Font8 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// + +const uint8_t Font8_Table[] = +{ + // @0 ' ' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @8 '!' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @16 '"' (5 pixels wide) + 0x50, // # # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @24 '#' (5 pixels wide) + 0x28, // # # + 0x50, // # # + 0xF8, // ##### + 0x50, // # # + 0xF8, // ##### + 0x50, // # # + 0xA0, // # # + 0x00, // + + // @32 '$' (5 pixels wide) + 0x20, // # + 0x30, // ## + 0x60, // ## + 0x30, // ## + 0x10, // # + 0x60, // ## + 0x20, // # + 0x00, // + + // @40 '%' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x18, // ## + 0x60, // ## + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @48 '&' (5 pixels wide) + 0x00, // + 0x38, // ### + 0x20, // # + 0x60, // ## + 0x50, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @56 ''' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @64 '(' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @72 ')' (5 pixels wide) + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + + // @80 '*' (5 pixels wide) + 0x20, // # + 0x70, // ### + 0x20, // # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @88 '+' (5 pixels wide) + 0x00, // + 0x20, // # + 0x20, // # + 0xF8, // ##### + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + + // @96 ',' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x10, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @104 '-' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @112 '.' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @120 '/' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x40, // # + 0x80, // # + 0x00, // + + // @128 '0' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x50, // # # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @136 '1' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @144 '2' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x40, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @152 '3' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x10, // # + 0x20, // # + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @160 '4' (5 pixels wide) + 0x10, // # + 0x30, // ## + 0x50, // # # + 0x78, // #### + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + + // @168 '5' (5 pixels wide) + 0x70, // ### + 0x40, // # + 0x60, // ## + 0x10, // # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @176 '6' (5 pixels wide) + 0x30, // ## + 0x40, // # + 0x60, // ## + 0x50, // # # + 0x50, // # # + 0x60, // ## + 0x00, // + 0x00, // + + // @184 '7' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + + // @192 '8' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x20, // # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @200 '9' (5 pixels wide) + 0x30, // ## + 0x50, // # # + 0x50, // # # + 0x30, // ## + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @208 ':' (5 pixels wide) + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @216 ';' (5 pixels wide) + 0x00, // + 0x00, // + 0x10, // # + 0x00, // + 0x10, // # + 0x20, // # + 0x00, // + 0x00, // + + // @224 '<' (5 pixels wide) + 0x00, // + 0x10, // # + 0x20, // # + 0xC0, // ## + 0x20, // # + 0x10, // # + 0x00, // + 0x00, // + + // @232 '=' (5 pixels wide) + 0x00, // + 0x70, // ### + 0x00, // + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @240 '>' (5 pixels wide) + 0x00, // + 0x40, // # + 0x20, // # + 0x18, // ## + 0x20, // # + 0x40, // # + 0x00, // + 0x00, // + + // @248 '?' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x10, // # + 0x20, // # + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @256 '@' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x58, // # ## + 0x48, // # # + 0x40, // # + 0x38, // ### + 0x00, // + + // @264 'A' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x50, // # # + 0x70, // ### + 0x88, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @272 'B' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @280 'C' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x40, // # + 0x40, // # + 0x40, // # + 0x30, // ## + 0x00, // + 0x00, // + + // @288 'D' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @296 'E' (5 pixels wide) + 0xF8, // ##### + 0x48, // # # + 0x60, // ## + 0x40, // # + 0x48, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @304 'F' (5 pixels wide) + 0xF8, // ##### + 0x48, // # # + 0x60, // ## + 0x40, // # + 0x40, // # + 0xE0, // ### + 0x00, // + 0x00, // + + // @312 'G' (5 pixels wide) + 0x70, // ### + 0x40, // # + 0x40, // # + 0x58, // # ## + 0x50, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @320 'H' (5 pixels wide) + 0xE8, // ### # + 0x48, // # # + 0x78, // #### + 0x48, // # # + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @328 'I' (5 pixels wide) + 0x70, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @336 'J' (5 pixels wide) + 0x38, // ### + 0x10, // # + 0x10, // # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @344 'K' (5 pixels wide) + 0xD8, // ## ## + 0x50, // # # + 0x60, // ## + 0x70, // ### + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @352 'L' (5 pixels wide) + 0xE0, // ### + 0x40, // # + 0x40, // # + 0x40, // # + 0x48, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @360 'M' (5 pixels wide) + 0xD8, // ## ## + 0xD8, // ## ## + 0xD8, // ## ## + 0xA8, // # # # + 0x88, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @368 'N' (5 pixels wide) + 0xD8, // ## ## + 0x68, // ## # + 0x68, // ## # + 0x58, // # ## + 0x58, // # ## + 0xE8, // ### # + 0x00, // + 0x00, // + + // @376 'O' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @384 'P' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x40, // # + 0xE0, // ### + 0x00, // + 0x00, // + + // @392 'Q' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x18, // ## + 0x00, // + + // @400 'R' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @408 'S' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x20, // # + 0x10, // # + 0x50, // # # + 0x70, // ### + 0x00, // + 0x00, // + + // @416 'T' (5 pixels wide) + 0xF8, // ##### + 0xA8, // # # # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @424 'U' (5 pixels wide) + 0xD8, // ## ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @432 'V' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0x48, // # # + 0x50, // # # + 0x50, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @440 'W' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0xA8, // # # # + 0xA8, // # # # + 0xA8, // # # # + 0x50, // # # + 0x00, // + 0x00, // + + // @448 'X' (5 pixels wide) + 0xD8, // ## ## + 0x50, // # # + 0x20, // # + 0x20, // # + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @456 'Y' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @464 'Z' (5 pixels wide) + 0x78, // #### + 0x48, // # # + 0x10, // # + 0x20, // # + 0x48, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @472 '[' (5 pixels wide) + 0x30, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x30, // ## + 0x00, // + + // @480 '\' (5 pixels wide) + 0x80, // # + 0x40, // # + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @488 ']' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x60, // ## + 0x00, // + + // @496 '^' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @504 '_' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0xF8, // ##### + + // @512 '`' (5 pixels wide) + 0x20, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @520 'a' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x10, // # + 0x70, // ### + 0x78, // #### + 0x00, // + 0x00, // + + // @528 'b' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @536 'c' (5 pixels wide) + 0x00, // + 0x00, // + 0x70, // ### + 0x40, // # + 0x40, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @544 'd' (5 pixels wide) + 0x18, // ## + 0x08, // # + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @552 'e' (5 pixels wide) + 0x00, // + 0x00, // + 0x70, // ### + 0x70, // ### + 0x40, // # + 0x30, // ## + 0x00, // + 0x00, // + + // @560 'f' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x70, // ### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @568 'g' (5 pixels wide) + 0x00, // + 0x00, // + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x08, // # + 0x30, // ## + + // @576 'h' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @584 'i' (5 pixels wide) + 0x20, // # + 0x00, // + 0x60, // ## + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @592 'j' (5 pixels wide) + 0x20, // # + 0x00, // + 0x70, // ### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x70, // ### + + // @600 'k' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x70, // ### + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @608 'l' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @616 'm' (5 pixels wide) + 0x00, // + 0x00, // + 0xD0, // ## # + 0xA8, // # # # + 0xA8, // # # # + 0xA8, // # # # + 0x00, // + 0x00, // + + // @624 'n' (5 pixels wide) + 0x00, // + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0xC8, // ## # + 0x00, // + 0x00, // + + // @632 'o' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @640 'p' (5 pixels wide) + 0x00, // + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x40, // # + 0xE0, // ### + + // @648 'q' (5 pixels wide) + 0x00, // + 0x00, // + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x08, // # + 0x18, // ## + + // @656 'r' (5 pixels wide) + 0x00, // + 0x00, // + 0x78, // #### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @664 's' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x20, // # + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @672 't' (5 pixels wide) + 0x00, // + 0x40, // # + 0xF0, // #### + 0x40, // # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @680 'u' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @688 'v' (5 pixels wide) + 0x00, // + 0x00, // + 0xC8, // ## # + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + + // @696 'w' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0xA8, // # # # + 0xA8, // # # # + 0x50, // # # + 0x00, // + 0x00, // + + // @704 'x' (5 pixels wide) + 0x00, // + 0x00, // + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x48, // # # + 0x00, // + 0x00, // + + // @712 'y' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x60, // ## + + // @720 'z' (5 pixels wide) + 0x00, // + 0x00, // + 0x78, // #### + 0x50, // # # + 0x28, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @728 '{' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x60, // ## + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @736 '|' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @744 '}' (5 pixels wide) + 0x40, // # + 0x20, // # + 0x20, // # + 0x30, // ## + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + + // @752 '~' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x28, // # # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // +}; + +sFONT Font8 = { + Font8_Table, + 5, /* Width */ + 8, /* Height */ +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Fonts/fonts.h b/Fonts/fonts.h new file mode 100644 index 0000000..e9a794b --- /dev/null +++ b/Fonts/fonts.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file fonts.h + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief Header for fonts.c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FONTS_H +#define __FONTS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @{ + */ + +/** @defgroup FONTS_Exported_Types + * @{ + */ +typedef struct _tFont +{ + const uint8_t *table; + uint16_t Width; + uint16_t Height; + +} sFONT; + +extern sFONT Font24; +extern sFONT Font20; +extern sFONT Font16; +extern sFONT Font12; +extern sFONT Font8; +/** + * @} + */ + +/** @defgroup FONTS_Exported_Constants + * @{ + */ +#define LINE(x) ((x) * (((sFONT *)BSP_LCD_GetFont())->Height)) + +/** + * @} + */ + +/** @defgroup FONTS_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup FONTS_Exported_Functions + * @{ + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FONTS_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c new file mode 100644 index 0000000..0900213 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -0,0 +1,1727 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.c + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * + * + *---------------------------------------------------------------------------- + * + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +/* + * ARM Compiler 4/5 + */ +#if defined ( __CC_ARM ) + + #define __ASM __asm + #define __INLINE __inline + #define __STATIC_INLINE static __inline + + #include "cmsis_armcc.h" + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #include +#endif + +extern void xPortSysTickHandler(void); + +/* Convert from CMSIS type osPriority to FreeRTOS priority number */ +static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority) +{ + unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY; + + if (priority != osPriorityError) { + fpriority += (priority - osPriorityIdle); + } + + return fpriority; +} + +#if (INCLUDE_uxTaskPriorityGet == 1) +/* Convert from FreeRTOS priority number to CMSIS type osPriority */ +static osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority) +{ + osPriority priority = osPriorityError; + + if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) { + priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY)); + } + + return priority; +} +#endif + + +/* Determine whether we are in thread mode or handler mode. */ +static int inHandlerMode (void) +{ + return __get_IPSR() != 0; +} + +/*********************** Kernel Control Functions *****************************/ +/** +* @brief Initialize the RTOS Kernel for creating objects. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelInitialize (void); + +/** +* @brief Start the RTOS Kernel with executing the specified thread. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osKernelStart (void) +{ + vTaskStartScheduler(); + + return osOK; +} + +/** +* @brief Check if the RTOS kernel is already started +* @param None +* @retval (0) RTOS is not started +* (1) RTOS is started +* (-1) if this feature is disabled in FreeRTOSConfig.h +* @note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +*/ +int32_t osKernelRunning(void) +{ +#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) + return 0; + else + return 1; +#else + return (-1); +#endif +} + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available +/** +* @brief Get the value of the Kernel SysTick timer +* @param None +* @retval None +* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +*/ +uint32_t osKernelSysTick(void) +{ + if (inHandlerMode()) { + return xTaskGetTickCountFromISR(); + } + else { + return xTaskGetTickCount(); + } +} +#endif // System Timer available +/*********************** Thread Management *****************************/ +/** +* @brief Create a thread and add it to Active Threads and set it to state READY. +* @param thread_def thread definition referenced with \ref osThread. +* @param argument pointer that is passed to the thread function as start argument. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) +{ + TaskHandle_t handle; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) { + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); + } + else { + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + + handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + thread_def->buffer, thread_def->controlblock); +#else + if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name, + thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority), + &handle) != pdPASS) { + return NULL; + } +#endif + + return handle; +} + +/** +* @brief Return the thread ID of the current running thread. +* @retval thread ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +*/ +osThreadId osThreadGetId (void) +{ +#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) + return xTaskGetCurrentTaskHandle(); +#else + return NULL; +#endif +} + +/** +* @brief Terminate execution of a thread and remove it from Active Threads. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadTerminate (osThreadId thread_id) +{ +#if (INCLUDE_vTaskDelete == 1) + vTaskDelete(thread_id); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Pass control to next thread that is in state \b READY. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadYield (void) +{ + taskYIELD(); + + return osOK; +} + +/** +* @brief Change priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param priority new priority value for the thread function. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +*/ +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) +{ +#if (INCLUDE_vTaskPrioritySet == 1) + vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority)); + return osOK; +#else + return osErrorOS; +#endif +} + +/** +* @brief Get current priority of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval current priority value of the thread function. +* @note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +*/ +osPriority osThreadGetPriority (osThreadId thread_id) +{ +#if (INCLUDE_uxTaskPriorityGet == 1) + if (inHandlerMode()) + { + return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id)); + } + else + { + return makeCmsisPriority(uxTaskPriorityGet(thread_id)); + } +#else + return osPriorityError; +#endif +} + +/*********************** Generic Wait Functions *******************************/ +/** +* @brief Wait for Timeout (Time Delay) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelay (uint32_t millisec) +{ +#if INCLUDE_vTaskDelay + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */ + + return osOK; +#else + (void) millisec; + + return osErrorResource; +#endif +} + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) /* Generic Wait available */ +/** +* @brief Wait for Signal, Message, Mail, or Timeout +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains signal, message, or mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osWait (uint32_t millisec); + +#endif /* Generic Wait available */ + +/*********************** Timer Management Functions ***************************/ +/** +* @brief Create a timer. +* @param timer_def timer object referenced with \ref osTimer. +* @param type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +* @param argument argument to the timer call back function. +* @retval timer ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +*/ +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) +{ +#if (configUSE_TIMERS == 1) + +#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + if(timer_def->controlblock != NULL) { + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TimerCallbackFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); + } + else { + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TimerCallbackFunction_t)timer_def->ptimer); + } +#elif( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xTimerCreateStatic((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TimerCallbackFunction_t)timer_def->ptimer, + (StaticTimer_t *)timer_def->controlblock); +#else + return xTimerCreate((const char *)"", + 1, // period should be filled when starting the Timer using osTimerStart + (type == osTimerPeriodic) ? pdTRUE : pdFALSE, + (void *) argument, + (TimerCallbackFunction_t)timer_def->ptimer); +#endif + +#else + return NULL; +#endif +} + +/** +* @brief Start or restart a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate. +* @param millisec time delay value of the timer. +* @retval status code that indicates the execution status of the function +* @note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks = millisec / portTICK_PERIOD_MS; + + if (ticks == 0) + ticks = 1; + + if (inHandlerMode()) + { + if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS) + { + result = osErrorOS; + } + else + { + portEND_SWITCHING_ISR(taskWoken); + } + } + else + { + if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS) + result = osErrorOS; + } + +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Stop a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerStop (osTimerId timer_id) +{ + osStatus result = osOK; +#if (configUSE_TIMERS == 1) + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xTimerStop(timer_id, 0) != pdPASS) { + result = osErrorOS; + } + } +#else + result = osErrorOS; +#endif + return result; +} + +/** +* @brief Delete a timer. +* @param timer_id timer ID obtained by \ref osTimerCreate +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osTimerDelete (osTimerId timer_id) +{ +osStatus result = osOK; + +#if (configUSE_TIMERS == 1) + + if (inHandlerMode()) { + return osErrorISR; + } + else { + if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) { + result = osErrorOS; + } + } + +#else + result = osErrorOS; +#endif + + return result; +} + +/*************************** Signal Management ********************************/ +/** +* @brief Set the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that should be set. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalSet (osThreadId thread_id, int32_t signal) +{ +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + uint32_t ulPreviousNotificationValue = 0; + + if (inHandlerMode()) + { + if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS ) + return 0x80000000; + + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS ) + return 0x80000000; + + return ulPreviousNotificationValue; +#else + (void) thread_id; + (void) signal; + + return 0x80000000; /* Task Notification not supported */ +#endif +} + +/** +* @brief Clear the specified Signal Flags of an active thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @param signals specifies the signal flags of the thread that shall be cleared. +* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSignalClear (osThreadId thread_id, int32_t signal); + +/** +* @brief Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +* @param signals wait until all specified signal flags set or 0 for any single signal flag. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event flag information or error code. +* @note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +*/ +osEvent osSignalWait (int32_t signals, uint32_t millisec) +{ + osEvent ret; + +#if( configUSE_TASK_NOTIFICATIONS == 1 ) + + TickType_t ticks; + + ret.value.signals = 0; + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) + { + ret.status = osErrorISR; /*Not allowed in ISR*/ + } + else + { + if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE) + { + if(ticks == 0) ret.status = osOK; + else ret.status = osEventTimeout; + } + else if(ret.value.signals < 0) + { + ret.status = osErrorValue; + } + else ret.status = osEventSignal; + } +#else + (void) signals; + (void) millisec; + + ret.status = osErrorOS; /* Task Notification not supported */ +#endif + + return ret; +} + +/**************************** Mutex Management ********************************/ +/** +* @brief Create and Initialize a Mutex object +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +*/ +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) +{ +#if ( configUSE_MUTEXES == 1) + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL) { + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Wait until a Mutex becomes available +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (mutex_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Mutex that was obtained by \ref osMutexWait +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexRelease (osMutexId mutex_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreGive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +} + +/** +* @brief Delete a Mutex +* @param mutex_id mutex ID obtained by \ref osMutexCreate. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMutexDelete (osMutexId mutex_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(mutex_id); + + return osOK; +} + +/******************** Semaphore Management Functions **************************/ + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) + +/** +* @brief Create and Initialize a Semaphore object used for managing resources +* @param semaphore_def semaphore definition referenced with \ref osSemaphore. +* @param count number of available resources. +* @retval semaphore ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +*/ +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) +{ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + osSemaphoreId sema; + + if (semaphore_def->controlblock != NULL){ + if (count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } + } + else { + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) // configSUPPORT_DYNAMIC_ALLOCATION == 0 + if(count == 1) { + return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock ); + } + else + { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock ); +#else + return NULL; +#endif + } +#else // configSUPPORT_STATIC_ALLOCATION == 0 && configSUPPORT_DYNAMIC_ALLOCATION == 1 + osSemaphoreId sema; + + if (count == 1) { + vSemaphoreCreateBinary(sema); + return sema; + } + else { +#if (configUSE_COUNTING_SEMAPHORES == 1 ) + return xSemaphoreCreateCounting(count, count); +#else + return NULL; +#endif + } +#endif +} + +/** +* @brief Wait until a Semaphore token becomes available +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @param millisec timeout value or 0 in case of no time-out. +* @retval number of available tokens, or -1 in case of incorrect parameters. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +*/ +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +{ + TickType_t ticks; + portBASE_TYPE taskWoken = pdFALSE; + + + if (semaphore_id == NULL) { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) { + return osErrorOS; + } + + return osOK; +} + +/** +* @brief Release a Semaphore token +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) +{ + osStatus result = osOK; + portBASE_TYPE taskWoken = pdFALSE; + + + if (inHandlerMode()) { + if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xSemaphoreGive(semaphore_id) != pdTRUE) { + result = osErrorOS; + } + } + + return result; +} + +/** +* @brief Delete a Semaphore +* @param semaphore_id semaphore object referenced with \ref osSemaphore. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +*/ +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vSemaphoreDelete(semaphore_id); + + return osOK; +} + +#endif /* Use Semaphores */ + +/******************* Memory Pool Management Functions ***********************/ + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) + +//TODO +//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management. +//A better implementation will have to modify heap_x.c! + + +typedef struct os_pool_cb { + void *pool; + uint8_t *markers; + uint32_t pool_sz; + uint32_t item_sz; + uint32_t currentIndex; +} os_pool_cb_t; + + +/** +* @brief Create and Initialize a memory pool +* @param pool_def memory pool definition referenced with \ref osPool. +* @retval memory pool ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +*/ +osPoolId osPoolCreate (const osPoolDef_t *pool_def) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + osPoolId thePool; + int itemSize = 4 * ((pool_def->item_sz + 3) / 4); + uint32_t i; + + /* First have to allocate memory for the pool control block. */ + thePool = pvPortMalloc(sizeof(os_pool_cb_t)); + + + if (thePool) { + thePool->pool_sz = pool_def->pool_sz; + thePool->item_sz = itemSize; + thePool->currentIndex = 0; + + /* Memory for markers */ + thePool->markers = pvPortMalloc(pool_def->pool_sz); + + if (thePool->markers) { + /* Now allocate the pool itself. */ + thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize); + + if (thePool->pool) { + for (i = 0; i < pool_def->pool_sz; i++) { + thePool->markers[i] = 0; + } + } + else { + vPortFree(thePool->markers); + vPortFree(thePool); + thePool = NULL; + } + } + else { + vPortFree(thePool); + thePool = NULL; + } + } + + return thePool; + +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolAlloc (osPoolId pool_id) +{ + int dummy = 0; + void *p = NULL; + uint32_t i; + uint32_t index; + + if (inHandlerMode()) { + dummy = portSET_INTERRUPT_MASK_FROM_ISR(); + } + else { + vPortEnterCritical(); + } + + for (i = 0; i < pool_id->pool_sz; i++) { + index = (pool_id->currentIndex + i) % pool_id->pool_sz; + + if (pool_id->markers[index] == 0) { + pool_id->markers[index] = 1; + p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz)); + pool_id->currentIndex = index; + break; + } + } + + if (inHandlerMode()) { + portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy); + } + else { + vPortExitCritical(); + } + + return p; +} + +/** +* @brief Allocate a memory block from a memory pool and set memory block to zero +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @retval address of the allocated memory block or NULL in case of no memory available. +* @note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osPoolCAlloc (osPoolId pool_id) +{ + void *p = osPoolAlloc(pool_id); + + if (p != NULL) + { + memset(p, 0, sizeof(pool_id->pool_sz)); + } + + return p; +} + +/** +* @brief Return an allocated memory block back to a specific memory pool +* @param pool_id memory pool ID obtain referenced with \ref osPoolCreate. +* @param block address of the allocated memory block that is returned to the memory pool. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osPoolFree (osPoolId pool_id, void *block) +{ + uint32_t index; + + if (pool_id == NULL) { + return osErrorParameter; + } + + if (block == NULL) { + return osErrorParameter; + } + + if (block < pool_id->pool) { + return osErrorParameter; + } + + index = (uint32_t)block - (uint32_t)(pool_id->pool); + if (index % pool_id->item_sz) { + return osErrorParameter; + } + index = index / pool_id->item_sz; + if (index >= pool_id->pool_sz) { + return osErrorParameter; + } + + pool_id->markers[index] = 0; + + return osOK; +} + + +#endif /* Use Memory Pool Management */ + +/******************* Message Queue Management Functions *********************/ + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) /* Use Message Queues */ + +/** +* @brief Create and Initialize a Message Queue +* @param queue_def queue definition referenced with \ref osMessageQ. +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval message queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +*/ +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) +{ + (void) thread_id; + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) { + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); + } + else { + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock); +#else + return xQueueCreate(queue_def->queue_sz, queue_def->item_sz); +#endif +} + +/** +* @brief Put a Message to a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param info message information. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) +{ + portBASE_TYPE taskWoken = pdFALSE; + TickType_t ticks; + + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a Message or Wait for a Message from a Queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + event.value.v = 0; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMessage; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +#endif /* Use Message Queues */ + +/******************** Mail Queue Management Functions ***********************/ +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) /* Use Mail Queues */ + + +typedef struct os_mailQ_cb { + const osMailQDef_t *queue_def; + QueueHandle_t handle; + osPoolId pool; +} os_mailQ_cb_t; + +/** +* @brief Create and Initialize mail queue +* @param queue_def reference to the mail queue definition obtain with \ref osMailQ +* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +* @retval mail queue ID for reference by other functions or NULL in case of error. +* @note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +*/ +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) +{ +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + (void) thread_id; + + osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL}; + + /* Create a mail queue control block */ + + *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb)); + + if (*(queue_def->cb) == NULL) { + return NULL; + } + (*(queue_def->cb))->queue_def = queue_def; + + /* Create a queue in FreeRTOS */ + (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *)); + + + if ((*(queue_def->cb))->handle == NULL) { + vPortFree(*(queue_def->cb)); + return NULL; + } + + /* Create a mail pool */ + (*(queue_def->cb))->pool = osPoolCreate(&pool_def); + if ((*(queue_def->cb))->pool == NULL) { + //TODO: Delete queue. How to do it in FreeRTOS? + vPortFree(*(queue_def->cb)); + return NULL; + } + + return *(queue_def->cb); +#else + return NULL; +#endif +} + +/** +* @brief Allocate a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) +{ + (void) millisec; + void *p; + + + if (queue_id == NULL) { + return NULL; + } + + p = osPoolAlloc(queue_id->pool); + + return p; +} + +/** +* @brief Allocate a memory block from a mail and set memory block to zero +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval pointer to memory block that can be filled with mail or NULL in case error. +* @note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +*/ +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) +{ + uint32_t i; + void *p = osMailAlloc(queue_id, millisec); + + if (p) { + for (i = 0; i < queue_id->queue_def->item_sz; i++) { + ((uint8_t *)p)[i] = 0; + } + } + + return p; +} + +/** +* @brief Put a mail to a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailPut (osMailQId queue_id, void *mail) +{ + portBASE_TYPE taskWoken; + + + if (queue_id == NULL) { + return osErrorParameter; + } + + taskWoken = pdFALSE; + + if (inHandlerMode()) { + if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) { + return osErrorOS; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { + return osErrorOS; + } + } + + return osOK; +} + +/** +* @brief Get a mail from a queue +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param millisec timeout value or 0 in case of no time-out +* @retval event that contains mail information or error code. +* @note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +*/ +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) +{ + portBASE_TYPE taskWoken; + TickType_t ticks; + osEvent event; + + event.def.mail_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + taskWoken = pdFALSE; + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (inHandlerMode()) { + if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = osOK; + } + portEND_SWITCHING_ISR(taskWoken); + } + else { + if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) { + /* We have mail */ + event.status = osEventMail; + } + else { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + } + + return event; +} + +/** +* @brief Free a memory block from a mail +* @param queue_id mail queue ID obtained with \ref osMailCreate. +* @param mail pointer to the memory block that was obtained with \ref osMailGet. +* @retval status code that indicates the execution status of the function. +* @note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +*/ +osStatus osMailFree (osMailQId queue_id, void *mail) +{ + if (queue_id == NULL) { + return osErrorParameter; + } + + return osPoolFree(queue_id->pool, mail); +} +#endif /* Use Mail Queues */ + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void) +{ + +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + } +#endif /* INCLUDE_xTaskGetSchedulerState */ +} + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id) +{ + eTaskState ThreadState; + osThreadState result; + + ThreadState = eTaskGetState(thread_id); + + switch (ThreadState) + { + case eRunning : + result = osThreadRunning; + break; + case eReady : + result = osThreadReady; + break; + case eBlocked : + result = osThreadBlocked; + break; + case eSuspended : + result = osThreadSuspended; + break; + case eDeleted : + result = osThreadDeleted; + break; + default: + result = osThreadError; + } + + return result; +} +#endif /* INCLUDE_eTaskGetState */ + +#if (INCLUDE_eTaskGetState == 1) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadIsSuspended(osThreadId thread_id) +{ + if (eTaskGetState(thread_id) == eSuspended) + return osOK; + else + return osErrorOS; +} +#endif /* INCLUDE_eTaskGetState */ +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + vTaskSuspend(thread_id); + + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id) +{ +#if (INCLUDE_vTaskSuspend == 1) + if(inHandlerMode()) + { + if (xTaskResumeFromISR(thread_id) == pdTRUE) + { + portYIELD_FROM_ISR(pdTRUE); + } + } + else + { + vTaskResume(thread_id); + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void) +{ + vTaskSuspendAll(); + + return osOK; +} + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void) +{ + if (xTaskResumeAll() == pdTRUE) + return osOK; + else + return osErrorOS; + +} + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec) +{ +#if INCLUDE_vTaskDelayUntil + TickType_t ticks = (millisec / portTICK_PERIOD_MS); + vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1); + + return osOK; +#else + (void) millisec; + (void) PreviousWakeTime; + + return osErrorResource; +#endif +} + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id) +{ +#if INCLUDE_xTaskAbortDelay + + xTaskAbortDelay(thread_id); + + return osOK; +#else + (void) thread_id; + + return osErrorResource; +#endif +} + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer) +{ +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) + vTaskList((char *)buffer); +#endif + return osOK; +} + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec) +{ + TickType_t ticks; + osEvent event; + + event.def.message_id = queue_id; + + if (queue_id == NULL) { + event.status = osErrorParameter; + return event; + } + + ticks = 0; + if (millisec == osWaitForever) { + ticks = portMAX_DELAY; + } + else if (millisec != 0) { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) { + ticks = 1; + } + } + + if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) + { + /* We have mail */ + event.status = osEventMessage; + } + else + { + event.status = (ticks == 0) ? osOK : osEventTimeout; + } + + return event; +} + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id) +{ + if (inHandlerMode()) { + return uxQueueMessagesWaitingFromISR(queue_id); + } + else + { + return uxQueueMessagesWaiting(queue_id); + } +} + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id) +{ + return uxQueueSpacesAvailable(queue_id); +} + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id) +{ + if (inHandlerMode()) { + return osErrorISR; + } + + vQueueDelete(queue_id); + + return osOK; +} + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + if (mutex_def->controlblock != NULL){ + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); + } + else { + return xSemaphoreCreateRecursiveMutex(); + } +#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) + return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock ); +#else + return xSemaphoreCreateRecursiveMutex(); +#endif +#else + return NULL; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + osStatus result = osOK; + + if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) + { + result = osErrorOS; + } + return result; +#else + return osErrorResource; +#endif +} + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec) +{ +#if (configUSE_RECURSIVE_MUTEXES == 1) + TickType_t ticks; + + if (mutex_id == NULL) + { + return osErrorParameter; + } + + ticks = 0; + if (millisec == osWaitForever) + { + ticks = portMAX_DELAY; + } + else if (millisec != 0) + { + ticks = millisec / portTICK_PERIOD_MS; + if (ticks == 0) + { + ticks = 1; + } + } + + if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) + { + return osErrorOS; + } + return osOK; +#else + return osErrorResource; +#endif +} + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id) +{ + return uxSemaphoreGetCount(semaphore_id); +} diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h new file mode 100644 index 0000000..1fb4186 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -0,0 +1,1026 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * + * + *---------------------------------------------------------------------------- + * + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" +#include "semphr.h" +#include "event_groups.h" + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used throughout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 1 ///< osFeature_Semaphore function: 1=available, 0=not available +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + +#if ( INCLUDE_eTaskGetState == 1 ) +/* Thread state returned by osThreadGetState */ +typedef enum { + osThreadRunning = 0x0, /* A thread is querying the state of itself, so must be running. */ + osThreadReady = 0x1 , /* The thread being queried is in a read or pending ready list. */ + osThreadBlocked = 0x2, /* The thread being queried is in the Blocked state. */ + osThreadSuspended = 0x3, /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + osThreadDeleted = 0x4, /* The thread being queried has been deleted, but its TCB has not yet been freed. */ + osThreadError = 0x7FFFFFFF +} osThreadState; +#endif /* INCLUDE_eTaskGetState */ + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef TaskHandle_t osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef TimerHandle_t osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef SemaphoreHandle_t osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef QueueHandle_t osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + +typedef StaticTask_t osStaticThreadDef_t; +typedef StaticTimer_t osStaticTimerDef_t; +typedef StaticSemaphore_t osStaticMutexDef_t; +typedef StaticSemaphore_t osStaticSemaphoreDef_t; +typedef StaticQueue_t osStaticMessageQDef_t; + +#endif + + + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + char *name; ///< Thread name + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint32_t *buffer; ///< stack buffer for static allocation; NULL for dynamic allocation + osStaticThreadDef_t *controlblock; ///< control block to hold thread's data for static allocation; NULL for dynamic allocation +#endif +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticTimerDef_t *controlblock; ///< control block to hold timer's data for static allocation; NULL for dynamic allocation +#endif +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticMutexDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + osStaticSemaphoreDef_t *controlblock; ///< control block for static allocation; NULL for dynamic allocation +#endif +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + uint8_t *buffer; ///< buffer for static allocation; NULL for dynamic allocation + osStaticMessageQDef_t *controlblock; ///< control block to hold queue's data for static allocation; NULL for dynamic allocation +#endif + //void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + struct os_mailQ_cb **cb; +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency (configTICK_RATE_HZ) + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, thread, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL } + +#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz), (buffer), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 + +#define osThreadDef(name, thread, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ #name, (thread), (priority), (instances), (stacksz)} +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +#define osTimerStaticDef(name, function, control) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return osOK if successful, osErrorOS if failed. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0, NULL } + +#define osMutexStaticDef(name, control) \ +const osMutexDef_t os_mutex_def_##name = { 0, (control) } +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } + +#endif + +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL } + +#define osSemaphoreStaticDef(name, control) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) } + +#else //configSUPPORT_STATIC_ALLOCATION == 0 +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type), NULL, NULL } + +#define osMessageQStaticDef(name, queue_sz, type, buffer, control) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) , (buffer), (control)} +#else //configSUPPORT_STATIC_ALLOCATION == 1 +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } + +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern struct os_mailQ_cb *os_mailQ_cb_##name \ +extern osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +struct os_mailQ_cb *os_mailQ_cb_##name; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + +/*************************** Additional specific APIs to Free RTOS ************/ +/** +* @brief Handles the tick increment +* @param none. +* @retval none. +*/ +void osSystickHandler(void); + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Obtain the state of any thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval the stae of the thread, states are encoded by the osThreadState enumerated type. +*/ +osThreadState osThreadGetState(osThreadId thread_id); +#endif /* INCLUDE_eTaskGetState */ + +#if ( INCLUDE_eTaskGetState == 1 ) +/** +* @brief Check if a thread is already suspended or not. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ + +osStatus osThreadIsSuspended(osThreadId thread_id); + +#endif /* INCLUDE_eTaskGetState */ + +/** +* @brief Suspend execution of a thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspend (osThreadId thread_id); + +/** +* @brief Resume execution of a suspended thread. +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResume (osThreadId thread_id); + +/** +* @brief Suspend execution of a all active threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadSuspendAll (void); + +/** +* @brief Resume execution of a all suspended threads. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadResumeAll (void); + +/** +* @brief Delay a task until a specified time +* @param PreviousWakeTime Pointer to a variable that holds the time at which the +* task was last unblocked. PreviousWakeTime must be initialised with the current time +* prior to its first use (PreviousWakeTime = osKernelSysTick() ) +* @param millisec time delay value +* @retval status code that indicates the execution status of the function. +*/ +osStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec); + +/** +* @brief Abort the delay for a specific thread +* @param thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId +* @retval status code that indicates the execution status of the function. +*/ +osStatus osAbortDelay(osThreadId thread_id); + +/** +* @brief Lists all the current threads, along with their current state +* and stack usage high water mark. +* @param buffer A buffer into which the above mentioned details +* will be written +* @retval status code that indicates the execution status of the function. +*/ +osStatus osThreadList (uint8_t *buffer); + +/** +* @brief Receive an item from a queue without removing the item from the queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval event information that includes status code. +*/ +osEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec); + +/** +* @brief Get the number of messaged stored in a queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval number of messages stored in a queue. +*/ +uint32_t osMessageWaiting(osMessageQId queue_id); + +/** +* @brief Get the available space in a message queue. +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval available space in a message queue. +*/ +uint32_t osMessageAvailableSpace(osMessageQId queue_id); + +/** +* @brief Delete a Message Queue +* @param queue_id message queue ID obtained with \ref osMessageCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osMessageDelete (osMessageQId queue_id); + +/** +* @brief Create and Initialize a Recursive Mutex +* @param mutex_def mutex definition referenced with \ref osMutex. +* @retval mutex ID for reference by other functions or NULL in case of error.. +*/ +osMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexRelease (osMutexId mutex_id); + +/** +* @brief Release a Recursive Mutex +* @param mutex_id mutex ID obtained by \ref osRecursiveMutexCreate. +* @param millisec timeout value or 0 in case of no time-out. +* @retval status code that indicates the execution status of the function. +*/ +osStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec); + +/** +* @brief Returns the current count value of a counting semaphore +* @param semaphore_id semaphore_id ID obtained by \ref osSemaphoreCreate. +* @retval count value +*/ +uint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id); + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c new file mode 100644 index 0000000..565691b --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c new file mode 100644 index 0000000..81c1965 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t const * const pxEventBits = xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t const * pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h new file mode 100644 index 0000000..45c778a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -0,0 +1,1278 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void *pvDummy5; + TaskFunction_t pvDummy6; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h new file mode 100644 index 0000000..000d866 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h new file mode 100644 index 0000000..a781749 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
+ void vCoRoutineSchedule( void );
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ crSTART( CoRoutineHandle_t xHandle );
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
+ crEND();
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h new file mode 100644 index 0000000..4d0ce01 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h new file mode 100644 index 0000000..522b0b6 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -0,0 +1,757 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
+ */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h new file mode 100644 index 0000000..b2bb46d --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -0,0 +1,412 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h new file mode 100644 index 0000000..9ee3f4d --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -0,0 +1,799 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
+
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+

+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+

+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+

+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+

+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+

+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+

+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 

+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..f0b3337
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,157 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..56d9c7e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,186 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGetIdleRunTimeCounter				MPU_xTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a1bb449
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..dbcf9bb
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..5072c45
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 

+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 

+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 

+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 

+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 

+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );

+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);

+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);

+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 

+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
void vQueueDelete( QueueHandle_t xQueue );

+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 

+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 

+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 

+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 

+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+ 

+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 

+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 

+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..32b4e5e
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 

+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )

+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 

+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )

+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 

+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 

+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 

+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..fb5ed15
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..5f9e012
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,855 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+

+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+

+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+

+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
+
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+

+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+

+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+

+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+

+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+

+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+

+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+

+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+

+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+

+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..4041bbf
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2421 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.2.0"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+   

+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );

+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   

+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   

+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   

+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelete( TaskHandle_t xTask );

+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   

+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskDelay( const TickType_t xTicksToDelay );

+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   

+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   

+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
eTaskState eTaskGetState( TaskHandle_t xTask );

+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   

+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   

+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   

+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskResume( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   

+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
void vTaskStartScheduler( void );

+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   

+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskEndScheduler( void );

+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   

+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskSuspendAll( void );

+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   

+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskResumeAll( void );

+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   

+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCount( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
TickType_t xTaskGetTickCountFromISR( void );

+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint16_t uxTaskGetNumberOfTasks( void );

+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	

+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
void vTaskList( char *pcWriteBuffer );

+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
TickType_t xTaskGetIdleRunTimeCounter( void );

+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..5abb7f1
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1295 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..9875b90
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..b5f5b65
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -0,0 +1,765 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	cpsid i								\n" /* Errata workaround. */
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	cpsie i								\n" /* Errata workaround. */
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( &xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrpts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..1d7d653
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,247 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	cpsid i													\n" \
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		"	cpsie i													\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	cpsid i													\n" \
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		"	cpsie i													\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..23714eb
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,436 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..6f79c92
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2941 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		}
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..8cda238
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f9c4eb6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5214 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = { 0 };/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = { 0 };						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = { 0 };						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = { 0 };						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+PRIVILEGED_DATA static List_t xTasksWaitingTermination = { 0 };				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList = { 0 };					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+
+			traceTASK_DELETE( pxTCB );
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+						uxPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( uxPendedTicks == ( UBaseType_t ) 0U )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+		{
+			xSwitchRequired = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+	TickType_t xTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..ea04327
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1102 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = { 0 };
+PRIVILEGED_DATA static List_t xActiveTimerList2 = { 0 };
+PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The autoreload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			autoreload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/STM32F746NGHX_FLASH.ld b/STM32F746NGHX_FLASH.ld
new file mode 100644
index 0000000..0f79995
--- /dev/null
+++ b/STM32F746NGHX_FLASH.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ *  Abstract    : Linker script for STM32F746G-DISCO Board embedding STM32F746NGHx Device from stm32f7 series
+ *                      1024Kbytes FLASH
+ *                      320Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * 
© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.

+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 320K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/STM32F746NGHX_RAM.ld b/STM32F746NGHX_RAM.ld
new file mode 100644
index 0000000..cdd8d19
--- /dev/null
+++ b/STM32F746NGHX_RAM.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ *  Abstract    : Linker script for STM32F746G-DISCO Board embedding STM32F746NGHx Device from stm32f7 series
+ *                      1024Kbytes FLASH
+ *                      320Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * 
© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.

+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 320K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "RAM" Ram type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM
+
+  /* The program code and other data into "RAM" Ram type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM
+
+  /* Constant data into "RAM" Ram type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >RAM
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >RAM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >RAM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/Space_Invaders.ioc b/Space_Invaders.ioc
new file mode 100644
index 0000000..d755d76
--- /dev/null
+++ b/Space_Invaders.ioc
@@ -0,0 +1,930 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_0
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag
+ADC1.NbrOfConversionFlag=1
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
+ADC1.master=1
+ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_6
+ADC3.Channel-IN4=ADC_CHANNEL_4
+ADC3.Channel-IN5=ADC_CHANNEL_5
+ADC3.IPParameters=Channel-IN5,Channel-0\#ChannelRegularConversion,Channel-IN4
+FREERTOS.FootprintOK=true
+FREERTOS.IPParameters=Tasks01,configUSE_APPLICATION_TASK_TAG,configUSE_RECURSIVE_MUTEXES,configUSE_COUNTING_SEMAPHORES,configUSE_IDLE_HOOK,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configTOTAL_HEAP_SIZE,FootprintOK
+FREERTOS.Tasks01=defaultTask,0,4096,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
+FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
+FREERTOS.configTOTAL_HEAP_SIZE=32768
+FREERTOS.configUSE_APPLICATION_TASK_TAG=1
+FREERTOS.configUSE_COUNTING_SEMAPHORES=1
+FREERTOS.configUSE_IDLE_HOOK=1
+FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
+FREERTOS.configUSE_RECURSIVE_MUTEXES=1
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+I2C1.IPParameters=Timing
+I2C1.Timing=0x00C0EAFF
+I2C3.IPParameters=Timing
+I2C3.Timing=0x00C0EAFF
+KeepUserPlacement=false
+LTDC.ActiveH=272
+LTDC.ActiveW=480
+LTDC.Alpha_L0=255
+LTDC.BlendingFactor1_L0=LTDC_BLENDING_FACTOR1_PAxCA
+LTDC.BlendingFactor2_L0=LTDC_BLENDING_FACTOR2_PAxCA
+LTDC.FBStartAdress_L0=0xC0000000
+LTDC.HBP=13
+LTDC.HFP=32
+LTDC.HSync=41
+LTDC.IPParameters=ActiveW,ActiveH,HSync,HBP,HFP,VSync,Layers,WindowX1_L0,WindowY1_L0,Alpha_L0,BlendingFactor1_L0,BlendingFactor2_L0,FBStartAdress_L0,ImageWidth_L0,PixelFormat_L0,ImageHeight_L0
+LTDC.ImageHeight_L0=272
+LTDC.ImageWidth_L0=480
+LTDC.Layers=0
+LTDC.PixelFormat_L0=LTDC_PIXEL_FORMAT_RGB565
+LTDC.VSync=10
+LTDC.WindowX1_L0=480
+LTDC.WindowY1_L0=272
+Mcu.Family=STM32F7
+Mcu.IP0=ADC1
+Mcu.IP1=ADC3
+Mcu.IP10=NVIC
+Mcu.IP11=RCC
+Mcu.IP12=RTC
+Mcu.IP13=SPI2
+Mcu.IP14=SYS
+Mcu.IP15=TIM1
+Mcu.IP16=TIM2
+Mcu.IP17=TIM3
+Mcu.IP18=TIM5
+Mcu.IP19=TIM8
+Mcu.IP2=CORTEX_M7
+Mcu.IP20=UART7
+Mcu.IP21=USART1
+Mcu.IP22=USART6
+Mcu.IP3=DAC
+Mcu.IP4=DMA2D
+Mcu.IP5=FMC
+Mcu.IP6=FREERTOS
+Mcu.IP7=I2C1
+Mcu.IP8=I2C3
+Mcu.IP9=LTDC
+Mcu.IPNb=23
+Mcu.Name=STM32F746NGHx
+Mcu.Package=TFBGA216
+Mcu.Pin0=PE4
+Mcu.Pin1=PE3
+Mcu.Pin10=PE5
+Mcu.Pin100=PG0
+Mcu.Pin101=PJ3
+Mcu.Pin102=PE8
+Mcu.Pin103=PG5
+Mcu.Pin104=PG4
+Mcu.Pin105=PH7
+Mcu.Pin106=PH9
+Mcu.Pin107=PH11
+Mcu.Pin108=PA5
+Mcu.Pin109=PF14
+Mcu.Pin11=PE6
+Mcu.Pin110=PJ2
+Mcu.Pin111=PF11
+Mcu.Pin112=PE9
+Mcu.Pin113=PE11
+Mcu.Pin114=PE14
+Mcu.Pin115=PH6
+Mcu.Pin116=PH8
+Mcu.Pin117=PH10
+Mcu.Pin118=PA3
+Mcu.Pin119=PB1
+Mcu.Pin12=PB9
+Mcu.Pin120=PB0
+Mcu.Pin121=PJ0
+Mcu.Pin122=PJ1
+Mcu.Pin123=PE7
+Mcu.Pin124=PE10
+Mcu.Pin125=PE12
+Mcu.Pin126=PE15
+Mcu.Pin127=PE13
+Mcu.Pin128=PB11
+Mcu.Pin129=PB14
+Mcu.Pin13=PB7
+Mcu.Pin130=PB15
+Mcu.Pin131=VP_DMA2D_VS_DMA2D
+Mcu.Pin132=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin133=VP_RTC_VS_RTC_Activate
+Mcu.Pin134=VP_RTC_VS_RTC_Calendar
+Mcu.Pin135=VP_RTC_VS_RTC_Alarm_B_Intern
+Mcu.Pin136=VP_RTC_VS_RTC_Alarm_A_Intern
+Mcu.Pin137=VP_SYS_VS_tim6
+Mcu.Pin138=VP_TIM1_VS_ClockSourceINT
+Mcu.Pin139=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin14=PG15
+Mcu.Pin140=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin141=VP_TIM3_VS_ClockSourceITR
+Mcu.Pin142=VP_TIM5_VS_ClockSourceINT
+Mcu.Pin143=VP_TIM8_VS_ClockSourceINT
+Mcu.Pin15=PJ13
+Mcu.Pin16=PJ12
+Mcu.Pin17=PD6
+Mcu.Pin18=PD0
+Mcu.Pin19=PI8
+Mcu.Pin2=PE1
+Mcu.Pin20=PK7
+Mcu.Pin21=PK6
+Mcu.Pin22=PK5
+Mcu.Pin23=PG12
+Mcu.Pin24=PJ14
+Mcu.Pin25=PD5
+Mcu.Pin26=PD3
+Mcu.Pin27=PD1
+Mcu.Pin28=PI3
+Mcu.Pin29=PI2
+Mcu.Pin3=PE0
+Mcu.Pin30=PC13
+Mcu.Pin31=PF0
+Mcu.Pin32=PI10
+Mcu.Pin33=PK4
+Mcu.Pin34=PK3
+Mcu.Pin35=PJ15
+Mcu.Pin36=PD4
+Mcu.Pin37=PH15
+Mcu.Pin38=PI1
+Mcu.Pin39=PC14/OSC32_IN
+Mcu.Pin4=PB8
+Mcu.Pin40=PF1
+Mcu.Pin41=PI12
+Mcu.Pin42=PI9
+Mcu.Pin43=PH14
+Mcu.Pin44=PI0
+Mcu.Pin45=PA9
+Mcu.Pin46=PC15/OSC32_OUT
+Mcu.Pin47=PK1
+Mcu.Pin48=PK2
+Mcu.Pin49=PA8
+Mcu.Pin5=PB5
+Mcu.Pin50=PH0/OSC_IN
+Mcu.Pin51=PF2
+Mcu.Pin52=PI13
+Mcu.Pin53=PI15
+Mcu.Pin54=PJ11
+Mcu.Pin55=PK0
+Mcu.Pin56=PC7
+Mcu.Pin57=PH1/OSC_OUT
+Mcu.Pin58=PF3
+Mcu.Pin59=PI14
+Mcu.Pin6=PB4
+Mcu.Pin60=PH4
+Mcu.Pin61=PJ8
+Mcu.Pin62=PJ10
+Mcu.Pin63=PG8
+Mcu.Pin64=PC6
+Mcu.Pin65=PF4
+Mcu.Pin66=PH5
+Mcu.Pin67=PH3
+Mcu.Pin68=PJ7
+Mcu.Pin69=PJ9
+Mcu.Pin7=PA15
+Mcu.Pin70=PG7
+Mcu.Pin71=PF7
+Mcu.Pin72=PF6
+Mcu.Pin73=PF5
+Mcu.Pin74=PH2
+Mcu.Pin75=PJ6
+Mcu.Pin76=PD15
+Mcu.Pin77=PB13
+Mcu.Pin78=PD10
+Mcu.Pin79=PF10
+Mcu.Pin8=PA14
+Mcu.Pin80=PF9
+Mcu.Pin81=PF8
+Mcu.Pin82=PC3
+Mcu.Pin83=PD14
+Mcu.Pin84=PB12
+Mcu.Pin85=PD9
+Mcu.Pin86=PD8
+Mcu.Pin87=PC0
+Mcu.Pin88=PC2
+Mcu.Pin89=PF12
+Mcu.Pin9=PA13
+Mcu.Pin90=PG1
+Mcu.Pin91=PF15
+Mcu.Pin92=PJ4
+Mcu.Pin93=PG3
+Mcu.Pin94=PG2
+Mcu.Pin95=PJ5
+Mcu.Pin96=PH12
+Mcu.Pin97=PA0/WKUP
+Mcu.Pin98=PA4
+Mcu.Pin99=PF13
+Mcu.PinsNb=144
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F746NGHx
+MxCube.Version=6.1.1
+MxDb.Version=DB.6.0.10
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.LTDC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+NVIC.SavedPendsvIrqHandlerGenerated=true
+NVIC.SavedSvcallIrqHandlerGenerated=true
+NVIC.SavedSystickIrqHandlerGenerated=true
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
+NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.TimeBase=TIM6_DAC_IRQn
+NVIC.TimeBaseIP=TIM6
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA0/WKUP.Locked=true
+PA0/WKUP.Signal=ADCx_IN0
+PA13.GPIOParameters=GPIO_Label
+PA13.GPIO_Label=SWDIO
+PA13.Locked=true
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.GPIOParameters=GPIO_Label
+PA14.GPIO_Label=SWCLK
+PA14.Locked=true
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA15.GPIOParameters=GPIO_Label
+PA15.GPIO_Label=BP2
+PA15.Locked=true
+PA15.Signal=GPIO_Input
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=ULPI_D0 [USB3320C-EZK_D0]
+PA3.Locked=true
+PA3.Mode=Host_HS
+PA3.Signal=USB_OTG_HS_ULPI_D0
+PA4.Locked=true
+PA4.Signal=COMP_DAC1_group
+PA5.GPIOParameters=GPIO_Label
+PA5.GPIO_Label=ULPI_CLK [USB3320C-EZK_CLKOUT]
+PA5.Locked=true
+PA5.Mode=Host_HS
+PA5.Signal=USB_OTG_HS_ULPI_CK
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=BP1
+PA8.Locked=true
+PA8.Signal=GPIO_Input
+PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PA9.GPIO_Label=VCP_TX [STM32F103CBT6_PA3]
+PA9.GPIO_Mode=GPIO_MODE_AF_PP
+PA9.GPIO_PuPd=GPIO_NOPULL
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA9.Locked=true
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=ULPI_D1 [USB3320C-EZK_D1]
+PB0.Locked=true
+PB0.Mode=Host_HS
+PB0.Signal=USB_OTG_HS_ULPI_D1
+PB1.GPIOParameters=GPIO_Label
+PB1.GPIO_Label=ULPI_D2 [USB3320C-EZK_D2]
+PB1.Locked=true
+PB1.Mode=Host_HS
+PB1.Signal=USB_OTG_HS_ULPI_D2
+PB11.GPIOParameters=GPIO_Label
+PB11.GPIO_Label=ULPI_D4 [USB3320C-EZK_D4]
+PB11.Locked=true
+PB11.Mode=Host_HS
+PB11.Signal=USB_OTG_HS_ULPI_D4
+PB12.GPIOParameters=GPIO_Label
+PB12.GPIO_Label=ULPI_D5 [USB3320C-EZK_D5]
+PB12.Locked=true
+PB12.Mode=Host_HS
+PB12.Signal=USB_OTG_HS_ULPI_D5
+PB13.GPIOParameters=GPIO_Label
+PB13.GPIO_Label=ULPI_D6 [USB3320C-EZK_D6]
+PB13.Locked=true
+PB13.Mode=Host_HS
+PB13.Signal=USB_OTG_HS_ULPI_D6
+PB14.Locked=true
+PB14.Mode=Full_Duplex_Master
+PB14.Signal=SPI2_MISO
+PB15.Locked=true
+PB15.Mode=Full_Duplex_Master
+PB15.Signal=SPI2_MOSI
+PB4.Locked=true
+PB4.Signal=S_TIM3_CH1
+PB5.GPIOParameters=GPIO_Label
+PB5.GPIO_Label=ULPI_D7 [USB3320C-EZK_D7]
+PB5.Locked=true
+PB5.Mode=Host_HS
+PB5.Signal=USB_OTG_HS_ULPI_D7
+PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB7.GPIO_Label=VCP_RX [STM32F103CBT6_PA2]
+PB7.GPIO_Mode=GPIO_MODE_AF_PP
+PB7.GPIO_PuPd=GPIO_NOPULL
+PB7.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB7.Locked=true
+PB7.Mode=Asynchronous
+PB7.Signal=USART1_RX
+PB8.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB8.GPIO_Label=ARDUINO SCL/D15
+PB8.GPIO_Mode=GPIO_MODE_AF_OD
+PB8.GPIO_PuPd=GPIO_NOPULL
+PB8.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB8.Locked=true
+PB8.Mode=I2C
+PB8.Signal=I2C1_SCL
+PB9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PB9.GPIO_Label=ARDUINO SDA/D14
+PB9.GPIO_Mode=GPIO_MODE_AF_OD
+PB9.GPIO_PuPd=GPIO_NOPULL
+PB9.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PB9.Locked=true
+PB9.Mode=I2C
+PB9.Signal=I2C1_SDA
+PC0.GPIOParameters=GPIO_Label
+PC0.GPIO_Label=ULPI_STP [USB3320C-EZK_STP]
+PC0.Locked=true
+PC0.Mode=Host_HS
+PC0.Signal=USB_OTG_HS_ULPI_STP
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=uSD_Detect
+PC13.Locked=true
+PC13.Signal=GPIO_Input
+PC14/OSC32_IN.GPIOParameters=GPIO_Label
+PC14/OSC32_IN.GPIO_Label=RCC_OSC32_IN
+PC14/OSC32_IN.Locked=true
+PC14/OSC32_IN.Mode=LSE-External-Oscillator
+PC14/OSC32_IN.Signal=RCC_OSC32_IN
+PC15/OSC32_OUT.GPIOParameters=GPIO_Label
+PC15/OSC32_OUT.GPIO_Label=RCC_OSC32_OUT
+PC15/OSC32_OUT.Locked=true
+PC15/OSC32_OUT.Mode=LSE-External-Oscillator
+PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
+PC2.GPIOParameters=GPIO_Label
+PC2.GPIO_Label=ULPI_DIR [USB3320C-EZK_DIR]
+PC2.Locked=true
+PC2.Mode=Host_HS
+PC2.Signal=USB_OTG_HS_ULPI_DIR
+PC3.Mode=SdramChipSelect1_1
+PC3.Signal=FMC_SDCKE0
+PC6.Locked=true
+PC6.Mode=Asynchronous
+PC6.Signal=USART6_TX
+PC7.Locked=true
+PC7.Mode=Asynchronous
+PC7.Signal=USART6_RX
+PD0.Signal=FMC_D2_DA2
+PD1.Signal=FMC_D3_DA3
+PD10.Signal=FMC_D15_DA15
+PD14.Signal=FMC_D0_DA0
+PD15.Signal=FMC_D1_DA1
+PD3.GPIOParameters=GPIO_Label
+PD3.GPIO_Label=LED16
+PD3.Locked=true
+PD3.Signal=GPIO_Output
+PD4.GPIOParameters=GPIO_Label
+PD4.GPIO_Label=OTG_FS_OverCurrent [STMPS2141STR_Fault]
+PD4.Locked=true
+PD4.Signal=GPIO_Input
+PD5.GPIOParameters=PinState,GPIO_Label
+PD5.GPIO_Label=OTG_FS_PowerSwitchOn [STMPS2141STR_EN]
+PD5.Locked=true
+PD5.PinState=GPIO_PIN_SET
+PD5.Signal=GPIO_Output
+PD6.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
+PD6.GPIO_Label=Audio_INT
+PD6.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING
+PD6.Locked=true
+PD6.Signal=GPXTI6
+PD8.Signal=FMC_D13_DA13
+PD9.Signal=FMC_D14_DA14
+PE0.Signal=FMC_NBL0
+PE1.Signal=FMC_NBL1
+PE10.Signal=FMC_D7_DA7
+PE11.Signal=FMC_D8_DA8
+PE12.Signal=FMC_D9_DA9
+PE13.Signal=FMC_D10_DA10
+PE14.Signal=FMC_D11_DA11
+PE15.Signal=FMC_D12_DA12
+PE3.Locked=true
+PE3.Signal=GPIO_Input
+PE4.GPIOParameters=GPIO_Label
+PE4.GPIO_Label=LCD_B0 [RK043FN48H-CT672B_B0]
+PE4.Locked=true
+PE4.Mode=RGB888
+PE4.Signal=LTDC_B0
+PE5.GPIOParameters=GPIO_Label
+PE5.GPIO_Label=LED14
+PE5.Locked=true
+PE5.Signal=GPIO_Output
+PE6.GPIOParameters=GPIO_Label
+PE6.GPIO_Label=LED15
+PE6.Locked=true
+PE6.Signal=GPIO_Output
+PE7.Signal=FMC_D4_DA4
+PE8.Signal=FMC_D5_DA5
+PE9.Signal=FMC_D6_DA6
+PF0.Signal=FMC_A0
+PF1.Signal=FMC_A1
+PF10.Locked=true
+PF10.Mode=IN8
+PF10.Signal=ADC3_IN8
+PF11.Signal=FMC_SDNRAS
+PF12.Signal=FMC_A6
+PF13.Signal=FMC_A7
+PF14.Signal=FMC_A8
+PF15.Signal=FMC_A9
+PF2.Signal=FMC_A2
+PF3.Signal=FMC_A3
+PF4.Signal=FMC_A4
+PF5.Signal=FMC_A5
+PF6.Mode=Asynchronous
+PF6.Signal=UART7_RX
+PF7.Locked=true
+PF7.Mode=Asynchronous
+PF7.Signal=UART7_TX
+PF8.Locked=true
+PF8.Mode=IN6
+PF8.Signal=ADC3_IN6
+PF9.Locked=true
+PF9.Mode=IN7
+PF9.Signal=ADC3_IN7
+PG0.Signal=FMC_A10
+PG1.Signal=FMC_A11
+PG12.GPIOParameters=GPIO_Label
+PG12.GPIO_Label=LCD_B4 [RK043FN48H-CT672B_B4]
+PG12.Locked=true
+PG12.Mode=RGB888
+PG12.Signal=LTDC_B4
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=RMII_RXER
+PG2.Locked=true
+PG2.Signal=GPIO_Input
+PG3.GPIOParameters=GPIO_Label
+PG3.GPIO_Label=EXT_RST
+PG3.Locked=true
+PG3.Signal=GPIO_Output
+PG4.Signal=FMC_A14_BA0
+PG5.Signal=FMC_A15_BA1
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=BP_JOYSTICK
+PG7.Locked=true
+PG7.Signal=GPIO_Input
+PG8.Signal=FMC_SDCLK
+PH0/OSC_IN.GPIOParameters=GPIO_Label
+PH0/OSC_IN.GPIO_Label=OSC_25M [NZ2520SB-25.00M_OUT]
+PH0/OSC_IN.Locked=true
+PH0/OSC_IN.Mode=HSE-External-Oscillator
+PH0/OSC_IN.Signal=RCC_OSC_IN
+PH1/OSC_OUT.Locked=true
+PH1/OSC_OUT.Mode=HSE-External-Oscillator
+PH1/OSC_OUT.Signal=RCC_OSC_OUT
+PH10.GPIOParameters=GPIO_Label
+PH10.GPIO_Label=LED18
+PH10.Locked=true
+PH10.Signal=GPIO_Output
+PH11.GPIOParameters=GPIO_Label
+PH11.GPIO_Label=LED12
+PH11.Locked=true
+PH11.Signal=GPIO_Output
+PH12.GPIOParameters=GPIO_Label
+PH12.GPIO_Label=LED17
+PH12.Locked=true
+PH12.Signal=GPIO_Output
+PH14.GPIOParameters=GPIO_Label
+PH14.GPIO_Label=LED13
+PH14.Locked=true
+PH14.Signal=GPIO_Output
+PH15.GPIOParameters=GPIO_Label
+PH15.GPIO_Label=TP3
+PH15.Locked=true
+PH15.Signal=GPIO_Input
+PH2.GPIOParameters=GPIO_Label
+PH2.GPIO_Label=NC2
+PH2.Locked=true
+PH2.Signal=GPIO_Input
+PH3.Mode=SdramChipSelect1_1
+PH3.Signal=FMC_SDNE0
+PH4.GPIOParameters=GPIO_Label
+PH4.GPIO_Label=ULPI_NXT [USB3320C-EZK_NXT]
+PH4.Locked=true
+PH4.Mode=Host_HS
+PH4.Signal=USB_OTG_HS_ULPI_NXT
+PH5.Signal=FMC_SDNWE
+PH6.GPIOParameters=GPIO_Label
+PH6.GPIO_Label=LED2
+PH6.Locked=true
+PH6.Signal=GPIO_Output
+PH7.GPIOParameters=GPIO_Label
+PH7.GPIO_Label=LCD_SCL [RK043FN48H-CT672B_SCL]
+PH7.Locked=true
+PH7.Mode=I2C
+PH7.Signal=I2C3_SCL
+PH8.GPIOParameters=GPIO_Label
+PH8.GPIO_Label=LCD_SDA [RK043FN48H-CT672B_SDA]
+PH8.Locked=true
+PH8.Mode=I2C
+PH8.Signal=I2C3_SDA
+PH9.GPIOParameters=GPIO_Label
+PH9.GPIO_Label=LED11
+PH9.Locked=true
+PH9.Signal=GPIO_Output
+PI0.Locked=true
+PI0.Mode=NSS_Signal_Hard_Output
+PI0.Signal=SPI2_NSS
+PI1.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
+PI1.GPIO_Label=ARDUINO SCK/D13
+PI1.GPIO_Mode=GPIO_MODE_AF_PP
+PI1.GPIO_PuPd=GPIO_NOPULL
+PI1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PI1.Locked=true
+PI1.Mode=Full_Duplex_Master
+PI1.Signal=SPI2_SCK
+PI10.GPIOParameters=GPIO_Label
+PI10.GPIO_Label=LCD_HSYNC [RK043FN48H-CT672B_HSYNC]
+PI10.Locked=true
+PI10.Mode=RGB888
+PI10.Signal=LTDC_HSYNC
+PI12.GPIOParameters=PinState,GPIO_Label
+PI12.GPIO_Label=LCD_DISP [RK043FN48H-CT672B_DISP] 
+PI12.Locked=true
+PI12.PinState=GPIO_PIN_SET
+PI12.Signal=GPIO_Output
+PI13.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
+PI13.GPIO_Label=LCD_INT
+PI13.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING
+PI13.Locked=true
+PI13.Signal=GPXTI13
+PI14.GPIOParameters=GPIO_Label
+PI14.GPIO_Label=LCD_CLK [RK043FN48H-CT672B_CLK]
+PI14.Locked=true
+PI14.Mode=RGB888
+PI14.Signal=LTDC_CLK
+PI15.GPIOParameters=GPIO_Label
+PI15.GPIO_Label=LCD_R0 [RK043FN48H-CT672B_R0]
+PI15.Locked=true
+PI15.Mode=RGB888
+PI15.Signal=LTDC_R0
+PI2.Locked=true
+PI2.Signal=S_TIM8_CH4
+PI3.GPIOParameters=GPIO_Label
+PI3.GPIO_Label=LED3
+PI3.Locked=true
+PI3.Signal=GPIO_Output
+PI8.GPIOParameters=GPIO_Label
+PI8.GPIO_Label=NC1 [TP2]
+PI8.Locked=true
+PI8.Mode=Timestamp enabled - Input Enabled to TS
+PI8.Signal=RTC_TS
+PI9.GPIOParameters=GPIO_Label
+PI9.GPIO_Label=LCD_VSYNC [RK043FN48H-CT672B_VSYNC]
+PI9.Locked=true
+PI9.Mode=RGB888
+PI9.Signal=LTDC_VSYNC
+PJ0.GPIOParameters=GPIO_Label
+PJ0.GPIO_Label=LCD_R1 [RK043FN48H-CT672B_R1]
+PJ0.Locked=true
+PJ0.Mode=RGB888
+PJ0.Signal=LTDC_R1
+PJ1.GPIOParameters=GPIO_Label
+PJ1.GPIO_Label=LCD_R2 [RK043FN48H-CT672B_R2]
+PJ1.Locked=true
+PJ1.Mode=RGB888
+PJ1.Signal=LTDC_R2
+PJ10.GPIOParameters=GPIO_Label
+PJ10.GPIO_Label=LCD_G3 [RK043FN48H-CT672B_G3]
+PJ10.Locked=true
+PJ10.Mode=RGB888
+PJ10.Signal=LTDC_G3
+PJ11.GPIOParameters=GPIO_Label
+PJ11.GPIO_Label=LCD_G4 [RK043FN48H-CT672B_G4]
+PJ11.Locked=true
+PJ11.Mode=RGB888
+PJ11.Signal=LTDC_G4
+PJ12.GPIOParameters=GPIO_Label
+PJ12.GPIO_Label=OTG_FS_VBUS
+PJ12.Locked=true
+PJ12.Signal=GPIO_Input
+PJ13.GPIOParameters=GPIO_Label
+PJ13.GPIO_Label=LCD_B1 [RK043FN48H-CT672B_B1]
+PJ13.Locked=true
+PJ13.Mode=RGB888
+PJ13.Signal=LTDC_B1
+PJ14.GPIOParameters=GPIO_Label
+PJ14.GPIO_Label=LCD_B2 [RK043FN48H-CT672B_B2]
+PJ14.Locked=true
+PJ14.Mode=RGB888
+PJ14.Signal=LTDC_B2
+PJ15.GPIOParameters=GPIO_Label
+PJ15.GPIO_Label=LCD_B3 [RK043FN48H-CT672B_B3]
+PJ15.Locked=true
+PJ15.Mode=RGB888
+PJ15.Signal=LTDC_B3
+PJ2.GPIOParameters=GPIO_Label
+PJ2.GPIO_Label=LCD_R3 [RK043FN48H-CT672B_R3]
+PJ2.Locked=true
+PJ2.Mode=RGB888
+PJ2.Signal=LTDC_R3
+PJ3.GPIOParameters=GPIO_Label
+PJ3.GPIO_Label=LCD_R4 [RK043FN48H-CT672B_R4]
+PJ3.Locked=true
+PJ3.Mode=RGB888
+PJ3.Signal=LTDC_R4
+PJ4.GPIOParameters=GPIO_Label
+PJ4.GPIO_Label=LCD_R5 [RK043FN48H-CT672B_R5]
+PJ4.Locked=true
+PJ4.Mode=RGB888
+PJ4.Signal=LTDC_R5
+PJ5.GPIOParameters=GPIO_Label
+PJ5.GPIO_Label=LCD_R6 [RK043FN48H-CT672B_R6]
+PJ5.Locked=true
+PJ5.Mode=RGB888
+PJ5.Signal=LTDC_R6
+PJ6.GPIOParameters=GPIO_Label
+PJ6.GPIO_Label=LCD_R7 [RK043FN48H-CT672B_R7]
+PJ6.Locked=true
+PJ6.Mode=RGB888
+PJ6.Signal=LTDC_R7
+PJ7.GPIOParameters=GPIO_Label
+PJ7.GPIO_Label=LCD_G0 [RK043FN48H-CT672B_G0]
+PJ7.Locked=true
+PJ7.Mode=RGB888
+PJ7.Signal=LTDC_G0
+PJ8.GPIOParameters=GPIO_Label
+PJ8.GPIO_Label=LCD_G1 [RK043FN48H-CT672B_G1]
+PJ8.Locked=true
+PJ8.Mode=RGB888
+PJ8.Signal=LTDC_G1
+PJ9.GPIOParameters=GPIO_Label
+PJ9.GPIO_Label=LCD_G2 [RK043FN48H-CT672B_G2]
+PJ9.Locked=true
+PJ9.Mode=RGB888
+PJ9.Signal=LTDC_G2
+PK0.GPIOParameters=GPIO_Label
+PK0.GPIO_Label=LCD_G5 [RK043FN48H-CT672B_G5]
+PK0.Locked=true
+PK0.Mode=RGB888
+PK0.Signal=LTDC_G5
+PK1.GPIOParameters=GPIO_Label
+PK1.GPIO_Label=LCD_G6 [RK043FN48H-CT672B_G6]
+PK1.Locked=true
+PK1.Mode=RGB888
+PK1.Signal=LTDC_G6
+PK2.GPIOParameters=GPIO_Label
+PK2.GPIO_Label=LCD_G7 [RK043FN48H-CT672B_G7]
+PK2.Locked=true
+PK2.Mode=RGB888
+PK2.Signal=LTDC_G7
+PK3.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
+PK3.GPIO_Label=LCD_BL_CTRL [STLD40DPUR_EN]
+PK3.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PK3.Locked=true
+PK3.PinState=GPIO_PIN_SET
+PK3.Signal=GPIO_Output
+PK4.GPIOParameters=GPIO_Label
+PK4.GPIO_Label=LCD_B5 [RK043FN48H-CT672B_B5]
+PK4.Locked=true
+PK4.Mode=RGB888
+PK4.Signal=LTDC_B5
+PK5.GPIOParameters=GPIO_Label
+PK5.GPIO_Label=LCD_B6 [RK043FN48H-CT672B_B6]
+PK5.Locked=true
+PK5.Mode=RGB888
+PK5.Signal=LTDC_B6
+PK6.GPIOParameters=GPIO_Label
+PK6.GPIO_Label=LCD_B7 [RK043FN48H-CT672B_B7]
+PK6.Locked=true
+PK6.Mode=RGB888
+PK6.Signal=LTDC_B7
+PK7.GPIOParameters=GPIO_Label
+PK7.GPIO_Label=LCD_DE [RK043FN48H-CT672B_DE]
+PK7.Locked=true
+PK7.Mode=RGB888
+PK7.Signal=LTDC_DE
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F746NGHx
+ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.16.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=test_.ioc
+ProjectManager.ProjectName=test_
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C3_Init-I2C3-false-HAL-true,6-MX_LTDC_Init-LTDC-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_SPI2_Init-SPI2-false-HAL-true,9-MX_TIM1_Init-TIM1-false-HAL-true,10-MX_TIM2_Init-TIM2-false-HAL-true,11-MX_TIM3_Init-TIM3-false-HAL-true,12-MX_TIM5_Init-TIM5-false-HAL-true,13-MX_TIM8_Init-TIM8-false-HAL-true,14-MX_USART1_UART_Init-USART1-false-HAL-true,15-MX_USART6_UART_Init-USART6-false-HAL-true,16-MX_ADC1_Init-ADC1-false-HAL-true,17-MX_DAC_Init-DAC-false-HAL-true,18-MX_UART7_Init-UART7-false-HAL-true,19-MX_FMC_Init-FMC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.AHBFreq_Value=200000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=50000000
+RCC.APB1TimFreq_Value=100000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=100000000
+RCC.APB2TimFreq_Value=200000000
+RCC.CECFreq_Value=32786.88524590164
+RCC.CortexFreq_Value=200000000
+RCC.EthernetFreq_Value=200000000
+RCC.FCLKCortexFreq_Value=200000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=200000000
+RCC.HSE_VALUE=25000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=50000000
+RCC.I2C2Freq_Value=50000000
+RCC.I2C3Freq_Value=50000000
+RCC.I2C4Freq_Value=50000000
+RCC.I2SFreq_Value=50000000
+RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLL48CLockSelection,PLLCLKFreq_Value,PLLI2SN,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIN,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIRDiv,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
+RCC.LCDTFToutputFreq_Value=9600000
+RCC.LPTIM1Freq_Value=50000000
+RCC.LSI_VALUE=32000
+RCC.MCO2PinFreq_Value=200000000
+RCC.PLL48CLockSelection=RCC_CLK48SOURCE_PLLSAIP
+RCC.PLLCLKFreq_Value=200000000
+RCC.PLLI2SN=100
+RCC.PLLI2SPCLKFreq_Value=50000000
+RCC.PLLI2SQCLKFreq_Value=50000000
+RCC.PLLI2SRCLKFreq_Value=50000000
+RCC.PLLI2SRoutputFreq_Value=50000000
+RCC.PLLM=25
+RCC.PLLN=400
+RCC.PLLQ=9
+RCC.PLLQCLKFreq_Value=44444444.44444445
+RCC.PLLQoutputFreq_Value=44444444.44444445
+RCC.PLLSAIN=384
+RCC.PLLSAIP=RCC_PLLSAIP_DIV8
+RCC.PLLSAIPCLKFreq_Value=48000000
+RCC.PLLSAIQCLKFreq_Value=192000000
+RCC.PLLSAIR=5
+RCC.PLLSAIRCLKFreq_Value=76800000
+RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_8
+RCC.PLLSAIoutputFreq_Value=48000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RNGFreq_Value=48000000
+RCC.SAI1Freq_Value=192000000
+RCC.SAI2Freq_Value=192000000
+RCC.SDMMCClockSelection=RCC_SDMMC1CLKSOURCE_CLK48
+RCC.SDMMCFreq_Value=48000000
+RCC.SPDIFRXFreq_Value=50000000
+RCC.SYSCLKFreq_VALUE=200000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=50000000
+RCC.UART5Freq_Value=50000000
+RCC.UART7Freq_Value=50000000
+RCC.UART8Freq_Value=50000000
+RCC.USART1Freq_Value=100000000
+RCC.USART2Freq_Value=50000000
+RCC.USART3Freq_Value=50000000
+RCC.USART6Freq_Value=100000000
+RCC.USBFreq_Value=48000000
+RCC.VCOI2SOutputFreq_Value=100000000
+RCC.VCOInputFreq_Value=1000000
+RCC.VCOOutputFreq_Value=400000000
+RCC.VCOSAIOutputFreq_Value=384000000
+RTC.Alarm-Alarm\ A=RTC_ALARM_A
+RTC.Alarm_B-Alarm\ B=RTC_ALARM_B
+RTC.IPParameters=Alarm-Alarm A,Alarm_B-Alarm B
+SH.ADCx_IN0.0=ADC1_IN0,IN0
+SH.ADCx_IN0.ConfNb=1
+SH.COMP_DAC1_group.0=DAC_OUT1,DAC_OUT1
+SH.COMP_DAC1_group.ConfNb=1
+SH.FMC_A0.0=FMC_A0,12b-sda1
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1,12b-sda1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10,12b-sda1
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11,12b-sda1
+SH.FMC_A11.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
+SH.FMC_A14_BA0.ConfNb=1
+SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
+SH.FMC_A15_BA1.ConfNb=1
+SH.FMC_A2.0=FMC_A2,12b-sda1
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3,12b-sda1
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4,12b-sda1
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5,12b-sda1
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6,12b-sda1
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7,12b-sda1
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8,12b-sda1
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9,12b-sda1
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
+SH.FMC_SDNWE.ConfNb=1
+SH.GPXTI13.0=GPIO_EXTI13
+SH.GPXTI13.ConfNb=1
+SH.GPXTI6.0=GPIO_EXTI6
+SH.GPXTI6.ConfNb=1
+SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
+SH.S_TIM3_CH1.ConfNb=1
+SH.S_TIM8_CH4.0=TIM8_CH4,PWM Generation4 CH4
+SH.S_TIM8_CH4.ConfNb=1
+SPI2.CalculateBaudRate=25.0 MBits/s
+SPI2.Direction=SPI_DIRECTION_2LINES
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualNSS=VM_NSSHARD
+SPI2.VirtualType=VM_MASTER
+TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM3.IPParameters=Channel-PWM Generation1 CH1
+TIM8.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
+TIM8.IPParameters=Channel-PWM Generation4 CH4
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USART6.IPParameters=VirtualMode-Asynchronous
+USART6.VirtualMode-Asynchronous=VM_ASYNC
+VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
+VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
+VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+VP_RTC_VS_RTC_Alarm_A_Intern.Mode=Alarm A
+VP_RTC_VS_RTC_Alarm_A_Intern.Signal=RTC_VS_RTC_Alarm_A_Intern
+VP_RTC_VS_RTC_Alarm_B_Intern.Mode=Alarm B
+VP_RTC_VS_RTC_Alarm_B_Intern.Signal=RTC_VS_RTC_Alarm_B_Intern
+VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
+VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
+VP_SYS_VS_tim6.Mode=TIM6
+VP_SYS_VS_tim6.Signal=SYS_VS_tim6
+VP_TIM1_VS_ClockSourceINT.Mode=Internal
+VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
+VP_TIM3_VS_ClockSourceINT.Mode=Internal
+VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
+VP_TIM3_VS_ClockSourceITR.Mode=TriggerSource_ITR0
+VP_TIM3_VS_ClockSourceITR.Signal=TIM3_VS_ClockSourceITR
+VP_TIM5_VS_ClockSourceINT.Mode=Internal
+VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT
+VP_TIM8_VS_ClockSourceINT.Mode=Internal
+VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
+board=STM32F746G-DISCO
+boardIOC=true
+isbadioc=false
diff --git a/test_ Debug.launch b/test_ Debug.launch
new file mode 100644
index 0000000..19f5be9
--- /dev/null
+++ b/test_ Debug.launch	
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