Better syntax highlighting for VHDL and Heptagon.

tools/hept_pygments/hept_pygments/__init__.py

@@ -13,6 +13,7 @@ class HeptagonLexer(RegexLexer):
             (r'open', Keyword.Namespace),
             (r'returns|let|tel|automaton|state|until|unless|if|then|else|end',
              Keyword),
+            (r'reset|every', Keyword),
             (r'map|fold|mapfold', Keyword),
             (r'when|merge|fby|do', Keyword),
             (r'present', Keyword.Reserved),
@@ -90,7 +91,9 @@ class VHDLLexer(RegexLexer):
               Keyword.Declaration),
             (r'library|use', Keyword.Namespace),
             (r'returns|begin|end|if|then|else|elsif|when|of', Keyword),
-            (r'natural|bit|std_ulogic', Keyword.Type),
+            (r'port|map|case|is|others', Keyword),
+            (r'natural|bit|std_logic|integer', Keyword.Type),
+            (r'\(|\)|;|\||:|\{|\}|,|\'|=>', Punctuation),
             (r'\+|\-|\/|=|&|not|<=|\.', Operator),
             (r'\d+', Number.Integer),
             (r' |\t', Whitespace),