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Better syntax highlighting for VHDL and Heptagon.

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This commit is contained in:
Adrien Guatto 2010-10-04 00:15:10 +02:00
parent 6ff8ed993f
commit f15a6c528e
1 changed files with 4 additions and 1 deletions
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5
tools/hept_pygments/hept_pygments/__init__.py
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@ -13,6 +13,7 @@ class HeptagonLexer(RegexLexer):
(r'open', Keyword.Namespace),
(r'returns|let|tel|automaton|state|until|unless|if|then|else|end',
Keyword),
(r'reset|every', Keyword),
(r'map|fold|mapfold', Keyword),
(r'when|merge|fby|do', Keyword),
(r'present', Keyword.Reserved),
@ -90,7 +91,9 @@ class VHDLLexer(RegexLexer):
Keyword.Declaration),
(r'library|use', Keyword.Namespace),
(r'returns|begin|end|if|then|else|elsif|when|of', Keyword),
(r'natural|bit|std_ulogic', Keyword.Type),
(r'port|map|case|is|others', Keyword),
(r'natural|bit|std_logic|integer', Keyword.Type),
(r'\(|\)|;|\||:|\{|\}|,|\'|=>', Punctuation),
(r'\+|\-|\/|=|&|not|<=|\.', Operator),
(r'\d+', Number.Integer),
(r' |\t', Whitespace),