299 lines
7.6 KiB
Text
299 lines
7.6 KiB
Text
@c Copyright (C) 2013-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c man end
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@ifset GENERIC
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@page
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@node NDS32-Dependent
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@chapter NDS32 Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter NDS32 Dependent Features
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@end ifclear
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@cindex NDS32 processor
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The NDS32 processors family includes high-performance and low-power 32-bit
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processors for high-end to low-end. @sc{gnu} @code{@value{AS}} for NDS32
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architectures supports NDS32 ISA version 3. For detail about NDS32
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instruction set, please see the AndeStar ISA User Manual which is available
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at http://www.andestech.com/en/index/index.htm
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@menu
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* NDS32 Options:: Assembler options
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* NDS32 Syntax:: High-level assembly macros
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@end menu
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@node NDS32 Options
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@section NDS32 Options
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@cindex NDS32 options
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@cindex options for NDS32
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The NDS32 configurations of @sc{gnu} @code{@value{AS}} support these
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special options:
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@c man begin OPTIONS
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@table @code
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@item -O1
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Optimize for performance.
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@item -Os
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Optimize for space.
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@item -EL
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Produce little endian data output.
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@item -EB
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Produce little endian data output.
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@item -mpic
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Generate PIC.
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@item -mno-fp-as-gp-relax
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Suppress fp-as-gp relaxation for this file.
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@item -mb2bb-relax
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Back-to-back branch optimization.
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@item -mno-all-relax
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Suppress all relaxation for this file.
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@item -march=<arch name>
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Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
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v3s, v2, v2j, v2f, v2s.
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@item -mbaseline=<baseline>
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Assemble for baseline <baseline> which could be v2, v3, v3m.
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@item -mfpu-freg=@var{FREG}
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Specify a FPU configuration.
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@table @code
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@item 0 8 SP / 4 DP registers
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@item 1 16 SP / 8 DP registers
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@item 2 32 SP / 16 DP registers
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@item 3 32 SP / 32 DP registers
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@end table
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@item -mabi=@var{abi}
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Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
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@item -m[no-]mac
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Enable/Disable Multiply instructions support.
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@item -m[no-]div
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Enable/Disable Divide instructions support.
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@item -m[no-]16bit-ext
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Enable/Disable 16-bit extension
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@item -m[no-]dx-regs
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Enable/Disable d0/d1 registers
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@item -m[no-]perf-ext
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Enable/Disable Performance extension
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@item -m[no-]perf2-ext
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Enable/Disable Performance extension 2
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@item -m[no-]string-ext
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Enable/Disable String extension
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@item -m[no-]reduced-regs
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Enable/Disable Reduced Register configuration (GPR16) option
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@item -m[no-]audio-isa-ext
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Enable/Disable AUDIO ISA extension
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@item -m[no-]fpu-sp-ext
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Enable/Disable FPU SP extension
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@item -m[no-]fpu-dp-ext
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Enable/Disable FPU DP extension
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@item -m[no-]fpu-fma
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Enable/Disable FPU fused-multiply-add instructions
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@item -mall-ext
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Turn on all extensions and instructions support
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@end table
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@c man end
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@node NDS32 Syntax
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@section Syntax
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@menu
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* NDS32-Chars:: Special Characters
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* NDS32-Regs:: Register Names
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* NDS32-Ops:: Pseudo Instructions
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@end menu
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@node NDS32-Chars
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@subsection Special Characters
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Use @samp{#} at column 1 and @samp{!} anywhere in the line except inside
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quotes.
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Multiple instructions in a line are allowed though not recommended and
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should be separated by @samp{;}.
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Assembler is not case-sensitive in general except user defined label.
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For example, @samp{jral F1} is different from @samp{jral f1} while it is
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the same as @samp{JRAL F1}.
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@node NDS32-Regs
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@subsection Register Names
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@table @code
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@item General purpose registers (GPR)
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There are 32 32-bit general purpose registers $r0 to $r31.
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@item Accumulators d0 and d1
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64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
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@item Assembler reserved register $ta
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Register $ta ($r15) is reserved for assembler using.
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@item Operating system reserved registers $p0 and $p1
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Registers $p0 ($r26) and $p1 ($r27) are used by operating system as scratch
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registers.
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@item Frame pointer $fp
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Register $r28 is regarded as the frame pointer.
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@item Global pointer
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Register $r29 is regarded as the global pointer.
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@item Link pointer
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Register $r30 is regarded as the link pointer.
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@item Stack pointer
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Register $r31 is regarded as the stack pointer.
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@end table
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@node NDS32-Ops
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@subsection Pseudo Instructions
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@table @code
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@item li rt5,imm32
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load 32-bit integer into register rt5. @samp{sethi rt5,hi20(imm32)} and then
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@samp{ori rt5,reg,lo12(imm32)}.
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@item la rt5,var
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Load 32-bit address of var into register rt5. @samp{sethi rt5,hi20(var)} and
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then @samp{ori reg,rt5,lo12(var)}
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@item l.[bhw] rt5,var
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Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then
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@samp{l[bhw]i rt5,[$ta+lo12(var)]}
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@item l.[bh]s rt5,var
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Load value of var into register rt5. @samp{sethi $ta,hi20(var)} and then
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@samp{l[bh]si rt5,[$ta+lo12(var)]}
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@item l.[bhw]p rt5,var,inc
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Load value of var into register rt5 and increment $ta by amount inc.
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@samp{la $ta,var} and then @samp{l[bhw]i.bi rt5,[$ta],inc}
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@item l.[bhw]pc rt5,inc
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Continue loading value of var into register rt5 and increment $ta by amount inc.
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@samp{l[bhw]i.bi rt5,[$ta],inc.}
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@item l.[bh]sp rt5,var,inc
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Load value of var into register rt5 and increment $ta by amount inc.
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@samp{la $ta,var} and then @samp{l[bh]si.bi rt5,[$ta],inc}
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@item l.[bh]spc rt5,inc
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Continue loading value of var into register rt5 and increment $ta by amount inc.
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@samp{l[bh]si.bi rt5,[$ta],inc.}
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@item s.[bhw] rt5,var
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Store register rt5 to var.
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@samp{sethi $ta,hi20(var)} and then @samp{s[bhw]i rt5,[$ta+lo12(var)]}
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@item s.[bhw]p rt5,var,inc
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Store register rt5 to var and increment $ta by amount inc.
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@samp{la $ta,var} and then @samp{s[bhw]i.bi rt5,[$ta],inc}
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@item s.[bhw]pc rt5,inc
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Continue storing register rt5 to var and increment $ta by amount inc.
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@samp{s[bhw]i.bi rt5,[$ta],inc.}
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@item not rt5,ra5
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Alias of @samp{nor rt5,ra5,ra5}.
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@item neg rt5,ra5
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Alias of @samp{subri rt5,ra5,0}.
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@item br rb5
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Depending on how it is assembled, it is translated into @samp{r5 rb5}
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or @samp{jr rb5}.
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@item b label
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Branch to label depending on how it is assembled, it is translated into
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@samp{j8 label}, @samp{j label}, or "@samp{la $ta,label} @samp{br $ta}".
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@item bral rb5
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Alias of jral br5 depending on how it is assembled, it is translated
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into @samp{jral5 rb5} or @samp{jral rb5}.
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@item bal fname
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Alias of jal fname depending on how it is assembled, it is translated into
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@samp{jal fname} or "@samp{la $ta,fname} @samp{bral $ta}".
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@item call fname
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Call function fname same as @samp{jal fname}.
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@item move rt5,ra5
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For 16-bit, this is @samp{mov55 rt5,ra5}.
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For no 16-bit, this is @samp{ori rt5,ra5,0}.
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@item move rt5,var
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This is the same as @samp{l.w rt5,var}.
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@item move rt5,imm32
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This is the same as @samp{li rt5,imm32}.
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@item pushm ra5,rb5
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Push contents of registers from ra5 to rb5 into stack.
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@item push ra5
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Push content of register ra5 into stack. (same @samp{pushm ra5,ra5}).
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@item push.d var
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Push value of double-word variable var into stack.
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@item push.w var
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Push value of word variable var into stack.
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@item push.h var
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Push value of half-word variable var into stack.
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@item push.b var
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Push value of byte variable var into stack.
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@item pusha var
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Push 32-bit address of variable var into stack.
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@item pushi imm32
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Push 32-bit immediate value into stack.
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@item popm ra5,rb5
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Pop top of stack values into registers ra5 to rb5.
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@item pop rt5
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Pop top of stack value into register. (same as @samp{popm rt5,rt5}.)
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@item pop.d var,ra5
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Pop value of double-word variable var from stack using register ra5
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as 2nd scratch register. (1st is $ta)
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@item pop.w var,ra5
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Pop value of word variable var from stack using register ra5.
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@item pop.h var,ra5
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Pop value of half-word variable var from stack using register ra5.
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@item pop.b var,ra5
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Pop value of byte variable var from stack using register ra5.
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@end table
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