--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC  VERSION_END


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--synthesis_resources = lut 8 
SUBDESIGN mux_ofb
( 
	data[31..0]	:	input;
	result[7..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w1_n0_mux_dataout	:	WIRE;
	l1_w1_n1_mux_dataout	:	WIRE;
	l1_w2_n0_mux_dataout	:	WIRE;
	l1_w2_n1_mux_dataout	:	WIRE;
	l1_w3_n0_mux_dataout	:	WIRE;
	l1_w3_n1_mux_dataout	:	WIRE;
	l1_w4_n0_mux_dataout	:	WIRE;
	l1_w4_n1_mux_dataout	:	WIRE;
	l1_w5_n0_mux_dataout	:	WIRE;
	l1_w5_n1_mux_dataout	:	WIRE;
	l1_w6_n0_mux_dataout	:	WIRE;
	l1_w6_n1_mux_dataout	:	WIRE;
	l1_w7_n0_mux_dataout	:	WIRE;
	l1_w7_n1_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w1_n0_mux_dataout	:	WIRE;
	l2_w2_n0_mux_dataout	:	WIRE;
	l2_w3_n0_mux_dataout	:	WIRE;
	l2_w4_n0_mux_dataout	:	WIRE;
	l2_w5_n0_mux_dataout	:	WIRE;
	l2_w6_n0_mux_dataout	:	WIRE;
	l2_w7_n0_mux_dataout	:	WIRE;
	data_wire[47..0]	: WIRE;
	result_wire_ext[7..0]	: WIRE;
	sel_wire[3..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16];
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
	l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17];
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18];
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
	l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19];
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20];
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
	l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21];
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22];
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
	l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23];
	l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[33..33] # !(sel_wire[3..3]) & data_wire[32..32];
	l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[35..35] # !(sel_wire[3..3]) & data_wire[34..34];
	l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[37..37] # !(sel_wire[3..3]) & data_wire[36..36];
	l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[39..39] # !(sel_wire[3..3]) & data_wire[38..38];
	l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[41..41] # !(sel_wire[3..3]) & data_wire[40..40];
	l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[43..43] # !(sel_wire[3..3]) & data_wire[42..42];
	l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[45..45] # !(sel_wire[3..3]) & data_wire[44..44];
	l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[47..47] # !(sel_wire[3..3]) & data_wire[46..46];
	data_wire[] = ( l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
	result[] = result_wire_ext[];
	result_wire_ext[] = ( l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout);
	sel_wire[] = ( sel[1..1], B"00", sel[0..0]);
END;
--VALID FILE