--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC  VERSION_END


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--synthesis_resources = lut 3 
SUBDESIGN mux_lfb
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w1_n0_mux_dataout	:	WIRE;
	l1_w2_n0_mux_dataout	:	WIRE;
	l1_w3_n0_mux_dataout	:	WIRE;
	l1_w4_n0_mux_dataout	:	WIRE;
	l1_w5_n0_mux_dataout	:	WIRE;
	l1_w6_n0_mux_dataout	:	WIRE;
	l1_w7_n0_mux_dataout	:	WIRE;
	data_wire[15..0]	: WIRE;
	result_wire_ext[7..0]	: WIRE;
	sel_wire[0..0]	: WIRE;

BEGIN 
	l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
	l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
	l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
	l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
	l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
	l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
	l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
	l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
	data_wire[] = ( data[]);
	result[] = result_wire_ext[];
	result_wire_ext[] = ( l1_w7_n0_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n0_mux_dataout);
	sel_wire[] = ( sel[0..0]);
END;
--VALID FILE