--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=16 LPM_WIDTH=4 data enable eq --VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END -- Copyright (C) 2022 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. --synthesis_resources = lut 18 SUBDESIGN decode_tma ( data[3..0] : input; enable : input; eq[15..0] : output; ) VARIABLE data_wire[3..0] : WIRE; enable_wire : WIRE; eq_node[15..0] : WIRE; eq_wire[15..0] : WIRE; w_anode1073w[1..0] : WIRE; w_anode1082w[3..0] : WIRE; w_anode1099w[3..0] : WIRE; w_anode1109w[3..0] : WIRE; w_anode1119w[3..0] : WIRE; w_anode1129w[3..0] : WIRE; w_anode1139w[3..0] : WIRE; w_anode1149w[3..0] : WIRE; w_anode1159w[3..0] : WIRE; w_anode1171w[1..0] : WIRE; w_anode1178w[3..0] : WIRE; w_anode1189w[3..0] : WIRE; w_anode1199w[3..0] : WIRE; w_anode1209w[3..0] : WIRE; w_anode1219w[3..0] : WIRE; w_anode1229w[3..0] : WIRE; w_anode1239w[3..0] : WIRE; w_anode1249w[3..0] : WIRE; w_data1071w[2..0] : WIRE; BEGIN data_wire[] = data[]; enable_wire = enable; eq[] = eq_node[]; eq_node[15..0] = eq_wire[15..0]; eq_wire[] = ( ( w_anode1249w[3..3], w_anode1239w[3..3], w_anode1229w[3..3], w_anode1219w[3..3], w_anode1209w[3..3], w_anode1199w[3..3], w_anode1189w[3..3], w_anode1178w[3..3]), ( w_anode1159w[3..3], w_anode1149w[3..3], w_anode1139w[3..3], w_anode1129w[3..3], w_anode1119w[3..3], w_anode1109w[3..3], w_anode1099w[3..3], w_anode1082w[3..3])); w_anode1073w[] = ( (w_anode1073w[0..0] & (! data_wire[3..3])), enable_wire); w_anode1082w[] = ( (w_anode1082w[2..2] & (! w_data1071w[2..2])), (w_anode1082w[1..1] & (! w_data1071w[1..1])), (w_anode1082w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); w_anode1099w[] = ( (w_anode1099w[2..2] & (! w_data1071w[2..2])), (w_anode1099w[1..1] & (! w_data1071w[1..1])), (w_anode1099w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); w_anode1109w[] = ( (w_anode1109w[2..2] & (! w_data1071w[2..2])), (w_anode1109w[1..1] & w_data1071w[1..1]), (w_anode1109w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); w_anode1119w[] = ( (w_anode1119w[2..2] & (! w_data1071w[2..2])), (w_anode1119w[1..1] & w_data1071w[1..1]), (w_anode1119w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); w_anode1129w[] = ( (w_anode1129w[2..2] & w_data1071w[2..2]), (w_anode1129w[1..1] & (! w_data1071w[1..1])), (w_anode1129w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); w_anode1139w[] = ( (w_anode1139w[2..2] & w_data1071w[2..2]), (w_anode1139w[1..1] & (! w_data1071w[1..1])), (w_anode1139w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); w_anode1149w[] = ( (w_anode1149w[2..2] & w_data1071w[2..2]), (w_anode1149w[1..1] & w_data1071w[1..1]), (w_anode1149w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); w_anode1159w[] = ( (w_anode1159w[2..2] & w_data1071w[2..2]), (w_anode1159w[1..1] & w_data1071w[1..1]), (w_anode1159w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); w_anode1171w[] = ( (w_anode1171w[0..0] & data_wire[3..3]), enable_wire); w_anode1178w[] = ( (w_anode1178w[2..2] & (! w_data1071w[2..2])), (w_anode1178w[1..1] & (! w_data1071w[1..1])), (w_anode1178w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); w_anode1189w[] = ( (w_anode1189w[2..2] & (! w_data1071w[2..2])), (w_anode1189w[1..1] & (! w_data1071w[1..1])), (w_anode1189w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); w_anode1199w[] = ( (w_anode1199w[2..2] & (! w_data1071w[2..2])), (w_anode1199w[1..1] & w_data1071w[1..1]), (w_anode1199w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); w_anode1209w[] = ( (w_anode1209w[2..2] & (! w_data1071w[2..2])), (w_anode1209w[1..1] & w_data1071w[1..1]), (w_anode1209w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); w_anode1219w[] = ( (w_anode1219w[2..2] & w_data1071w[2..2]), (w_anode1219w[1..1] & (! w_data1071w[1..1])), (w_anode1219w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); w_anode1229w[] = ( (w_anode1229w[2..2] & w_data1071w[2..2]), (w_anode1229w[1..1] & (! w_data1071w[1..1])), (w_anode1229w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); w_anode1239w[] = ( (w_anode1239w[2..2] & w_data1071w[2..2]), (w_anode1239w[1..1] & w_data1071w[1..1]), (w_anode1239w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); w_anode1249w[] = ( (w_anode1249w[2..2] & w_data1071w[2..2]), (w_anode1249w[1..1] & w_data1071w[1..1]), (w_anode1249w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); w_data1071w[2..0] = data_wire[2..0]; END; --VALID FILE