--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC  VERSION_END


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--synthesis_resources = lut 4 
SUBDESIGN decode_8la
( 
	data[1..0]	:	input;
	enable	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode279w[2..0]	: WIRE;
	w_anode292w[2..0]	: WIRE;
	w_anode300w[2..0]	: WIRE;
	w_anode308w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode308w[2..2], w_anode300w[2..2], w_anode292w[2..2], w_anode279w[2..2]);
	w_anode279w[] = ( (w_anode279w[1..1] & (! data_wire[1..1])), (w_anode279w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode292w[] = ( (w_anode292w[1..1] & (! data_wire[1..1])), (w_anode292w[0..0] & data_wire[0..0]), enable_wire);
	w_anode300w[] = ( (w_anode300w[1..1] & data_wire[1..1]), (w_anode300w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode308w[] = ( (w_anode308w[1..1] & data_wire[1..1]), (w_anode308w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE