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==== General Purpose Input and Output Port (GPIO)

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|=======================
| Hardware source file(s): | neorv32_gpio.vhd | 
| Software driver file(s): | neorv32_gpio.c |
|                          | neorv32_gpio.h |
| Top entity port:         | `gpio_o` | 64-bit parallel output port
|                          | `gpio_i` | 64-bit parallel input port
| Configuration generics:  | _IO_GPIO_EN_ | implement GPIO port when _true_
| CPU interrupts:          | none |
|=======================

The general purpose parallel IO port unit provides a simple 64-bit parallel input port and a 64-bit parallel
output port. These ports can be used chip-externally (for example to drive status LEDs, connect buttons, etc.)
or chip-internally to provide control signals for other IP modules. The component is disabled for
implementation when the _IO_GPIO_EN_ generic is set _false_. In this case the GPIO output port `gpio_o` is tied to all-zero.

.Access Atomicity
[NOTE]
The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
be performed within a single clock cycle.

.INPUT is read-only
[NOTE]
Write accesses to the `NEORV32_GPIO.INPUT_LO` and `NEORV32_GPIO.INPUT_HI` registers will raise a store bus
error exception. The BUSKEEPER will indicate a "DEVICE_ERR" in this case.


**Register Map**

.GPIO unit register map (`struct NEORV32_GPIO`)
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|=======================
| Address      | Name [C]                 | Bit(s) | R/W | Function
| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO`  | 31:0   | r/- | parallel input port pins 31:0
| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI`  | 31:0   | r/- | parallel input port pins 63:32
| `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0   | r/w | parallel output port pins 31:0
| `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0   | r/w | parallel output port pins 63:32
|=======================
