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==== Data Memory (DMEM)

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|=======================
| Hardware source file(s): | neorv32_dmem.entity.vhd      | entity-only definition
|                          | mem/neorv32_dmem.default.vhd | default _platform-agnostic_ memory architecture
| Software driver file(s): | none                         | _implicitly used_
| Top entity port:         | none                         | 
| Configuration generics:  | _MEM_INT_DMEM_EN_            | implement processor-internal DMEM when _true_
|                          | _MEM_INT_DMEM_SIZE_          | DMEM size in bytes
| CPU interrupts:          | none                         | 
|=======================

Implementation of the processor-internal data memory is enabled via the processor's _MEM_INT_DMEM_EN_
generic. The size in bytes is defined via the _MEM_INT_DMEM_SIZE_ generic. If the DMEM is implemented,
the memory is mapped into the data memory space and located right at the beginning of the data memory
space (default `dspace_base_c` = 0x80000000). The DMEM is always implemented as true RAM.

.Access Latency
[NOTE]
By default, the DMEM has a fixed access latency of one clock cycle (like all other processor-internal
modules). However, custom versions of this module may also have higher access latency. See section <<_bus_interface>>
for more information.

.VHDL Source File
[NOTE]
The actual DMEM is split into two design files: a plain entity definition (`neorv32_dmem.entity.vhd`) and the actual
architecture definition (`mem/neorv32_dmem.default.vhd`). This **default architecture** provides a _generic_ and
_platform independent_ memory design that (should) infers embedded memory block. You can replace/modify the architecture
source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
and/or timing.

.Execute from RAM
[TIP]
The CPU is capable of executing code also from DMEM.
