stnolting neorv32 RISC-V 1.6.4 The NEORV32 RISC-V Processor NEORV32 r2p0 little true true false false true true 0 false 8 32 32 read-write 0x00000000 0x00000000 CFS Custom functions subsystem CFS 0xFFFFFE00 CFS_FIRQ1 0 0x80 registers REG0Application-defined0x00 REG1Application-defined0x04 REG2Application-defined0x08 REG3Application-defined0x0C REG4Application-defined0x10 REG5Application-defined0x14 REG6Application-defined0x18 REG7Application-defined0x1C REG8Application-defined0x20 REG9Application-defined0x24 REG10Application-defined0x28 REG11Application-defined0x2C REG12Application-defined0x30 REG13Application-defined0x34 REG14Application-defined0x38 REG15Application-defined0x3C REG16Application-defined0x40 REG17Application-defined0x44 REG18Application-defined0x48 REG19Application-defined0x4C REG20Application-defined0x50 REG21Application-defined0x54 REG22Application-defined0x58 REG23Application-defined0x5C REG24Application-defined0x60 REG25Application-defined0x64 REG26Application-defined0x68 REG27Application-defined0x6C REG28Application-defined0x70 REG29Application-defined0x74 REG30Application-defined0x78 REG31Application-defined0x7C PWM Pulse-width modulation controller PWM 0xFFFFFE80 0 0x40 registers CTRL Control register 0x00 PWM_CTRL_EN [0:0] PWM controller enable flag PWM_CTRL_PRSCx [3:1] Clock prescaler select DUTY0 Duty cycle register 0 0x04 DUTY1 Duty cycle register 1 0x08 DUTY2 Duty cycle register 2 0x0C DUTY3 Duty cycle register 3 0x10 DUTY4 Duty cycle register 4 0x14 DUTY5 Duty cycle register 5 0x18 DUTY6 Duty cycle register 6 0x1C DUTY7 Duty cycle register 7 0x20 DUTY8 Duty cycle register 8 0x24 DUTY9 Duty cycle register 9 0x28 DUTY10 Duty cycle register 10 0x2C DUTY11 Duty cycle register 11 0x30 DUTY12 Duty cycle register 12 0x34 DUTY13 Duty cycle register 13 0x38 DUTY14 Duty cycle register 14 0x3C SLINK Stream link interface SLINK 0xFFFFFEC0 SLINK_RX_FIRQ10 SLINK_TX_FIRQ11 0 0x40 registers CTRL Control register 0x00 IRQ Link interrupt configuration register 0x04 RX_STATUS Status of RX link FIFOs 0x08 TX_STATUS Status of TX link FIFOs 0x0C DATA0 Link 0 RTX data register 0x20 DATA1 Link 1 RTX data register 0x24 DATA2 Link 2 RTX data register 0x28 DATA3 Link 3 RTX data register 0x2C DATA4 Link 4 RTX data register 0x30 DATA5 Link 5 RTX data register 0x34 DATA6 Link 6 RTX data register 0x38 DATA7 Link 7 RTX data register 0x3C XIP Execute In Place Module CIP 0xFFFFFF40 0 0x10 registers CTRL Control register 0x00 XIP_CTRL_EN [0:0] XIP module enable flag XIP_CTRL_PRSC [3:1] SPI clock prescaler select XIP_CTRL_CPOL [4:4] SPI clock (idle) polarity XIP_CTRL_CPHA [5:5] SPI clock phase XIP_CTRL_SPI_NBYTES [9:6] Number of bytes in SPI transmission XIP_CTRL_XIP_EN [10:10] XIP mode enable XIP_CTRL_XIP_ABYTES [12:11] Number of XIP address bytes (minus 1) XIP_CTRL_RD_CMD [20:13] SPI flash read command XIP_CTRL_XIP_PAGE [24:21] XIP memory page XIP_CTRL_SPI_CSEN [25:25] SPI chip-select enable XIP_CTRL_HIGHSPEED [26:26] SPI high-speed mode enable (ignoring XIP_CTRL_PRSC) XIP_CTRL_BURST_EN [27:27] Enable burst mode (for XIP accesses) XIP_CTRL_PHY_BUSY [30:30] read-only SPI PHY busy XIP_CTRL_XIP_BUSY [31:31] read-only XIP access in progress DATA_LO Direct SPI access - data register low 0x08 DATA_HI Direct SPI access - data register high 0x0C GPTMR General purpose timer GPTMR 0xFFFFFF60 GPTMR_FIRQ12 0 0x10 registers CTRL Control register 0x00 GPTMR_CTRL_EN [0:0] Timer enable flag GPTMR_CTRL_PRSC [3:1] Clock prescaler select GPTMR_CTRL_MODE [4:4] Timer mode: 0=single-shot mode, 1=continuous mode THRES Threshold register 0x04 COUNT Counter register 0x08 ONEWIRE 1-Wire Interface Controller ONEWIRE 0xFFFFFF70 ONEWIRE_FIRQ13 0 0x08 registers CTRL Control register 0x00 ONEWIRE_CTRL_EN [0:0] ONEWIRE controller enable ONEWIRE_CTRL_PRSC [2:1] Clock prescaler select ONEWIRE_CTRL_CLKDIV [10:3] Clock divider ONEWIRE_CTRL_TRIG_RST [11:11] Trigger reset pulse and presence detect operation, auto-clears ONEWIRE_CTRL_TRIG_BIT [12:12] Trigger single-bit transmission operation, auto-clears ONEWIRE_CTRL_TRIG_BYTE [13:13] Trigger full-byte transmission operation, auto-clears ONEWIRE_CTRL_SENSE [29:29] read-only Current state of the 1-wire bus line ONEWIRE_CTRL_PRESENCE [30:30] read-only Set if device(s) found during presence detect phase ONEWIRE_CTRL_BUSY [31:31] read-only Operation in progress when set DATA Read/write transmission data register 0x04 ONEWIRE_DATA [7:0] RTX data, transmitted LSB-first BUSKEEPER Bus keeper BUSKEEPER 0xFFFFFF78 0 0x04 registers CTRL Control register 0x00 BUSKEEPER_ERR_TYPE [0:0] read-only Bus error type: 0=device error, 1=access timeout BUSKEEPER_ERR_FLAG [31:31] Sticky error flag, clears after read or write access XIRQ External interrupts controller XIRQ 0xFFFFFF80 XIRQ_FIRQ8 0 0x10 registers IER IRQ input enable register 0x00 IPR IRQ pending/ack/clear register 0x04 SCR IRQ source register 0x08 MTIME Machine timer MTIME 0xFFFFFF90 0 0x10 registers TIME_LO System time register - low 0x00 TIME_HI System time register - high 0x04 TIMECMP_LO Time compare register - low 0x08 TIMECMP_HI Time compare register - high 0x0C UART0 Primary universal asynchronous receiver and transmitter UART0 0xFFFFFFA0 UART0_RX_FIRQ2 UART0_TX_FIRQ3 0 0x08 registers CTRL Control register 0x00 UART_CTRL_BAUD [11:0] Baud rate divisor UART_CTRL_SIM_MODE [12:12] Simulation output override enable, for use in simulation only UART_CTRL_RX_EMPTY [13:13] read-only RX FIFO is empty UART_CTRL_RX_HALF [14:14] read-only RX FIFO is at least half-full UART_CTRL_RX_FULL [15:15] read-only RX FIFO is full UART_CTRL_TX_EMPTY [16:16] read-only TX FIFO is empty UART_CTRL_TX_HALF [17:17] read-only TX FIFO is at least half-full UART_CTRL_TX_FULL [18:18] read-only TX FIFO is full UART_CTRL_RTS_EN [20:20] Enable hardware flow control: Assert RTS output if UART.RX is ready to receive UART_CTRL_CTS_EN [21:21] Enable hardware flow control: UART.TX starts sending only if CTS input is asserted UART_CTRL_PMODE0 [22:22] Parity configuration (0=even; 1=odd) UART_CTRL_PMODE1 [23:23] Parity bit enabled when set UART_CTRL_PRSC [26:24] Clock prescaler select UART_CTRL_CTS [27:27] read-only current state of CTS input UART_CTRL_EN [28:28] UART enable flag UART_CTRL_RX_IRQ [29:29] RX IRQ mode: 1=FIFO at least half-full; 0=FIFO not empty UART_CTRL_TX_IRQ [30:30] TX IRQ mode: 1=FIFO less than half-full; 0=FIFO not full UART_CTRL_TX_BUSY [31:31] read-only Transmitter is busy when set DATA RX/TX data register 0x04 UART_DATA [7:0] Receive/transmit data UART_DATA_PERR [28:28] read-only RX parity error detected when set UART_DATA_FERR [29:29] read-only RX frame error (no valid stop bit) detected when set UART_DATA_OVERR [30:30] read-only RX parity error detected when set UART_DATA_AVAIL [31:31] read-only RX data available when set UART1 Secondary universal asynchronous receiver and transmitter UART1 0xFFFFFFD0 UART1_RX_FIRQ4 UART1_TX_FIRQ5 0 0x08 registers SPI Serial peripheral interface controller SPI 0xFFFFFFA8 SPI_FIRQ6 0 0x08 registers CTRL Control register 0x00 SPI_CTRL_EN [0:0] SPI enable flag SPI_CTRL_CPHA [1:1] Clock phase SPI_CTRL_CPOL [2:2] Clock polarity SPI_CTRL_SIZE [4:3] Data transfer size SPI_CTRL_CS_SEL [7:5] CS select SPI_CTRL_CS_EN [8:8] Enable selected CS line SPI_CTRL_PRSC [11:9] Clock prescaler select SPI_CTRL_CDIV [15:12] SPI clock divider SPI_CTRL_IRQ [17:16] Interrupt configuration SPI_CTRL_FIFO [26:23] read-only log2(FIFO size) SPI_CTRL_RX_AVAIL [27:27] read-only RX FIFO data available (RX FIFO not empty) SPI_CTRL_TX_EMPTY [28:28] read-only TX FIFO is empty SPI_CTRL_TX_HALF [29:29] read-only TX FIFO is at least half full SPI_CTRL_TX_FULL [30:30] read-only TX FIFO is full SPI_CTRL_BUSY [31:31] read-only SPI busy flag DATA RX/TX data register 0x04 TWI Two-wire interface controller SPI 0xFFFFFFB0 TWI_FIRQ7 0 0x08 registers CTRL Control register 0x00 TWI_CTRL_EN [0:0] TWI enable flag TWI_CTRL_START [1:1] Generate START condition, auto-clears TWI_CTRL_STOP [2:2] Generate STOP condition, auto-clears TWI_CTRL_MACK [3:3] Generate ACK by controller for each transmission TWI_CTRL_CSEN [4:4] Allow clock stretching when set TWI_CTRL_PRSC [7:5] Clock prescaler select TWI_CTRL_CDIV [11:8] TWI clock divider TWI_CTRL_CLAIMED [29:29] read-only Set if the TWI bus is currently claimed by any controller TWI_CTRL_ACK [30:30] read-only ACK received when set TWI_CTRL_BUSY [31:31] read-only Transfer in progress, busy flag DATA RX/TX data register 0x04 TWI_DATA [7:0] RX/TX data TRNG True random number generator TRNG 0xFFFFFFB8 0 0x04 registers CTRL Control and data register 0x00 TRNG_CTRL_DATA [7:0] read-only Random data TRNG_CTRL_FIFO_CLR [28:28] Clear data FIFO when set (auto clears) TRNG_CTRL_SIM_MODE [29:29] read-only TRNG simulation mode (PRNG!) active TRNG_CTRL_EN [30:30] TRNG enable flag TRNG_CTRL_VALID [31:31] read-only Random data output valid WDT Watchdog timer WDT 0xFFFFFFBC WDT_FIRQ0 0 0x04 registers CTRL Control register 0x00 WDT_CTRL_EN [0:0] WDT enable flag WDT_CTRL_CLK_SEL [3:1] Clock prescaler select WDT_CTRL_MODE [4:4] Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset WDT_CTRL_RCAUSE [5:5] read-only Cause of last system reset: 0=external reset, 1=watchdog WDT_CTRL_RESET [6:6] Reset WDT counter when set, auto-clears WDT_CTRL_FORCE [7:7] Force WDT action, auto-clears WDT_CTRL_LOCK [8:8] Lock write access to control register, clears on reset (HW or WDT) only WDT_CTRL_DBEN [9:9] Allow WDT to continue operation even when in debug mode WDT_CTRL_HALF [10:10] read-only Set if at least half of the max. timeout counter value has been reached WDT_CTRL_PAUSE [11:11] Pause WDT when CPU is in sleep mode WDT_CTRL_PWD [31:16] Watchdog password, has to be `0xCA36` - otherwise any write access is ignored, reads as zero GPIO General purpose input/output port GPIO 0xFFFFFFc0 0 0x10 registers INPUT_LO Parallel input register - low 0x00 read-only INPUT_HI Parallel input register - high 0x04 read-only OUTPUT_LO Parallel output register - low 0x08 OUTPUT_HI Parallel output register - high 0x0C NEOLED Smart LED hardware interface NEOLED 0xFFFFFFD8 NEOLED_FIRQ9 0 0x08 registers CTRL Control register 0x00 NEOLED_CTRL_EN [0:0] NEOLED enable flag NEOLED_CTRL_MODE [1:1] TX mode (0=24-bit, 1=32-bit) NEOLED_CTRL_STROBE [2:2] Strobe (0=send normal data, 1=send RESET command on data write) NEOLED_CTRL_PRSC [5:3] Clock prescaler select NEOLED_CTRL_BUFS [9:6] read-only log2(tx buffer size) NEOLED_CTRL_T_TOT [14:10] pulse-clock ticks per total period bit NEOLED_CTRL_T_ZERO_H [19:15] pulse-clock ticks per ZERO high-time NEOLED_CTRL_T_ONE_H [24:20] pulse-clock ticks per ONE high-time NEOLED_CTRL_IRQ_CONF [27:27] TX FIFO interrupt: 0=IRQ if FIFO is less than half-full, 1=IRQ if FIFO is empty NEOLED_CTRL_TX_EMPTY [28:28] read-only TX FIFO is empty NEOLED_CTRL_TX_HALF [29:29] read-only TX FIFO is at least half-full NEOLED_CTRL_TX_FULL [30:30] read-only TX FIFO is full NEOLED_CTRL_TX_BUSY [31:31] read-only busy flag DATA Data register 0x04 SYSINFO System configuration information memory SYSINFO 0xFFFFFFE0 0 0x20 registers CLK Clock speed in Hz 0x00 read-only CUSTOM_ID Custom user-defined ID 0x04 read-only SOC SoC features 0x08 read-only SYSINFO_SOC_BOOTLOADER[0:0]Bootloader implemented SYSINFO_SOC_MEM_EXT[1:1]External bus interface implemented SYSINFO_SOC_MEM_INT_IMEM[2:2]Processor-internal instruction memory implemented SYSINFO_SOC_MEM_INT_DMEM[3:3]Processor-internal data memory implemented SYSINFO_SOC_MEM_EXT_ENDIAN[4:4]External bus interface uses BIG-endian byte-order SYSINFO_SOC_ICACHE[5:5]Processor-internal instruction cache implemented SYSINFO_SOC_IS_SIM[13:13]Set if processor is being simulated SYSINFO_SOC_OCD[14:14]On-chip debugger implemented SYSINFO_SOC_IO_GPIO[16:16]General purpose input/output port unit implemented SYSINFO_SOC_IO_MTIME[17:17]Machine system timer implemented SYSINFO_SOC_IO_UART0[18:18]Primary universal asynchronous receiver/transmitter 0 implemented SYSINFO_SOC_IO_SPI[19:19]Serial peripheral interface implemented SYSINFO_SOC_IO_TWI[20:20]Two-wire interface implemented SYSINFO_SOC_IO_PWM[21:21]Pulse-width modulation unit implemented SYSINFO_SOC_IO_WDT[22:22]Watchdog timer implemented SYSINFO_SOC_IO_CFS[23:23]Custom functions subsystem implemented SYSINFO_SOC_IO_TRNG[24:24]True random number generator implemented SYSINFO_SOC_IO_SLINK[25:25]Stream link interface implemented SYSINFO_SOC_IO_UART1[26:26]Secondary universal asynchronous receiver/transmitter 1 implemented SYSINFO_SOC_IO_NEOLED[27:27]NeoPixel-compatible smart LED interface implemented SYSINFO_SOC_IO_XIRQ[28:28]External interrupt controller implemented SYSINFO_SOC_IO_GPTMR[29:29]General purpose timer implemented SYSINFO_SOC_IO_XIP[30:30]Execute in place module implemented CACHE Cache configuration 0x0C read-only SYSINFO_CACHE_IC_BLOCK_SIZE[3:0]i-cache: log2(Block size in bytes) SYSINFO_CACHE_IC_NUM_BLOCKS[7:4]i-cache: log2(Number of cache blocks/pages/lines) SYSINFO_CACHE_IC_ASSOCIATIVITY[11:8]i-cache: log2(associativity) SYSINFO_CACHE_IC_REPLACEMENT[15:12]i-cache: replacement policy (0001 = LRU if associativity > 0) ISPACE_BASE Instruction memory address space base address 0x10 read-only DSPACE_BASE Data memory address space base address 0x14 read-only IMEM_SIZE Internal instruction memory (IMEM) size in bytes 0x18 read-only DMEM_SIZE Internal data memory (DMEM) size in bytes 0x1C read-only