451 lines
15 KiB
C
451 lines
15 KiB
C
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/*
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* QEMU Sparc SLAVIO timer controller emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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/*
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* Registers of hardware timer in sun4m.
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*
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* This is the timer/counter part of chip STP2001 (Slave I/O), also
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* produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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* are zero. Bit 31 is 1 when count has been reached.
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*
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* Per-CPU timers interrupt local CPU, system timer uses normal
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* interrupt routing.
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*
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*/
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#define MAX_CPUS 16
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typedef struct CPUTimerState {
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qemu_irq irq;
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ptimer_state *timer;
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uint32_t count, counthigh, reached;
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/* processor only */
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uint32_t run;
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uint64_t limit;
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} CPUTimerState;
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#define TYPE_SLAVIO_TIMER "slavio_timer"
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OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_TIMERState, SLAVIO_TIMER)
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struct SLAVIO_TIMERState {
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SysBusDevice parent_obj;
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uint32_t num_cpus;
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uint32_t cputimer_mode;
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CPUTimerState cputimer[MAX_CPUS + 1];
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};
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typedef struct TimerContext {
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MemoryRegion iomem;
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SLAVIO_TIMERState *s;
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unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
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} TimerContext;
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#define SYS_TIMER_SIZE 0x14
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#define CPU_TIMER_SIZE 0x10
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#define TIMER_LIMIT 0
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#define TIMER_COUNTER 1
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#define TIMER_COUNTER_NORST 2
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#define TIMER_STATUS 3
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#define TIMER_MODE 4
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#define TIMER_COUNT_MASK32 0xfffffe00
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#define TIMER_LIMIT_MASK32 0x7fffffff
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#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
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#define TIMER_MAX_COUNT32 0x7ffffe00ULL
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#define TIMER_REACHED 0x80000000
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#define TIMER_PERIOD 500ULL // 500ns
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#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
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#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
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static int slavio_timer_is_user(TimerContext *tc)
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{
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SLAVIO_TIMERState *s = tc->s;
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unsigned int timer_index = tc->timer_index;
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return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
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}
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// Update count, set irq, update expire_time
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// Convert from ptimer countdown units
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static void slavio_timer_get_out(CPUTimerState *t)
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{
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uint64_t count, limit;
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if (t->limit == 0) { /* free-run system or processor counter */
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limit = TIMER_MAX_COUNT32;
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} else {
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limit = t->limit;
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}
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count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
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trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
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t->count = count & TIMER_COUNT_MASK32;
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t->counthigh = count >> 32;
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}
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// timer callback
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static void slavio_timer_irq(void *opaque)
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{
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TimerContext *tc = opaque;
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SLAVIO_TIMERState *s = tc->s;
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CPUTimerState *t = &s->cputimer[tc->timer_index];
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slavio_timer_get_out(t);
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trace_slavio_timer_irq(t->counthigh, t->count);
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/* if limit is 0 (free-run), there will be no match */
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if (t->limit != 0) {
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t->reached = TIMER_REACHED;
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}
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/* there is no interrupt if user timer or free-run */
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if (!slavio_timer_is_user(tc) && t->limit != 0) {
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qemu_irq_raise(t->irq);
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}
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}
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static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
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unsigned size)
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{
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TimerContext *tc = opaque;
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SLAVIO_TIMERState *s = tc->s;
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uint32_t saddr, ret;
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unsigned int timer_index = tc->timer_index;
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CPUTimerState *t = &s->cputimer[timer_index];
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saddr = addr >> 2;
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switch (saddr) {
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case TIMER_LIMIT:
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// read limit (system counter mode) or read most signifying
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// part of counter (user mode)
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if (slavio_timer_is_user(tc)) {
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// read user timer MSW
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slavio_timer_get_out(t);
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ret = t->counthigh | t->reached;
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} else {
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// read limit
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// clear irq
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qemu_irq_lower(t->irq);
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t->reached = 0;
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ret = t->limit & TIMER_LIMIT_MASK32;
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}
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break;
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case TIMER_COUNTER:
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// read counter and reached bit (system mode) or read lsbits
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// of counter (user mode)
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slavio_timer_get_out(t);
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if (slavio_timer_is_user(tc)) { // read user timer LSW
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ret = t->count & TIMER_MAX_COUNT64;
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} else { // read limit
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ret = (t->count & TIMER_MAX_COUNT32) |
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t->reached;
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}
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break;
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case TIMER_STATUS:
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// only available in processor counter/timer
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// read start/stop status
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if (timer_index > 0) {
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ret = t->run;
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} else {
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ret = 0;
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}
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break;
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case TIMER_MODE:
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// only available in system counter
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// read user/system mode
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ret = s->cputimer_mode;
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break;
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default:
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trace_slavio_timer_mem_readl_invalid(addr);
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ret = 0;
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break;
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}
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trace_slavio_timer_mem_readl(addr, ret);
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return ret;
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}
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static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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TimerContext *tc = opaque;
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SLAVIO_TIMERState *s = tc->s;
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uint32_t saddr;
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unsigned int timer_index = tc->timer_index;
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CPUTimerState *t = &s->cputimer[timer_index];
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trace_slavio_timer_mem_writel(addr, val);
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saddr = addr >> 2;
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switch (saddr) {
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case TIMER_LIMIT:
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ptimer_transaction_begin(t->timer);
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if (slavio_timer_is_user(tc)) {
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uint64_t count;
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// set user counter MSW, reset counter
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t->limit = TIMER_MAX_COUNT64;
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t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
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t->reached = 0;
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count = ((uint64_t)t->counthigh << 32) | t->count;
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trace_slavio_timer_mem_writel_limit(timer_index, count);
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ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
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} else {
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// set limit, reset counter
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qemu_irq_lower(t->irq);
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t->limit = val & TIMER_MAX_COUNT32;
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if (t->limit == 0) { /* free-run */
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ptimer_set_limit(t->timer,
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LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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} else {
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ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
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}
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}
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ptimer_transaction_commit(t->timer);
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break;
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case TIMER_COUNTER:
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if (slavio_timer_is_user(tc)) {
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uint64_t count;
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// set user counter LSW, reset counter
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t->limit = TIMER_MAX_COUNT64;
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t->count = val & TIMER_MAX_COUNT64;
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t->reached = 0;
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count = ((uint64_t)t->counthigh) << 32 | t->count;
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trace_slavio_timer_mem_writel_limit(timer_index, count);
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ptimer_transaction_begin(t->timer);
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ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
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ptimer_transaction_commit(t->timer);
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} else {
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trace_slavio_timer_mem_writel_counter_invalid();
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}
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break;
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case TIMER_COUNTER_NORST:
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// set limit without resetting counter
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t->limit = val & TIMER_MAX_COUNT32;
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ptimer_transaction_begin(t->timer);
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if (t->limit == 0) { /* free-run */
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ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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} else {
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ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
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}
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ptimer_transaction_commit(t->timer);
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break;
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case TIMER_STATUS:
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ptimer_transaction_begin(t->timer);
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if (slavio_timer_is_user(tc)) {
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// start/stop user counter
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if (val & 1) {
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trace_slavio_timer_mem_writel_status_start(timer_index);
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ptimer_run(t->timer, 0);
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} else {
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trace_slavio_timer_mem_writel_status_stop(timer_index);
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ptimer_stop(t->timer);
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}
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}
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t->run = val & 1;
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ptimer_transaction_commit(t->timer);
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break;
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case TIMER_MODE:
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if (timer_index == 0) {
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unsigned int i;
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for (i = 0; i < s->num_cpus; i++) {
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unsigned int processor = 1 << i;
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CPUTimerState *curr_timer = &s->cputimer[i + 1];
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ptimer_transaction_begin(curr_timer->timer);
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// check for a change in timer mode for this processor
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if ((val & processor) != (s->cputimer_mode & processor)) {
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if (val & processor) { // counter -> user timer
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qemu_irq_lower(curr_timer->irq);
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// counters are always running
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if (!curr_timer->run) {
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ptimer_stop(curr_timer->timer);
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}
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// user timer limit is always the same
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curr_timer->limit = TIMER_MAX_COUNT64;
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ptimer_set_limit(curr_timer->timer,
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LIMIT_TO_PERIODS(curr_timer->limit),
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1);
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// set this processors user timer bit in config
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// register
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s->cputimer_mode |= processor;
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trace_slavio_timer_mem_writel_mode_user(timer_index);
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} else { // user timer -> counter
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// start the counter
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ptimer_run(curr_timer->timer, 0);
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// clear this processors user timer bit in config
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// register
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s->cputimer_mode &= ~processor;
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trace_slavio_timer_mem_writel_mode_counter(timer_index);
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}
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}
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ptimer_transaction_commit(curr_timer->timer);
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}
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} else {
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trace_slavio_timer_mem_writel_mode_invalid();
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}
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break;
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default:
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trace_slavio_timer_mem_writel_invalid(addr);
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break;
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}
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}
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static const MemoryRegionOps slavio_timer_mem_ops = {
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.read = slavio_timer_mem_readl,
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.write = slavio_timer_mem_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const VMStateDescription vmstate_timer = {
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.name ="timer",
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.version_id = 3,
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.minimum_version_id = 3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(limit, CPUTimerState),
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VMSTATE_UINT32(count, CPUTimerState),
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VMSTATE_UINT32(counthigh, CPUTimerState),
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VMSTATE_UINT32(reached, CPUTimerState),
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VMSTATE_UINT32(run , CPUTimerState),
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VMSTATE_PTIMER(timer, CPUTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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|
||
|
|
static const VMStateDescription vmstate_slavio_timer = {
|
||
|
|
.name ="slavio_timer",
|
||
|
|
.version_id = 3,
|
||
|
|
.minimum_version_id = 3,
|
||
|
|
.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
|
||
|
|
vmstate_timer, CPUTimerState),
|
||
|
|
VMSTATE_END_OF_LIST()
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
static void slavio_timer_reset(DeviceState *d)
|
||
|
|
{
|
||
|
|
SLAVIO_TIMERState *s = SLAVIO_TIMER(d);
|
||
|
|
unsigned int i;
|
||
|
|
CPUTimerState *curr_timer;
|
||
|
|
|
||
|
|
for (i = 0; i <= MAX_CPUS; i++) {
|
||
|
|
curr_timer = &s->cputimer[i];
|
||
|
|
curr_timer->limit = 0;
|
||
|
|
curr_timer->count = 0;
|
||
|
|
curr_timer->reached = 0;
|
||
|
|
if (i <= s->num_cpus) {
|
||
|
|
ptimer_transaction_begin(curr_timer->timer);
|
||
|
|
ptimer_set_limit(curr_timer->timer,
|
||
|
|
LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
|
||
|
|
ptimer_run(curr_timer->timer, 0);
|
||
|
|
curr_timer->run = 1;
|
||
|
|
ptimer_transaction_commit(curr_timer->timer);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
s->cputimer_mode = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void slavio_timer_init(Object *obj)
|
||
|
|
{
|
||
|
|
SLAVIO_TIMERState *s = SLAVIO_TIMER(obj);
|
||
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
||
|
|
unsigned int i;
|
||
|
|
TimerContext *tc;
|
||
|
|
|
||
|
|
for (i = 0; i <= MAX_CPUS; i++) {
|
||
|
|
uint64_t size;
|
||
|
|
char timer_name[20];
|
||
|
|
|
||
|
|
tc = g_new0(TimerContext, 1);
|
||
|
|
tc->s = s;
|
||
|
|
tc->timer_index = i;
|
||
|
|
|
||
|
|
s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc,
|
||
|
|
PTIMER_POLICY_LEGACY);
|
||
|
|
ptimer_transaction_begin(s->cputimer[i].timer);
|
||
|
|
ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
|
||
|
|
ptimer_transaction_commit(s->cputimer[i].timer);
|
||
|
|
|
||
|
|
size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
|
||
|
|
snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
|
||
|
|
memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc,
|
||
|
|
timer_name, size);
|
||
|
|
sysbus_init_mmio(dev, &tc->iomem);
|
||
|
|
|
||
|
|
sysbus_init_irq(dev, &s->cputimer[i].irq);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property slavio_timer_properties[] = {
|
||
|
|
DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
|
||
|
|
DEFINE_PROP_END_OF_LIST(),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void slavio_timer_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->reset = slavio_timer_reset;
|
||
|
|
dc->vmsd = &vmstate_slavio_timer;
|
||
|
|
device_class_set_props(dc, slavio_timer_properties);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo slavio_timer_info = {
|
||
|
|
.name = TYPE_SLAVIO_TIMER,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(SLAVIO_TIMERState),
|
||
|
|
.instance_init = slavio_timer_init,
|
||
|
|
.class_init = slavio_timer_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void slavio_timer_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&slavio_timer_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(slavio_timer_register_types)
|