Flow report for test_neorv32
Wed Feb  8 15:44:03 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log
  8. Flow Messages
  9. Flow Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2022  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+--------------------------------------------------------------------------------------+
; Flow Summary                                                                         ;
+---------------------------------+----------------------------------------------------+
; Flow Status                     ; Successful - Wed Feb  8 15:44:03 2023              ;
; Quartus Prime Version           ; 22.1std.0 Build 915 10/25/2022 SC Standard Edition ;
; Revision Name                   ; test_neorv32                                       ;
; Top-level Entity Name           ; neorv32_test_setup_approm                          ;
; Family                          ; Cyclone V                                          ;
; Device                          ; 5CSEMA5F31C6                                       ;
; Timing Models                   ; Final                                              ;
; Logic utilization (in ALMs)     ; 1,616 / 32,070 ( 5 % )                             ;
; Total registers                 ; 1548                                               ;
; Total pins                      ; 10 / 457 ( 2 % )                                   ;
; Total virtual pins              ; 0                                                  ;
; Total block memory bits         ; 67,584 / 4,065,280 ( 2 % )                         ;
; Total DSP Blocks                ; 0 / 87 ( 0 % )                                     ;
; Total HSSI RX PCSs              ; 0                                                  ;
; Total HSSI PMA RX Deserializers ; 0                                                  ;
; Total HSSI TX PCSs              ; 0                                                  ;
; Total HSSI PMA TX Serializers   ; 0                                                  ;
; Total PLLs                      ; 0 / 6 ( 0 % )                                      ;
; Total DLLs                      ; 0 / 4 ( 0 % )                                      ;
+---------------------------------+----------------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 02/08/2023 15:41:22 ;
; Main task         ; Compilation         ;
; Revision Name     ; test_neorv32        ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                                                              ;
+--------------------------------------+----------------------------------------+---------------+---------------------------+-----------------------------------+
; Assignment Name                      ; Value                                  ; Default Value ; Entity Name               ; Section Id                        ;
+--------------------------------------+----------------------------------------+---------------+---------------------------+-----------------------------------+
; COMPILER_SIGNATURE_ID                ; 92407695964.167586728216681            ; --            ; --                        ; --                                ;
; EDA_GENERATE_FUNCTIONAL_NETLIST      ; Off                                    ; --            ; --                        ; eda_board_design_timing           ;
; EDA_GENERATE_FUNCTIONAL_NETLIST      ; Off                                    ; --            ; --                        ; eda_board_design_boundary_scan    ;
; EDA_GENERATE_FUNCTIONAL_NETLIST      ; Off                                    ; --            ; --                        ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST      ; Off                                    ; --            ; --                        ; eda_board_design_symbol           ;
; EDA_OUTPUT_DATA_FORMAT               ; Verilog Hdl                            ; --            ; --                        ; eda_simulation                    ;
; EDA_SIMULATION_TOOL                  ; Questa Intel FPGA (Verilog)            ; <None>        ; --                        ; --                                ;
; EDA_TIME_SCALE                       ; 1 ps                                   ; --            ; --                        ; eda_simulation                    ;
; FITTER_EFFORT                        ; Standard Fit                           ; Auto Fit      ; --                        ; --                                ;
; MAX_CORE_JUNCTION_TEMP               ; 85                                     ; --            ; --                        ; --                                ;
; MIN_CORE_JUNCTION_TEMP               ; 0                                      ; --            ; --                        ; --                                ;
; MUX_RESTRUCTURE                      ; Off                                    ; Auto          ; --                        ; --                                ;
; OPTIMIZATION_MODE                    ; Aggressive Performance                 ; Balanced      ; --                        ; --                                ;
; OPTIMIZATION_TECHNIQUE               ; Speed                                  ; Balanced      ; --                        ; --                                ;
; PARTITION_COLOR                      ; -- (Not supported for targeted family) ; --            ; neorv32_test_setup_approm ; Top                               ;
; PARTITION_FITTER_PRESERVATION_LEVEL  ; -- (Not supported for targeted family) ; --            ; neorv32_test_setup_approm ; Top                               ;
; PARTITION_NETLIST_TYPE               ; -- (Not supported for targeted family) ; --            ; neorv32_test_setup_approm ; Top                               ;
; PHYSICAL_SYNTHESIS_COMBO_LOGIC       ; On                                     ; Off           ; --                        ; --                                ;
; PHYSICAL_SYNTHESIS_REGISTER_RETIMING ; On                                     ; Off           ; --                        ; --                                ;
; PLACEMENT_EFFORT_MULTIPLIER          ; 4.0                                    ; 1.0           ; --                        ; --                                ;
; POWER_BOARD_THERMAL_MODEL            ; None (CONSERVATIVE)                    ; --            ; --                        ; --                                ;
; POWER_PRESET_COOLING_SOLUTION        ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --                        ; --                                ;
; PROJECT_OUTPUT_DIRECTORY             ; output_files                           ; --            ; --                        ; --                                ;
; ROUTER_TIMING_OPTIMIZATION_LEVEL     ; MAXIMUM                                ; Normal        ; --                        ; --                                ;
; TOP_LEVEL_ENTITY                     ; neorv32_test_setup_approm              ; test_neorv32  ; --                        ; --                                ;
+--------------------------------------+----------------------------------------+---------------+---------------------------+-----------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                        ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:18     ; 1.0                     ; 632 MB              ; 00:00:23                           ;
; Fitter               ; 00:02:05     ; 1.1                     ; 1957 MB             ; 00:03:06                           ;
; Assembler            ; 00:00:06     ; 1.0                     ; 542 MB              ; 00:00:05                           ;
; Timing Analyzer      ; 00:00:06     ; 2.0                     ; 911 MB              ; 00:00:12                           ;
; EDA Netlist Writer   ; 00:00:02     ; 1.0                     ; 726 MB              ; 00:00:01                           ;
; Total                ; 00:02:37     ; --                      ; --                  ; 00:03:47                           ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+


+----------------------------------------------------------------------------------------+
; Flow OS Summary                                                                        ;
+----------------------+------------------+----------------+------------+----------------+
; Module Name          ; Machine Hostname ; OS Name        ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; seti-VirtualBox  ; Ubuntu 22.04.1 ; 22         ; x86_64         ;
; Fitter               ; seti-VirtualBox  ; Ubuntu 22.04.1 ; 22         ; x86_64         ;
; Assembler            ; seti-VirtualBox  ; Ubuntu 22.04.1 ; 22         ; x86_64         ;
; Timing Analyzer      ; seti-VirtualBox  ; Ubuntu 22.04.1 ; 22         ; x86_64         ;
; EDA Netlist Writer   ; seti-VirtualBox  ; Ubuntu 22.04.1 ; 22         ; x86_64         ;
+----------------------+------------------+----------------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off test_neorv32 -c test_neorv32
quartus_fit --read_settings_files=off --write_settings_files=off test_neorv32 -c test_neorv32
quartus_asm --read_settings_files=off --write_settings_files=off test_neorv32 -c test_neorv32
quartus_sta test_neorv32 -c test_neorv32
quartus_eda --read_settings_files=off --write_settings_files=off test_neorv32 -c test_neorv32



