116 lines
3.9 KiB
C++
116 lines
3.9 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __UCA_H__
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#define __UCA_H__
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#include "area.h"
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#include "bank.h"
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#include "component.h"
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#include "parameter.h"
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#include "htree2.h"
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#include "memorybus.h"
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#include "basic_circuit.h"
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#include "cacti_interface.h"
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class UCA : public Component
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{
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public:
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UCA(const DynamicParameter & dyn_p);
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~UCA();
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double compute_delays(double inrisetime); // returns outrisetime
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void compute_power_energy();
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DynamicParameter dp;
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Bank bank;
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Htree2 * htree_in_add;
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Htree2 * htree_in_data;
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Htree2 * htree_out_data;
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Htree2 * htree_in_search;
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Htree2 * htree_out_search;
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Memorybus * membus_RAS;
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Memorybus * membus_CAS;
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Memorybus * membus_data;
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powerDef power_routing_to_bank;
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uint32_t nbanks;
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int num_addr_b_bank;
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int num_di_b_bank;
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int num_do_b_bank;
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int num_si_b_bank;
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int num_so_b_bank;
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int RWP, ERP, EWP,SCHP;
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double area_all_dataramcells;
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double total_area_per_die;
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double dyn_read_energy_from_closed_page;
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double dyn_read_energy_from_open_page;
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double dyn_read_energy_remaining_words_in_burst;
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double refresh_power; // only for DRAM
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double activate_energy;
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double read_energy;
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double write_energy;
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double precharge_energy;
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double leak_power_subbank_closed_page;
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double leak_power_subbank_open_page;
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double leak_power_request_and_reply_networks;
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double delay_array_to_sa_mux_lev_1_decoder;
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double delay_array_to_sa_mux_lev_2_decoder;
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double delay_before_subarray_output_driver;
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double delay_from_subarray_out_drv_to_out;
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double access_time;
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double precharge_delay;
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double multisubbank_interleave_cycle_time;
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double t_RAS, t_CAS, t_RCD, t_RC, t_RP, t_RRD;
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double activate_power, read_power, write_power;
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double delay_TSV_tot, area_TSV_tot, dyn_pow_TSV_tot, dyn_pow_TSV_per_access;
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unsigned int num_TSV_tot;
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unsigned int comm_bits, row_add_bits, col_add_bits, data_bits;
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double area_lwl_drv, area_row_predec_dec, area_col_predec_dec,
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area_subarray, area_bus, area_address_bus, area_data_bus, area_data_drv, area_IOSA, area_sense_amp,
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area_per_bank;
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};
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#endif
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