114 lines
3.6 KiB
INI
114 lines
3.6 KiB
INI
//-size (bytes) 16777216
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//-size (bytes) 33554432
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-size (bytes) 134217728
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//-size (bytes) 67108864
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//-size (bytes) 1073741824
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-block size (bytes) 64
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-associativity 1
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-read-write port 1
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-exclusive read port 0
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-exclusive write port 0
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-single ended read ports 0
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-UCA bank count 1
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//-technology (u) 0.032
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//-technology (u) 0.045
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-technology (u) 0.068
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//-technology (u) 0.078
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# following three parameters are meaningful only for main memories
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-page size (bits) 8192
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-burst length 8
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-internal prefetch width 8
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# following parameter can have one of the five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
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-Data array cell type - "comm-dram"
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# following parameter can have one of the three values -- (itrs-hp, itrs-lstp, itrs-lop)
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-Data array peripheral type - "itrs-hp"
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# following parameter can have one of the five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
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-Tag array cell type - "itrs-hp"
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# following parameter can have one of the three values -- (itrs-hp, itrs-lstp, itrs-lop)
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-Tag array peripheral type - "itrs-hp"
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# Bus width include data bits and address bits required by the decoder
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//-output/input bus width 512
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-output/input bus width 64
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-operating temperature (K) 350
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-cache type "main memory"
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# to model special structure like branch target buffers, directory, etc.
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# change the tag size parameter
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# if you want cacti to calculate the tagbits, set the tag size to "default"
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-tag size (b) "default"
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//-tag size (b) 45
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# fast - data and tag access happen in parallel
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# sequential - data array is accessed after accessing the tag array
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# normal - data array lookup and tag access happen in parallel
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# final data block is broadcasted in data array h-tree
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# after getting the signal from the tag array
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//-access mode (normal, sequential, fast) - "fast"
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-access mode (normal, sequential, fast) - "normal"
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//-access mode (normal, sequential, fast) - "sequential"
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# DESIGN OBJECTIVE for UCA (or banks in NUCA)
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//-design objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:0
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-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:100:0
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-deviate (delay, dynamic power, leakage power, cycle time, area) 20:100000:100000:100000:1000000
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//-deviate (delay, dynamic power, leakage power, cycle time, area) 200:100000:100000:100000:20
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-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
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-Cache model (NUCA, UCA) - "UCA"
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//-Wire signalling (fullswing, lowswing, default) - "default"
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-Wire signalling (fullswing, lowswing, default) - "Global_10"
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-Wire inside mat - "global"
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//-Wire inside mat - "semi-global"
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-Wire outside mat - "global"
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-Interconnect projection - "conservative"
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//-Interconnect projection - "aggressive"
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-Add ECC - "true"
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-Print level (DETAILED, CONCISE) - "DETAILED"
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# for debugging
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-Print input parameters - "true"
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# force CACTI to model the cache with the
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# following Ndbl, Ndwl, Nspd, Ndsam,
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# and Ndcm values
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//-Force cache config - "true"
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-Force cache config - "false"
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-Ndwl 1
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-Ndbl 1
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-Nspd 0
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-Ndcm 1
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-Ndsam1 0
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-Ndsam2 0
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########### NUCA Params ############
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# Objective for NUCA
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-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100
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-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
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# Contention in network (which is a function of core count and cache level) is one of
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# the critical factor used for deciding the optimal bank count value
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# core count can be 4, 8, or 16
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//-Core count 4
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-Core count 8
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//-Core count 16
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-Cache level (L2/L3) - "L3"
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# In order for CACTI to find the optimal NUCA bank value the following
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# variable should be assigned 0.
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-NUCA bank count 0
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