174 lines
5.5 KiB
C++
174 lines
5.5 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <time.h>
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#include <math.h>
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#include "area.h"
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#include "basic_circuit.h"
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#include "component.h"
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#include "const.h"
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#include "parameter.h"
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#include "cacti_interface.h"
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#include "Ucache.h"
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#include <pthread.h>
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#include <iostream>
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#include <algorithm>
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using namespace std;
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bool mem_array::lt(const mem_array * m1, const mem_array * m2)
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{
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if (m1->Nspd < m2->Nspd) return true;
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else if (m1->Nspd > m2->Nspd) return false;
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else if (m1->Ndwl < m2->Ndwl) return true;
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else if (m1->Ndwl > m2->Ndwl) return false;
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else if (m1->Ndbl < m2->Ndbl) return true;
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else if (m1->Ndbl > m2->Ndbl) return false;
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else if (m1->deg_bl_muxing < m2->deg_bl_muxing) return true;
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else if (m1->deg_bl_muxing > m2->deg_bl_muxing) return false;
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else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) return true;
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else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) return false;
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else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) return true;
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else return false;
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}
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void uca_org_t::find_delay()
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{
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mem_array * data_arr = data_array2;
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mem_array * tag_arr = tag_array2;
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// check whether it is a regular cache or scratch ram
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if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)
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{
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access_time = data_arr->access_time;
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}
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// Both tag and data lookup happen in parallel
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// and the entire set is sent over the data array h-tree without
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// waiting for the way-select signal --TODO add the corresponding
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// power overhead Nav
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else if (g_ip->fast_access == true)
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{
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access_time = MAX(tag_arr->access_time, data_arr->access_time);
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}
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// Tag is accessed first. On a hit, way-select signal along with the
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// address is sent to read/write the appropriate block in the data
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// array
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else if (g_ip->is_seq_acc == true)
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{
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access_time = tag_arr->access_time + data_arr->access_time;
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}
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// Normal access: tag array access and data array access happen in parallel.
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// But, the data array will wait for the way-select and transfer only the
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// appropriate block over the h-tree.
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else
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{
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access_time = MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder,
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data_arr->delay_before_subarray_output_driver) +
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data_arr->delay_from_subarray_output_driver_to_output;
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}
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}
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void uca_org_t::find_energy()
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{
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if (!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache)
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power = data_array2->power + tag_array2->power;
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else
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power = data_array2->power;
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}
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void uca_org_t::find_area()
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{
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if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)//(g_ip->is_cache == false)
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{
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cache_ht = data_array2->height;
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cache_len = data_array2->width;
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}
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else
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{
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cache_ht = MAX(tag_array2->height, data_array2->height);
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cache_len = tag_array2->width + data_array2->width;
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}
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area = cache_ht * cache_len;
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}
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void uca_org_t::adjust_area()
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{
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double area_adjust;
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if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)
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{
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if (data_array2->area_efficiency/100.0<0.2)
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{
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//area_adjust = sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2));
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area_adjust = sqrt(0.2/(data_array2->area_efficiency/100.0));
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cache_ht = cache_ht/area_adjust;
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cache_len = cache_len/area_adjust;
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}
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}
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area = cache_ht * cache_len;
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}
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void uca_org_t::find_cyc()
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{
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if ((g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache == false)
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{
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cycle_time = data_array2->cycle_time;
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}
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else
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{
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cycle_time = MAX(tag_array2->cycle_time,
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data_array2->cycle_time);
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}
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}
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uca_org_t :: uca_org_t()
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:tag_array2(0),
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data_array2(0)
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{
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}
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void uca_org_t :: cleanup()
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{
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if (data_array2!=0)
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delete data_array2;
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if (tag_array2!=0)
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delete tag_array2;
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}
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