150 lines
5.3 KiB
C++
150 lines
5.3 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __MEMORYBUS_H__
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#define __MEMORYBUS_H__
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#include "basic_circuit.h"
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#include "component.h"
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#include "parameter.h"
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//#include "assert.h"
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#include "cacti_interface.h"
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//#include "wire.h"
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class Wire;
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//#include "area.h"
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#include "decoder.h"
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class Memorybus : public Component
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{
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public:
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Memorybus(enum Wire_type wire_model, double mat_w, double mat_h, double subarray_w, double subarray_h,
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int _row_add_bits, int _col_add_bits, int _data_bits, int _ndbl, int _ndwl, /*enum Htree_type htree_type,*/
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enum Memorybus_type membus_type, const DynamicParameter & dp_,
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/*TechnologyParameter::*/DeviceType *dt = &(g_tp.peri_global)
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);
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~Memorybus();
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//void in_membus();
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//void out_membus();
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void Network();
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// repeaters only at h-tree nodes
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void limited_in_membus();
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void limited_out_membus();
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void input_nand(double s1, double s2, double l);
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//void output_buffer(double s1, double s2, double l);
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const DynamicParameter & dp;
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double in_rise_time, out_rise_time;
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void set_in_rise_time(double rt)
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{
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in_rise_time = rt;
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}
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double max_unpipelined_link_delay;
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powerDef power_bit;
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void memory_bus();
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double height_bank, length_bank; // The actual height and length of a single bank including all wires between subarrays.
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Wire * center_stripe;
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Wire * bank_bus;
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Wire * global_WL; //3 hierarchical connection wires.
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Wire * column_sel;
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Wire * local_data;
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Wire * global_data;
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Wire * out_seg;
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// Driver for LWL connecting GWL, same as in mat.cc
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double lwl_driver_c_gate_load, lwl_driver_c_wire_load, lwl_driver_r_wire_load;
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powerDef power_bus;
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powerDef power_lwl_drv;
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powerDef power_add_decoders;
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powerDef power_global_WL;
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powerDef power_local_WL;
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powerDef power_add_predecoder;
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powerDef power_burst;
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powerDef power_col_sel;
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powerDef power_local_data;
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powerDef power_global_data;
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double delay_bus, delay_add_predecoder, delay_add_decoder, delay_lwl_drv, delay_global_data, delay_local_data, delay_data_buffer;
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double area_lwl_drv, area_row_predec_dec, area_col_predec_dec, area_subarray, area_bus, area_address_bus, area_data_bus, area_data_drv, area_IOSA, area_local_dataline, area_sense_amp;
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Area cell;
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bool is_dram;
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Driver * lwl_drv, * local_data_drv, * global_data_drv ;
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Predec * add_predec;
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Decoder * add_dec;
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double compute_delays(double inrisetime); // return outrisetime
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void compute_power_energy(); //
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private:
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double wire_bw;
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double init_wire_bw; // bus width at root
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enum Memorybus_type membus_type;
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// double htree_hnodes;
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// double htree_vnodes;
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double mat_width;
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double mat_height;
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double subarray_width, subarray_height;
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//int add_bits, data_in_bits,search_data_in_bits,data_out_bits, search_data_out_bits;
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int row_add_bits, col_add_bits;
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int add_bits, data_bits, num_dec_signals;
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int semi_repeated_global_line;
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int ndbl, ndwl;
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// bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
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// bool search_tree;
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enum Wire_type wt;
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double min_w_nmos;
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double min_w_pmos;
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int num_lwl_drv; //Ratio between GWL and LWL, how many local WL drives each GWL drives.
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int chip_IO_width;
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int burst_length;
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int num_subarray_global_IO;
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double C_GWL, C_LWL, R_GWL, R_LWL, C_colsel, R_colsel, C_global_data, R_global_data; // Capacitance of global/local WLs.
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/*TechnologyParameter::*/DeviceType *deviceType;
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};
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#endif
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