640 lines
23 KiB
C++
640 lines
23 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include "htree2.h"
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#include "wire.h"
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#include <assert.h>
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#include <iostream>
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Htree2::Htree2(
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enum Wire_type wire_model, double mat_w, double mat_h,
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int a_bits, int d_inbits, int search_data_in, int d_outbits, int search_data_out, int bl, int wl, enum Htree_type htree_type,
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bool uca_tree_, bool search_tree_, /*TechnologyParameter::*/DeviceType *dt)
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:in_rise_time(0), out_rise_time(0),
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tree_type(htree_type), mat_width(mat_w), mat_height(mat_h),
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add_bits(a_bits), data_in_bits(d_inbits), search_data_in_bits(search_data_in),data_out_bits(d_outbits),
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search_data_out_bits(search_data_out), ndbl(bl), ndwl(wl),
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uca_tree(uca_tree_), search_tree(search_tree_), wt(wire_model), deviceType(dt)
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{
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assert(ndbl >= 2 && ndwl >= 2);
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// if (ndbl == 1 && ndwl == 1)
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// {
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// delay = 0;
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// power.readOp.dynamic = 0;
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// power.readOp.leakage = 0;
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// area.w = mat_w;
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// area.h = mat_h;
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// return;
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// }
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// if (ndwl == 1) ndwl++;
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// if (ndbl == 1) ndbl++;
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max_unpipelined_link_delay = 0; //TODO
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min_w_nmos = g_tp.min_w_nmos_;
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min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * min_w_nmos;
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switch (htree_type)
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{
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case Add_htree:
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wire_bw = init_wire_bw = add_bits;
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in_htree();
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break;
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case Data_in_htree:
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wire_bw = init_wire_bw = data_in_bits;
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in_htree();
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break;
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case Data_out_htree:
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wire_bw = init_wire_bw = data_out_bits;
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out_htree();
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break;
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case Search_in_htree:
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wire_bw = init_wire_bw = search_data_in_bits;//in_search_tree is broad cast, out_htree is not.
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in_htree();
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break;
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case Search_out_htree:
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wire_bw = init_wire_bw = search_data_out_bits;
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out_htree();
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break;
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default:
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assert(0);
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break;
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}
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power_bit = power;
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power.readOp.dynamic *= init_wire_bw;
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assert(power.readOp.dynamic >= 0);
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assert(power.readOp.leakage >= 0);
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}
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// nand gate sizing calculation
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void Htree2::input_nand(double s1, double s2, double l_eff)
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{
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Wire w1(wt, l_eff);
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double pton_size = deviceType->n_to_p_eff_curr_drv_ratio;
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// input capacitance of a repeater = input capacitance of nand.
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double nsize = s1*(1 + pton_size)/(2 + pton_size);
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nsize = (nsize < 1) ? 1 : nsize;
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double tc = 2*tr_R_on(nsize*min_w_nmos, NCH, 1) *
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(drain_C_(nsize*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)*2 +
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2 * gate_C(s2*(min_w_nmos + min_w_pmos), 0));
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delay+= horowitz (w1.out_rise_time, tc,
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deviceType->Vth/deviceType->Vdd, deviceType->Vth/deviceType->Vdd, RISE);
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power.readOp.dynamic += 0.5 *
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(2*drain_C_(pton_size * nsize*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+ drain_C_(nsize*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+ 2*gate_C(s2*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd;
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power.searchOp.dynamic += 0.5 *
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(2*drain_C_(pton_size * nsize*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+ drain_C_(nsize*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+ 2*gate_C(s2*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd * wire_bw ;
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power.readOp.leakage += (wire_bw*cmos_Isub_leakage(min_w_nmos*(nsize*2), min_w_pmos * nsize * 2, 2, nand))*deviceType->Vdd;
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power.readOp.gate_leakage += (wire_bw*cmos_Ig_leakage(min_w_nmos*(nsize*2), min_w_pmos * nsize * 2, 2, nand))*deviceType->Vdd;
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}
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// tristate buffer model consisting of not, nand, nor, and driver transistors
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void Htree2::output_buffer(double s1, double s2, double l_eff)
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{
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Wire w1(wt, l_eff);
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double pton_size = deviceType->n_to_p_eff_curr_drv_ratio;
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// input capacitance of repeater = input capacitance of nand + nor.
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double size = s1*(1 + pton_size)/(2 + pton_size + 1 + 2*pton_size);
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double s_eff = //stage eff of a repeater in a wire
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(gate_C(s2*(min_w_nmos + min_w_pmos), 0) + w1.wire_cap(l_eff*1e-6,true))/
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gate_C(s2*(min_w_nmos + min_w_pmos), 0);
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double tr_size = gate_C(s1*(min_w_nmos + min_w_pmos), 0) * 1/2/(s_eff*gate_C(min_w_pmos, 0));
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size = (size < 1) ? 1 : size;
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double res_nor = 2*tr_R_on(size*min_w_pmos, PCH, 1);
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double res_ptrans = tr_R_on(tr_size*min_w_nmos, NCH, 1);
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double cap_nand_out = drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 +
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gate_C(tr_size*min_w_pmos, 0);
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double cap_ptrans_out = 2 *(drain_C_(tr_size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(tr_size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)) +
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gate_C(s1*(min_w_nmos + min_w_pmos), 0);
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double tc = res_nor * cap_nand_out + (res_nor + res_ptrans) * cap_ptrans_out;
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delay += horowitz (w1.out_rise_time, tc,
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deviceType->Vth/deviceType->Vdd, deviceType->Vth/deviceType->Vdd, RISE);
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//nand
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power.readOp.dynamic += 0.5 *
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(2*drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) +
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gate_C(tr_size*(min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd;
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power.searchOp.dynamic += 0.5 *
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(2*drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def) +
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gate_C(tr_size*(min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd*init_wire_bw;
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//not
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power.readOp.dynamic += 0.5 *
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(drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+gate_C(size*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd;
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power.searchOp.dynamic += 0.5 *
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(drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+gate_C(size*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd*init_wire_bw;
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//nor
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power.readOp.dynamic += 0.5 *
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(drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+ 2*drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+gate_C(tr_size*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd;
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power.searchOp.dynamic += 0.5 *
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(drain_C_(size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+ 2*drain_C_(size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def)
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+gate_C(tr_size*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd*init_wire_bw;
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//output transistor
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power.readOp.dynamic += 0.5 *
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((drain_C_(tr_size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+drain_C_(tr_size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def))*2
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+ gate_C(s1*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd;
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power.searchOp.dynamic += 0.5 *
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((drain_C_(tr_size*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)
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+drain_C_(tr_size*min_w_nmos, NCH, 1, 1, g_tp.cell_h_def))*2
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+ gate_C(s1*(min_w_nmos + min_w_pmos), 0)) *
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deviceType->Vdd * deviceType->Vdd*init_wire_bw;
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if(uca_tree) {
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*tr_size*2, min_w_pmos*tr_size*2, 1, inv)*deviceType->Vdd*wire_bw;/*inverter + output tr*/
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nand)*deviceType->Vdd*wire_bw;//nand
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nor)*deviceType->Vdd*wire_bw;//nor
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*tr_size*2, min_w_pmos*tr_size*2, 1, inv)*deviceType->Vdd*wire_bw;/*inverter + output tr*/
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nand)*deviceType->Vdd*wire_bw;//nand
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nor)*deviceType->Vdd*wire_bw;//nor
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//power.readOp.gate_leakage *=;
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}
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else {
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*tr_size*2, min_w_pmos*tr_size*2, 1, inv)*deviceType->Vdd*wire_bw;/*inverter + output tr*/
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nand)*deviceType->Vdd*wire_bw;//nand
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power.readOp.leakage += cmos_Isub_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nor)*deviceType->Vdd*wire_bw;//nor
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*tr_size*2, min_w_pmos*tr_size*2, 1, inv)*deviceType->Vdd*wire_bw;/*inverter + output tr*/
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nand)*deviceType->Vdd*wire_bw;//nand
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power.readOp.gate_leakage += cmos_Ig_leakage(min_w_nmos*size*3, min_w_pmos*size*3, 2, nor)*deviceType->Vdd*wire_bw;//nor
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//power.readOp.gate_leakage *=deviceType->Vdd*wire_bw;
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}
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}
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/* calculates the input h-tree delay/power
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* A nand gate is used at each node to
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* limit the signal
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* The area of an unbalanced htree (rows != columns)
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* depends on how data is traversed.
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* In the following function, if ( no. of rows < no. of columns),
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* then data first traverse in excess hor. links until vertical
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* and horizontal nodes are same.
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* If no. of rows is bigger, then data traverse in
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* a hor. link followed by a ver. link in a repeated
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* fashion (similar to a balanced tree) until there are no
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* hor. links left. After this it goes through the remaining vertical
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* links.
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*/
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void
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Htree2::in_htree()
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{
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//temp var
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double s1 = 0, s2 = 0, s3 = 0;
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double l_eff = 0;
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Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0;
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double len = 0, ht = 0;
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int option = 0;
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int h = (int) _log2(ndwl/2); // horizontal nodes
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int v = (int) _log2(ndbl/2); // vertical nodes
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double len_temp;
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double ht_temp;
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if (uca_tree)
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{//: this computation do not consider the wires that route from edge to middle.
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ht_temp = (mat_height*ndbl/2 +/* since uca_tree models interbank tree, mat_height => bank height */
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((add_bits + data_in_bits + data_out_bits + (search_data_in_bits + search_data_out_bits)) * g_tp.wire_outside_mat.pitch *
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2 * (1-pow(0.5,h))))/2;
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len_temp = (mat_width*ndwl/2 +
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((add_bits + data_in_bits + data_out_bits + (search_data_in_bits + search_data_out_bits)) * g_tp.wire_outside_mat.pitch *
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2 * (1-pow(0.5,v))))/2;
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}
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else
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{
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if (ndwl == ndbl) {
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ht_temp = ((mat_height*ndbl/2) +
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((add_bits + (search_data_in_bits + search_data_out_bits))* (ndbl/2-1) * g_tp.wire_outside_mat.pitch) +
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((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)
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)/2;
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len_temp = (mat_width*ndwl/2 +
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((add_bits + (search_data_in_bits + search_data_out_bits)) * (ndwl/2-1) * g_tp.wire_outside_mat.pitch) +
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((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v))/2;
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}
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else if (ndwl > ndbl) {
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double excess_part = (_log2(ndwl/2) - _log2(ndbl/2));
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ht_temp = ((mat_height*ndbl/2) +
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((add_bits + + (search_data_in_bits + search_data_out_bits)) * ((ndbl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
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(data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch *
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(2*(1 - pow(0.5, h-v)) + pow(0.5, v-h) * v))/2;
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len_temp = (mat_width*ndwl/2 +
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((add_bits + (search_data_in_bits + search_data_out_bits))* (ndwl/2-1) * g_tp.wire_outside_mat.pitch) +
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((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v))/2;
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}
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else {
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double excess_part = (_log2(ndbl/2) - _log2(ndwl/2));
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ht_temp = ((mat_height*ndbl/2) +
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((add_bits + (search_data_in_bits + search_data_out_bits))* ((ndwl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
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((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)
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)/2;
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len_temp = (mat_width*ndwl/2 +
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((add_bits + (search_data_in_bits + search_data_out_bits)) * ((ndwl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
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(data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * (h + 2*(1-pow(0.5, v-h))))/2;
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}
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}
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area.h = ht_temp * 2;
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area.w = len_temp * 2;
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delay = 0;
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power.readOp.dynamic = 0;
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power.readOp.leakage = 0;
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power.searchOp.dynamic =0;
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len = len_temp;
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ht = ht_temp/2;
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while (v > 0 || h > 0)
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{
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if (wtemp1) delete wtemp1;
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if (wtemp2) delete wtemp2;
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if (wtemp3) delete wtemp3;
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if (h > v)
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{
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//the iteration considers only one horizontal link
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wtemp1 = new Wire(wt, len); // hor
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wtemp2 = new Wire(wt, len/2); // ver
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len_temp = len;
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len /= 2;
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wtemp3 = 0;
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h--;
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option = 0;
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}
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else if (v>0 && h>0)
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{
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//considers one horizontal link and one vertical link
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wtemp1 = new Wire(wt, len); // hor
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wtemp2 = new Wire(wt, ht); // ver
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wtemp3 = new Wire(wt, len/2); // next hor
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len_temp = len;
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ht_temp = ht;
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len /= 2;
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ht /= 2;
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v--;
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h--;
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option = 1;
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}
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else
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{
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// considers only one vertical link
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assert(h == 0);
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wtemp1 = new Wire(wt, ht); // ver
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wtemp2 = new Wire(wt, ht/2); // hor
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ht_temp = ht;
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ht /= 2;
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wtemp3 = 0;
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v--;
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option = 2;
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}
|
|
|
|
delay += wtemp1->delay;
|
|
power.readOp.dynamic += wtemp1->power.readOp.dynamic;
|
|
power.searchOp.dynamic += wtemp1->power.readOp.dynamic*wire_bw;
|
|
power.readOp.leakage += wtemp1->power.readOp.leakage*wire_bw;
|
|
power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage*wire_bw;
|
|
if ((uca_tree == false && option == 2) || search_tree==true)
|
|
{
|
|
wire_bw*=2; // wire bandwidth doubles only for vertical branches
|
|
}
|
|
|
|
if (uca_tree == false)
|
|
{
|
|
if (len_temp > wtemp1->repeater_spacing)
|
|
{
|
|
s1 = wtemp1->repeater_size;
|
|
l_eff = wtemp1->repeater_spacing;
|
|
}
|
|
else
|
|
{
|
|
s1 = (len_temp/wtemp1->repeater_spacing) * wtemp1->repeater_size;
|
|
l_eff = len_temp;
|
|
}
|
|
|
|
if (ht_temp > wtemp2->repeater_spacing)
|
|
{
|
|
s2 = wtemp2->repeater_size;
|
|
}
|
|
else
|
|
{
|
|
s2 = (len_temp/wtemp2->repeater_spacing) * wtemp2->repeater_size;
|
|
}
|
|
// first level
|
|
input_nand(s1, s2, l_eff);
|
|
}
|
|
|
|
|
|
if (option != 1)
|
|
{
|
|
continue;
|
|
}
|
|
|
|
// second level
|
|
delay += wtemp2->delay;
|
|
power.readOp.dynamic += wtemp2->power.readOp.dynamic;
|
|
power.searchOp.dynamic += wtemp2->power.readOp.dynamic*wire_bw;
|
|
power.readOp.leakage += wtemp2->power.readOp.leakage*wire_bw;
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
|
|
if (uca_tree)
|
|
{
|
|
power.readOp.leakage += (wtemp2->power.readOp.leakage*wire_bw);
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
}
|
|
else
|
|
{
|
|
power.readOp.leakage += (wtemp2->power.readOp.leakage*wire_bw);
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
wire_bw*=2;
|
|
|
|
if (ht_temp > wtemp3->repeater_spacing)
|
|
{
|
|
s3 = wtemp3->repeater_size;
|
|
l_eff = wtemp3->repeater_spacing;
|
|
}
|
|
else
|
|
{
|
|
s3 = (len_temp/wtemp3->repeater_spacing) * wtemp3->repeater_size;
|
|
l_eff = ht_temp;
|
|
}
|
|
|
|
input_nand(s2, s3, l_eff);
|
|
}
|
|
}
|
|
|
|
if (wtemp1) delete wtemp1;
|
|
if (wtemp2) delete wtemp2;
|
|
if (wtemp3) delete wtemp3;
|
|
}
|
|
|
|
|
|
|
|
/* a tristate buffer is used to handle fan-ins
|
|
* The area of an unbalanced htree (rows != columns)
|
|
* depends on how data is traversed.
|
|
* In the following function, if ( no. of rows < no. of columns),
|
|
* then data first traverse in excess hor. links until vertical
|
|
* and horizontal nodes are same.
|
|
* If no. of rows is bigger, then data traverse in
|
|
* a hor. link followed by a ver. link in a repeated
|
|
* fashion (similar to a balanced tree) until there are no
|
|
* hor. links left. After this it goes through the remaining vertical
|
|
* links.
|
|
*/
|
|
void Htree2::out_htree()
|
|
{
|
|
//temp var
|
|
double s1 = 0, s2 = 0, s3 = 0;
|
|
double l_eff = 0;
|
|
Wire *wtemp1 = 0, *wtemp2 = 0, *wtemp3 = 0;
|
|
double len = 0, ht = 0;
|
|
int option = 0;
|
|
|
|
int h = (int) _log2(ndwl/2);
|
|
int v = (int) _log2(ndbl/2);
|
|
double len_temp;
|
|
double ht_temp;
|
|
if (uca_tree)
|
|
{
|
|
ht_temp = (mat_height*ndbl/2 +/* since uca_tree models interbank tree, mat_height => bank height */
|
|
((add_bits + data_in_bits + data_out_bits + (search_data_in_bits + search_data_out_bits)) * g_tp.wire_outside_mat.pitch *
|
|
2 * (1-pow(0.5,h))))/2;
|
|
len_temp = (mat_width*ndwl/2 +
|
|
((add_bits + data_in_bits + data_out_bits + (search_data_in_bits + search_data_out_bits)) * g_tp.wire_outside_mat.pitch *
|
|
2 * (1-pow(0.5,v))))/2;
|
|
}
|
|
else
|
|
{
|
|
if (ndwl == ndbl) {
|
|
ht_temp = ((mat_height*ndbl/2) +
|
|
((add_bits+ (search_data_in_bits + search_data_out_bits)) * (ndbl/2-1) * g_tp.wire_outside_mat.pitch) +
|
|
((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)
|
|
)/2;
|
|
len_temp = (mat_width*ndwl/2 +
|
|
((add_bits + (search_data_in_bits + search_data_out_bits)) * (ndwl/2-1) * g_tp.wire_outside_mat.pitch) +
|
|
((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v))/2;
|
|
|
|
}
|
|
else if (ndwl > ndbl) {
|
|
double excess_part = (_log2(ndwl/2) - _log2(ndbl/2));
|
|
ht_temp = ((mat_height*ndbl/2) +
|
|
((add_bits + (search_data_in_bits + search_data_out_bits)) * ((ndbl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
|
|
(data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch *
|
|
(2*(1 - pow(0.5, h-v)) + pow(0.5, v-h) * v))/2;
|
|
len_temp = (mat_width*ndwl/2 +
|
|
((add_bits + (search_data_in_bits + search_data_out_bits))* (ndwl/2-1) * g_tp.wire_outside_mat.pitch) +
|
|
((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * v))/2;
|
|
}
|
|
else {
|
|
double excess_part = (_log2(ndbl/2) - _log2(ndwl/2));
|
|
ht_temp = ((mat_height*ndbl/2) +
|
|
((add_bits + (search_data_in_bits + search_data_out_bits))* ((ndwl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
|
|
((data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * h)
|
|
)/2;
|
|
len_temp = (mat_width*ndwl/2 +
|
|
((add_bits + (search_data_in_bits + search_data_out_bits))* ((ndwl/2-1) + excess_part) * g_tp.wire_outside_mat.pitch) +
|
|
(data_in_bits + data_out_bits) * g_tp.wire_outside_mat.pitch * (h + 2*(1-pow(0.5, v-h))))/2;
|
|
}
|
|
}
|
|
area.h = ht_temp * 2;
|
|
area.w = len_temp * 2;
|
|
delay = 0;
|
|
power.readOp.dynamic = 0;
|
|
power.readOp.leakage = 0;
|
|
power.readOp.gate_leakage = 0;
|
|
//cout<<"power.readOp.gate_leakage"<<power.readOp.gate_leakage<<endl;
|
|
len = len_temp;
|
|
ht = ht_temp/2;
|
|
|
|
while (v > 0 || h > 0)
|
|
{ //finds delay/power of each link in the tree
|
|
if (wtemp1) delete wtemp1;
|
|
if (wtemp2) delete wtemp2;
|
|
if (wtemp3) delete wtemp3;
|
|
|
|
if(h > v) {
|
|
//the iteration considers only one horizontal link
|
|
wtemp1 = new Wire(wt, len); // hor
|
|
wtemp2 = new Wire(wt, len/2); // ver
|
|
len_temp = len;
|
|
len /= 2;
|
|
wtemp3 = 0;
|
|
h--;
|
|
option = 0;
|
|
}
|
|
else if (v>0 && h>0) {
|
|
//considers one horizontal link and one vertical link
|
|
wtemp1 = new Wire(wt, len); // hor
|
|
wtemp2 = new Wire(wt, ht); // ver
|
|
wtemp3 = new Wire(wt, len/2); // next hor
|
|
len_temp = len;
|
|
ht_temp = ht;
|
|
len /= 2;
|
|
ht /= 2;
|
|
v--;
|
|
h--;
|
|
option = 1;
|
|
}
|
|
else {
|
|
// considers only one vertical link
|
|
assert(h == 0);
|
|
wtemp1 = new Wire(wt, ht); // hor
|
|
wtemp2 = new Wire(wt, ht/2); // ver
|
|
ht_temp = ht;
|
|
ht /= 2;
|
|
wtemp3 = 0;
|
|
v--;
|
|
option = 2;
|
|
}
|
|
delay += wtemp1->delay;
|
|
power.readOp.dynamic += wtemp1->power.readOp.dynamic;
|
|
power.searchOp.dynamic += wtemp1->power.readOp.dynamic*init_wire_bw;
|
|
power.readOp.leakage += wtemp1->power.readOp.leakage*wire_bw;
|
|
power.readOp.gate_leakage += wtemp1->power.readOp.gate_leakage*wire_bw;
|
|
//cout<<"power.readOp.gate_leakage"<<power.readOp.gate_leakage<<endl;
|
|
if ((uca_tree == false && option == 2) || search_tree==true)
|
|
{
|
|
wire_bw*=2;
|
|
}
|
|
|
|
if (uca_tree == false)
|
|
{
|
|
if (len_temp > wtemp1->repeater_spacing)
|
|
{
|
|
s1 = wtemp1->repeater_size;
|
|
l_eff = wtemp1->repeater_spacing;
|
|
}
|
|
else
|
|
{
|
|
s1 = (len_temp/wtemp1->repeater_spacing) * wtemp1->repeater_size;
|
|
l_eff = len_temp;
|
|
}
|
|
if (ht_temp > wtemp2->repeater_spacing)
|
|
{
|
|
s2 = wtemp2->repeater_size;
|
|
}
|
|
else
|
|
{
|
|
s2 = (len_temp/wtemp2->repeater_spacing) * wtemp2->repeater_size;
|
|
}
|
|
// first level
|
|
output_buffer(s1, s2, l_eff);
|
|
}
|
|
|
|
|
|
if (option != 1)
|
|
{
|
|
continue;
|
|
}
|
|
|
|
// second level
|
|
delay += wtemp2->delay;
|
|
power.readOp.dynamic += wtemp2->power.readOp.dynamic;
|
|
power.searchOp.dynamic += wtemp2->power.readOp.dynamic*init_wire_bw;
|
|
power.readOp.leakage += wtemp2->power.readOp.leakage*wire_bw;
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
//cout<<"power.readOp.gate_leakage"<<power.readOp.gate_leakage<<endl;
|
|
if (uca_tree)
|
|
{
|
|
power.readOp.leakage += (wtemp2->power.readOp.leakage*wire_bw);
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
}
|
|
else
|
|
{
|
|
power.readOp.leakage += (wtemp2->power.readOp.leakage*wire_bw);
|
|
power.readOp.gate_leakage += wtemp2->power.readOp.gate_leakage*wire_bw;
|
|
wire_bw*=2;
|
|
|
|
if (ht_temp > wtemp3->repeater_spacing)
|
|
{
|
|
s3 = wtemp3->repeater_size;
|
|
l_eff = wtemp3->repeater_spacing;
|
|
}
|
|
else
|
|
{
|
|
s3 = (len_temp/wtemp3->repeater_spacing) * wtemp3->repeater_size;
|
|
l_eff = ht_temp;
|
|
}
|
|
|
|
output_buffer(s2, s3, l_eff);
|
|
}
|
|
//cout<<"power.readOp.leakage"<<power.readOp.leakage<<endl;
|
|
//cout<<"power.readOp.gate_leakage"<<power.readOp.gate_leakage<<endl;
|
|
//cout<<"wtemp2->power.readOp.gate_leakage"<<wtemp2->power.readOp.gate_leakage<<endl;
|
|
}
|
|
|
|
if (wtemp1) delete wtemp1;
|
|
if (wtemp2) delete wtemp2;
|
|
if (wtemp3) delete wtemp3;
|
|
}
|
|
|