194 lines
6.4 KiB
INI
194 lines
6.4 KiB
INI
# Cache size
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//-size (bytes) 528
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//-size (bytes) 4096
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//-size (bytes) 262144
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//-size (bytes) 1048576
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//-size (bytes) 2097152
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//-size (bytes) 4194304
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//-size (bytes) 8388608
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//-size (bytes) 16777216
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//-size (bytes) 33554432
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//-size (bytes) 134217728
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//-size (bytes) 268435456
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//-size (bytes) 536870912
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//-size (bytes) 67108864
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//-size (bytes) 536870912
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//-size (bytes) 1073741824
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# For 3D DRAM memory please use Gb as units
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-size (Gb) 1
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# Line size
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//-block size (bytes) 8
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-block size (bytes) 128
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# To model Fully Associative cache, set associativity to zero
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//-associativity 0
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//-associativity 2
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//-associativity 4
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-associativity 1
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//-associativity 16
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-read-write port 1
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-exclusive read port 0
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-exclusive write port 0
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-single ended read ports 0
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# Multiple banks connected using a bus
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-UCA bank count 8
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//-technology (u) 0.032
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//-technology (u) 0.040
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//-technology (u) 0.065
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-technology (u) 0.078
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//-technology (u) 0.080
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# following three parameters are meaningful only for main memories
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//-page size (bits) 8192
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-burst length 4
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-internal prefetch width 1
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# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
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//-Data array cell type - "itrs-hp"
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//-Data array cell type - "itrs-lstp"
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//-Data array cell type - "itrs-lop"
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-Data array cell type - "comm-dram"
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# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
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//-Data array peripheral type - "itrs-hp"
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-Data array peripheral type - "itrs-lstp"
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//-Data array peripheral type - "itrs-lop"
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# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
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-Tag array cell type - "itrs-hp"
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//-Tag array cell type - "itrs-lstp"
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# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
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-Tag array peripheral type - "itrs-hp"
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//-Tag array peripheral type - "itrs-lstp"
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# Bus width include data bits and address bits required by the decoder
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//-output/input bus width 16
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//-output/input bus width 64
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-output/input bus width 64
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// 300-400 in steps of 10
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-operating temperature (K) 350
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# Type of memory - cache (with a tag array) or ram (scratch ram similar to a register file)
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# or main memory (no tag array and every access will happen at a page granularity Ref: CACTI 5.3 report)
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//-cache type "cache"
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//-cache type "ram"
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//-cache type "main memory"
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-cache type "3D memory or 2D main memory"
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## Parameters for 3D DRAM
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-page size (bits) 16384
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//-page size (bits) 8192
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-burst depth 8
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-IO width 4
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-system frequency (MHz) 533
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-stacked die count 1
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-partitioning granularity 0 // 0: coarse-grained rank-level; 1: fine-grained rank-level
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//-TSV projection 1 // 0: ITRS aggressive; 1: industrial conservative
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## End of parameters for 3D DRAM
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# to model special structure like branch target buffers, directory, etc.
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# change the tag size parameter
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# if you want cacti to calculate the tagbits, set the tag size to "default"
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-tag size (b) "default"
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//-tag size (b) 45
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# fast - data and tag access happen in parallel
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# sequential - data array is accessed after accessing the tag array
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# normal - data array lookup and tag access happen in parallel
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# final data block is broadcasted in data array h-tree
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# after getting the signal from the tag array
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-access mode (normal, sequential, fast) - "fast"
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//-access mode (normal, sequential, fast) - "normal"
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//-access mode (normal, sequential, fast) - "sequential"
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# DESIGN OBJECTIVE for UCA (or banks in NUCA)
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-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:0:10
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# Percentage deviation from the minimum value
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# Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization
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# that compromises at most 10% delay.
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# NOTE: Try reasonable values for % deviation. Inconsistent deviation
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# percentage values will not produce any valid organizations. For example,
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# 0:0:100:100:100 will try to identify an organization that has both
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# least delay and dynamic power. Since such an organization is not possible, CACTI will
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# throw an error. Refer CACTI-6 Technical report for more details
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-deviate (delay, dynamic power, leakage power, cycle time, area) 50:100000:100000:100000:1000000
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# Objective for NUCA
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-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100
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-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
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# Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for
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# energy-delay or energy-delay sq. product
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# Note: Optimize tag will disable weight or deviate values mentioned above
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# Set it to NONE to let weight and deviate values determine the
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# appropriate cache configuration
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//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED"
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//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED^2"
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-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
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-Cache model (NUCA, UCA) - "UCA"
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//-Cache model (NUCA, UCA) - "NUCA"
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# In order for CACTI to find the optimal NUCA bank value the following
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# variable should be assigned 0.
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-NUCA bank count 0
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# NOTE: for nuca network frequency is set to a default value of
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# 5GHz in time.c. CACTI automatically
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# calculates the maximum possible frequency and downgrades this value if necessary
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# By default CACTI considers both full-swing and low-swing
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# wires to find an optimal configuration. However, it is possible to
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# restrict the search space by changing the signaling from "default" to
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# "fullswing" or "lowswing" type.
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-Wire signaling (fullswing, lowswing, default) - "Global_30"
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//-Wire signaling (fullswing, lowswing, default) - "default"
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//-Wire signaling (fullswing, lowswing, default) - "lowswing"
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//-Wire inside mat - "global"
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-Wire inside mat - "semi-global"
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-Wire outside mat - "global"
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//-Wire outside mat - "semi-global"
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-Interconnect projection - "conservative"
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//-Interconnect projection - "aggressive"
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# Contention in network (which is a function of core count and cache level) is one of
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# the critical factor used for deciding the optimal bank count value
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# core count can be 4, 8, or 16
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//-Core count 4
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-Core count 8
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//-Core count 16
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-Cache level (L2/L3) - "L3"
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-Add ECC - "true"
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//-Print level (DETAILED, CONCISE) - "CONCISE"
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-Print level (DETAILED, CONCISE) - "DETAILED"
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# for debugging
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//-Print input parameters - "true"
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-Print input parameters - "false"
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# force CACTI to model the cache with the
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# following Ndbl, Ndwl, Nspd, Ndsam,
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# and Ndcm values
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-Force cache config - "true"
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//-Force cache config - "false"
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-Ndwl 16
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-Ndbl 16
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-Nspd 1
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-Ndcm 1
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-Ndsam1 1
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-Ndsam2 1
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