311 lines
10 KiB
C++
311 lines
10 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include "router.h"
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Router::Router(
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double flit_size_,
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double vc_buf, /* vc size = vc_buffer_size * flit_size */
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double vc_c,
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/*TechnologyParameter::*/DeviceType *dt,
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double I_,
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double O_,
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double M_
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):flit_size(flit_size_),
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deviceType(dt),
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I(I_),
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O(O_),
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M(M_)
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{
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vc_buffer_size = vc_buf;
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vc_count = vc_c;
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min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio*g_tp.min_w_nmos_;
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double technology = g_ip->F_sz_um;
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Vdd = dt->Vdd;
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/*Crossbar parameters. Transmisson gate is employed for connector*/
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NTtr = 10*technology*1e-6/2; /*Transmission gate's nmos tr. length*/
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PTtr = 20*technology*1e-6/2; /* pmos tr. length*/
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wt = 15*technology*1e-6/2; /*track width*/
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ht = 15*technology*1e-6/2; /*track height*/
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// I = 5; /*Number of crossbar input ports*/
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// O = 5; /*Number of crossbar output ports*/
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NTi = 12.5*technology*1e-6/2;
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PTi = 25*technology*1e-6/2;
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NTid = 60*technology*1e-6/2; //m
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PTid = 120*technology*1e-6/2; // m
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NTod = 60*technology*1e-6/2; // m
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PTod = 120*technology*1e-6/2; // m
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calc_router_parameters();
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}
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Router::~Router(){}
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double //wire cap with triple spacing
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Router::Cw3(double length) {
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Wire wc(g_ip->wt, length, 1, 3, 3);
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return (wc.wire_cap(length));
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}
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/*Function to calculate the gate capacitance*/
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double
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Router::gate_cap(double w) {
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return (double) gate_C (w*1e6 /*u*/, 0);
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}
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/*Function to calculate the diffusion capacitance*/
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double
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Router::diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/,
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double s /*number of stacking transistors*/) {
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return (double) drain_C_(w*1e6 /*u*/, type, (int) s, 1, g_tp.cell_h_def);
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}
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/*crossbar related functions */
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// Model for simple transmission gate
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double
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Router::transmission_buf_inpcap() {
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return diff_cap(NTtr, 0, 1)+diff_cap(PTtr, 1, 1);
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}
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double
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Router::transmission_buf_outcap() {
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return diff_cap(NTtr, 0, 1)+diff_cap(PTtr, 1, 1);
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}
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double
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Router::transmission_buf_ctrcap() {
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return gate_cap(NTtr)+gate_cap(PTtr);
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}
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double
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Router::crossbar_inpline() {
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return (Cw3(O*flit_size*wt) + O*transmission_buf_inpcap() + gate_cap(NTid) +
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gate_cap(PTid) + diff_cap(NTid, 0, 1) + diff_cap(PTid, 1, 1));
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}
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double
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Router::crossbar_outline() {
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return (Cw3(I*flit_size*ht) + I*transmission_buf_outcap() + gate_cap(NTod) +
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gate_cap(PTod) + diff_cap(NTod, 0, 1) + diff_cap(PTod, 1, 1));
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}
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double
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Router::crossbar_ctrline() {
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return (Cw3(0.5*O*flit_size*wt) + flit_size*transmission_buf_ctrcap() +
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diff_cap(NTi, 0, 1) + diff_cap(PTi, 1, 1) +
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gate_cap(NTi) + gate_cap(PTi));
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}
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double
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Router::tr_crossbar_power() {
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return (crossbar_inpline()*Vdd*Vdd*flit_size/2 +
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crossbar_outline()*Vdd*Vdd*flit_size/2)*2;
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}
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void Router::buffer_stats()
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{
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DynamicParameter dyn_p;
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dyn_p.is_tag = false;
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dyn_p.pure_cam = false;
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dyn_p.fully_assoc = false;
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dyn_p.pure_ram = true;
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dyn_p.is_dram = false;
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dyn_p.is_main_mem = false;
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dyn_p.num_subarrays = 1;
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dyn_p.num_mats = 1;
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dyn_p.Ndbl = 1;
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dyn_p.Ndwl = 1;
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dyn_p.Nspd = 1;
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dyn_p.deg_bl_muxing = 1;
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dyn_p.deg_senseamp_muxing_non_associativity = 1;
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dyn_p.Ndsam_lev_1 = 1;
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dyn_p.Ndsam_lev_2 = 1;
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dyn_p.Ndcm = 1;
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dyn_p.number_addr_bits_mat = 8;
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dyn_p.number_way_select_signals_mat = 1;
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dyn_p.number_subbanks_decode = 0;
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dyn_p.num_act_mats_hor_dir = 1;
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dyn_p.V_b_sense = Vdd; // FIXME check power calc.
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dyn_p.ram_cell_tech_type = 0;
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dyn_p.num_r_subarray = (int) vc_buffer_size;
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dyn_p.num_c_subarray = (int) flit_size * (int) vc_count;
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dyn_p.num_mats_h_dir = 1;
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dyn_p.num_mats_v_dir = 1;
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dyn_p.num_do_b_subbank = (int)flit_size;
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dyn_p.num_di_b_subbank = (int)flit_size;
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dyn_p.num_do_b_mat = (int) flit_size;
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dyn_p.num_di_b_mat = (int) flit_size;
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dyn_p.num_do_b_mat = (int) flit_size;
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dyn_p.num_di_b_mat = (int) flit_size;
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dyn_p.num_do_b_bank_per_port = (int) flit_size;
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dyn_p.num_di_b_bank_per_port = (int) flit_size;
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dyn_p.out_w = (int) flit_size;
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dyn_p.use_inp_params = 1;
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dyn_p.num_wr_ports = (unsigned int) vc_count;
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dyn_p.num_rd_ports = 1;//(unsigned int) vc_count;//based on Bill Dally's book
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dyn_p.num_rw_ports = 0;
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dyn_p.num_se_rd_ports =0;
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dyn_p.num_search_ports =0;
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dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_wr_ports +
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dyn_p.num_rw_ports - 1 + dyn_p.num_rd_ports);
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dyn_p.cell.w = g_tp.sram.b_w + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_rw_ports - 1 +
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(dyn_p.num_rd_ports - dyn_p.num_se_rd_ports) +
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dyn_p.num_wr_ports) + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports;
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Mat buff(dyn_p);
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buff.compute_delays(0);
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buff.compute_power_energy();
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buffer.power.readOp = buff.power.readOp;
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buffer.power.writeOp = buffer.power.readOp; //FIXME
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buffer.area = buff.area;
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}
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void
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Router::cb_stats ()
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{
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if (1) {
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Crossbar c_b(I, O, flit_size);
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c_b.compute_power();
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crossbar.delay = c_b.delay;
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crossbar.power.readOp.dynamic = c_b.power.readOp.dynamic;
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crossbar.power.readOp.leakage = c_b.power.readOp.leakage;
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crossbar.power.readOp.gate_leakage = c_b.power.readOp.gate_leakage;
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crossbar.area = c_b.area;
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// c_b.print_crossbar();
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}
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else {
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crossbar.power.readOp.dynamic = tr_crossbar_power();
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crossbar.power.readOp.leakage = flit_size * I * O *
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cmos_Isub_leakage(NTtr*g_tp.min_w_nmos_, PTtr*min_w_pmos, 1, tg);
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crossbar.power.readOp.gate_leakage = flit_size * I * O *
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cmos_Ig_leakage(NTtr*g_tp.min_w_nmos_, PTtr*min_w_pmos, 1, tg);
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}
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}
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void
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Router::get_router_power()
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{
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/* calculate buffer stats */
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buffer_stats();
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/* calculate cross-bar stats */
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cb_stats();
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/* calculate arbiter stats */
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Arbiter vcarb(vc_count, flit_size, buffer.area.w);
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Arbiter cbarb(I, flit_size, crossbar.area.w);
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vcarb.compute_power();
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cbarb.compute_power();
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arbiter.power.readOp.dynamic = vcarb.power.readOp.dynamic * I +
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cbarb.power.readOp.dynamic * O;
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arbiter.power.readOp.leakage = vcarb.power.readOp.leakage * I +
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cbarb.power.readOp.leakage * O;
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arbiter.power.readOp.gate_leakage = vcarb.power.readOp.gate_leakage * I +
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cbarb.power.readOp.gate_leakage * O;
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// arb_stats();
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power.readOp.dynamic = ((buffer.power.readOp.dynamic+buffer.power.writeOp.dynamic) +
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crossbar.power.readOp.dynamic +
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arbiter.power.readOp.dynamic)*MIN(I, O)*M;
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double pppm_t[4] = {1,I,I,1};
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power = power + (buffer.power*pppm_t + crossbar.power + arbiter.power)*pppm_lkg;
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}
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void
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Router::get_router_delay ()
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{
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FREQUENCY=5; // move this to config file --TODO
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cycle_time = (1/(double)FREQUENCY)*1e3; //ps
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delay = 4;
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max_cyc = 17 * g_tp.FO4; //s
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max_cyc *= 1e12; //ps
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if (cycle_time < max_cyc) {
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FREQUENCY = (1/max_cyc)*1e3; //GHz
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}
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}
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void
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Router::get_router_area()
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{
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area.h = I*buffer.area.h;
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area.w = buffer.area.w+crossbar.area.w;
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}
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void
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Router::calc_router_parameters()
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{
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/* calculate router frequency and pipeline cycles */
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get_router_delay();
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/* router power stats */
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get_router_power();
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/* area stats */
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get_router_area();
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}
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void
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Router::print_router()
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{
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cout << "\n\nRouter stats:\n";
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cout << "\tRouter Area - "<< area.get_area()*1e-6<<"(mm^2)\n";
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cout << "\tMaximum possible network frequency - " << (1/max_cyc)*1e3 << "GHz\n";
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cout << "\tNetwork frequency - " << FREQUENCY <<" GHz\n";
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cout << "\tNo. of Virtual channels - " << vc_count << "\n";
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cout << "\tNo. of pipeline stages - " << delay << endl;
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cout << "\tLink bandwidth - " << flit_size << " (bits)\n";
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cout << "\tNo. of buffer entries per virtual channel - "<< vc_buffer_size << "\n";
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cout << "\tSimple buffer Area - "<< buffer.area.get_area()*1e-6<<"(mm^2)\n";
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cout << "\tSimple buffer access (Read) - " << buffer.power.readOp.dynamic * 1e9 <<" (nJ)\n";
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cout << "\tSimple buffer leakage - " << buffer.power.readOp.leakage * 1e3 <<" (mW)\n";
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cout << "\tCrossbar Area - "<< crossbar.area.get_area()*1e-6<<"(mm^2)\n";
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cout << "\tCross bar access energy - " << crossbar.power.readOp.dynamic * 1e9<<" (nJ)\n";
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cout << "\tCross bar leakage power - " << crossbar.power.readOp.leakage * 1e3<<" (mW)\n";
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cout << "\tArbiter access energy (VC arb + Crossbar arb) - "<<arbiter.power.readOp.dynamic * 1e9 <<" (nJ)\n";
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cout << "\tArbiter leakage (VC arb + Crossbar arb) - "<<arbiter.power.readOp.leakage * 1e3 <<" (mW)\n";
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}
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