234 lines
7.3 KiB
Text
234 lines
7.3 KiB
Text
Cache size : 131072
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Block size : 64
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Associativity : 2
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Read only ports : 0
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Write only ports : 0
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Read write ports : 1
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Single ended read ports : 0
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Cache banks (UCA) : 1
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Technology : 0.09
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Temperature : 360
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Tag size : 42
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array type : Cache
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Model as memory : 0
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Model as 3D memory : 0
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Access mode : 0
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Data array cell type : 0
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Data array peripheral type : 0
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Tag array cell type : 0
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Tag array peripheral type : 0
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Optimization target : 2
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Design objective (UCA wt) : 0 0 0 100 0
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Design objective (UCA dev) : 20 100000 100000 100000 100000
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Cache model : 0
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Nuca bank : 0
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Wire inside mat : 1
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Wire outside mat : 1
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Interconnect projection : 1
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Wire signaling : 1
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Print level : 1
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ECC overhead : 1
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Page size : 8192
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Burst length : 8
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Internal prefetch width : 8
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Force cache config : 0
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Subarray Driver direction : 1
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iostate : WRITE
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dram_ecc : NO_ECC
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io_type : DDR3
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dram_dimm : UDIMM
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IO Area (sq.mm) = inf
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IO Timing Margin (ps) = -14.1667
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IO Votlage Margin (V) = 0.155
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IO Dynamic Power (mW) = 1506.36 PHY Power (mW) = 232.752 PHY Wakeup Time (us) = 27.503
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IO Termination and Bias Power (mW) = 2505.96
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---------- CACTI (version 7.0.3DD Prerelease of Aug, 2012), Uniform Cache Access SRAM Model ----------
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Cache Parameters:
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Total cache size (bytes): 131072
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Number of banks: 1
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Associativity: 2
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Block size (bytes): 64
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Read/write Ports: 1
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Read ports: 0
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Write ports: 0
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Technology size (nm): 90
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Access time (ns): 1.47098
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Cycle time (ns): 1.86851
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Total dynamic read energy per access (nJ): 0.303592
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Total dynamic write energy per access (nJ): 0.615022
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Total leakage power of a bank (mW): 59.1454
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Total gate leakage power of a bank (mW): 4.55691
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Cache height x width (mm): 1.57965 x 1.42405
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Best Ndwl : 2
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Best Ndbl : 2
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Best Nspd : 1
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Best Ndcm : 2
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Best Ndsam L1 : 2
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Best Ndsam L2 : 1
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Best Ntwl : 2
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Best Ntbl : 2
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Best Ntspd : 4
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Best Ntcm : 1
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Best Ntsam L1 : 8
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Best Ntsam L2 : 1
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Data array, H-tree wire type: Global wires with 30% delay penalty
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Tag array, H-tree wire type: Global wires with 30% delay penalty
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Time Components:
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Data side (with Output driver) (ns): 1.47098
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H-tree input delay (ns): 0
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Decoder + wordline delay (ns): 0.752867
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Bitline delay (ns): 0.546781
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Sense Amplifier delay (ns): 0.0107354
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H-tree output delay (ns): 0.160596
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Tag side (with Output driver) (ns): 0.71334
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H-tree input delay (ns): 0
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Decoder + wordline delay (ns): 0.466679
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Bitline delay (ns): 0.147706
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Sense Amplifier delay (ns): 0.0107949
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Comparator delay (ns): 0.131234
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H-tree output delay (ns): 0.08816
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Power Components:
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Data array: Total dynamic read energy/access (nJ): 0.286158
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Total energy in H-tree (that includes both address and data transfer) (nJ): 0
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Output Htree inside bank Energy (nJ): 0
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Decoder (nJ): 0.00164907
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Wordline (nJ): 0.00212735
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Bitline mux & associated drivers (nJ): 0.00335251
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Sense amp mux & associated drivers (nJ): 0
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Bitlines precharge and equalization circuit (nJ): 0.0161369
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Bitlines (nJ): 0.116857
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Sense amplifier energy (nJ): 0.00726078
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Sub-array output driver (nJ): 0.137516
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Total leakage power of a bank (mW): 55.1285
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Total leakage power in H-tree (that includes both address and data network) ((mW)): 0
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Total leakage power in cells (mW): 0
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Total leakage power in row logic(mW): 0
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Total leakage power in column logic(mW): 0
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Total gate leakage power in H-tree (that includes both address and data network) ((mW)): 0
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Tag array: Total dynamic read energy/access (nJ): 0.0174337
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Total leakage read/write power of a bank (mW): 4.01688
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Total energy in H-tree (that includes both address and data transfer) (nJ): 0
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Output Htree inside a bank Energy (nJ): 0
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Decoder (nJ): 0.000340468
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Wordline (nJ): 0.000710492
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Bitline mux & associated drivers (nJ): 0
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Sense amp mux & associated drivers (nJ): 0.000330669
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Bitlines precharge and equalization circuit (nJ): 0.00425803
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Bitlines (nJ): 0.00759182
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Sense amplifier energy (nJ): 0.00354912
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Sub-array output driver (nJ): 0.000194898
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Total leakage power of a bank (mW): 4.01688
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Total leakage power in H-tree (that includes both address and data network) ((mW)): 0
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Total leakage power in cells (mW): 0
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Total leakage power in row logic(mW): 0
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Total leakage power in column logic(mW): 0
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Total gate leakage power in H-tree (that includes both address and data network) ((mW)): 0
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Area Components:
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Data array: Area (mm2): 1.78124
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Height (mm): 1.57965
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Width (mm): 1.12762
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Area efficiency (Memory cell area/Total area) - 78.3192 %
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MAT Height (mm): 1.57965
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MAT Length (mm): 1.12762
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Subarray Height (mm): 0.672768
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Subarray Length (mm): 0.5427
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Tag array: Area (mm2): 0.108777
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Height (mm): 0.366956
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Width (mm): 0.296431
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Area efficiency (Memory cell area/Total area) - 77.9289 %
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MAT Height (mm): 0.366956
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MAT Length (mm): 0.296431
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Subarray Height (mm): 0.168192
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Subarray Length (mm): 0.1314
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Wire Properties:
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Delay Optimal
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Repeater size - 61.5792
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Repeater spacing - 0.321831 (mm)
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Delay - 0.137938 (ns/mm)
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PowerD - 0.000766371 (nJ/mm)
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PowerL - 0.00525075 (mW/mm)
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PowerLgate - 0.000882254 (mW/mm)
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Wire width - 0.09 microns
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Wire spacing - 0.09 microns
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5% Overhead
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Repeater size - 34.5792
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Repeater spacing - 0.421831 (mm)
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Delay - 0.144333 (ns/mm)
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PowerD - 0.000519963 (nJ/mm)
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PowerL - 0.00224953 (mW/mm)
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PowerLgate - 0.000377976 (mW/mm)
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Wire width - 0.09 microns
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Wire spacing - 0.09 microns
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10% Overhead
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Repeater size - 32.5792
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Repeater spacing - 0.521831 (mm)
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Delay - 0.151515 (ns/mm)
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PowerD - 0.000485471 (nJ/mm)
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PowerL - 0.00171327 (mW/mm)
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PowerLgate - 0.000287871 (mW/mm)
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Wire width - 0.09 microns
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Wire spacing - 0.09 microns
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20% Overhead
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Repeater size - 27.5792
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Repeater spacing - 0.621831 (mm)
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Delay - 0.164984 (ns/mm)
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PowerD - 0.000447956 (nJ/mm)
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PowerL - 0.00121709 (mW/mm)
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PowerLgate - 0.000204502 (mW/mm)
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Wire width - 0.09 microns
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Wire spacing - 0.09 microns
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30% Overhead
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Repeater size - 21.5792
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Repeater spacing - 0.621831 (mm)
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Delay - 0.179014 (ns/mm)
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PowerD - 0.000419905 (nJ/mm)
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PowerL - 0.000952309 (mW/mm)
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PowerLgate - 0.000160011 (mW/mm)
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Wire width - 0.09 microns
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Wire spacing - 0.09 microns
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Low-swing wire (1 mm) - Note: Unlike repeated wires,
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delay and power values of low-swing wires do not
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have a linear relationship with length.
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delay - 0.611231 (ns)
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powerD - 2.52036e-05 (nJ)
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PowerL - 2.71875e-07 (mW)
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PowerLgate - 8.41995e-08 (mW)
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Wire width - 1.8e-07 microns
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Wire spacing - 1.8e-07 microns
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top 3 best memory configurations are:
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Memory cap: 80 GB num_bobs: 1 bw: 533 (MHz) cost: $731.2 energy: 32.6101 (nJ)
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{
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(0) BoB cap: 80 GB num_channels: 1 bw: 533 (MHz) cost: $731.2 energy: 32.6101 (nJ)
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==============
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(0) cap: 80 GB bw: 533 (MHz) cost: $731.2 dpc: 3 energy: 32.6101 (nJ) DIMM: RDIMM low power: F [ 0(4GB) 0(8GB) 1(16GB) 2(32GB) 0(64GB) ]
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==============
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}
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=============================================
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