237 lines
7.4 KiB
C++
237 lines
7.4 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include <assert.h>
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#include <iostream>
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#include <math.h>
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#include "bank.h"
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#include "component.h"
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#include "decoder.h"
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using namespace std;
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Component::Component()
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:area(), power(), rt_power(),delay(0)
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{
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}
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Component::~Component()
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{
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}
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double Component::compute_diffusion_width(int num_stacked_in, int num_folded_tr)
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{
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double w_poly = g_ip->F_sz_um;
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double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
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double total_diff_w = 2 * spacing_poly_to_poly + // for both source and drain
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num_stacked_in * w_poly +
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(num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
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if (num_folded_tr > 1)
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{
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total_diff_w += (num_folded_tr - 2) * 2 * spacing_poly_to_poly +
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(num_folded_tr - 1) * num_stacked_in * w_poly +
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(num_folded_tr - 1) * (num_stacked_in - 1) * g_tp.spacing_poly_to_poly;
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}
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return total_diff_w;
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}
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double Component::compute_gate_area(
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int gate_type,
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int num_inputs,
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double w_pmos,
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double w_nmos,
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double h_gate)
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{
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if (w_pmos <= 0.0 || w_nmos <= 0.0)
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{
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return 0.0;
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}
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double w_folded_pmos, w_folded_nmos;
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int num_folded_pmos, num_folded_nmos;
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double total_ndiff_w, total_pdiff_w;
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Area gate;
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double h_tr_region = h_gate - 2 * g_tp.HPOWERRAIL;
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double ratio_p_to_n = w_pmos / (w_pmos + w_nmos);
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if (ratio_p_to_n >= 1 || ratio_p_to_n <= 0)
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{
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return 0.0;
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}
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w_folded_pmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * ratio_p_to_n;
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w_folded_nmos = (h_tr_region - g_tp.MIN_GAP_BET_P_AND_N_DIFFS) * (1 - ratio_p_to_n);
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assert(w_folded_pmos > 0);
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num_folded_pmos = (int) (ceil(w_pmos / w_folded_pmos));
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num_folded_nmos = (int) (ceil(w_nmos / w_folded_nmos));
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switch (gate_type)
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{
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case INV:
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total_ndiff_w = compute_diffusion_width(1, num_folded_nmos);
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total_pdiff_w = compute_diffusion_width(1, num_folded_pmos);
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break;
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case NOR:
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total_ndiff_w = compute_diffusion_width(1, num_inputs * num_folded_nmos);
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total_pdiff_w = compute_diffusion_width(num_inputs, num_folded_pmos);
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break;
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case NAND:
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total_ndiff_w = compute_diffusion_width(num_inputs, num_folded_nmos);
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total_pdiff_w = compute_diffusion_width(1, num_inputs * num_folded_pmos);
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break;
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default:
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cout << "Unknown gate type: " << gate_type << endl;
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exit(1);
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}
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gate.w = MAX(total_ndiff_w, total_pdiff_w);
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if (w_folded_nmos > w_nmos)
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{
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//means that the height of the gate can
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//be made smaller than the input height specified, so calculate the height of the gate.
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gate.h = w_nmos + w_pmos + g_tp.MIN_GAP_BET_P_AND_N_DIFFS + 2 * g_tp.HPOWERRAIL;
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}
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else
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{
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gate.h = h_gate;
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}
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return gate.get_area();
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}
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double Component::compute_tr_width_after_folding(
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double input_width,
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double threshold_folding_width)
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{//This is actually the width of the cell not the width of a device.
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//The width of a cell and the width of a device is orthogonal.
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if (input_width <= 0)
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{
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return 0;
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}
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int num_folded_tr = (int) (ceil(input_width / threshold_folding_width));
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double spacing_poly_to_poly = g_tp.w_poly_contact + 2 * g_tp.spacing_poly_to_contact;
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double width_poly = g_ip->F_sz_um;
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double total_diff_width = num_folded_tr * width_poly + (num_folded_tr + 1) * spacing_poly_to_poly;
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return total_diff_width;
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}
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double Component::height_sense_amplifier(double pitch_sense_amp)
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{
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// compute the height occupied by all PMOS transistors
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double h_pmos_tr = compute_tr_width_after_folding(g_tp.w_sense_p, pitch_sense_amp) * 2 +
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compute_tr_width_after_folding(g_tp.w_iso, pitch_sense_amp) +
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2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
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// compute the height occupied by all NMOS transistors
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double h_nmos_tr = compute_tr_width_after_folding(g_tp.w_sense_n, pitch_sense_amp) * 2 +
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compute_tr_width_after_folding(g_tp.w_sense_en, pitch_sense_amp) +
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2 * g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS;
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// compute total height by considering gap between the p and n diffusion areas
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return h_pmos_tr + h_nmos_tr + g_tp.MIN_GAP_BET_P_AND_N_DIFFS;
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}
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int Component::logical_effort(
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int num_gates_min,
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double g,
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double F,
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double * w_n,
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double * w_p,
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double C_load,
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double p_to_n_sz_ratio,
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bool is_dram_,
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bool is_wl_tr_,
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double max_w_nmos)
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{
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int num_gates = (int) (log(F) / log(fopt));
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// check if num_gates is odd. if so, add 1 to make it even
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num_gates+= (num_gates % 2) ? 1 : 0;
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num_gates = MAX(num_gates, num_gates_min);
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// recalculate the effective fanout of each stage
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double f = pow(F, 1.0 / num_gates);
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int i = num_gates - 1;
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double C_in = C_load / f;
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w_n[i] = (1.0 / (1.0 + p_to_n_sz_ratio)) * C_in / gate_C(1, 0, is_dram_, false, is_wl_tr_);
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w_n[i] = MAX(w_n[i], g_tp.min_w_nmos_);
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w_p[i] = p_to_n_sz_ratio * w_n[i];
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if (w_n[i] > max_w_nmos) // && !g_ip->is_3d_mem)
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{
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double C_ld = gate_C((1 + p_to_n_sz_ratio) * max_w_nmos, 0, is_dram_, false, is_wl_tr_);
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F = g * C_ld / gate_C(w_n[0] + w_p[0], 0, is_dram_, false, is_wl_tr_);
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num_gates = (int) (log(F) / log(fopt)) + 1;
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num_gates+= (num_gates % 2) ? 1 : 0;
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num_gates = MAX(num_gates, num_gates_min);
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f = pow(F, 1.0 / (num_gates - 1));
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i = num_gates - 1;
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w_n[i] = max_w_nmos;
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w_p[i] = p_to_n_sz_ratio * w_n[i];
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}
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for (i = num_gates - 2; i >= 1; i--)
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{
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w_n[i] = MAX(w_n[i+1] / f, g_tp.min_w_nmos_);
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w_p[i] = p_to_n_sz_ratio * w_n[i];
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}
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assert(num_gates <= MAX_NUMBER_GATES_STAGE);
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return num_gates;
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}
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