904 lines
27 KiB
C++
904 lines
27 KiB
C++
/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __CACTI_INTERFACE_H__
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#define __CACTI_INTERFACE_H__
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#include <map>
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#include <string>
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#include <vector>
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#include <list>
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#include <iostream>
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#include "const.h"
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using namespace std;
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class min_values_t;
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class mem_array;
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class uca_org_t;
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class powerComponents
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{
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public:
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double dynamic;
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double leakage;
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double gate_leakage;
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double short_circuit;
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double longer_channel_leakage;
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powerComponents() : dynamic(0), leakage(0), gate_leakage(0), short_circuit(0), longer_channel_leakage(0) { }
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powerComponents(const powerComponents & obj) { *this = obj; }
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powerComponents & operator=(const powerComponents & rhs)
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{
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dynamic = rhs.dynamic;
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leakage = rhs.leakage;
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gate_leakage = rhs.gate_leakage;
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short_circuit = rhs.short_circuit;
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longer_channel_leakage = rhs.longer_channel_leakage;
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return *this;
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}
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void reset() { dynamic = 0; leakage = 0; gate_leakage = 0; short_circuit = 0;longer_channel_leakage = 0;}
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friend powerComponents operator+(const powerComponents & x, const powerComponents & y);
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friend powerComponents operator*(const powerComponents & x, double const * const y);
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};
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class powerDef
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{
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public:
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powerComponents readOp;
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powerComponents writeOp;
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powerComponents searchOp;//: for CAM and FA
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powerDef() : readOp(), writeOp(), searchOp() { }
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void reset() { readOp.reset(); writeOp.reset(); searchOp.reset();}
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friend powerDef operator+(const powerDef & x, const powerDef & y);
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friend powerDef operator*(const powerDef & x, double const * const y);
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};
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enum Wire_type
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{
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Global /* gloabl wires with repeaters */,
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Global_5 /* 5% delay penalty */,
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Global_10 /* 10% delay penalty */,
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Global_20 /* 20% delay penalty */,
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Global_30 /* 30% delay penalty */,
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Low_swing /* differential low power wires with high area overhead */,
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Semi_global /* mid-level wires with repeaters*/,
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Full_swing /* models all global wires with different latencies (Global_x )*/,
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Transmission /* tranmission lines with high area overhead */,
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Optical /* optical wires */,
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Invalid_wtype
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};
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enum TSV_type
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{
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Fine, /*ITRS high density*/
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Coarse /*Industry reported in 2010*/
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};
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// ali
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enum Mem_IO_type
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{
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DDR3,
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DDR4,
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LPDDR2,
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WideIO,
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Low_Swing_Diff,
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Serial
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};
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enum Mem_DIMM
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{
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UDIMM,
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RDIMM,
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LRDIMM
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};
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enum Mem_state
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{
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READ,
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WRITE,
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IDLE,
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SLEEP
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};
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enum Mem_ECC
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{
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NO_ECC,
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SECDED, // single error correction, double error detection
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CHIP_KILL
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};
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enum DIMM_Model
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{
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JUST_UDIMM,JUST_RDIMM,JUST_LRDIMM,ALL
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};
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enum MemCad_metrics
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{
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Bandwidth, Energy, Cost
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};
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/**
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enum BoB_LINK
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{
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PARALLEL, // e.g. Intel SMB c104
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SERIAL // e.g. Intel SMB 7510, IBM AMB
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};
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**/
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// end ali
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class InputParameter
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{
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public:
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InputParameter();
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void parse_cfg(const string & infile);
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bool error_checking(); // return false if the input parameters are problematic
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void display_ip();
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unsigned int cache_sz; // in bytes
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unsigned int line_sz;
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unsigned int assoc;
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unsigned int nbanks;
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unsigned int out_w;// == nr_bits_out
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bool specific_tag;
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unsigned int tag_w;
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unsigned int access_mode;
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unsigned int obj_func_dyn_energy;
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unsigned int obj_func_dyn_power;
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unsigned int obj_func_leak_power;
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unsigned int obj_func_cycle_t;
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double F_sz_nm; // feature size in nm
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double F_sz_um; // feature size in um
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unsigned int num_rw_ports;
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unsigned int num_rd_ports;
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unsigned int num_wr_ports;
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unsigned int num_se_rd_ports; // number of single ended read ports
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unsigned int num_search_ports; // : number of search ports for CAM
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bool is_main_mem;
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bool is_3d_mem;
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bool print_detail_debug;
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bool is_cache;
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bool pure_ram;
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bool pure_cam;
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bool rpters_in_htree; // if there are repeaters in htree segment
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unsigned int ver_htree_wires_over_array;
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unsigned int broadcast_addr_din_over_ver_htrees;
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unsigned int temp;
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unsigned int ram_cell_tech_type;
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unsigned int peri_global_tech_type;
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unsigned int data_arr_ram_cell_tech_type;
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unsigned int data_arr_peri_global_tech_type;
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unsigned int tag_arr_ram_cell_tech_type;
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unsigned int tag_arr_peri_global_tech_type;
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unsigned int burst_len;
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unsigned int int_prefetch_w;
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unsigned int page_sz_bits;
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unsigned int num_die_3d;
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unsigned int burst_depth;
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unsigned int io_width;
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unsigned int sys_freq_MHz;
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unsigned int tsv_is_subarray_type;
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unsigned int tsv_os_bank_type;
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unsigned int TSV_proj_type;
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int partition_gran;
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unsigned int num_tier_row_sprd;
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unsigned int num_tier_col_sprd;
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bool fine_gran_bank_lvl;
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unsigned int ic_proj_type; // interconnect_projection_type
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unsigned int wire_is_mat_type; // wire_inside_mat_type
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unsigned int wire_os_mat_type; // wire_outside_mat_type
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enum Wire_type wt;
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int force_wiretype;
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bool print_input_args;
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unsigned int nuca_cache_sz; // TODO
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int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm;
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bool force_cache_config;
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int cache_level;
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int cores;
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int nuca_bank_count;
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int force_nuca_bank;
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int delay_wt, dynamic_power_wt, leakage_power_wt,
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cycle_time_wt, area_wt;
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int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca,
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cycle_time_wt_nuca, area_wt_nuca;
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int delay_dev, dynamic_power_dev, leakage_power_dev,
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cycle_time_dev, area_dev;
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int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca,
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cycle_time_dev_nuca, area_dev_nuca;
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int ed; //ED or ED2 optimization
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int nuca;
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bool fast_access;
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unsigned int block_sz; // bytes
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unsigned int tag_assoc;
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unsigned int data_assoc;
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bool is_seq_acc;
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bool fully_assoc;
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unsigned int nsets; // == number_of_sets
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int print_detail;
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bool add_ecc_b_;
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//parameters for design constraint
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double throughput;
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double latency;
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bool pipelinable;
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int pipeline_stages;
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int per_stage_vector;
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bool with_clock_grid;
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bool array_power_gated;
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bool bitline_floating;
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bool wl_power_gated;
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bool cl_power_gated;
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bool interconect_power_gated;
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bool power_gating;
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double perfloss;
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bool cl_vertical;
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// Parameters related to off-chip I/O
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double addr_timing, duty_cycle, mem_density, bus_bw, activity_dq, activity_ca, bus_freq;
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int mem_data_width, num_mem_dq, num_clk, num_ca, num_dqs, num_dq;
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double rtt_value, ron_value, tflight_value; //FIXME
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Mem_state iostate;
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///char iostate, dram_ecc, io_type;
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Mem_ECC dram_ecc;
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Mem_IO_type io_type;
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Mem_DIMM dram_dimm;
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int num_bobs; // BoB is buffer-on-board such as Intel SMB c102
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int capacity; // in GB
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int num_channels_per_bob; // 1 means no bob
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MemCad_metrics first_metric;
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MemCad_metrics second_metric;
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MemCad_metrics third_metric;
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DIMM_Model dimm_model;
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bool low_power_permitted; // Not yet implemented. It determines acceptable VDDs.
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double load; // between 0 to 1
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double row_buffer_hit_rate;
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double rd_2_wr_ratio;
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bool same_bw_in_bob; // true if all the channels in the bob have the same bandwidth.
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bool mirror_in_bob;// true if all the channels in the bob have the same configs
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bool total_power; // false means just considering I/O Power
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bool verbose;
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};
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typedef struct{
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int Ndwl;
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int Ndbl;
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double Nspd;
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int deg_bl_muxing;
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int Ndsam_lev_1;
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int Ndsam_lev_2;
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int number_activated_mats_horizontal_direction;
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int number_subbanks;
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int page_size_in_bits;
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double delay_route_to_bank;
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double delay_crossbar;
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double delay_addr_din_horizontal_htree;
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double delay_addr_din_vertical_htree;
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double delay_row_predecode_driver_and_block;
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double delay_row_decoder;
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double delay_bitlines;
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double delay_sense_amp;
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double delay_subarray_output_driver;
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double delay_bit_mux_predecode_driver_and_block;
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double delay_bit_mux_decoder;
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double delay_senseamp_mux_lev_1_predecode_driver_and_block;
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double delay_senseamp_mux_lev_1_decoder;
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double delay_senseamp_mux_lev_2_predecode_driver_and_block;
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double delay_senseamp_mux_lev_2_decoder;
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double delay_input_htree;
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double delay_output_htree;
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double delay_dout_vertical_htree;
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double delay_dout_horizontal_htree;
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double delay_comparator;
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double access_time;
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double cycle_time;
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double multisubbank_interleave_cycle_time;
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double delay_request_network;
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double delay_inside_mat;
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double delay_reply_network;
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double trcd;
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double cas_latency;
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double precharge_delay;
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powerDef power_routing_to_bank;
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powerDef power_addr_input_htree;
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powerDef power_data_input_htree;
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powerDef power_data_output_htree;
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powerDef power_addr_horizontal_htree;
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powerDef power_datain_horizontal_htree;
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powerDef power_dataout_horizontal_htree;
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powerDef power_addr_vertical_htree;
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powerDef power_datain_vertical_htree;
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powerDef power_row_predecoder_drivers;
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powerDef power_row_predecoder_blocks;
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powerDef power_row_decoders;
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powerDef power_bit_mux_predecoder_drivers;
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powerDef power_bit_mux_predecoder_blocks;
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powerDef power_bit_mux_decoders;
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powerDef power_senseamp_mux_lev_1_predecoder_drivers;
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powerDef power_senseamp_mux_lev_1_predecoder_blocks;
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powerDef power_senseamp_mux_lev_1_decoders;
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powerDef power_senseamp_mux_lev_2_predecoder_drivers;
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powerDef power_senseamp_mux_lev_2_predecoder_blocks;
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powerDef power_senseamp_mux_lev_2_decoders;
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powerDef power_bitlines;
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powerDef power_sense_amps;
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powerDef power_prechg_eq_drivers;
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powerDef power_output_drivers_at_subarray;
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powerDef power_dataout_vertical_htree;
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powerDef power_comparators;
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powerDef power_crossbar;
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powerDef total_power;
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double area;
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double all_banks_height;
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double all_banks_width;
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double bank_height;
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double bank_width;
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double subarray_memory_cell_area_height;
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double subarray_memory_cell_area_width;
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double mat_height;
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double mat_width;
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double routing_area_height_within_bank;
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double routing_area_width_within_bank;
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double area_efficiency;
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// double perc_power_dyn_routing_to_bank;
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// double perc_power_dyn_addr_horizontal_htree;
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// double perc_power_dyn_datain_horizontal_htree;
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// double perc_power_dyn_dataout_horizontal_htree;
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// double perc_power_dyn_addr_vertical_htree;
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// double perc_power_dyn_datain_vertical_htree;
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// double perc_power_dyn_row_predecoder_drivers;
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// double perc_power_dyn_row_predecoder_blocks;
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// double perc_power_dyn_row_decoders;
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// double perc_power_dyn_bit_mux_predecoder_drivers;
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// double perc_power_dyn_bit_mux_predecoder_blocks;
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// double perc_power_dyn_bit_mux_decoders;
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// double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers;
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// double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks;
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// double perc_power_dyn_senseamp_mux_lev_1_decoders;
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// double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers;
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// double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks;
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// double perc_power_dyn_senseamp_mux_lev_2_decoders;
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// double perc_power_dyn_bitlines;
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// double perc_power_dyn_sense_amps;
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// double perc_power_dyn_prechg_eq_drivers;
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// double perc_power_dyn_subarray_output_drivers;
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// double perc_power_dyn_dataout_vertical_htree;
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// double perc_power_dyn_comparators;
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// double perc_power_dyn_crossbar;
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// double perc_power_dyn_spent_outside_mats;
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// double perc_power_leak_routing_to_bank;
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// double perc_power_leak_addr_horizontal_htree;
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// double perc_power_leak_datain_horizontal_htree;
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// double perc_power_leak_dataout_horizontal_htree;
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// double perc_power_leak_addr_vertical_htree;
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// double perc_power_leak_datain_vertical_htree;
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// double perc_power_leak_row_predecoder_drivers;
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// double perc_power_leak_row_predecoder_blocks;
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// double perc_power_leak_row_decoders;
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// double perc_power_leak_bit_mux_predecoder_drivers;
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// double perc_power_leak_bit_mux_predecoder_blocks;
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// double perc_power_leak_bit_mux_decoders;
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// double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers;
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// double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks;
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// double perc_power_leak_senseamp_mux_lev_1_decoders;
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// double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers;
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// double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks;
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// double perc_power_leak_senseamp_mux_lev_2_decoders;
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// double perc_power_leak_bitlines;
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// double perc_power_leak_sense_amps;
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// double perc_power_leak_prechg_eq_drivers;
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// double perc_power_leak_subarray_output_drivers;
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// double perc_power_leak_dataout_vertical_htree;
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// double perc_power_leak_comparators;
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// double perc_power_leak_crossbar;
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// double perc_leak_mats;
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// double perc_active_mats;
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double refresh_power;
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double dram_refresh_period;
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double dram_array_availability;
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double dyn_read_energy_from_closed_page;
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double dyn_read_energy_from_open_page;
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double leak_power_subbank_closed_page;
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double leak_power_subbank_open_page;
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double leak_power_request_and_reply_networks;
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double activate_energy;
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double read_energy;
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double write_energy;
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double precharge_energy;
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} results_mem_array;
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class uca_org_t
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{
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public:
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mem_array * tag_array2;
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mem_array * data_array2;
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double access_time;
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double cycle_time;
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double area;
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double area_efficiency;
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powerDef power;
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double leak_power_with_sleep_transistors_in_mats;
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double cache_ht;
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double cache_len;
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char file_n[100];
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double vdd_periph_global;
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bool valid;
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results_mem_array tag_array;
|
|
results_mem_array data_array;
|
|
|
|
uca_org_t();
|
|
void find_delay();
|
|
void find_energy();
|
|
void find_area();
|
|
void find_cyc();
|
|
void adjust_area();//for McPAT only to adjust routing overhead
|
|
void cleanup();
|
|
~uca_org_t(){};
|
|
};
|
|
|
|
|
|
class IO_org_t
|
|
{
|
|
public:
|
|
double io_area;
|
|
double io_timing_margin;
|
|
double io_voltage_margin;
|
|
double io_dynamic_power;
|
|
double io_phy_power;
|
|
double io_wakeup_time;
|
|
double io_termination_power;
|
|
IO_org_t():io_area(0),io_timing_margin(0),io_voltage_margin(0)
|
|
,io_dynamic_power(0),io_phy_power(0),io_wakeup_time(0),io_termination_power(0)
|
|
{}
|
|
};
|
|
|
|
|
|
void reconfigure(InputParameter *local_interface, uca_org_t *fin_res);
|
|
|
|
uca_org_t cacti_interface(const string & infile_name);
|
|
//McPAT's plain interface, please keep !!!
|
|
uca_org_t cacti_interface(InputParameter * const local_interface);
|
|
//McPAT's plain interface, please keep !!!
|
|
uca_org_t init_interface(InputParameter * const local_interface);
|
|
//McPAT's plain interface, please keep !!!
|
|
uca_org_t cacti_interface(
|
|
int cache_size,
|
|
int line_size,
|
|
int associativity,
|
|
int rw_ports,
|
|
int excl_read_ports,
|
|
int excl_write_ports,
|
|
int single_ended_read_ports,
|
|
int search_ports,
|
|
int banks,
|
|
double tech_node,
|
|
int output_width,
|
|
int specific_tag,
|
|
int tag_width,
|
|
int access_mode,
|
|
int cache,
|
|
int main_mem,
|
|
int obj_func_delay,
|
|
int obj_func_dynamic_power,
|
|
int obj_func_leakage_power,
|
|
int obj_func_cycle_time,
|
|
int obj_func_area,
|
|
int dev_func_delay,
|
|
int dev_func_dynamic_power,
|
|
int dev_func_leakage_power,
|
|
int dev_func_area,
|
|
int dev_func_cycle_time,
|
|
int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
|
|
int temp,
|
|
int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
|
|
int data_arr_ram_cell_tech_flavor_in,
|
|
int data_arr_peri_global_tech_flavor_in,
|
|
int tag_arr_ram_cell_tech_flavor_in,
|
|
int tag_arr_peri_global_tech_flavor_in,
|
|
int interconnect_projection_type_in,
|
|
int wire_inside_mat_type_in,
|
|
int wire_outside_mat_type_in,
|
|
int REPEATERS_IN_HTREE_SEGMENTS_in,
|
|
int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
|
|
int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
|
|
int PAGE_SIZE_BITS_in,
|
|
int BURST_LENGTH_in,
|
|
int INTERNAL_PREFETCH_WIDTH_in,
|
|
int force_wiretype,
|
|
int wiretype,
|
|
int force_config,
|
|
int ndwl,
|
|
int ndbl,
|
|
int nspd,
|
|
int ndcm,
|
|
int ndsam1,
|
|
int ndsam2,
|
|
int ecc);
|
|
// int cache_size,
|
|
// int line_size,
|
|
// int associativity,
|
|
// int rw_ports,
|
|
// int excl_read_ports,
|
|
// int excl_write_ports,
|
|
// int single_ended_read_ports,
|
|
// int banks,
|
|
// double tech_node,
|
|
// int output_width,
|
|
// int specific_tag,
|
|
// int tag_width,
|
|
// int access_mode,
|
|
// int cache,
|
|
// int main_mem,
|
|
// int obj_func_delay,
|
|
// int obj_func_dynamic_power,
|
|
// int obj_func_leakage_power,
|
|
// int obj_func_area,
|
|
// int obj_func_cycle_time,
|
|
// int dev_func_delay,
|
|
// int dev_func_dynamic_power,
|
|
// int dev_func_leakage_power,
|
|
// int dev_func_area,
|
|
// int dev_func_cycle_time,
|
|
// int temp,
|
|
// int data_arr_ram_cell_tech_flavor_in,
|
|
// int data_arr_peri_global_tech_flavor_in,
|
|
// int tag_arr_ram_cell_tech_flavor_in,
|
|
// int tag_arr_peri_global_tech_flavor_in,
|
|
// int interconnect_projection_type_in,
|
|
// int wire_inside_mat_type_in,
|
|
// int wire_outside_mat_type_in,
|
|
// int REPEATERS_IN_HTREE_SEGMENTS_in,
|
|
// int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
|
|
// int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
|
|
//// double MAXAREACONSTRAINT_PERC_in,
|
|
//// double MAXACCTIMECONSTRAINT_PERC_in,
|
|
//// double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in,
|
|
// int PAGE_SIZE_BITS_in,
|
|
// int BURST_LENGTH_in,
|
|
// int INTERNAL_PREFETCH_WIDTH_in);
|
|
|
|
//Naveen's interface
|
|
uca_org_t cacti_interface(
|
|
int cache_size,
|
|
int line_size,
|
|
int associativity,
|
|
int rw_ports,
|
|
int excl_read_ports,
|
|
int excl_write_ports,
|
|
int single_ended_read_ports,
|
|
int banks,
|
|
double tech_node,
|
|
int page_sz,
|
|
int burst_length,
|
|
int pre_width,
|
|
int output_width,
|
|
int specific_tag,
|
|
int tag_width,
|
|
int access_mode, //0 normal, 1 seq, 2 fast
|
|
int cache, //scratch ram or cache
|
|
int main_mem,
|
|
int obj_func_delay,
|
|
int obj_func_dynamic_power,
|
|
int obj_func_leakage_power,
|
|
int obj_func_area,
|
|
int obj_func_cycle_time,
|
|
int dev_func_delay,
|
|
int dev_func_dynamic_power,
|
|
int dev_func_leakage_power,
|
|
int dev_func_area,
|
|
int dev_func_cycle_time,
|
|
int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
|
|
int temp,
|
|
int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
|
|
int data_arr_ram_cell_tech_flavor_in,
|
|
int data_arr_peri_global_tech_flavor_in,
|
|
int tag_arr_ram_cell_tech_flavor_in,
|
|
int tag_arr_peri_global_tech_flavor_in,
|
|
int interconnect_projection_type_in, // 0 - aggressive, 1 - normal
|
|
int wire_inside_mat_type_in,
|
|
int wire_outside_mat_type_in,
|
|
int is_nuca, // 0 - UCA, 1 - NUCA
|
|
int core_count,
|
|
int cache_level, // 0 - L2, 1 - L3
|
|
int nuca_bank_count,
|
|
int nuca_obj_func_delay,
|
|
int nuca_obj_func_dynamic_power,
|
|
int nuca_obj_func_leakage_power,
|
|
int nuca_obj_func_area,
|
|
int nuca_obj_func_cycle_time,
|
|
int nuca_dev_func_delay,
|
|
int nuca_dev_func_dynamic_power,
|
|
int nuca_dev_func_leakage_power,
|
|
int nuca_dev_func_area,
|
|
int nuca_dev_func_cycle_time,
|
|
int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported
|
|
int p_input);
|
|
|
|
|
|
//CACTI3DD interface
|
|
uca_org_t cacti_interface(
|
|
int cache_size,
|
|
int line_size,
|
|
int associativity,
|
|
int rw_ports,
|
|
int excl_read_ports,// para5
|
|
int excl_write_ports,
|
|
int single_ended_read_ports,
|
|
int search_ports,
|
|
int banks,
|
|
double tech_node,//para10
|
|
int output_width,
|
|
int specific_tag,
|
|
int tag_width,
|
|
int access_mode,
|
|
int cache, //para15
|
|
int main_mem,
|
|
int obj_func_delay,
|
|
int obj_func_dynamic_power,
|
|
int obj_func_leakage_power,
|
|
int obj_func_cycle_time, //para20
|
|
int obj_func_area,
|
|
int dev_func_delay,
|
|
int dev_func_dynamic_power,
|
|
int dev_func_leakage_power,
|
|
int dev_func_area, //para25
|
|
int dev_func_cycle_time,
|
|
int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
|
|
int temp,
|
|
int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
|
|
int data_arr_ram_cell_tech_flavor_in,//para30
|
|
int data_arr_peri_global_tech_flavor_in,
|
|
int tag_arr_ram_cell_tech_flavor_in,
|
|
int tag_arr_peri_global_tech_flavor_in,
|
|
int interconnect_projection_type_in,
|
|
int wire_inside_mat_type_in,//para35
|
|
int wire_outside_mat_type_in,
|
|
int REPEATERS_IN_HTREE_SEGMENTS_in,
|
|
int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
|
|
int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
|
|
int PAGE_SIZE_BITS_in,//para40
|
|
int BURST_LENGTH_in,
|
|
int INTERNAL_PREFETCH_WIDTH_in,
|
|
int force_wiretype,
|
|
int wiretype,
|
|
int force_config,//para45
|
|
int ndwl,
|
|
int ndbl,
|
|
int nspd,
|
|
int ndcm,
|
|
int ndsam1,//para50
|
|
int ndsam2,
|
|
int ecc,
|
|
int is_3d_dram,
|
|
int burst_depth,
|
|
int IO_width,
|
|
int sys_freq,
|
|
int debug_detail,
|
|
int num_dies,
|
|
int tsv_gran_is_subarray,
|
|
int tsv_gran_os_bank,
|
|
int num_tier_row_sprd,
|
|
int num_tier_col_sprd,
|
|
int partition_level);
|
|
|
|
class mem_array
|
|
{
|
|
public:
|
|
int Ndcm;
|
|
int Ndwl;
|
|
int Ndbl;
|
|
double Nspd;
|
|
int deg_bl_muxing;
|
|
int Ndsam_lev_1;
|
|
int Ndsam_lev_2;
|
|
double access_time;
|
|
double cycle_time;
|
|
double multisubbank_interleave_cycle_time;
|
|
double area_ram_cells;
|
|
double area;
|
|
powerDef power;
|
|
double delay_senseamp_mux_decoder;
|
|
double delay_before_subarray_output_driver;
|
|
double delay_from_subarray_output_driver_to_output;
|
|
double height;
|
|
double width;
|
|
|
|
double mat_height;
|
|
double mat_length;
|
|
double subarray_length;
|
|
double subarray_height;
|
|
|
|
double delay_route_to_bank,
|
|
delay_input_htree,
|
|
delay_row_predecode_driver_and_block,
|
|
delay_row_decoder,
|
|
delay_bitlines,
|
|
delay_sense_amp,
|
|
delay_subarray_output_driver,
|
|
delay_dout_htree,
|
|
delay_comparator,
|
|
delay_matchlines;
|
|
//CACTI3DD 3d stats
|
|
double delay_row_activate_net,
|
|
delay_local_wordline,
|
|
|
|
delay_column_access_net,
|
|
delay_column_predecoder,
|
|
delay_column_decoder,
|
|
delay_column_selectline,
|
|
delay_datapath_net,
|
|
delay_global_data,
|
|
delay_local_data_and_drv,
|
|
delay_data_buffer;
|
|
|
|
double energy_row_activate_net,
|
|
energy_row_predecode_driver_and_block,
|
|
energy_row_decoder,
|
|
energy_local_wordline,
|
|
energy_bitlines,
|
|
energy_sense_amp,
|
|
energy_column_access_net,
|
|
energy_column_predecoder,
|
|
energy_column_decoder,
|
|
energy_column_selectline,
|
|
energy_datapath_net,
|
|
energy_global_data,
|
|
energy_local_data_and_drv,
|
|
energy_data_buffer,
|
|
energy_subarray_output_driver;
|
|
|
|
double all_banks_height,
|
|
all_banks_width,
|
|
area_efficiency;
|
|
|
|
powerDef power_routing_to_bank;
|
|
powerDef power_addr_input_htree;
|
|
powerDef power_data_input_htree;
|
|
powerDef power_data_output_htree;
|
|
powerDef power_htree_in_search;
|
|
powerDef power_htree_out_search;
|
|
powerDef power_row_predecoder_drivers;
|
|
powerDef power_row_predecoder_blocks;
|
|
powerDef power_row_decoders;
|
|
powerDef power_bit_mux_predecoder_drivers;
|
|
powerDef power_bit_mux_predecoder_blocks;
|
|
powerDef power_bit_mux_decoders;
|
|
powerDef power_senseamp_mux_lev_1_predecoder_drivers;
|
|
powerDef power_senseamp_mux_lev_1_predecoder_blocks;
|
|
powerDef power_senseamp_mux_lev_1_decoders;
|
|
powerDef power_senseamp_mux_lev_2_predecoder_drivers;
|
|
powerDef power_senseamp_mux_lev_2_predecoder_blocks;
|
|
powerDef power_senseamp_mux_lev_2_decoders;
|
|
powerDef power_bitlines;
|
|
powerDef power_sense_amps;
|
|
powerDef power_prechg_eq_drivers;
|
|
powerDef power_output_drivers_at_subarray;
|
|
powerDef power_dataout_vertical_htree;
|
|
powerDef power_comparators;
|
|
|
|
powerDef power_cam_bitline_precharge_eq_drv;
|
|
powerDef power_searchline;
|
|
powerDef power_searchline_precharge;
|
|
powerDef power_matchlines;
|
|
powerDef power_matchline_precharge;
|
|
powerDef power_matchline_to_wordline_drv;
|
|
|
|
min_values_t *arr_min;
|
|
enum Wire_type wt;
|
|
|
|
// dram stats
|
|
double activate_energy, read_energy, write_energy, precharge_energy,
|
|
refresh_power, leak_power_subbank_closed_page, leak_power_subbank_open_page,
|
|
leak_power_request_and_reply_networks;
|
|
|
|
double precharge_delay;
|
|
|
|
//Power-gating stats
|
|
double array_leakage;
|
|
double wl_leakage;
|
|
double cl_leakage;
|
|
|
|
double sram_sleep_tx_width, wl_sleep_tx_width, cl_sleep_tx_width;
|
|
double sram_sleep_tx_area, wl_sleep_tx_area, cl_sleep_tx_area;
|
|
double sram_sleep_wakeup_latency, wl_sleep_wakeup_latency, cl_sleep_wakeup_latency, bl_floating_wakeup_latency;
|
|
double sram_sleep_wakeup_energy, wl_sleep_wakeup_energy, cl_sleep_wakeup_energy, bl_floating_wakeup_energy;
|
|
|
|
int num_active_mats;
|
|
int num_submarray_mats;
|
|
|
|
static bool lt(const mem_array * m1, const mem_array * m2);
|
|
|
|
//CACTI3DD 3d dram stats
|
|
double t_RCD, t_RAS, t_RC, t_CAS, t_RP, t_RRD;
|
|
double activate_power, read_power, write_power, peak_read_power;
|
|
int num_row_subarray, num_col_subarray;
|
|
double delay_TSV_tot, area_TSV_tot, dyn_pow_TSV_tot, dyn_pow_TSV_per_access;
|
|
unsigned int num_TSV_tot;
|
|
double area_lwl_drv, area_row_predec_dec, area_col_predec_dec,
|
|
area_subarray, area_bus, area_address_bus, area_data_bus, area_data_drv, area_IOSA, area_sense_amp;
|
|
|
|
};
|
|
|
|
|
|
#endif
|
|
|