library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity machine is port ( clock : IN std_logic; START : IN std_logic; RESET : IN std_logic; INPUT : IN std_logic_vector(7 downto 0); OUTPUT : OUT std_logic_vector(7 downto 0); count : OUT std_logic_vector(7 downto 0) ) ; end machine; architecture behavior of machine is type etat is (attente, init, calcul, fin); type cal is ('0','1'); signal state : etat := attente; signal done : cal; BEGIN Racine : process(clock) variable X : integer; variable V : integer; variable Z : integer; variable n : integer := 5; variable cond : integer; variable i : integer; begin if(rising_edge(clock)) then if RESET = '1' then state <= attente; end if; case state is when attente => if START = '1' then state <= init; else state <= attente; end if; done <= '0'; when init => X := to_integer(unsigned(INPUT)); V := 256; Z := 0; i := 5; done <= '0'; state <= calcul; when calcul => Z := Z+V; cond := X-Z; if cond >= 0 then X := X-Z; Z := (Z+V)/2; else Z := (Z-V)/2; end if; V := V/4; i := i-1; count <= std_logic_vector(to_unsigned(i, count'length)); done <= '0'; if i = 0 then state <= fin; else state <= calcul; end if; when fin => done <= '1'; OUTPUT <= std_logic_vector(to_unsigned(Z, OUTPUT'length)); if START = '1' then state <= fin; else state <= attente; end if; when others => state <= attente; end case; end if; end process Racine; end behavior;