library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is
end testbench;

architecture test_decounter of testbench is
signal clk, sig_init, sig_eqz, sig_en : std_logic;

begin

sig_init <= '1', '0' after 20 ns;
sig_en <= '0', '1' after 90 ns;

DUT: entity work.decounter(proced)
		generic map(nb_bits => 4, nb_iter => 16)
		port map(encount => sig_en, clk => clk, init => sig_init, ceqz => sig_eqz);

Gene_clk: process
				begin
					clk <= '0';
					wait for 10 ns;
					for i in 1 to 30 loop
						clk <= '1';
						wait for 10 ns;
						clk <= '0';
						wait for 10 ns;
					end loop;
					wait;
end process;

end test_decounter;

architecture test_mux2_1 of testbench is
signal sig_sel : std_logic;
signal sig_A, sig_B, sig_S : std_logic_vector(15 downto 0);

begin

sig_sel <= '1', '0' after 50 ns;
sig_A <= std_logic_vector(to_unsigned(100,16));
sig_B <= std_logic_vector(to_unsigned(0,16));

DUT: entity work.mux2_1(proced)
		generic map(nb_bits => 16)
		port map(I0 => sig_A, I1 => sig_B, sel => sig_sel, S => sig_S);

end test_mux2_1;

architecture test_add_sub of testbench is
signal sig_op, sig_cout : std_logic;
signal sig_A, sig_B, sig_res : std_logic_vector(15 downto 0);

begin

sig_op <= '0', '1' after 100 ns, '0' after 200 ns;
sig_A <= std_logic_vector(to_unsigned(1,16)), std_logic_vector(to_unsigned(0,16)) after 50 ns;
sig_B <= std_logic_vector(to_unsigned(1,16));

DUT: entity work.add_sub(proced)
		generic map(nb_bits => 16)
		port map(A => sig_A, B => sig_B, op => sig_op, S => sig_res, cout => sig_cout);

end test_add_sub;


architecture test_mux3_1 of testbench is
signal sig_sel : std_logic_vector(1 downto 0);
signal sig_A, sig_B, sig_C, sig_S : std_logic_vector(15 downto 0);

begin

sig_sel <= "00", "01" after 50 ns, "10" after 100 ns, "11" after 150 ns, "00" after 200 ns;
sig_A <= std_logic_vector(to_unsigned(100,16));
sig_B <= std_logic_vector(to_unsigned(0,16));
sig_C <= std_logic_vector(to_unsigned(32,16));


DUT: entity work.mux3_1(proced)
		generic map(nb_bits => 16)
		port map(I0 => sig_A, I1 => sig_B, I2 => sig_C, sel => sig_sel, S => sig_S);

end test_mux3_1;