library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg is
generic(nb_bits : natural);
			
port(	Init : in STD_LOGIC; -- Initialization command
    init_value : in STD_LOGIC_VECTOR(nb_bits-1 downto 0); -- Init value with unsigned type to cover all possible values with large nb_bits
		ld : in STD_LOGIC; -- load command
		clk : in STD_LOGIC;
		E : in STD_LOGIC_VECTOR(nb_bits-1 downto 0);
		S : out STD_LOGIC_VECTOR(nb_bits-1 downto 0));
end reg;

architecture proced of reg is
signal Sint : unsigned(nb_bits-1 downto 0);
begin

Ps: process(clk, Init)
begin
	if (Init = '1') then
		Sint <= unsigned(init_value); 
	elsif (clk'event and (clk = '1') and (ld ='1')) then
		Sint <= unsigned(E);
	end if;
end process;

S <= std_logic_vector(Sint);

end proced;