35 lines
876 B
VHDL
35 lines
876 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity add_sub is
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generic(nb_bits : natural:=16);
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port( A,B : in STD_LOGIC_VECTOR(nb_bits-1 downto 0);
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Op : in STD_LOGIC; -- operation choice: '0' --> addition, '1' subtraction
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S : out STD_LOGIC_VECTOR(nb_bits-1 downto 0); -- result
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Cout : out STD_LOGIC); -- carry out
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end add_sub;
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architecture proced of add_sub is
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signal Aint, Bint : unsigned(nb_bits downto 0); -- we add one bit to make error free computations
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signal Sint : unsigned(nb_bits downto 0);
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begin
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Aint(nb_bits-1 downto 0) <= unsigned(A);
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Aint(nb_bits) <= '0';
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Bint(nb_bits-1 downto 0) <= unsigned(B);
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Bint(nb_bits) <= '0';
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process(Op, Aint, Bint)
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begin
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if (Op = '0') then
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Sint <= Aint + Bint;
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else
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Sint <= Aint - Bint;
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end if;
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end process;
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S <= std_logic_vector(Sint(nb_bits-1 downto 0));
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Cout <= Sint(nb_bits);
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end proced;
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