274 lines
9.3 KiB
C
274 lines
9.3 KiB
C
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __CONST_H__
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#define __CONST_H__
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include <math.h>
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/* The following are things you might want to change
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* when compiling
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*/
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/*
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* Address bits in a word, and number of output bits from the cache
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*/
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/*
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was: #define ADDRESS_BITS 32
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now: 42 bits as in the Power4
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This is 36 bits in Pentium 4
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and 40 bits in Opteron.
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*/
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const int ADDRESS_BITS = 42;
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/*dt: In addition to the tag bits, the tags also include 1 valid bit, 1 dirty bit, 2 bits for a 4-state
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cache coherency protocoll (MESI), 1 bit for MRU (change this to log(ways) for full LRU).
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So in total we have 1 + 1 + 2 + 1 = 5 */
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const int EXTRA_TAG_BITS = 5;
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/* limits on the various N parameters */
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const unsigned int MAXDATAN = 512; // maximum for Ndwl and Ndbl
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const unsigned int MAXSUBARRAYS = 1048576; // maximum subarrays for data and tag arrays
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const unsigned int MAXDATASPD = 256; // maximum for Nspd
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const unsigned int MAX_COL_MUX = 256;
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#define ROUTER_TYPES 3
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#define WIRE_TYPES 6
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const double Cpolywire = 0;
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/* Threshold voltages (as a proportion of Vdd)
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If you don't know them, set all values to 0.5 */
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#define VTHFA1 0.452
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#define VTHFA2 0.304
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#define VTHFA3 0.420
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#define VTHFA4 0.413
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#define VTHFA5 0.405
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#define VTHFA6 0.452
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#define VSINV 0.452
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#define VTHCOMPINV 0.437
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#define VTHMUXNAND 0.548 // TODO : this constant must be revisited
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#define VTHEVALINV 0.452
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#define VTHSENSEEXTDRV 0.438
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//WmuxdrvNANDn and WmuxdrvNANDp are no longer being used but it's part of the old
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//delay_comparator function which we are using exactly as it used to be, so just setting these to 0
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const double WmuxdrvNANDn = 0;
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const double WmuxdrvNANDp = 0;
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/*===================================================================*/
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/*
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* The following are things you probably wouldn't want to change.
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*/
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#define BIGNUM 1e30
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#define INF 9999999
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#define MAX(a,b) (((a)>(b))?(a):(b))
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#define MIN(a,b) (((a)<(b))?(a):(b))
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/* Used to communicate with the horowitz model */
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#define RISE 1
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#define FALL 0
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#define NCH 1
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#define PCH 0
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#define EPSILON 0.5 //v4.1: This constant is being used in order to fix floating point -> integer
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//conversion problems that were occuring within CACTI. Typical problem that was occuring was
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//that with different compilers a floating point number like 3.0 would get represented as either
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//2.9999....or 3.00000001 and then the integer part of the floating point number (3.0) would
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//be computed differently depending on the compiler. What we are doing now is to replace
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//int (x) with (int) (x+EPSILON) where EPSILON is 0.5. This would fix such problems. Note that
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//this works only when x is an integer >= 0.
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/*
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* thinks this is more a solution to solve the simple truncate problem
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* (http://www.cs.tut.fi/~jkorpela/round.html) rather than the problem mentioned above.
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* Unfortunately, this solution causes nasty bugs (different results when using O0 and O3).
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* Moreover, round is not correct in CACTI since when an extra fraction of bit/line is needed,
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* we need to provide a complete bit/line even the fraction is just 0.01.
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* So, in later version than 6.5 we use (int)ceil() to get double to int conversion.
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*/
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#define EPSILON2 0.1
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#define EPSILON3 0.6
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#define MINSUBARRAYROWS 16 //For simplicity in modeling, for the row decoding structure, we assume
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//that each row predecode block is composed of at least one 2-4 decoder. When the outputs from the
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//row predecode blocks are combined this means that there are at least 4*4=16 row decode outputs
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#define MAXSUBARRAYROWS 262144 //Each row predecode block produces a max of 2^9 outputs. So
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//the maximum number of row decode outputs will be 2^9*2^9
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#define MINSUBARRAYCOLS 2
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#define MAXSUBARRAYCOLS 262144
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#define INV 0
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#define NOR 1
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#define NAND 2
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#define NUMBER_TECH_FLAVORS 4
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#define NUMBER_INTERCONNECT_PROJECTION_TYPES 2 //aggressive and conservative
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//0 = Aggressive projections, 1 = Conservative projections
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#define NUMBER_WIRE_TYPES 4 //local, semi-global and global
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//1 = 'Semi-global' wire type, 2 = 'Global' wire type
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#define NUMBER_TSV_TYPES 3
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//0 = ITRS projected fine TSV type, 1 = Industrial reported large TSV type, 2 = TBD
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const int dram_cell_tech_flavor = 3;
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#define VBITSENSEMIN 0.08 //minimum bitline sense voltage is fixed to be 80 mV.
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#define fopt 4.0
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#define INPUT_WIRE_TO_INPUT_GATE_CAP_RATIO 0
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#define BUFFER_SEPARATION_LENGTH_MULTIPLIER 1
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#define NUMBER_MATS_PER_REDUNDANT_MAT 8
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#define NUMBER_STACKED_DIE_LAYERS 1
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// this variable can be set to carry out solution optimization for
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// a maximum area allocation.
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#define STACKED_DIE_LAYER_ALLOTED_AREA_mm2 0 //6.24 //6.21//71.5
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// this variable can also be employed when solution optimization
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// with maximum area allocation is carried out.
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#define MAX_PERCENT_AWAY_FROM_ALLOTED_AREA 50
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// this variable can also be employed when solution optimization
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// with maximum area allocation is carried out.
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#define MIN_AREA_EFFICIENCY 20
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// this variable can be employed when solution with a desired
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// aspect ratio is required.
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#define STACKED_DIE_LAYER_ASPECT_RATIO 1
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// this variable can be employed when solution with a desired
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// aspect ratio is required.
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#define MAX_PERCENT_AWAY_FROM_ASPECT_RATIO 101
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// this variable can be employed to carry out solution optimization
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// for a certain target random cycle time.
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#define TARGET_CYCLE_TIME_ns 1000000000
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#define NUMBER_PIPELINE_STAGES 4
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// this can be used to model the length of interconnect
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// between a bank and a crossbar
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#define LENGTH_INTERCONNECT_FROM_BANK_TO_CROSSBAR 0 //3791 // 2880//micron
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#define IS_CROSSBAR 0
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#define NUMBER_INPUT_PORTS_CROSSBAR 8
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#define NUMBER_OUTPUT_PORTS_CROSSBAR 8
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#define NUMBER_SIGNALS_PER_PORT_CROSSBAR 256
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#define MAT_LEAKAGE_REDUCTION_DUE_TO_SLEEP_TRANSISTORS_FACTOR 1
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#define LEAKAGE_REDUCTION_DUE_TO_LONG_CHANNEL_HP_TRANSISTORS_FACTOR 1
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#define PAGE_MODE 0
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#define MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA 60
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// We are actually not using this variable in the CACTI code. We just want to acknowledge that
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// this current should be multiplied by the DDR(n) system VDD value to compute the standby power
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// consumed during precharge.
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const double VDD_STORAGE_LOSS_FRACTION_WORST = 0.125;
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const double CU_RESISTIVITY = 0.022; //ohm-micron
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const double BULK_CU_RESISTIVITY = 0.018; //ohm-micron
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const double PERMITTIVITY_FREE_SPACE = 8.854e-18; //F/micron
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const static uint32_t sram_num_cells_wl_stitching_ = 16;
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const static uint32_t dram_num_cells_wl_stitching_ = 64;
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const static uint32_t comm_dram_num_cells_wl_stitching_ = 256;
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const static double num_bits_per_ecc_b_ = 8.0;
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const double bit_to_byte = 8.0;
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#define MAX_NUMBER_GATES_STAGE 20
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#define MAX_NUMBER_HTREE_NODES 20
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#define NAND2_LEAK_STACK_FACTOR 0.2
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#define NAND3_LEAK_STACK_FACTOR 0.2
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#define NOR2_LEAK_STACK_FACTOR 0.2
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#define INV_LEAK_STACK_FACTOR 0.5
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#define MAX_NUMBER_ARRAY_PARTITIONS 1000000
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// abbreviations used in this project
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// ----------------------------------
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//
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// num : number
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// rw : read/write
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// rd : read
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// wr : write
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// se : single-ended
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// sz : size
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// F : feature
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// w : width
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// h : height or horizontal
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// v : vertical or velocity
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enum ram_cell_tech_type_num
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{
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itrs_hp = 0,
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itrs_lstp = 1,
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itrs_lop = 2,
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lp_dram = 3,
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comm_dram = 4
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};
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const double pppm[4] = {1,1,1,1};
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const double pppm_lkg[4] = {0,1,1,0};
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const double pppm_dyn[4] = {1,0,0,0};
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const double pppm_Isub[4] = {0,1,0,0};
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const double pppm_Ig[4] = {0,0,1,0};
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const double pppm_sc[4] = {0,0,0,1};
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const double Ilinear_to_Isat_ratio =2.0;
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#endif
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