306 lines
7.2 KiB
C
306 lines
7.2 KiB
C
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __BASIC_CIRCUIT_H__
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#define __BASIC_CIRCUIT_H__
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#include "const.h"
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///#include "cacti_interface.h"
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using namespace std;
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#define UNI_LEAK_STACK_FACTOR 0.43
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int powers (int base, int n);
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bool is_pow2(int64_t val);
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uint32_t _log2(uint64_t num);
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int factorial(int n, int m = 1);
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int combination(int n, int m);
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//#define DBG
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#ifdef DBG
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#define PRINTDW(a);\
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a;
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#else
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#define PRINTDW(a);\
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#endif
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enum Wire_placement {
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outside_mat,
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inside_mat,
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local_wires
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};
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enum Htree_type {
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Add_htree,
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Data_in_htree,
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Data_out_htree,
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Search_in_htree,
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Search_out_htree,
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};
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//CACTI3DD
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enum Memorybus_type {
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Row_add_path,
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Col_add_path,
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Data_path
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/*in_network,
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out_network*/
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};
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/*enum Part_grain {
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Coarse_rank_level, //amsung 2009 3D DRAM
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Fine_rank_level, //Micron HMC 2011
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Coarse_bank_level, //ITRS fine TSV supported
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Fine_bank_level
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};*/
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enum Gate_type {
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nmos,
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pmos,
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inv,
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nand,
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nor,
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tri,
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tg
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};
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enum Half_net_topology {
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parallel,
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series
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};
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double logtwo (double x);
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double gate_C(
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double width,
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double wirelength,
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bool _is_dram = false,
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bool _is_sram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double gate_C_pass(
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double width,
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double wirelength,
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bool _is_dram = false,
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bool _is_sram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double drain_C_(
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double width,
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int nchannel,
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int stack,
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int next_arg_thresh_folding_width_or_height_cell,
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double fold_dimension,
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bool _is_dram = false,
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bool _is_sram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double tr_R_on(
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double width,
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int nchannel,
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int stack,
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bool _is_dram = false,
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bool _is_sram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double R_to_w(
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double res,
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int nchannel,
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bool _is_dram = false,
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bool _is_sram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double horowitz (
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double inputramptime,
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double tf,
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double vs1,
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double vs2,
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int rise);
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double pmos_to_nmos_sz_ratio(
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bool _is_dram = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double simplified_nmos_leakage(
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double nwidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double simplified_pmos_leakage(
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double pwidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double simplified_nmos_Isat(
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double nwidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double simplified_pmos_Isat(
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double pwidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double cmos_Ileak(
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double nWidth,
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double pWidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false);
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double cmos_Ig_n(
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double nWidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr= false,
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bool _is_sleep_tx = false);
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double cmos_Ig_p(
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double pWidth,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr= false,
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bool _is_sleep_tx = false);
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double cmos_Isub_leakage(
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double nWidth,
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double pWidth,
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int fanin,
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enum Gate_type g_type,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false,
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enum Half_net_topology topo = series);
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double cmos_Ig_leakage(
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double nWidth,
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double pWidth,
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int fanin,
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enum Gate_type g_type,
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bool _is_dram = false,
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bool _is_cell = false,
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bool _is_wl_tr = false,
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bool _is_sleep_tx = false,
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enum Half_net_topology topo = series);
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double shortcircuit(
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double vt,
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double velocity_index,
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double c_in,
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double c_out,
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double w_nmos,
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double w_pmos,
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double i_on_n,
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double i_on_p,
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double i_on_n_in,
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double i_on_p_in,
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double vdd);
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double shortcircuit_simple(
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double vt,
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double velocity_index,
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double c_in,
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double c_out,
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double w_nmos,
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double w_pmos,
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double i_on_n,
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double i_on_p,
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double i_on_n_in,
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double i_on_p_in,
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double vdd);
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//set power point product mask; strictly speaking this is not real point product
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inline void set_pppm(
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double * pppv,
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double a=1,
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double b=1,
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double c=1,
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double d=1
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){
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pppv[0]= a;
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pppv[1]= b;
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pppv[2]= c;
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pppv[3]= d;
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}
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inline void set_sppm(
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double * sppv,
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double a=1,
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double b=1,
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double c=1,
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double d=1
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){
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sppv[0]= a;
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sppv[1]= b;
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sppv[2]= c;
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}
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//ali
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double wire_resistance(double resistivity, double wire_width, double wire_thickness,
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double barrier_thickness, double dishing_thickness, double alpha_scatter);
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double wire_capacitance(double wire_width, double wire_thickness, double wire_spacing,
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double ild_thickness, double miller_value, double horiz_dielectric_constant,
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double vert_dielectric_constant, double fringe_cap);
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double tsv_resistance(double resistivity, double tsv_len, double tsv_diam, double tsv_contact_resistance);
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double tsv_capacitance(double tsv_len, double tsv_diam, double tsv_pitch, double dielec_thickness, double liner_dielectric_constant, double depletion_width);
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double tsv_area(double tsv_pitch);
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// end ali
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#endif
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