243 lines
9.1 KiB
C++
243 lines
9.1 KiB
C++
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include "TSV.h"
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TSV::TSV(enum TSV_type tsv_type,
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/*TechnologyParameter::*/DeviceType *dt)://TSV driver's device type set to be peri_global
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deviceType(dt), tsv_type(tsv_type)
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{
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num_gates = 1;
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num_gates_min = 1;//Is there a minimum number of stages?
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min_w_pmos = deviceType -> n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
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switch (tsv_type)
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{
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case Fine:
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cap = g_tp.tsv_parasitic_capacitance_fine;
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res = g_tp.tsv_parasitic_resistance_fine;
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min_area = g_tp.tsv_minimum_area_fine;
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break;
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case Coarse:
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cap = g_tp.tsv_parasitic_capacitance_coarse;
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res = g_tp.tsv_parasitic_resistance_coarse;
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min_area = g_tp.tsv_minimum_area_coarse;
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break;
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default:
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break;
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}
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for (int i = 0; i < MAX_NUMBER_GATES_STAGE; i++)
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{
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w_TSV_n[i] = 0;
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w_TSV_p[i] = 0;
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}
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double first_buf_stg_coef = 5; // To tune the total buffer delay.
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w_TSV_n[0] = g_tp.min_w_nmos_*first_buf_stg_coef;
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w_TSV_p[0] = min_w_pmos *first_buf_stg_coef;
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is_dram = 0;
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is_wl_tr = 0;
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//What does the function assert() mean? Should I put the function here?
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compute_buffer_stage();
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compute_area();
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compute_delay();
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}
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TSV::~TSV()
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{
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}
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void TSV::compute_buffer_stage()
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{
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double p_to_n_sz_ratio = deviceType->n_to_p_eff_curr_drv_ratio;
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//BEOL parasitics in Katti's E modeling and charac. of TSV. Needs further detailed values.
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//double res_beol = 0.1;//inaccurate
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//double cap_beol = 1e-15;
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//C_load_TSV = cap_beol + cap + cap_beol + gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0);
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C_load_TSV = cap + gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0); //+ 57.5e-15;
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if(g_ip->print_detail_debug)
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{
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cout << " The input cap of 1st buffer: " << gate_C(w_TSV_n[0] + w_TSV_p[0], 0) * 1e15 << " fF";
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}
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double F = C_load_TSV / gate_C(w_TSV_n[0] + w_TSV_p[0], 0);
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if(g_ip->print_detail_debug)
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{
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cout<<"\nF is "<<F<<" \n";
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}
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//Obtain buffer chain stages using logic effort function. Does stage number have to be even?
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num_gates = logical_effort(
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num_gates_min,
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1,
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F,
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w_TSV_n,
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w_TSV_p,
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C_load_TSV,
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p_to_n_sz_ratio,
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is_dram,
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is_wl_tr,
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g_tp.max_w_nmos_/*Correct? Decoder uses max_w_nmos_dec*/);
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}
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void TSV::compute_area()
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{
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//Obtain the driver chain area and leakage power for TSV
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double Vdd = deviceType->Vdd;
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double cumulative_area = 0;
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double cumulative_curr = 0; // cumulative leakage current
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double cumulative_curr_Ig = 0; // cumulative leakage current
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Buffer_area.h = g_tp.cell_h_def;//cell_h_def is the assigned height for memory cell (5um), is it correct to use it here?
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//logic_effort() didn't give the size of w_n[0] and w_p[0], which is min size inverter
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//w_TSV_n[0] = g_tp.min_w_nmos_;
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//w_TSV_p[0] = min_w_pmos;
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int i;
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for (i = 0; i < num_gates; i++)
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{
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cumulative_area += compute_gate_area(INV, 1, w_TSV_p[i], w_TSV_n[i], Buffer_area.h);
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if(g_ip->print_detail_debug)
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{
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cout << "\n\tArea up to the " << i+1 << " stages is: " << cumulative_area << " um2";
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}
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cumulative_curr += cmos_Isub_leakage(w_TSV_n[i], w_TSV_p[i], 1, inv, is_dram);
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cumulative_curr_Ig += cmos_Ig_leakage(w_TSV_n[i], w_TSV_p[i], 1, inv, is_dram);// The operator += is mistakenly put as = in decoder.cc
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}
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power.readOp.leakage = cumulative_curr * Vdd;
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power.readOp.gate_leakage = cumulative_curr_Ig * Vdd;
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Buffer_area.set_area(cumulative_area);
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Buffer_area.w = (cumulative_area / Buffer_area.h);
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TSV_metal_area.set_area(min_area * 3.1416/16);
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if( Buffer_area.get_area() < min_area - TSV_metal_area.get_area() )
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area.set_area(min_area);
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else
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area.set_area(Buffer_area.get_area() + TSV_metal_area.get_area());
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}
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void TSV::compute_delay()
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{
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//Buffer chain delay and Dynamic Power
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double rd, tf, this_delay, c_load, c_intrinsic, inrisetime = 0/*The initial time*/;
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//is_dram, is_wl_tr are declared to be false in the constructor
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rd = tr_R_on(w_TSV_n[0], NCH, 1, is_dram, false, is_wl_tr);
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c_load = gate_C(w_TSV_n[1] + w_TSV_p[1], 0.0, is_dram, false, is_wl_tr);
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c_intrinsic = drain_C_(w_TSV_p[0], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) +
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drain_C_(w_TSV_n[0], NCH, 1, 1, area.h, is_dram, false, is_wl_tr);
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tf = rd * (c_intrinsic + c_load);
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//Refer to horowitz function definition
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this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE);
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delay += this_delay;
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inrisetime = this_delay / (1.0 - 0.5);
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double Vdd = deviceType -> Vdd;
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power.readOp.dynamic += (c_load + c_intrinsic) * Vdd * Vdd;
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int i;
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for (i = 1; i < num_gates - 1; ++i)
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{
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rd = tr_R_on(w_TSV_n[i], NCH, 1, is_dram, false, is_wl_tr);
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c_load = gate_C(w_TSV_p[i+1] + w_TSV_n[i+1], 0.0, is_dram, false, is_wl_tr);
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c_intrinsic = drain_C_(w_TSV_p[i], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) +
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drain_C_(w_TSV_n[i], NCH, 1, 1, area.h, is_dram, false, is_wl_tr);
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tf = rd * (c_intrinsic + c_load);
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this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE);
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delay += this_delay;
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inrisetime = this_delay / (1.0 - 0.5);
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power.readOp.dynamic += (c_load + c_intrinsic) * Vdd * Vdd;
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}
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// add delay of final inverter that drives the TSV
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i = num_gates - 1;
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c_load = C_load_TSV;
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rd = tr_R_on(w_TSV_n[i], NCH, 1, is_dram, false, is_wl_tr);
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c_intrinsic = drain_C_(w_TSV_p[i], PCH, 1, 1, area.h, is_dram, false, is_wl_tr) +
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drain_C_(w_TSV_n[i], NCH, 1, 1, area.h, is_dram, false, is_wl_tr);
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//The delay method for the last stage of buffer chain in Decoder.cc
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//double res_beol = 0.1;//inaccurate
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//double R_TSV_out = res_beol + res + res_beol;
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double R_TSV_out = res;
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tf = rd * (c_intrinsic + c_load) + R_TSV_out * c_load / 2;
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this_delay = horowitz(inrisetime, tf, 0.5, 0.5, RISE);
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delay += this_delay;
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power.readOp.dynamic += (c_load + c_intrinsic) * Vdd * Vdd; //Dynamic power done
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//Is the delay actually delay/(1.0-0.5)??
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//ret_val = this_delay / (1.0 - 0.5);
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//return ret_val;//Originally for decoder.cc to get outrise time
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/* This part is to obtain delay in the TSV path, refer to Katti's paper.
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* It can be used alternatively as the step to get the final-stage delay
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double C_ext = c_intrinsic;
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R_dr = rd;
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double C_int = gate_C(g_tp.min_w_nmos_ + min_w_pmos, 0.0, is_dram, false, is_wl_tr);
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delay_TSV_path = 0.693 * (R_dr * C_ext + (R_dr + res_beol) * cap_beol + (R_dr + res_beol + 0.5 * res) * cap
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+ (R_dr + res_beol + res + res_beol) * (cap_beol + C_int);
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delay += delay_TSV_path;
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*/
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}
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void TSV::print_TSV()
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{
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cout << "\nTSV Properties:\n\n";
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cout << " Delay Optimal - "<<
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" \n\tTSV Cap: " << cap * 1e15 << " fF" <<
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" \n\tTSV Res: " << res * 1e3 << " mOhm"<<
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" \n\tNumber of Buffer Chain stages - " << num_gates <<
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" \n\tDelay - " << delay * 1e9 << " (ns) "
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" \n\tPowerD - " << power.readOp.dynamic * 1e9<< " (nJ)"
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" \n\tPowerL - " << power.readOp.leakage * 1e3<< " (mW)"
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" \n\tPowerLgate - " << power.readOp.gate_leakage * 1e3<< " (mW)\n" <<
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" \n\tBuffer Area: " << Buffer_area.get_area() << " um2" <<
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" \n\tBuffer Height: " << Buffer_area.h << " um" <<
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" \n\tBuffer Width: " << Buffer_area.w << " um" <<
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" \n\tTSV metal area: " << TSV_metal_area.get_area() << " um2" <<
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" \n\tTSV minimum occupied area: " <<min_area << " um2"<<
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" \n\tTotal area: " << area.get_area() << " um2";
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cout <<endl;
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cout <<endl;
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}
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