226 lines
8.9 KiB
C
226 lines
8.9 KiB
C
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#ifndef __EXTIO_TECH__
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#define __EXTIO_TECH__
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#include <iostream>
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#include "parameter.h"
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#include "const.h"
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#define NUM_DIMM 1
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extern const double rtt1_wr_lrdimm_ddr3[8][4];
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extern const double rtt2_wr_lrdimm_ddr3[8][4];
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extern const double rtt1_rd_lrdimm_ddr3[8][4];
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extern const double rtt2_rd_lrdimm_ddr3[8][4];
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extern const double rtt1_wr_host_dimm_ddr3[3][4];
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extern const double rtt2_wr_host_dimm_ddr3[3][4];
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extern const double rtt1_rd_host_dimm_ddr3[3][4];
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extern const double rtt2_rd_host_dimm_ddr3[3][4];
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extern const double rtt1_wr_bob_dimm_ddr3[3][4];
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extern const double rtt2_wr_bob_dimm_ddr3[3][4];
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extern const double rtt1_rd_bob_dimm_ddr3[3][4];
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extern const double rtt2_rd_bob_dimm_ddr3[3][4];
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extern const double rtt1_wr_lrdimm_ddr4[8][4];
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extern const double rtt2_wr_lrdimm_ddr4[8][4];
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extern const double rtt1_rd_lrdimm_ddr4[8][4];
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extern const double rtt2_rd_lrdimm_ddr4[8][4];
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extern const double rtt1_wr_host_dimm_ddr4[3][4];
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extern const double rtt2_wr_host_dimm_ddr4[3][4];
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extern const double rtt1_rd_host_dimm_ddr4[3][4];
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extern const double rtt2_rd_host_dimm_ddr4[3][4];
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extern const double rtt1_wr_bob_dimm_ddr4[3][4];
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extern const double rtt2_wr_bob_dimm_ddr4[3][4];
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extern const double rtt1_rd_bob_dimm_ddr4[3][4];
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extern const double rtt2_rd_bob_dimm_ddr4[3][4];
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class IOTechParam
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{
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public:
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IOTechParam(InputParameter *);
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// connection : 0(bob-dimm), 1(host-dimm), 2(on-dimm)
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IOTechParam(InputParameter *, Mem_IO_type io_type, int num_mem_dq, int mem_data_width, int num_dq, int connection, int num_loads, double freq) ;
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~IOTechParam();
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double num_mem_ca; /* Number of loads on the address bus
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based on total number of memories in the channel.For
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registered or buffered configurations, the num_mem_dq and num_mem_ca is per buffer. */
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double num_mem_clk; /* Number of loads on the clock as total
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memories in the channel / number of clock lines available */
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//Technology Parameters
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// IO Supply voltage (V)
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double vdd_io; /* Voltage swing on CLK/CLKB (V) (swing on the CLK pin if it
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is differentially terminated) */
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double v_sw_clk;
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// Loading parameters
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double c_int; /*Internal IO loading (pF) (loading within the IO, due to
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predriver nets) */
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double c_tx; /* IO TX self-load including package (pF) (loading at the
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CPU TX pin) */
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double c_data; /* Device loading per memory data pin (pF) (DRAM device
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load for DQ per die) */
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double c_addr; /* Device loading per memory address pin (pF) (DRAM
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device load for CA per die) */
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double i_bias; /* Bias current (mA) (includes bias current for the whole memory
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bus due to RX Vref based receivers */
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double i_leak; // Active leakage current per pin (nA)
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// IO Area coefficients
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double ioarea_c; /* sq.mm. (IO Area baseline coeeficient for control
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circuitry and overhead) */
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double ioarea_k0; /* sq.mm * ohms (IO Area coefficient for the driver, for
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unit drive strength or output impedance) */
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double ioarea_k1; /* sq.mm * ohms / MHz (IO Area coefficient for the
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predriver final stage, based on fanout needed) */
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double ioarea_k2; /* sq.mm * ohms / MHz^2 (IO Area coefficient for
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predriver middle stage, based on fanout needed) */
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double ioarea_k3; /* sq.mm * ohms / MHz^3 (IO Area coefficient for
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predriver first stage, based on fanout needed) */
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// Timing parameters (ps)
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double t_ds; //DQ setup time at DRAM
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double t_is; //CA setup time at DRAM
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double t_dh; //DQ hold time at DRAM
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double t_ih; //CA hold time at DRAM
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double t_dcd_soc; //Duty-cycle distortion at the CPU/SOC
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double t_dcd_dram; //Duty-cycle distortion at the DRAM
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double t_error_soc; //Timing error due to edge placement uncertainty of the DLL
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double t_skew_setup;//Setup skew between DQ/DQS or CA/CLK after deskewing the lines
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double t_skew_hold; //Hold skew between DQ/DQS or CA/CLK after deskewing the lines
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double t_dqsq; //DQ-DQS skew at the DRAM output during Read
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//double t_qhs; //DQ-DQS hold factor at the DRAM output during Read FIXME: I am commenting it as the variable is never used.
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double t_soc_setup; //Setup time at SOC input dueing Read
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double t_soc_hold; //Hold time at SOC input during Read
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double t_jitter_setup; /* Half-cycle jitter on the DQS at DRAM input
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affecting setup time */
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double t_jitter_hold; /* Half-cycle jitter on the DQS at the DRAM input
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affecting hold time */
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double t_jitter_addr_setup; /* Half-cycle jitter on the CLK at DRAM input
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affecting setup time */
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double t_jitter_addr_hold; /* Half-cycle jitter on the CLK at the DRAM
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input affecting hold time */
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double t_cor_margin; // Statistical correlation margin
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//Termination Parameters
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double r_diff_term; /* Differential termination resister if
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used for CLK (Ohm) */
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// ODT related termination resistor values (Ohm)
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double rtt1_dq_read; //DQ Read termination at CPU
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double rtt2_dq_read; //DQ Read termination at inactive DRAM
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double rtt1_dq_write; //DQ Write termination at active DRAM
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double rtt2_dq_write; //DQ Write termination at inactive DRAM
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double rtt_ca; //CA fly-by termination
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double rs1_dq; //Series resistor at active DRAM
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double rs2_dq; //Series resistor at inactive DRAM
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double r_stub_ca; //Series resistor for the fly-by channel
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double r_on; //Driver impedance
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double r_on_ca; //CA driver impedance
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double z0; //Line impedance (ohms): Characteristic impedance of the route.
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double t_flight; /* Flight time of the interconnect (ns) (approximately
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180ps/inch for FR4) */
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double t_flight_ca; /* Flight time of the Control/Address (CA)
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interconnect (ns) (approximately 180ps/inch for FR4) */
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// Voltage noise coeffecients
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double k_noise_write; //Proportional noise coefficient for Write mode
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double k_noise_read; //Proportional noise coefficient for Read mode
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double k_noise_addr; //Proportional noise coefficient for Address bus
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double v_noise_independent_write; //Independent noise voltage for Write mode
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double v_noise_independent_read; //Independent noise voltage for Read mode
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double v_noise_independent_addr; //Independent noise voltage for Address bus
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//SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE
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/* This is a user-defined section that depends on the channel sensitivity
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* to IO and DRAM parameters. The t_jitter_* and k_noise_* are the
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* parameters that are impacted based on the channel analysis. The user
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* can define any relationship between the termination, loading and
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* configuration parameters AND the t_jitter/k_noise parameters. */
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double k_noise_write_sen;
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double k_noise_read_sen;
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double k_noise_addr_sen;
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double t_jitter_setup_sen;
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double t_jitter_hold_sen;
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double t_jitter_addr_setup_sen;
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double t_jitter_addr_hold_sen;
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//SWING AND TERMINATION CALCULATIONS
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//R|| calculation
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double rpar_write;
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double rpar_read;
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//Swing calculation
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double v_sw_data_read_load1; //Swing for DQ at dram1 during READ
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double v_sw_data_read_load2; //Swing for DQ at dram2 during READ
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double v_sw_data_read_line; //Swing for DQ on the line during READ
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double v_sw_addr; //Swing for the address bus
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double v_sw_data_write_load1; //Swing for DQ at dram1 during WRITE
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double v_sw_data_write_load2; //Swing for DQ at dram2 during WRITE
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double v_sw_data_write_line; //Swing for DQ on the line during WRITE
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// PHY Static Power Coefficients (mW)
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double phy_datapath_s; // Datapath Static Power
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double phy_phase_rotator_s; // Phase Rotator Static Power
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double phy_clock_tree_s; // Clock Tree Static Power
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double phy_rx_s; // Receiver Static Power
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double phy_dcc_s; // Duty Cycle Correction Static Power
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double phy_deskew_s; // Deskewing Static Power
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double phy_leveling_s; // Write and Read Leveling Static Power
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double phy_pll_s; // PHY PLL Static Power
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// PHY Dynamic Power Coefficients (mW/Gbps)
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double phy_datapath_d; // Datapath Dynamic Power
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double phy_phase_rotator_d; // Phase Rotator Dynamic Power
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double phy_clock_tree_d; // Clock Tree Dynamic Power
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double phy_rx_d; // Receiver Dynamic Power
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double phy_dcc_d; // Duty Cycle Correction Dynamic Power
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double phy_deskew_d; // Deskewing Dynamic Power
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double phy_leveling_d; // Write and Read Leveling Dynamic Power
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double phy_pll_d; // PHY PLL Dynamic Power
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//PHY Wakeup Times (Sleep to Active) (microseconds)
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double phy_pll_wtime; // PHY PLL Wakeup Time
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double phy_phase_rotator_wtime; // Phase Rotator Wakeup Time
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double phy_rx_wtime; // Receiver Wakeup Time
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double phy_bandgap_wtime; // Bandgap Wakeup Time
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double phy_deskew_wtime; // Deskewing Wakeup Time
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double phy_vrefgen_wtime; // VREF Generator Wakeup Time
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// RTT values depends on the number of loads, frequency, and link_type
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double frequency;
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Mem_IO_type io_type;
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int frequnecy_index(Mem_IO_type type);
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};
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#endif
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