162 lines
7.2 KiB
C++
162 lines
7.2 KiB
C++
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include "crossbar.h"
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#define ASPECT_THRESHOLD .8
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#define ADJ 1
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Crossbar::Crossbar(
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double n_inp_,
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double n_out_,
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double flit_size_,
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/*TechnologyParameter::*/DeviceType *dt
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):n_inp(n_inp_), n_out(n_out_), flit_size(flit_size_), deviceType(dt)
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{
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min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio*g_tp.min_w_nmos_;
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Vdd = dt->Vdd;
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CB_ADJ = 1;
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}
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Crossbar::~Crossbar(){}
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double Crossbar::output_buffer()
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{
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//Wire winit(4, 4);
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double l_eff = n_inp*flit_size*g_tp.wire_outside_mat.pitch;
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Wire w1(g_ip->wt, l_eff);
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//double s1 = w1.repeater_size *l_eff*ADJ/w1.repeater_spacing;
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double s1 = w1.repeater_size * (l_eff <w1.repeater_spacing? l_eff *ADJ/w1.repeater_spacing : ADJ);
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double pton_size = deviceType->n_to_p_eff_curr_drv_ratio;
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// the model assumes input capacitance of the wire driver = input capacitance of nand + nor = input cap of the driver transistor
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TriS1 = s1*(1 + pton_size)/(2 + pton_size + 1 + 2*pton_size);
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TriS2 = s1; //driver transistor
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if (TriS1 < 1)
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TriS1 = 1;
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double input_cap = gate_C(TriS1*(2*min_w_pmos + g_tp.min_w_nmos_), 0) +
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gate_C(TriS1*(min_w_pmos + 2*g_tp.min_w_nmos_), 0);
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// input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
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// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 +
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// gate_C(TriS2*g_tp.min_w_nmos_, 0)+
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// drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 +
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// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
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// gate_C(TriS2*min_w_pmos, 0);
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tri_int_cap = drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 +
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gate_C(TriS2*g_tp.min_w_nmos_, 0)+
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drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 +
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drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
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gate_C(TriS2*min_w_pmos, 0);
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double output_cap = drain_C_(TriS2*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) +
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drain_C_(TriS2*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def);
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double ctr_cap = gate_C(TriS2 *(min_w_pmos + g_tp.min_w_nmos_), 0);
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tri_inp_cap = input_cap;
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tri_out_cap = output_cap;
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tri_ctr_cap = ctr_cap;
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return input_cap + output_cap + ctr_cap;
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}
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void Crossbar::compute_power()
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{
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Wire winit(4, 4);
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double tri_cap = output_buffer();
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assert(tri_cap > 0);
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//area of a tristate logic
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double g_area = compute_gate_area(INV, 1, TriS2*g_tp.min_w_nmos_, TriS2*min_w_pmos, g_tp.cell_h_def);
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g_area *= 2; // to model area of output transistors
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g_area += compute_gate_area (NAND, 2, TriS1*2*g_tp.min_w_nmos_, TriS1*min_w_pmos, g_tp.cell_h_def);
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g_area += compute_gate_area (NOR, 2, TriS1*g_tp.min_w_nmos_, TriS1*2*min_w_pmos, g_tp.cell_h_def);
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double width /*per tristate*/ = g_area/(CB_ADJ * g_tp.cell_h_def);
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// effective no. of tristate buffers that need to be laid side by side
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int ntri = (int)ceil(g_tp.cell_h_def/(g_tp.wire_outside_mat.pitch));
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double wire_len = MAX(width*ntri*n_out, flit_size*g_tp.wire_outside_mat.pitch*n_out);
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Wire w1(g_ip->wt, wire_len);
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area.w = wire_len;
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area.h = g_tp.wire_outside_mat.pitch*n_inp*flit_size * CB_ADJ;
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Wire w2(g_ip->wt, area.h);
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double aspect_ratio_cb = (area.h/area.w)*(n_out/n_inp);
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if (aspect_ratio_cb > 1) aspect_ratio_cb = 1/aspect_ratio_cb;
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if (aspect_ratio_cb < ASPECT_THRESHOLD) {
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if (n_out > 2 && n_inp > 2) {
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CB_ADJ+=0.2;
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//cout << "CB ADJ " << CB_ADJ << endl;
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if (CB_ADJ < 4) {
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this->compute_power();
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}
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}
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}
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power.readOp.dynamic = (w1.power.readOp.dynamic + w2.power.readOp.dynamic + (tri_inp_cap * n_out + tri_out_cap * n_inp + tri_ctr_cap + tri_int_cap) * Vdd*Vdd)*flit_size;
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power.readOp.leakage = n_inp * n_out * flit_size * (
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cmos_Isub_leakage(g_tp.min_w_nmos_*TriS2*2, min_w_pmos*TriS2*2, 1, inv) *Vdd+
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cmos_Isub_leakage(g_tp.min_w_nmos_*TriS1*3, min_w_pmos*TriS1*3, 2, nand)*Vdd+
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cmos_Isub_leakage(g_tp.min_w_nmos_*TriS1*3, min_w_pmos*TriS1*3, 2, nor) *Vdd+
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w1.power.readOp.leakage + w2.power.readOp.leakage);
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power.readOp.gate_leakage = n_inp * n_out * flit_size * (
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cmos_Ig_leakage(g_tp.min_w_nmos_*TriS2*2, min_w_pmos*TriS2*2, 1, inv) *Vdd+
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cmos_Ig_leakage(g_tp.min_w_nmos_*TriS1*3, min_w_pmos*TriS1*3, 2, nand)*Vdd+
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cmos_Ig_leakage(g_tp.min_w_nmos_*TriS1*3, min_w_pmos*TriS1*3, 2, nor) *Vdd+
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w1.power.readOp.gate_leakage + w2.power.readOp.gate_leakage);
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// delay calculation
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double l_eff = n_inp*flit_size*g_tp.wire_outside_mat.pitch;
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Wire wdriver(g_ip->wt, l_eff);
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double res = g_tp.wire_outside_mat.R_per_um * (area.w+area.h) + tr_R_on(g_tp.min_w_nmos_*wdriver.repeater_size, NCH, 1);
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double cap = g_tp.wire_outside_mat.C_per_um * (area.w + area.h) + n_out*tri_inp_cap + n_inp*tri_out_cap;
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delay = horowitz(w1.signal_rise_time(), res*cap, deviceType->Vth/deviceType->Vdd, deviceType->Vth/deviceType->Vdd, RISE);
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Wire wreset();
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}
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void Crossbar::print_crossbar()
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{
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cout << "\nCrossbar Stats (" << n_inp << "x" << n_out << ")\n\n";
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cout << "Flit size : " << flit_size << " bits" << endl;
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cout << "Width : " << area.w << " u" << endl;
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cout << "Height : " << area.h << " u" << endl;
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cout << "Dynamic Power : " << power.readOp.dynamic*1e9 * MIN(n_inp, n_out) << " (nJ)" << endl;
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cout << "Leakage Power : " << power.readOp.leakage*1e3 << " (mW)" << endl;
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cout << "Gate Leakage Power : " << power.readOp.gate_leakage*1e3 << " (mW)" << endl;
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cout << "Crossbar Delay : " << delay*1e12 << " ps\n";
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}
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