273 lines
7.2 KiB
C
273 lines
7.2 KiB
C
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#ifndef __DECODER_H__
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#define __DECODER_H__
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#include "area.h"
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#include "component.h"
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#include "parameter.h"
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#include "powergating.h"
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#include <vector>
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using namespace std;
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class Decoder : public Component
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{
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public:
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Decoder(
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int _num_dec_signals,
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bool flag_way_select,
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double _C_ld_dec_out,
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double _R_wire_dec_out,
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bool fully_assoc_,
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bool is_dram_,
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bool is_wl_tr_,
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const Area & cell_);
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bool exist;
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int num_in_signals;
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double C_ld_dec_out;
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double R_wire_dec_out;
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int num_gates;
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int num_gates_min;
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double w_dec_n[MAX_NUMBER_GATES_STAGE];
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double w_dec_p[MAX_NUMBER_GATES_STAGE];
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double delay;
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//powerDef power;
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bool fully_assoc;
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bool is_dram;
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bool is_wl_tr;
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double total_driver_nwidth;
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double total_driver_pwidth;
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Sleep_tx * sleeptx;
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const Area & cell;
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int nodes_DSTN;
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void compute_widths();
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void compute_area();
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double compute_delays(double inrisetime); // return outrisetime
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void compute_power_gating();
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void leakage_feedback(double temperature);
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~Decoder()
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{
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if (!sleeptx)
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delete sleeptx;
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};
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};
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class PredecBlk : public Component
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{
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public:
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PredecBlk(
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int num_dec_signals,
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Decoder * dec,
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double C_wire_predec_blk_out,
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double R_wire_predec_blk_out,
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int num_dec_per_predec,
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bool is_dram_,
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bool is_blk1);
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Decoder * dec;
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bool exist;
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int number_input_addr_bits;
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double C_ld_predec_blk_out;
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double R_wire_predec_blk_out;
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int branch_effort_nand2_gate_output;
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int branch_effort_nand3_gate_output;
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bool flag_two_unique_paths;
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int flag_L2_gate;
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int number_inputs_L1_gate;
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int number_gates_L1_nand2_path;
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int number_gates_L1_nand3_path;
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int number_gates_L2;
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int min_number_gates_L1;
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int min_number_gates_L2;
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int num_L1_active_nand2_path;
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int num_L1_active_nand3_path;
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double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
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double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
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double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
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double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
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double w_L2_n[MAX_NUMBER_GATES_STAGE];
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double w_L2_p[MAX_NUMBER_GATES_STAGE];
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double delay_nand2_path;
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double delay_nand3_path;
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powerDef power_nand2_path;
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powerDef power_nand3_path;
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powerDef power_L2;
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bool is_dram_;
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void compute_widths();
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void compute_area();
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void leakage_feedback(double temperature);
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pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
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// return <outrise_nand2, outrise_nand3>
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};
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class PredecBlkDrv : public Component
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{
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public:
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PredecBlkDrv(
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int way_select,
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PredecBlk * blk_,
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bool is_dram);
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int flag_driver_exists;
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int number_input_addr_bits;
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int number_gates_nand2_path;
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int number_gates_nand3_path;
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int min_number_gates;
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int num_buffers_driving_1_nand2_load;
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int num_buffers_driving_2_nand2_load;
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int num_buffers_driving_4_nand2_load;
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int num_buffers_driving_2_nand3_load;
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int num_buffers_driving_8_nand3_load;
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int num_buffers_nand3_path;
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double c_load_nand2_path_out;
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double c_load_nand3_path_out;
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double r_load_nand2_path_out;
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double r_load_nand3_path_out;
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double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
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double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
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double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
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double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
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double delay_nand2_path;
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double delay_nand3_path;
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powerDef power_nand2_path;
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powerDef power_nand3_path;
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PredecBlk * blk;
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Decoder * dec;
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bool is_dram_;
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int way_select;
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void compute_widths();
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void compute_area();
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void leakage_feedback(double temperature);
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pair<double, double> compute_delays(
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double inrisetime_nand2_path,
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double inrisetime_nand3_path); // return <outrise_nand2, outrise_nand3>
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inline int num_addr_bits_nand2_path()
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{
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return num_buffers_driving_1_nand2_load +
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num_buffers_driving_2_nand2_load +
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num_buffers_driving_4_nand2_load;
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}
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inline int num_addr_bits_nand3_path()
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{
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return num_buffers_driving_2_nand3_load +
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num_buffers_driving_8_nand3_load;
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}
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double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
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};
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class Predec : public Component
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{
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public:
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Predec(
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PredecBlkDrv * drv1,
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PredecBlkDrv * drv2);
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double compute_delays(double inrisetime); // return outrisetime
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void leakage_feedback(double temperature);
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PredecBlk * blk1;
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PredecBlk * blk2;
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PredecBlkDrv * drv1;
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PredecBlkDrv * drv2;
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powerDef block_power;
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powerDef driver_power;
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private:
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// returns <delay, risetime>
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pair<double, double> get_max_delay_before_decoder(
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pair<double, double> input_pair1,
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pair<double, double> input_pair2);
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};
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class Driver : public Component
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{
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public:
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Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
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int number_gates;
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int min_number_gates;
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double width_n[MAX_NUMBER_GATES_STAGE];
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double width_p[MAX_NUMBER_GATES_STAGE];
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double c_gate_load;
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double c_wire_load;
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double r_wire_load;
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double delay;
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// powerDef power;
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bool is_dram_;
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double total_driver_nwidth;
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double total_driver_pwidth;
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Sleep_tx * sleeptx;
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void compute_widths();
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void compute_area();
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double compute_delay(double inrisetime);
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void compute_power_gating();
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~Driver()
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{
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if (!sleeptx)
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delete sleeptx;
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};
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};
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#endif
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