207 lines
8.3 KiB
C++
207 lines
8.3 KiB
C++
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/*****************************************************************************
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* CACTI 7.0
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* SOFTWARE LICENSE AGREEMENT
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* Copyright 2015 Hewlett-Packard Development Company, L.P.
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
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*
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***************************************************************************/
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#include "bank.h"
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#include <iostream>
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Bank::Bank(const DynamicParameter & dyn_p):
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dp(dyn_p), mat(dp),
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num_addr_b_mat(dyn_p.number_addr_bits_mat),
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num_mats_hor_dir(dyn_p.num_mats_h_dir), num_mats_ver_dir(dyn_p.num_mats_v_dir),
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array_leakage(0),
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wl_leakage(0),
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cl_leakage(0)
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{
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// Mat temp(dyn_p);
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int RWP;
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int ERP;
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int EWP;
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int SCHP;
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if (dp.use_inp_params)
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{
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RWP = dp.num_rw_ports;
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ERP = dp.num_rd_ports;
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EWP = dp.num_wr_ports;
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SCHP = dp.num_search_ports;
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}
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else
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{
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RWP = g_ip->num_rw_ports;
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ERP = g_ip->num_rd_ports;
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EWP = g_ip->num_wr_ports;
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SCHP = g_ip->num_search_ports;
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}
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int total_addrbits = (dp.number_addr_bits_mat + dp.number_subbanks_decode)*(RWP+ERP+EWP);
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int datainbits = dp.num_di_b_bank_per_port * (RWP + EWP);
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int dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP);
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int searchinbits;
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int searchoutbits;
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if (dp.fully_assoc || dp.pure_cam)
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{
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datainbits = dp.num_di_b_bank_per_port * (RWP + EWP);
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dataoutbits = dp.num_do_b_bank_per_port * (RWP + ERP);
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searchinbits = dp.num_si_b_bank_per_port * SCHP;
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searchoutbits = dp.num_so_b_bank_per_port * SCHP;
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}
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if (!(dp.fully_assoc || dp.pure_cam))
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{
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if (g_ip->fast_access && dp.is_tag == false)
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{
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dataoutbits *= g_ip->data_assoc;
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}
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htree_in_add = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits, 0,dataoutbits,0, num_mats_ver_dir*2, num_mats_hor_dir*2, Add_htree);
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htree_in_data = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits, 0,dataoutbits,0, num_mats_ver_dir*2, num_mats_hor_dir*2, Data_in_htree);
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htree_out_data = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits, 0,dataoutbits,0, num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree);
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// htree_out_data = new Htree2 (g_ip->wt,(double) 100, (double)100,
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// total_addrbits, datainbits, 0,dataoutbits,0, num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree);
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area.w = htree_in_data->area.w;
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area.h = htree_in_data->area.h;
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}
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else
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{
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htree_in_add = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits, searchinbits,dataoutbits,searchoutbits, num_mats_ver_dir*2, num_mats_hor_dir*2, Add_htree);
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htree_in_data = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits,searchinbits, dataoutbits, searchoutbits, num_mats_ver_dir*2, num_mats_hor_dir*2, Data_in_htree);
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htree_out_data = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits,searchinbits, dataoutbits, searchoutbits,num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree);
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htree_in_search = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits,searchinbits, dataoutbits, searchoutbits, num_mats_ver_dir*2, num_mats_hor_dir*2, Data_in_htree,true, true);
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htree_out_search = new Htree2 (dp.wtype/*g_ip->wt*/,(double) mat.area.w, (double)mat.area.h,
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total_addrbits, datainbits,searchinbits, dataoutbits, searchoutbits,num_mats_ver_dir*2, num_mats_hor_dir*2, Data_out_htree,true);
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area.w = htree_in_data->area.w;
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area.h = htree_in_data->area.h;
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}
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num_addr_b_row_dec = _log2(mat.subarray.num_rows);
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num_addr_b_routed_to_mat_for_act = num_addr_b_row_dec;
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num_addr_b_routed_to_mat_for_rd_or_wr = num_addr_b_mat - num_addr_b_row_dec;
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}
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Bank::~Bank()
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{
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delete htree_in_add;
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delete htree_out_data;
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delete htree_in_data;
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if (dp.fully_assoc || dp.pure_cam)
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{
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delete htree_in_search;
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delete htree_out_search;
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}
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}
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double Bank::compute_delays(double inrisetime)
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{
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return mat.compute_delays(inrisetime);
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}
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void Bank::compute_power_energy()
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{
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mat.compute_power_energy();
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if (!(dp.fully_assoc || dp.pure_cam))
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{
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power.readOp.dynamic += mat.power.readOp.dynamic * dp.num_act_mats_hor_dir;
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power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats;
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power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats;
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power.readOp.dynamic += htree_in_add->power.readOp.dynamic;
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power.readOp.dynamic += htree_out_data->power.readOp.dynamic;
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array_leakage += mat.array_leakage*dp.num_mats;
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wl_leakage += mat.wl_leakage*dp.num_mats;
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cl_leakage += mat.cl_leakage*dp.num_mats;
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//
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// power.readOp.leakage += htree_in_add->power.readOp.leakage;
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// power.readOp.leakage += htree_in_data->power.readOp.leakage;
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// power.readOp.leakage += htree_out_data->power.readOp.leakage;
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// power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage;
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// power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage;
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// power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage;
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}
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else
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{
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power.readOp.dynamic += mat.power.readOp.dynamic ;//for fa and cam num_act_mats_hor_dir is 1 for plain r/w
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power.readOp.leakage += mat.power.readOp.leakage * dp.num_mats;
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power.readOp.gate_leakage += mat.power.readOp.gate_leakage * dp.num_mats;
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power.searchOp.dynamic += mat.power.searchOp.dynamic * dp.num_mats;
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power.searchOp.dynamic += mat.power_bl_precharge_eq_drv.searchOp.dynamic +
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mat.power_sa.searchOp.dynamic +
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mat.power_bitline.searchOp.dynamic +
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mat.power_subarray_out_drv.searchOp.dynamic+
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mat.ml_to_ram_wl_drv->power.readOp.dynamic;
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power.readOp.dynamic += htree_in_add->power.readOp.dynamic;
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power.readOp.dynamic += htree_out_data->power.readOp.dynamic;
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power.searchOp.dynamic += htree_in_search->power.searchOp.dynamic;
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power.searchOp.dynamic += htree_out_search->power.searchOp.dynamic;
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power.readOp.leakage += htree_in_add->power.readOp.leakage;
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power.readOp.leakage += htree_in_data->power.readOp.leakage;
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power.readOp.leakage += htree_out_data->power.readOp.leakage;
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power.readOp.leakage += htree_in_search->power.readOp.leakage;
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power.readOp.leakage += htree_out_search->power.readOp.leakage;
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power.readOp.gate_leakage += htree_in_add->power.readOp.gate_leakage;
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power.readOp.gate_leakage += htree_in_data->power.readOp.gate_leakage;
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power.readOp.gate_leakage += htree_out_data->power.readOp.gate_leakage;
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power.readOp.gate_leakage += htree_in_search->power.readOp.gate_leakage;
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power.readOp.gate_leakage += htree_out_search->power.readOp.gate_leakage;
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}
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}
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