93 lines
2 KiB
VHDL
93 lines
2 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity racine_machine is
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port (
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clock : IN std_logic;
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START : IN std_logic;
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RESET : IN std_logic;
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m_in : IN std_logic_vector(3 downto 0);
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m_out : OUT std_logic_vector(3 downto 0)
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-- count : OUT std_logic_vector(3 downto 0)
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) ;
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end racine_machine;
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architecture behavior of racine_machine is
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type etat is (attente, init, calcul, fin);
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type cal is ('0','1');
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signal state : etat := attente;
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signal done : cal;
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BEGIN
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Racine : process(clock)
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variable X : integer;
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variable V : integer;
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variable Z : integer;
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variable n : integer := 5;
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variable cond : integer;
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variable i : integer;
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begin
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if(rising_edge(clock)) then
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if RESET = '1' then
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state <= attente;
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else
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case state is
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when attente =>
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if START = '1' then
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state <= init;
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else
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state <= attente;
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end if;
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done <= '0';
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when init =>
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X := to_integer(unsigned(m_in));
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V := 256;
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Z := 0;
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i := 5;
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done <= '0';
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state <= calcul;
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when calcul =>
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Z := Z+V;
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cond := X-Z;
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if cond >= 0 then
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X := X-Z;
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Z := (Z+V)/2;
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else
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Z := (Z-V)/2;
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end if;
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V := V/4;
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i := i-1;
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-- count <= std_logic_vector(to_unsigned(i, count'length));
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done <= '0';
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if i = 0 then
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state <= fin;
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else
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state <= calcul;
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end if;
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when fin =>
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done <= '1';
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m_out <= std_logic_vector(to_unsigned(Z, m_out'length));
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if START = '1' then
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state <= fin;
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else
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state <= attente;
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end if;
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when others =>
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state <= attente;
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end case;
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end if;
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end if;
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end process Racine;
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end behavior;
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