31 lines
779 B
VHDL
31 lines
779 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity reg is
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generic(nb_bits : natural);
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port( Init : in STD_LOGIC; -- Initialization command
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init_value : in STD_LOGIC_VECTOR(nb_bits-1 downto 0); -- Init value with unsigned type to cover all possible values with large nb_bits
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ld : in STD_LOGIC; -- load command
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clk : in STD_LOGIC;
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E : in STD_LOGIC_VECTOR(nb_bits-1 downto 0);
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S : out STD_LOGIC_VECTOR(nb_bits-1 downto 0));
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end reg;
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architecture proced of reg is
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signal Sint : unsigned(nb_bits-1 downto 0);
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begin
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Ps: process(clk, Init)
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begin
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if (Init = '1') then
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Sint <= unsigned(init_value);
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elsif (clk'event and (clk = '1') and (ld ='1')) then
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Sint <= unsigned(E);
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end if;
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end process;
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S <= std_logic_vector(Sint);
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end proced;
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