26 lines
635 B
VHDL
26 lines
635 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mux3_1 is
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generic(nb_bits : natural );
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port( I0,I1,I2 : in STD_LOGIC_VECTOR(nb_bits-1 downto 0);
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sel : in STD_LOGIC_VECTOR(1 downto 0); -- select input
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S : out STD_LOGIC_VECTOR(nb_bits-1 downto 0));
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end mux3_1;
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architecture proced of mux3_1 is
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signal Sint : STD_LOGIC_VECTOR(nb_bits-1 downto 0);-- internal signal since process cannot directly modify an output
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begin
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process(sel, I0, I1)
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begin
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if (sel = "00") then
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Sint <= I0;
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elsif (sel = "01") then
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Sint <= I1;
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else
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Sint <= I2;
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end if;
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end process;
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S <= Sint;
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end proced;
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