judas/src/bsp/rpi3/memory_map.rs

//! The memory map of the board.

use crate::utils::field::Field;

pub const GPIO_OFFSET: usize = 0x0020_0000;
pub const UART0_OFFSET: usize = 0x0020_1000;

pub const START_PHYSICAL_ADDRESS: usize = 0x3F00_0000;

pub const UART0_START: usize = START_PHYSICAL_ADDRESS + UART0_OFFSET;

// ** GPIO addresses **
/// Beginning of the GPIO adresses
pub const GPIO_START: usize = START_PHYSICAL_ADDRESS + GPIO_OFFSET;

// Function Select
/// GPIO Function Select 0, R/W register.
/// bits 29-27: FSEL9
/// bits 26-24: FSEL8
/// bits 23-21: FSEL7
/// bits 20-18: FSEL6
/// bits 17-15: FSEL5
/// bits 14-12: FSEL4
/// bits 11-9: FSEL3
/// bits 8-6: FSEL2
/// bits 5-3: FSEL1
/// bits 2-0: FSEL0
pub const GPFSEL0: usize = GPIO_START + 0x00;
/// GPIO Function Select 1, R/W register.
/// bits 29-27: FSEL19
/// bits 26-24: FSEL18
/// bits 23-21: FSEL17
/// bits 20-18: FSEL16
/// bits 17-15: FSEL15
/// bits 14-12: FSEL14
/// bits 11-9: FSEL13
/// bits 8-6: FSEL12
/// bits 5-3: FSEL11
/// bits 2-0: FSEL10
pub const GPFSEL1:usize = GPIO_START + 0x04;
/// GPIO Function Select 2, R/W register.
/// bits 29-27: FSEL29
/// bits 26-24: FSEL28
/// bits 23-21: FSEL27
/// bits 20-18: FSEL26
/// bits 17-15: FSEL25
/// bits 14-12: FSEL24
/// bits 11-9: FSEL23
/// bits 8-6: FSEL22
/// bits 5-3: FSEL21
/// bits 2-0: FSEL20
pub const GPFSEL2:usize = GPIO_START + 0x08;
/// GPIO Function Select 3, R/W register.
/// bits 29-27: FSEL39
/// bits 26-24: FSEL38
/// bits 23-21: FSEL37
/// bits 20-18: FSEL36
/// bits 17-15: FSEL35
/// bits 14-12: FSEL34
/// bits 11-9: FSEL33
/// bits 8-6: FSEL32
/// bits 5-3: FSEL31
/// bits 2-0: FSEL30
pub const GPFSEL3:usize = GPIO_START + 0x0C;
/// GPIO Function Select 4, R/W register.
/// bits 29-27: FSEL49
/// bits 26-24: FSEL48
/// bits 23-21: FSEL47
/// bits 20-18: FSEL46
/// bits 17-15: FSEL45
/// bits 14-12: FSEL44
/// bits 11-9: FSEL43
/// bits 8-6: FSEL42
/// bits 5-3: FSEL41
/// bits 2-0: FSEL40
pub const GPFSEL4:usize = GPIO_START + 0x10;
/// GPIO Function Select 5, R/W register.
/// bits 11-9: FSEL53
/// bits 8-6: FSEL52
/// bits 5-3: FSEL51
/// bits 2-0: FSEL50
pub const GPFSEL5:usize = GPIO_START + 0x14;

/// Return the field FSELn.
/// 
/// # Panic
/// 
/// Panic if the pin `n` does not exist.
pub const fn get_fsel(n: usize) -> Field {
    if n > 53 {
        panic!("The PIN does not exist");
    }
    let address = [GPFSEL0, GPFSEL1, GPFSEL2, GPFSEL3, GPFSEL4, GPFSEL5][n/10];
    let offset = 3*(n%10);
    let size = 3;
    Field::new(address, offset, size)
}

// Pin Output Set
/// Pin Output Set 0, W register.
/// bit 31: SET31
/// ...
/// bit 0: SET0
pub const GPSET0:usize = GPIO_START + 0x1C;
/// Pin Output Set 1, W register.
/// bit 21: SET53
/// ...
/// bit 0: SET32
pub const GPSET1:usize = GPIO_START + 0x20;

/// Return the field SETn.
/// 
/// # Panic
/// 
/// Panic if the pin `n` does not exist.
pub const fn get_set(n: usize) -> Field {
    if n > 53 {
        panic!("The PIN does not exist");
    }
    let (address, offset) = if n < 32 {
        (GPSET0, n)
    } else {
        (GPSET1, n-32)
    };
    let size = 1;
    Field::new(address, offset, size)
}

// Pin Output Clear
/// Pin Output Clear 0, W register.
/// bit 31: CLR31
/// ...
/// bit 0: CLR0
pub const GPCLR0:usize = GPIO_START + 0x28;
/// Pin Output Clear 1, W register.
/// bit 21: CLR53
/// ...
/// bit 0: CLR32
pub const GPCLR1:usize = GPIO_START + 0x2C;

/// Return the field CLRn.
/// 
/// # Panic
/// 
/// Panic if the pin `n` does not exist.
pub const fn get_clr(n: usize) -> Field {
    if n > 53 {
        panic!("The PIN does not exist");
    }
    let (address, offset) = if n < 32 {
        (GPCLR0, n)
    } else {
        (GPCLR1, n-32)
    };
    let size = 1;
    Field::new(address, offset, size)
}

// Pin Level
/// Pin Level 0, R register.
pub const GPLEV0:usize = GPIO_START + 0x34;
/// Pin Level 1, R register.
pub const GPLEV1:usize = GPIO_START + 0x38;

// Pin Event Detect Status
/// Pin Event Detect Status 0, R/W register.
pub const GPEDS0:usize = GPIO_START + 0x40;
/// Pin Event Detect Status 1, R/W register.
pub const GPEDS1:usize = GPIO_START + 0x44;

// Pin Rising Edge Detect Enable
/// Pin Rising Edge Detect Enable 0, R/W register.
pub const GPREN0:usize = GPIO_START + 0x4C;
/// Pin Rising Edge Detect Enable 1, R/W register.
pub const GPREN1:usize = GPIO_START + 0x50;

// Pin Falling Edge Detect Enable
/// Pin Falling Edge Detect Enable 0, R/W register.
pub const GPFEN0:usize = GPIO_START + 0x58;
/// Pin Falling Edge Detect Enable 1, R/W register.
pub const GPFEN1:usize = GPIO_START + 0x5C;

// Pin High Detect Enable
/// Pin High Detect Enable 0, R/W register.
pub const GPHEN0:usize = GPIO_START + 0x64;
/// Pin High Detect Enable 1, R/W register.
pub const GPHEN1:usize = GPIO_START + 0x68;

// Pin Low Detect Enable
/// Pin Low Detect Enable 0, R/W register.
pub const GPLEN0:usize = GPIO_START + 0x70;
/// Pin Low Detect Enable 1, R/W register.
pub const GPLEN1:usize = GPIO_START + 0x74;

// Pin Async, Rising Edge Detect
/// Pin Async, Rising Edge Detect 0, R/W register.
pub const GPAREN0:usize = GPIO_START + 0x7C;
/// Pin Async, Rising Edge Detect 1, R/W register.
pub const GPAREN1:usize = GPIO_START + 0x80;

// Pin Async, Falling Edge Detect
/// Pin Async, Falling Edge Detect 0, R/W register.
pub const GPAFEN0:usize = GPIO_START + 0x88;
/// Pin Async, Falling Edge Detect1, R/W register.
pub const GPAFEN1:usize = GPIO_START + 0x8C;

// Pin Pull-up/down Enable, R/W
/// Pin Pull-up/down Enable, R/W register.
pub const GPPUD:usize = GPIO_START + 0x94;

// Pin Pull-up/down enable clock, R/W
/// Pin Pull-up/down enable clock 0, R/W register.
pub const GPPUDCLK0:usize = GPIO_START + 0x98;
/// Pin Pull-up/down enable clock 1, R/W register.
pub const GPPUDCLK1:usize = GPIO_START + 0x9C;

// Test ?, R/W, 4 bits
/// Test register? only 4 bits long.
pub const GPIO_TEST:usize = GPIO_START + 0xB0;
// ** GPIO addresses **