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@ -2,7 +2,6 @@
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use crate::utils::field::Field;
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pub const START_PHYSICAL_ADDRESS: usize = 0x3F00_0000;
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// ** GPIO addresses **
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@ -45,7 +44,7 @@ pub mod gpio {
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/// - 8-6: FSEL12
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/// - 5-3: FSEL11
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/// - 2-0: FSEL10
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pub const GPFSEL1:usize = GPIO_START + 0x04;
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pub const GPFSEL1: usize = GPIO_START + 0x04;
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/// GPIO Function Select 2, R/W register.
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///
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/// # Bits distribution:
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@ -60,7 +59,7 @@ pub mod gpio {
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/// - 8-6: FSEL22
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/// - 5-3: FSEL21
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/// - 2-0: FSEL20
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pub const GPFSEL2:usize = GPIO_START + 0x08;
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pub const GPFSEL2: usize = GPIO_START + 0x08;
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/// GPIO Function Select 3, R/W register.
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///
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/// # Bits distribution:
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@ -75,7 +74,7 @@ pub mod gpio {
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/// - 8-6: FSEL32
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/// - 5-3: FSEL31
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/// - 2-0: FSEL30
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pub const GPFSEL3:usize = GPIO_START + 0x0C;
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pub const GPFSEL3: usize = GPIO_START + 0x0C;
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/// GPIO Function Select 4, R/W register.
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///
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/// # Bits distribution:
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@ -90,7 +89,7 @@ pub mod gpio {
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/// - 8-6: FSEL42
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/// - 5-3: FSEL41
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/// - 2-0: FSEL40
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pub const GPFSEL4:usize = GPIO_START + 0x10;
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pub const GPFSEL4: usize = GPIO_START + 0x10;
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/// GPIO Function Select 5, R/W register.
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///
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/// # Bits distribution:
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@ -99,23 +98,23 @@ pub mod gpio {
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/// - 8-6: FSEL52
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/// - 5-3: FSEL51
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/// - 2-0: FSEL50
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pub const GPFSEL5:usize = GPIO_START + 0x14;
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pub const GPFSEL5: usize = GPIO_START + 0x14;
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/// Return the field FSELn.
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///
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///
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/// # Panic
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///
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///
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/// Panic if the pin `n` does not exist.
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pub const fn get_fsel(n: usize) -> Field {
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if n > 53 {
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panic!("The PIN does not exist");
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}
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let address = [GPFSEL0, GPFSEL1, GPFSEL2, GPFSEL3, GPFSEL4, GPFSEL5][n/10];
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let offset = 3*(n%10);
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let address = [GPFSEL0, GPFSEL1, GPFSEL2, GPFSEL3, GPFSEL4, GPFSEL5][n / 10];
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let offset = 3 * (n % 10);
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let size = 3;
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Field::new(address, offset, size)
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}
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// Pin Output Set
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/// Pin Output Set 0, W register.
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///
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@ -124,7 +123,7 @@ pub mod gpio {
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/// - 31: SET31
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/// - ...
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/// - 0: SET0
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pub const GPSET0:usize = GPIO_START + 0x1C;
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pub const GPSET0: usize = GPIO_START + 0x1C;
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/// Pin Output Set 1, W register.
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///
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/// # Bits distribution:
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@ -132,12 +131,12 @@ pub mod gpio {
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/// - 21: SET53
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/// - ...
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/// - 0: SET32
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pub const GPSET1:usize = GPIO_START + 0x20;
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pub const GPSET1: usize = GPIO_START + 0x20;
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/// Return the field SETn.
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///
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///
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/// # Panic
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///
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///
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/// Panic if the pin `n` does not exist.
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pub const fn get_set(n: usize) -> Field {
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if n > 53 {
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@ -146,12 +145,12 @@ pub mod gpio {
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let (address, offset) = if n < 32 {
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(GPSET0, n)
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} else {
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(GPSET1, n-32)
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(GPSET1, n - 32)
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};
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let size = 1;
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Field::new(address, offset, size)
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}
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// Pin Output Clear
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/// Pin Output Clear 0, W register.
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///
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@ -160,7 +159,7 @@ pub mod gpio {
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/// - 31: CLR31
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/// - ...
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/// - 0: CLR0
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pub const GPCLR0:usize = GPIO_START + 0x28;
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pub const GPCLR0: usize = GPIO_START + 0x28;
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/// Pin Output Clear 1, W register.
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///
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/// # Bits distribution:
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@ -168,12 +167,12 @@ pub mod gpio {
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/// - 21: CLR53
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/// - ...
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/// - 0: CLR32
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pub const GPCLR1:usize = GPIO_START + 0x2C;
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pub const GPCLR1: usize = GPIO_START + 0x2C;
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/// Return the field CLRn.
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///
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///
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/// # Panic
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///
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///
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/// Panic if the pin `n` does not exist.
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pub const fn get_clr(n: usize) -> Field {
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if n > 53 {
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@ -182,73 +181,73 @@ pub mod gpio {
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let (address, offset) = if n < 32 {
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(GPCLR0, n)
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} else {
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(GPCLR1, n-32)
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(GPCLR1, n - 32)
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};
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let size = 1;
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Field::new(address, offset, size)
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}
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// Pin Level
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/// Pin Level 0, R register.
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pub const GPLEV0:usize = GPIO_START + 0x34;
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pub const GPLEV0: usize = GPIO_START + 0x34;
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/// Pin Level 1, R register.
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pub const GPLEV1:usize = GPIO_START + 0x38;
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pub const GPLEV1: usize = GPIO_START + 0x38;
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// Pin Event Detect Status
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/// Pin Event Detect Status 0, R/W register.
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pub const GPEDS0:usize = GPIO_START + 0x40;
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pub const GPEDS0: usize = GPIO_START + 0x40;
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/// Pin Event Detect Status 1, R/W register.
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pub const GPEDS1:usize = GPIO_START + 0x44;
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pub const GPEDS1: usize = GPIO_START + 0x44;
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// Pin Rising Edge Detect Enable
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/// Pin Rising Edge Detect Enable 0, R/W register.
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pub const GPREN0:usize = GPIO_START + 0x4C;
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pub const GPREN0: usize = GPIO_START + 0x4C;
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/// Pin Rising Edge Detect Enable 1, R/W register.
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pub const GPREN1:usize = GPIO_START + 0x50;
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pub const GPREN1: usize = GPIO_START + 0x50;
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// Pin Falling Edge Detect Enable
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/// Pin Falling Edge Detect Enable 0, R/W register.
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pub const GPFEN0:usize = GPIO_START + 0x58;
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pub const GPFEN0: usize = GPIO_START + 0x58;
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/// Pin Falling Edge Detect Enable 1, R/W register.
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pub const GPFEN1:usize = GPIO_START + 0x5C;
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pub const GPFEN1: usize = GPIO_START + 0x5C;
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// Pin High Detect Enable
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/// Pin High Detect Enable 0, R/W register.
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pub const GPHEN0:usize = GPIO_START + 0x64;
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pub const GPHEN0: usize = GPIO_START + 0x64;
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/// Pin High Detect Enable 1, R/W register.
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pub const GPHEN1:usize = GPIO_START + 0x68;
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pub const GPHEN1: usize = GPIO_START + 0x68;
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// Pin Low Detect Enable
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/// Pin Low Detect Enable 0, R/W register.
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pub const GPLEN0:usize = GPIO_START + 0x70;
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pub const GPLEN0: usize = GPIO_START + 0x70;
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/// Pin Low Detect Enable 1, R/W register.
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pub const GPLEN1:usize = GPIO_START + 0x74;
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pub const GPLEN1: usize = GPIO_START + 0x74;
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// Pin Async, Rising Edge Detect
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/// Pin Async, Rising Edge Detect 0, R/W register.
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pub const GPAREN0:usize = GPIO_START + 0x7C;
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pub const GPAREN0: usize = GPIO_START + 0x7C;
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/// Pin Async, Rising Edge Detect 1, R/W register.
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pub const GPAREN1:usize = GPIO_START + 0x80;
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pub const GPAREN1: usize = GPIO_START + 0x80;
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// Pin Async, Falling Edge Detect
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/// Pin Async, Falling Edge Detect 0, R/W register.
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pub const GPAFEN0:usize = GPIO_START + 0x88;
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pub const GPAFEN0: usize = GPIO_START + 0x88;
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/// Pin Async, Falling Edge Detect1, R/W register.
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pub const GPAFEN1:usize = GPIO_START + 0x8C;
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pub const GPAFEN1: usize = GPIO_START + 0x8C;
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// Pin Pull-up/down Enable, R/W
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/// Pin Pull-up/down Enable, R/W register.
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pub const GPPUD:usize = GPIO_START + 0x94;
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pub const GPPUD: usize = GPIO_START + 0x94;
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// Pin Pull-up/down enable clock, R/W
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/// Pin Pull-up/down enable clock 0, R/W register.
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pub const GPPUDCLK0:usize = GPIO_START + 0x98;
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pub const GPPUDCLK0: usize = GPIO_START + 0x98;
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/// Pin Pull-up/down enable clock 1, R/W register.
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pub const GPPUDCLK1:usize = GPIO_START + 0x9C;
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pub const GPPUDCLK1: usize = GPIO_START + 0x9C;
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// Test ?, R/W, 4 bits
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/// Test register? only 4 bits long.
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pub const GPIO_TEST:usize = GPIO_START + 0xB0;
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pub const GPIO_TEST: usize = GPIO_START + 0xB0;
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}
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// ** GPIO addresses **
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@ -276,31 +275,30 @@ pub mod uart {
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pub dr: Field,
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/// OE, Overrun Error. Set to 1 if data received with FIFO full, R/W.
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///
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///
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/// Field located inside the Data Register [`dr`].
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pub dr_oe: Field,
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/// BE, Break Error. Set to 1 if a break condition was detected, R/W.
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///
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///
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/// Field located inside the Data Register [`dr`].
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pub dr_be: Field,
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/// PE, Parity Error. Set to 1 when the parity don't match data, R/W.
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///
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///
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/// Field located inside the Data Register [`dr`].
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pub dr_pe: Field,
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/// FE, Framing Error. Set to 1 when character don't have valid stop bit, R/W.
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///
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///
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/// Field located inside the Data Register [`dr`].
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pub dr_fe: Field,
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/// DATA, Data character. R/W.
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///
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///
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/// Field located inside the Data Register [`dr`].
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pub dr_data: Field,
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/// Receive Status Register/Error Clear Register, 32 bits long.
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///
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/// # Bits distribution:
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@ -313,22 +311,22 @@ pub mod uart {
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pub rsrecr: Field,
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/// OE, Overrun Error. Set to 1 if data received with FIFO full, R/W.
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///
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///
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/// Field located inside the Receive Status Register/Error Clear Register [`rsrecr`].
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pub rsrecr_oe: Field,
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/// BE, Break Error. Set to 1 if a break condition was detected, R/W.
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///
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///
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/// Field located inside the Receive Status Register/Error Clear Register [`rsrecr`].
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pub rsrecr_be: Field,
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/// PE, Parity Error. Set to 1 when the parity don't match data, R/W.
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///
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///
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/// Field located inside the Receive Status Register/Error Clear Register [`rsrecr`].
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pub rsrecr_pe: Field,
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/// FE, Framing Error. Set to 1 when characteur don't have valid stop bit, R/W.
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///
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///
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/// Field located inside the Receive Status Register/Error Clear Register [`rsrecr`].
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pub rsrecr_fe: Field,
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@ -349,7 +347,7 @@ pub mod uart {
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/// - 3: BUSY. Is set, UART is busy transmitting data. R/W.
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/// - 2: DCD, unsuported. Write as 0, value read don't have meaning, R/W.
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/// - 1: DSR, unsuported. Write as 0, value read don't have meaning, R/W.
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/// - 0: CTS, Clear To Send.
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/// - 0: CTS, Clear To Send.
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pub fr: Field,
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/// RI, unsuported. Write as 0, value read don't have meaning, R/W.
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@ -396,7 +394,7 @@ pub mod uart {
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/// Field located inside the Flag Register [`fr`].
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pub fr_dsr: Field,
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/// CTS, Clear To Send.
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/// CTS, Clear To Send.
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///
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/// Field located inside the Flag Register [`fr`].
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pub fr_cts: Field,
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@ -430,7 +428,7 @@ pub mod uart {
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/// - 6-5: WLEN: World lenght. Number of data bits transmitted by frame (0b00 -> 5b, 0b11 ->
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/// 8b), R/W.
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/// - 4: FEN, Enable FIFOs. 0: FIFOs disabled, 1: FIFO buffers are enables, R/W.
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/// - 3: STP2, 2 Stop bit select. 1: 2 stop bits are transmitted at the end of the frame
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/// - 3: STP2, 2 Stop bit select. 1: 2 stop bits are transmitted at the end of the frame
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/// (rx logic is not affected), R/W.
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/// - 2: EPS, Event Parity Select. 0: odd parity, check for odd number of 1 in data+parity
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/// bits, 1: event parity, check for even number of 1 in data+parity. No effect when
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@ -457,7 +455,7 @@ pub mod uart {
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/// Field located inside the Line Constrol Register [`lcrh`].
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pub lcrh_fen: Field,
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/// STP2, 2 Stop bit select. 1: 2 stop bits are transmitted at the end of the frame
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/// STP2, 2 Stop bit select. 1: 2 stop bits are transmitted at the end of the frame
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/// (rx logic is not affected), R/W.
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///
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/// Field located inside the Line Constrol Register [`lcrh`].
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@ -486,7 +484,7 @@ pub mod uart {
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/// # Warning
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///
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/// To program the CR:
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///
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///
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/// - 1) Disable UART
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/// - 2) Wait for the end of tx/rx of the current char
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/// - 3) Flush the transmit FIFO by setting `FEN` to 0 in [`LCRH`]
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@ -510,7 +508,7 @@ pub mod uart {
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/// - 6-3: reserved. Write as 0, value read don't have meaning, R/W.
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/// - 2: SIRLP, unsuported, Write as 0, value read don't have meaning, R.
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/// - 1: SIREN, unsuported, Write as 0, value read don't have meaning, R.
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/// - 0: UARTEN, UART enable. If set, the UART is enable, R/W.
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/// - 0: UARTEN, UART enable. If set, the UART is enable, R/W.
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pub cr: Field,
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/// CTSEN, CTS hardware flow control enable. If set, data is only transmitted when
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@ -639,7 +637,7 @@ pub mod uart {
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/// Field located inside the Control Register [`cr`].
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pub cr_siren: Field,
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/// UARTEN, UART enable. If set, the UART is enable, R/W.
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/// UARTEN, UART enable. If set, the UART is enable, R/W.
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///
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/// Field located inside the Control Register [`cr`].
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///
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@ -658,7 +656,6 @@ pub mod uart {
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pub cr_uarten: Field,
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// TODO: Finish detailling the registers
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/// Interrupt FIFO Level Select register, 32 bits long.
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///
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/// # Bits distribution:
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@ -666,7 +663,7 @@ pub mod uart {
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/// - 31-12: reserved. Write as 0, value read don't have meaning, R/W.
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/// - 11-9: RXIFPSEL, unsuported, Write as 0, value read don't have meaning, R.
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/// - 8-6: TXIFPSEL, unsuported, Write as 0, value read don't have meaning, R.
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/// - 5-3: RXIFLSEL, Receive Interrupt FIFO Level Select. The level from which the
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/// - 5-3: RXIFLSEL, Receive Interrupt FIFO Level Select. The level from which the
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/// reveive interrupt is send:
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/// - `0b000`: Send when FIFO becom 1/8 full
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/// - `0b001`: Send when FIFO becom 1/4 full
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@ -675,7 +672,7 @@ pub mod uart {
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/// - `0b100`: Send when FIFO becom 7/7 full
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/// - Other values are reserved.
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/// R/W.
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/// - 2-0: TXIFLSEL, Transmit Interrupt FIFO Level Select. The level from which the
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/// - 2-0: TXIFLSEL, Transmit Interrupt FIFO Level Select. The level from which the
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/// transmit interrupt is send:
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/// - `0b000`: Send when FIFO becom 1/8 full
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/// - `0b001`: Send when FIFO becom 1/4 full
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@ -809,7 +806,6 @@ pub mod uart {
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/// - 31-11: reserved. Write as 0, value read don't have meaning, R.
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/// - 10-0: TDR10_0. When ITCRI1 is set to 1, data read an write directly from the FIFOs, R/W.
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pub tdr: Field,
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}
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impl UartMemoryMap {
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@ -878,5 +874,4 @@ pub mod uart {
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}
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pub const UART: UartMemoryMap = UartMemoryMap::new(UART_START);
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}
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