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@ -29,7 +29,7 @@ impl<'a> UartInner<'a> {
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self.flush();
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// Stop UART
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// Stop UART, see doc of CR register for the config process (P 185, doc BCM2835)
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self.memory_map.cr_uarten.read_and_write(0);
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// Flush the FIFOs
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@ -54,7 +54,8 @@ impl<'a> UartInner<'a> {
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self.memory_map.lcrh.write_without_read(lcrh_val);
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let cr_val = self.memory_map.cr_txe.read_and_write_to_u32(1, 0);
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// TODO: let cr_val = self.memory_map.cr_rxe.read_and_write_to_u32(1, 0); to enable read
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let cr_val = self.memory_map.cr_rxe.read_and_write_to_u32(1, cr_val);
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// Again, see doc of CR register for the config process (P 185, doc BCM2835)
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self.memory_map.cr.write_without_read(cr_val);
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// Start the UART
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@ -67,11 +68,16 @@ impl<'a> UartInner<'a> {
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self.memory_map.fr_busy.read() != 0
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}
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/// Test if the the TX FIFO is full.
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/// Test if the TX FIFO is full.
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fn is_tx_full(&self) -> bool {
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self.memory_map.fr_txff.read() != 0
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}
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/// Test if the RX FIFO is empty
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fn is_rx_empty(&self) -> bool {
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self.memory_map.fr_rxfe.read() != 0
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}
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/// Write a character to the Uart
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fn write_char(&self, c: char) {
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if !self.initialized {
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@ -85,12 +91,28 @@ impl<'a> UartInner<'a> {
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self.memory_map.dr_data.write_without_read(c as u32);
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}
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/// Flush the uart
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/// Read a character from the UART.
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/// Blocking.
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fn blocking_read_char(&self) -> char {
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while self.is_rx_empty() {
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unsafe { asm!("nop") };
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}
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self.memory_map.dr_data.read() as u8 as char
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}
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/// Flush the output of the uart
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fn flush(&self) {
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while self.is_busy() {
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unsafe { asm!("nop") };
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}
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}
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/// Flush the input of the uart
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fn flush_input(&self) {
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while !self.is_rx_empty() {
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let _ = self.memory_map.dr_data.read() as u8 as char;
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}
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}
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}
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// Allow the use of uart for fmt::Write::write_fmt.
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@ -122,10 +144,12 @@ impl Write for Uart<'_> {
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impl Read for Uart<'_> {
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fn read_char(&self) -> char {
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todo!()
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self.inner.lock(|uart| uart.blocking_read_char())
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}
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fn flush_input(&self) {}
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fn flush_input(&self) {
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self.inner.lock(|uart| uart.flush_input())
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}
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}
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impl<'a> Uart<'a> {
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